Memory testing method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a memory testing method and device, electronic equipment and a storage medium, and relates to the technical field of computer storage. The method comprises the following steps: starting firmware; a memory configuration program, a memory hardware fault test program and a memory running program are arranged in the firmware, and the memory hardware fault test program is arranged between the memory configuration program and the memory running program; performing parameter configuration on the memory according to the memory configuration program; and executing the memory hardware fault test program after the memory parameter configuration and before the memory operation, and testing the memory. After firmware is started, after memory parameter configuration and before memory operation, a memory hardware fault test program is executed, the memory is tested, other hardware factors are basically not involved, convenience is brought to memory testing, the memory testing efficiency can be improved, and due to the fact that other hardware factors are basically not involved, if faults exist in memory testing, the memory testing efficiency can be improved. And the memory hardware fault can be intuitively and accurately represented.

Description

Technical Field

[0001] This invention relates to the field of computer storage technology, and in particular to a memory testing method, a memory testing device, an electronic device, and a storage medium. Background Technology

[0002] Computer testing typically includes a software debugging phase, which in turn includes a memory debugging phase, specifically memory testing. Memory testing directly reflects the integrity and stability of memory functionality. The integrity and stability of memory functionality directly affect the stability of other programs, which here refer to programs loaded into memory.

[0003] Currently, memory testing is performed indirectly. These indirect methods can include: determining the stability of a program running in memory, or testing the memory using memory testing tools after entering the operating system.

[0004] However, in the above-mentioned indirect memory testing methods, if the test fails, it is not possible to completely determine what kind of memory failure it is, which makes the memory testing method unable to accurately reflect the memory failure situation. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a memory testing method that overcomes or at least partially solves the above problems, so as to accurately reflect memory failure conditions.

[0006] In a first aspect, the present invention provides a memory testing method, the method comprising: Start the firmware; wherein the firmware includes a memory configuration program, a memory hardware fault test program, and a memory running program, and the memory hardware fault test program is located between the memory configuration program and the memory running program; According to the memory configuration program, the memory is configured with parameters, including: the identifier of the first memory cell to be tested, the total number of memory cells to be tested, and the test items for each memory cell. The test items include: address line testing, data line testing, and memory chip testing, at least one of these three. If the number of test items for a memory cell to be tested is greater than or equal to 2, the parameters also include: the test order of each test item for the memory cell to be tested. The test order of each test item for the memory cell to be tested includes: data line testing before address line testing, address line testing before memory chip testing, and data line testing before memory chip testing. After the memory parameters are configured and before the memory is run, a memory hardware fault test program is executed. Starting from the first storage unit to be tested, each of the test items of all the storage units to be tested is tested to test the memory.

[0007] In a second aspect, the present invention provides a memory testing apparatus, comprising: A firmware startup module is used to start the firmware; wherein the firmware includes a memory configuration program, a memory hardware fault test program, and a memory running program, and the memory hardware fault test program is located between the memory configuration program and the memory running program; The configuration module is used to configure memory parameters according to the memory configuration program. The parameters include: the identifier of the first memory cell to be tested, the total number of memory cells to be tested, and the test items for each memory cell. The test items include at least one of address line testing, data line testing, and memory chip testing. If the number of test items for a memory cell to be tested is greater than or equal to two, the parameters also include: the test order of each test item for the memory cell to be tested. The test order of each test item for the memory cell to be tested includes: data line testing before address line testing, address line testing before memory chip testing, and data line testing before memory chip testing. The testing module is used to execute the memory hardware fault test program after the memory parameters are configured and before the memory is run, starting from the first storage unit to be tested, and testing each of the test items of all the storage units to be tested in order to test the memory.

[0008] Thirdly, the present invention provides an electronic device, comprising: a processor, firmware, and a computer program stored on the firmware and executable on the processor, wherein the processor executes the program to implement the above-described memory testing method.

[0009] Fourthly, the present invention provides a readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the above-described memory testing method.

[0010] Fifthly, the present invention provides a computer program product including instructions that, when executed by a processor in an electronic device, cause the electronic device to perform any of the aforementioned memory testing methods.

[0011] This invention has the following advantages: The firmware includes a memory configuration program, a memory hardware fault test program, and a memory execution program. The memory hardware fault test program is positioned between the memory configuration and execution programs. Following the order of these programs in the firmware, after firmware startup, the memory hardware fault test program is executed after memory parameter configuration and before memory execution. Starting with the first memory cell under test, it performs tests on all memory cells for each item, thus testing the entire memory in one go. This involves automated testing of each and every test item for each memory cell under test, based on the memory parameter configuration. This high degree of automation and efficiency ensures efficient memory testing. Since other hardware is not yet running or initialized after memory parameter configuration but before memory execution, memory testing at this stage largely avoids involvement of other hardware factors, improving efficiency and allowing for direct and accurate characterization of memory hardware faults if any are found. Meanwhile, the data lines, which have a relatively basic function, are the first item in the test. Furthermore, testing the memory chips in the storage unit is only meaningful after confirming that there are no faults in the data lines and address lines. The above test order setting can make the test results more accurately reflect the actual situation of the memory, reduce invalid memory test steps, and improve memory test efficiency. Attached Figure Description

[0012] Figure 1 A flowchart illustrating the steps of an embodiment of the memory testing method of the present invention is shown; Figure 2 A structural block diagram of an embodiment of the memory testing device of the present invention is shown; Figure 3 A schematic diagram illustrating partial steps of computer startup according to the present invention is shown; Figure 4 A schematic diagram illustrating the steps of a memory test according to the present invention is shown; Figure 5 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0013] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] The inventors discovered that the main reason why the aforementioned indirect memory testing method cannot definitively determine if a memory hardware failure is the cause of the test failure is that this indirect method involves multiple hardware factors, but is not solely a memory hardware issue. Specifically, methods for judging the stability of a program running in memory cannot be used as a complete basis for determining whether there is a memory problem, because issues with the program itself, incompatibility between the program and computer hardware, etc., can all lead to program instability. Furthermore, using memory testing tools after entering the operating system has some limitations. On the one hand, entering the operating system requires using a firmware-booted system image, and there is a possibility of successful system booting when memory stability is relatively good (even if stability is actually problematic). On the other hand, even if the system image boots successfully, operating system anomalies may occur during the boot process; these anomalies may be caused by hardware problems other than memory hardware issues, memory instability, or problems with the program itself.

[0015] To address the aforementioned technical problems, one of the core concepts of this invention is that, after firmware startup, a memory hardware fault test program is executed after memory parameter configuration and before memory operation to test the memory. Since other hardware has not yet started or initialized, memory testing at this stage involves virtually no other hardware factors, facilitating memory testing and improving efficiency. Furthermore, because it largely avoids other hardware factors, any memory faults can be directly and accurately characterized. Moreover, by configuring memory parameters, starting from the first storage unit under test, all test items for all storage units under test are performed, allowing for a one-time testing of the entire memory. This involves automated testing of each test item for each storage unit under test, automatically implementing memory testing based on parameter configuration, resulting in a high degree of automation and testing efficiency.

[0016] Figure 1 A flowchart illustrating the steps of an embodiment of the memory testing method of the present invention is shown below. Figure 1 The memory testing method may specifically include the following steps: Step 101: Start the firmware. The firmware includes a memory configuration program, a memory hardware fault test program, and a memory running program, with the memory hardware fault test program located between the memory configuration program and the memory running program.

[0017] The firmware mentioned here can refer to the Basic Input Output System (BIOS), which stores the computer's most important basic input / output programs, power-on self-test (POST) programs, and system startup programs. Its main function is to provide the lowest-level, most direct hardware settings and control for the computer. Firmware includes many types. For example, firmware can refer to PMON, UEFI (Unified Extensible Firmware Interface), etc. PMON is an open-source software that combines some functions of BIOS and Bootloader, and is often used in embedded systems.

[0018] The firmware includes a memory hardware fault test program located between the memory configuration program and the memory execution program. The memory configuration program is primarily for configuring memory parameters, while the memory execution program is for adjusting memory operation. By placing this memory hardware fault test program between these two programs and executing them sequentially, memory testing can be easily performed after memory parameter configuration and before memory execution.

[0019] It should be noted that the memory hardware fault test program here refers to a memory hardware fault test program that has undergone multiple tests in advance to prove that it is correct or has no faults. Therefore, if the memory hardware fault test program is correct and there is no other hardware interference, if there is a fault in the memory test, it can intuitively and accurately characterize the memory hardware fault.

[0020] Optionally, the memory hardware fault test program in step 101 above is a C language memory hardware fault test program. Specifically, C is a procedural, abstract, general-purpose programming language widely used in low-level development. C can easily compile and process low-level memory. C is a highly efficient programming language that generates only a small amount of machine language and can run without any runtime environment support. The memory hardware fault test program provided by this invention is a C language memory hardware fault test program, which is convenient to read and maintain, and has strong portability. For example, it is easy to port to different types of firmware and different architectures.

[0021] Step 102: Configure memory parameters according to the memory configuration program; the parameters include: the identifier of the first storage unit to be tested in memory, the total number of storage units to be tested in memory, and the test items for the storage units to be tested; the test items include: address line test, data line test, and memory chip test, at least one of the three; if the number of test items for the storage unit to be tested is greater than or equal to 2, the parameters also include: the test order of each test item for the storage unit to be tested; wherein, the test order of each test item for the storage unit to be tested includes: data line test before address line test, address line test before memory chip test, and data line test before memory chip test.

[0022] Memory contains many storage units, and the storage unit to be tested refers to the storage unit that needs to be tested. Testing memory can be done on all storage units or on a subset of them; there is no specific limitation here. The first storage unit to be tested in memory refers to the first storage unit to be tested, based on its address, etc. For example, if all storage units in memory are being tested, the first storage unit to be tested is the first storage unit in that memory. The identifier of the first storage unit to be tested refers to the identifier used to distinguish it from other storage units. Here, the first storage unit to be tested can be characterized by its starting address; there is no specific limitation on this.

[0023] The total number of memory units to be tested refers to the total number of memory units to be tested. The total number of memory units to be tested can be represented by their size. The test items for each memory unit refer to the specific tests performed on that memory unit.

[0024] The memory test items or contents may include: data line testing, address line testing, and memory chip testing, etc., without specific limitations. The memory includes at least one memory segment, which refers to multiple consecutive units to be tested. This can be a full test, where every storage unit in the memory segment to be tested is tested, or an interval test can be performed on the memory segment to be tested. Regardless of whether it is a full test or an interval test, it is necessary to cover the memory segment to be tested.

[0025] By configuring memory parameters here, memory testing can be automatically performed later based on these parameters, resulting in a high degree of automation and testing efficiency.

[0026] It should be noted that step 102 may further include configuring test parameters and test result output according to the aforementioned memory configuration program. For example, it may configure the maximum memory error output, whether to apply a cache, and whether to output the initialization parameter configuration during the test. The maximum memory error output here refers to the number of errors detected in a computer's memory test before the test stops and a memory hardware failure is reported. This application may or may not use a cache. Using a cache can improve testing efficiency, but it may introduce cache failures, potentially reducing test accuracy.

[0027] Step 103: After configuring the memory parameters and before the memory is running, execute the memory hardware fault test program. Starting from the first storage unit to be tested, test each of the test items of all the storage units to be tested to test the memory.

[0028] In electronic devices, other hardware such as USB, display, hard drive, and PCIe (Peripheral Component Interconnect Express) typically initialize after the memory is running, and then the operating system starts. In this invention, the memory test is performed under firmware, after memory parameters are configured but before the memory runs. At this stage, other hardware has not yet initialized, meaning it is not running. Therefore, this stage of memory testing largely avoids involvement of other hardware factors, facilitating memory testing. Furthermore, because it largely avoids involvement of other hardware factors, any memory hardware faults can be directly and accurately characterized.

[0029] The testing process involves executing a memory hardware fault test program after the memory parameters are configured and before the memory is run. Starting from the first storage unit to be tested, each test item of each storage unit to be tested is performed one by one.

[0030] This invention is particularly suitable for memory testing in newly designed computers. In such computers, other components may exhibit numerous malfunctions. In this scenario, using existing indirect memory testing methods would involve many other hardware components besides the memory itself. The involvement of numerous hardware devices significantly increases the probability of malfunctions, even if those malfunctions are not memory-related. Therefore, this invention tests the memory after configuration and before operation in newly designed computers, minimizing the involvement of other hardware factors. This simplifies memory testing for newly designed computers, improves testing efficiency, and, because it largely avoids other hardware factors, allows for a more direct and accurate characterization of memory hardware failures if they are detected.

[0031] Optionally, the test items for the storage unit under test in step 103 may include at least one of the following: address line test, data line test, and memory chip test. Address lines are used to transmit address information. Typically, when searching for data in memory, the address is first found using the address lines, and then the data is retrieved using the data lines. Address line testing checks for faults in the memory's address lines. Data line testing checks for faults in the data lines. Memory chip testing checks for faults in the memory chips.

[0032] Optionally, when the number of test items is greater than or equal to 2, the parameters in step 103 above further include: the test order of each test item of the storage unit under test. The test order of each test item of the storage unit under test may include: data line testing before address line testing, address line testing before memory chip testing, and data line testing before memory chip testing. The test order refers to the specific test order of each test item for one storage unit under test. That is, when the test items of the storage unit under test include the aforementioned three items, the test order of each test item is data line testing, address line testing, and memory chip testing, in that order. When the test items of the storage unit under test only include data line testing and address line testing, the test order of each test item is data line testing first, then address line testing. When the test items of the storage unit under test only include address line testing and memory chip testing, the test order of each test item is address line testing first, then memory chip testing. When the test items for the storage unit under test only include data line testing and memory chip testing, the testing order for each item is: data line testing first, followed by memory chip testing. That is, in the memory testing process, the order of data line testing is superior to the order of address line testing, and the order of address line testing is superior to the order of memory chip testing. By adopting this technical solution, the more fundamental data line is placed as the first test item. Furthermore, testing the memory chips of the storage unit is only meaningful after confirming that both the data lines and address lines are fault-free. This test order setting allows the test results to more accurately reflect the actual situation of the memory, reduces unnecessary memory testing steps, and improves memory testing efficiency.

[0033] Optionally, the test items for the storage unit to be tested include: address line test, data line test, and memory chip test, a total of three test items. Step 103 may include: Step 1031: Starting from the first storage unit to be tested, write test values ​​to the aforementioned storage units in the order of data line test, address line test, and memory chip test, and then read the stored value of the aforementioned test unit. If the stored value and the test value are equal, the memory test passes. The test value here can be any value, without specific limitations. Normally, only when the address lines, data lines, and memory chips are all functioning correctly will the value written to the storage unit to be tested be the same as or equal to the value read from the storage unit to be tested. By comparing whether the value written to the storage unit to be tested is the same as or equal to the value read from the storage unit to be tested, the accuracy of whether the address line test, data line test, and memory chip test of the storage unit to be tested are faulty can be determined. It should be noted that the test value here can be content that is easy to compare, for example, it can be all 0 values ​​or all 1 values, without specific limitations.

[0034] Optionally, step 1031 may include steps 10311 to 10313. Step 10311: Starting from the first storage cell to be tested, a first preset value is written into one of the storage cells to be tested, and then a second value is read from the storage cell to be tested. If the second value is equal to the first preset value, the data line test of the storage cell to be tested passes.

[0035] The first preset value here can be any value, and there is no specific limitation. By comparing whether the value written to a storage cell under test is the same as or equal to the value read from the storage cell under test, it can be accurately determined whether the data line of the storage cell under test is faulty. If the first preset value written to a storage cell is equal to the second value read from the storage cell, it means that the data line of the storage cell under test is normal, and the data line test of the storage cell under test passes; otherwise, the data line test of the storage cell under test fails or the data line is faulty.

[0036] Step 10312: If the data line test of all the storage units to be tested in the memory passes, starting from the first storage unit to be tested, write a third preset value into the storage unit to be tested through the address number, and then read out the fourth value in the storage unit to be tested through the address number. If the fourth value is equal to the third preset value, the address line test of the storage unit to be tested passes.

[0037] The third preset value here can be any value, without specific limitations. After obtaining the address number, addressing will be performed via the address lines. The third preset value is written to the memory cell under test using the address number. If the address lines of the memory cell under test are functioning correctly, addressing will be performed via the address lines, and then the third preset value will be written to the memory cell under test corresponding to that address number. Therefore, the fourth value in the memory cell under test at that address number is read. If the fourth value equals the aforementioned third preset value, it indicates that the address lines of the memory cell under test are normal, and the address line test of the memory cell under test has passed. Otherwise, it indicates that the address line test of the memory cell under test has failed or that the address lines are faulty.

[0038] Optionally, the third preset value here may include the address number of the unit under test. That is, the address number of the unit under test is written into the unit under test. If the address lines of the unit under test are not faulty, addressing will be performed through the address lines, and then the address number of the unit under test will be written into the corresponding unit. Therefore, the fourth value in the unit under test is read. If the fourth value equals the address number of the unit under test, it indicates that the address lines of the unit under test are normal and the address line test is passed. Otherwise, it indicates that the address line test of the unit under test has failed or that the address lines are faulty. Since each unit under test has an address number, there is no need to specifically generate a third preset value, improving testing efficiency.

[0039] Since the data lines of the memory cells play a more fundamental role, the address lines of the memory cells to be tested should only be tested after all the data line tests of all the memory cells to be tested in the memory have passed. This can reduce invalid memory testing steps and improve memory testing efficiency.

[0040] Step 10313: If the address line tests of all test storage units in the memory pass, starting from the first test storage unit, select a predetermined number of consecutively distributed test storage units as a test storage unit group; the total number of bits corresponding to a test storage unit group is equal to the bit width of the memory; write a fifth preset value into all test storage units in a test storage unit group, and then read out the sixth value from all test storage units in the test storage unit group. If each bit of the sixth value is equal to each bit of the fifth preset value, it is determined that the memory chip test of all test storage units in the test storage unit group has passed; the number of bits of the fifth preset value is equal to the bit width of the memory.

[0041] The bit width of memory refers to how many bits of data are read from memory at a time. For example, if memory reads 64 bits of data at a time, then the bit width of that memory is 64 bits.

[0042] Since the address lines of a memory cell play a relatively basic role, the memory chip test of the memory cell to be tested can be performed only after the address line tests of all memory cells to be tested in the memory have passed. This can reduce invalid memory testing steps and improve memory testing efficiency.

[0043] Here, starting with the first test cell, a predetermined number of consecutively distributed test cells are selected as a test cell group. The total number of bits corresponding to a test cell group refers to the sum of the number of bits of data that each test cell in that group can store. The total number of bits corresponding to a test cell group is equal to the bit width of the memory. The number of bits that a storage cell can store × the predetermined number = bit width. For example, if a storage cell can store 8 bits and the memory bit width is 64 bits, then a test cell group includes 8 consecutively distributed test cells, and the predetermined number here is 8.

[0044] The fifth preset value here can be any value, without specific limitations. The fifth preset value is written to all test cells in a test cell group. Then, the sixth value is read from all test cells in that test cell group. If each bit of the sixth value corresponds to each bit of the aforementioned fifth preset value, it is determined that the memory chip test of all test cells in that test cell group has passed. Here, the number of bits in the fifth preset value is equal to the memory's bit width, thus completing the test of multiple memory cells' memory chips at once, resulting in high testing efficiency. Each value in the fifth preset value corresponds to at least one bit in the memory's bit width, and each bit in the memory's bit width corresponds to at least one memory chip in the test cell. If a value in the fifth preset value is not equal to the corresponding bit in the read sixth value, it indicates that the memory chip in the corresponding memory cell is faulty.

[0045] Optionally, in this invention, the test result of a storage unit under test can be output after a certain test item or all test items of a storage unit under test have been completed. Alternatively, the test result of a test segment can be output after a certain test item or several test items of all storage units under test in the memory test segment have been completed, etc., without specific limitations. By outputting the test results, the test results can be conveniently and clearly communicated to the testers. Especially in the case of hardware faults, the output results can indicate the approximate location of the fault, etc., which can help the testers resolve the corresponding faults as quickly as possible.

[0046] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0047] Reference Figure 2 , Figure 2 A structural block diagram of an embodiment of the memory testing device of the present invention is shown, which may specifically include the following modules: Firmware startup module 201 is used to start firmware; wherein, the firmware includes a memory configuration program, a memory hardware fault test program and a memory running program, and the memory hardware fault test program is located between the memory configuration program and the memory running program; The configuration module 202 is used to configure memory parameters according to the memory configuration program. The parameters include: the identifier of the first memory cell to be tested, the total number of memory cells to be tested, and the test items for each memory cell. The test items include at least one of address line testing, data line testing, and memory chip testing. If the number of test items for a memory cell to be tested is greater than or equal to 2, the parameters also include: the test order of each test item for the memory cell to be tested. The test order of each test item for the memory cell to be tested includes: data line testing before address line testing, address line testing before memory chip testing, and data line testing before memory chip testing. The test module 203 is used to execute the memory hardware fault test program after the memory parameters are configured and before the memory is running, starting from the first storage unit to be tested, and testing each of the test items of all the storage units to be tested in order to test the memory.

[0048] Optionally, the test module 203 includes: The test unit is used to write test values ​​into the first memory cell to be tested in the order of data line test, address line test and memory chip test, starting from the first memory cell to be tested. Then, it reads out the stored value of the test unit. If the stored value and the test value are equal, the memory test is passed.

[0049] Optionally, the test unit includes: The first test subunit is used to write a first preset value into a storage unit under test, starting from the first storage unit under test, and then read out a second value from the storage unit under test. If the second value is equal to the first preset value, the data line test of the storage unit under test is passed. The second test subunit is used to write a third preset value into a test storage unit starting from the first test storage unit, through the address number, and then read out the fourth value in the test storage unit through the address number. If the fourth value is equal to the third preset value, the address line test of the test storage unit is passed. The third test subunit is used to select a predetermined number of consecutively distributed test cells as a test cell group, starting from the first test cell, if all address line tests of all test cells in the memory pass. The total number of bits corresponding to a test cell group is equal to the bit width of the memory. A fifth preset value is written into all test cells of a test cell group, and then a sixth value is read from all test cells of the test cell group. If each bit of the sixth value is equal to each bit of the fifth preset value, it is determined that the memory chip test of all test cells in the test cell group has passed. The number of bits of the fifth preset value is equal to the bit width of the memory.

[0050] Optionally, the device further includes: The output module is used to output memory test results.

[0051] Optionally, the memory hardware fault test program is a C language memory hardware fault test program.

[0052] It should be noted that the memory testing device can refer to the aforementioned memory testing method and has the same or similar beneficial effects. To avoid repetition, it will not be described again here.

[0053] The present application will be further explained below with reference to specific embodiments.

[0054] Figure 3 A schematic diagram illustrating partial steps of computer startup according to the present invention is shown. This computer may be a newly designed computer, and its firmware may include: PMON and UEFI. (See reference...) Figure 3As shown, for a newly designed computer, CPU configuration is performed first. This CPU configuration can involve entering the firmware or booting the firmware. Then, the process jumps to cache execution, entering the C language environment. The memory testing method in this invention is mainly performed after the memory parameter configuration stage and before the memory execution stage. After the memory parameter configuration stage and before the memory execution stage, other hardware besides the memory hardware has not yet been initialized, or in other words, has not yet started. After the memory parameter configuration is completed, the process jumps to memory execution. After successful memory execution, other devices will be initialized. If the initialization of other devices is successful, then the boot is successful.

[0055] Figure 4 A schematic diagram illustrating the steps of a memory test according to the present invention is shown. Figure 4 The initialization of test parameters corresponds to the memory parameter configuration in step 102 above, where the memory configuration program configures the memory parameters. Before configuring the memory parameters, a memory hardware fault test program, written in C language, has been set up between the memory configuration program and the memory execution program in the firmware. (Refer to...) Figure 4 The memory hardware fault test program is located in code 3A to 7A within the firmware. Memory controller configuration initializes the memory controller. Test parameter initialization configures the memory parameters according to the memory configuration program. The test items for the memory unit under test include: address line test, data line test, and memory chip test. The test order for the three items is: data line test first, then address line test, and finally memory chip test.

[0056] The data cable test can be performed by writing a first preset value "A" to the Xth test memory cell and a first preset value "B" to the Yth test memory cell, then reading the value of the Xth memory cell. If the value is not "A", it proves that there is a fault in the data cable. Here, the Xth test memory cell can be any one of the test memory cells in the memory, and the Yth test memory cell can be any one of the test memory cells in the memory except for the Xth test memory cell.

[0057] After all data line tests of the storage units under test are completed, if a fault is found, detailed results of the data line test faults for all storage units under test will be output. If all data line tests of the storage units under test pass without errors, address line tests will be performed. Address line testing can be performed by writing address numbers to the corresponding storage units. For example, writing the value "1" to the first storage unit and the value "8" to the eighth storage unit. After writing, the values ​​of the written data storage units are read sequentially using the address numbers. If the read value does not match the storage unit number or address number, the address test is considered a failure. After all address line tests of the storage units under test are completed, if a fault is found, detailed results of the address line test faults for all storage units under test will be output.

[0058] If all address line tests of the memory cells under test pass without error, then the memory chip test is performed. For example, if the memory has a 64-bit width and each memory cell can store 8 bits of data, then the eight consecutive memory cells under test are grouped together. A fifth preset value, "0x55555555555555555," is written to one group. This fifth preset value is in hexadecimal, and each digit in the fifth preset value represents 4 bits. Then, the sixth value of all memory cells under test in this group is read. If the sixth value is "0x5555555555555554," it means that the first bit in the hexadecimal representation is faulty. 0x5 is 0101 in binary, and 0x4 is 0100 in binary. Therefore, the first bit in the binary representation is faulty, meaning the first memory cell in this group, representing the first bit, has failed.

[0059] After all memory chip tests of all storage units under test are completed, if a fault is found, the detailed fault information of the memory chip test faults of all storage units under test will be output.

[0060] If all test items of all storage units to be tested pass the test, then jump to memory operation and continue to execute other boot processes, such as initialization of other devices and startup of the operating system.

[0061] Figure 5 This is a structural diagram of an electronic device provided in an embodiment of the present invention. (Refer to...) Figure 5 The present invention also provides an electronic device, see [link to relevant documentation]. Figure 5The system includes a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the various embodiments of the memory testing described above. Optionally, the memory 502 here may be the aforementioned firmware.

[0062] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the steps of the embodiments of the memory testing method described above.

[0063] This invention also provides a computer program product, including instructions that, when executed by a processor in an electronic device, cause the electronic device to perform the steps of the various embodiments of the memory testing method described above. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between the various embodiments can be referred to interchangeably.

[0064] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0065] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0066] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0067] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0068] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0069] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0070] The present invention has provided a detailed description of a memory testing method and apparatus, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A memory testing method, characterized by, include: Start the firmware; wherein the firmware includes a memory configuration program, a memory hardware fault test program, and a memory running program, and the memory hardware fault test program is located between the memory configuration program and the memory running program; According to the memory configuration program, the memory is configured with parameters, including: the identifier of the first memory cell to be tested, the total number of memory cells to be tested, and the test items for each memory cell. The test items include: address line testing, data line testing, and memory chip testing, at least one of these three. If the number of test items for a memory cell to be tested is greater than or equal to 2, the parameters also include: the test order of each test item for the memory cell to be tested. The test order of each test item for the memory cell to be tested includes: data line testing before address line testing, address line testing before memory chip testing, and data line testing before memory chip testing. After the memory parameters are configured and before the memory is run, the memory hardware fault test program is executed. Starting from the first storage unit to be tested, each of the test items of all the storage units to be tested is tested to test the memory.

2. The memory testing method of claim 1, wherein, Starting with the first storage unit to be tested, the test items for each of all the storage units to be tested are performed, including: Starting with the first memory cell to be tested, test values ​​are written to the memory cell in the order of data line test, address line test, and memory chip test. Then, the stored value of the test cell is read out. If the stored value and the test value are equal, the memory test is passed.

3. The memory testing method of claim 2, wherein, Starting with the first memory cell to be tested, test values ​​are written to the memory cell in the order of data line testing, address line testing, and memory chip testing. Then, the stored value of the test cell is read out. If the stored value and the test value are equal, the memory test passes. This includes: Starting with the first storage unit to be tested, a first preset value is written into one of the storage units to be tested, and then a second value is read out from the storage unit to be tested. If the second value is equal to the first preset value, the data line test of the storage unit to be tested is passed. If the data line test of all the storage units to be tested in the memory passes, starting from the first storage unit to be tested, a third preset value is written to the storage unit to be tested through the address number, and then a fourth value in the storage unit to be tested is read out through the address number. If the fourth value is equal to the third preset value, the address line test of the storage unit to be tested passes. In the case that the address line test of all the to-be-tested storage units in the memory passes, starting from the first to-be-tested storage unit, a preset number of to-be-tested storage units that are continuously distributed are selected as a to-be-tested storage unit group; the total number of bits corresponding to the to-be-tested storage unit group is equal to the bit width of the memory; a fifth preset value is written into all the to-be-tested storage units of the to-be-tested storage unit group, and then a sixth value in all the to-be-tested storage units of the to-be-tested storage unit group is read out; in the case that each bit of the sixth value corresponds to and is equal to each bit of the fifth preset value, it is determined that the memory particle test of all the to-be-tested storage units of the to-be-tested storage unit group passes; the number of bits of the fifth preset value is equal to the bit width of the memory.

4. The memory testing method of claim 3, wherein, The third preset value comprises an address number of the to-be-tested unit.

5. The memory testing method according to any one of claims 1 to 4, wherein Further comprising: Outputting a memory test result.

6. A memory testing apparatus, characterized by comprising: The device comprises: A firmware starting module configured to start a firmware; wherein the firmware is provided with a memory configuration program, a memory hardware fault test program and a memory running program, and the memory hardware fault test program is arranged between the memory configuration program and the memory running program; A configuration module configured to perform parameter configuration on a memory according to the memory configuration program; the parameters comprise an identifier of a first to-be-tested storage unit in the memory, a total number of to-be-tested storage units in the memory, and test items of the to-be-tested storage units; the test items comprise at least one of an address line test, a data line test and a memory particle test; in the case that the number of test items of the to-be-tested storage units is greater than or equal to 2, the parameters further comprise a test order of each test item of the to-be-tested storage units; wherein the test order of each test item of the to-be-tested storage units comprises that the data line test precedes the address line test, the address line test precedes the memory particle test, and the data line test precedes the memory particle test; A test module configured to execute the memory hardware fault test program after the parameter configuration on the memory and before the running of the memory, and to test each test item of all the to-be-tested storage units starting from the first to-be-tested storage unit, so as to test the memory.

7. The memory testing device of claim 6, wherein, The test module comprises: A test unit configured to write a test value into the to-be-tested storage unit in the order of the data line test, the address line test and the memory particle test starting from the first to-be-tested storage unit, and then to read a storage value of the test unit; in the case that the storage value is equal to the test value, the memory test passes.

8. An electronic device, comprising: Comprise: A processor, a firmware and a computer program stored on the firmware and executable on the processor, characterized in that the processor implements the memory test method of any one of claims 1 to 5 when executing the program.

9. A readable storage medium, characterized by, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device can execute the memory test method of any one of claims 1 to 5.

10. A computer program product, comprising instructions which, when executed by a processor in an electronic device, cause the electronic device to perform the memory testing method of any one of claims 1 to 5.

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