An electronic product defect detection method based on multi-dimensional data fusion

Abstract

The present application relates to the technical field of electronic product defect detection, and particularly relates to an electronic product defect detection method based on multi-dimensional data fusion, which comprises selecting a target area circuit board, obtaining a three-dimensional image of the area based on specific circuit board image unit segmentation; analyzing the abnormal area of the image based on defect feature to determine fatal defects or non-fatal defects; obtaining the actual defect density of the circuit board based on the number of non-fatal defect categories and the reference area of the circuit board, determining the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density interval; and determining the electronic product defect grade based on the defect impact value and its corresponding defect impact weight. The present application has the advantages of high detection accuracy, high automation degree and strong adaptability, and has a wide application prospect in the fields of electronic product manufacturing and quality control, can effectively improve product quality and production efficiency, and promote the development of electronic manufacturing industry.

Description

Technical Field

[0001] This invention relates to the field of defect detection technology, and in particular to a method for detecting defects in electronic products based on multidimensional data fusion. Background Technology

[0002] With the widespread use of electronic devices, circuit boards, as the core components of electronic products, directly affect the performance and stability of the devices. Timely detection and repair of circuit board defects are crucial to ensuring the reliability and production efficiency of electronic products. Traditional circuit board defect detection methods mainly rely on manual inspection and automated inspection based on simple image processing, which have certain limitations.

[0003] Chinese Patent Publication No. CN119941726A discloses a method and system for detecting surface defects on circuit boards, comprising the following steps: acquiring images of the circuit board surface, preprocessing the images to generate candidate defect regions, extracting image features using a deep learning model, employing a target detection network and channel attention mechanism to locate and classify potential defect regions, using multi-scale feature fusion technology to optimize the system by combining image features of different scales, predicting the defect evolution trend using temporal dynamic analysis, and dynamically adjusting the defect detection strategy based on the prediction results. The system of this invention adopts a multi-module collaborative approach, possessing high flexibility and adaptability, and can achieve efficient and accurate detection of minute defects on the circuit board surface.

[0004] It is evident that the existing technology has the following problems: when performing circuit board defect detection, the lack of comprehensive detection of component positioning defects, solder joint connection defects, and actual component coordinate deviation values ​​leads to inaccurate detection results and inaccurate differentiation of product defect levels. Summary of the Invention

[0005] Therefore, this invention provides an electronic product defect detection method based on multi-dimensional data fusion to overcome the problems in the prior art where the detection of circuit board defects is inaccurate due to the lack of comprehensive detection of component positioning defects, solder joint connection defects and actual component coordinate deviation values, resulting in inaccurate detection results and inaccurate differentiation of product defect levels.

[0006] To achieve the above objectives, the present invention provides a method for detecting defects in electronic products based on multi-dimensional data fusion, comprising:

[0007] A circuit board within a target area is selected, and a three-dimensional image of the circuit board is acquired based on an image sensor group. The three-dimensional image is then segmented based on the circuit board image unit to obtain a three-dimensional image of the region.

[0008] Compare the three-dimensional image of the region with a standard three-dimensional image to obtain the image anomaly region, and determine whether it is a fatal or non-fatal defect based on the analysis results of the defect characteristics of the image anomaly region;

[0009] Based on the non-fatal defects, determine the non-fatal defect categories and the number of non-fatal defect categories. Based on the number of non-fatal defect categories and the reference area of ​​the circuit board, obtain the actual defect density of the circuit board. Based on the actual defect density and the standard defect density range, determine the defect impact value of the corresponding non-fatal defect category.

[0010] The defect level of electronic products is determined based on the defect impact value and its corresponding defect impact weight.

[0011] The defect characteristics include the actual coordinate deviation of the component, the area ratio of the solder joint, the pin offset, and the actual positional distance between the solder joint and the component. The non-fatal defect categories include component positioning defects and solder joint connection defects.

[0012] Furthermore, the process of segmenting the three-dimensional image based on circuit board image units to obtain a regional three-dimensional image includes:

[0013] Randomly select finished circuit boards from the production line, perform 3D scanning on the finished circuit boards to obtain 3D images of the circuit boards, and perform unit segmentation on the 3D images based on the area of ​​the circuit board image units to obtain regional 3D images of the circuit boards.

[0014] The area of ​​the circuit board image unit is the image area of ​​a single circuit board with product functions.

[0015] Furthermore, the process of determining fatal defects based on the analysis results of the defect features of the abnormal region in the image includes:

[0016] Select any abnormal region in the image and obtain the actual three-dimensional coordinates of the components in the abnormal region. Compare the actual three-dimensional coordinates of the components with the standard three-dimensional coordinates of the components to obtain the actual coordinate deviation value of the components. Based on the comparison result of the actual coordinate deviation value of the components and the component coordinate deviation value threshold, determine the fatal defect.

[0017] Furthermore, the process of analyzing the abnormal regions of the image based on defect features to determine fatal defects also includes:

[0018] Select any abnormal region in the image and obtain the solder joint area ratio and pin offset in the abnormal region to determine the solder joint abnormal value. Determine the fatal defect based on the comparison result between the solder joint abnormal value and the solder joint abnormal threshold, or determine the fatal defect based on the actual position distance between the solder joint and the component.

[0019] Wherein, the solder joint area ratio is the ratio of the solder joint coverage area to the pad area; the pin offset is the offset between the actual coordinates and the standard coordinates of the pin.

[0020] Furthermore, the process of determining fatal defects based on the actual distance between the solder joint and the component includes:

[0021] The actual position distance is obtained based on the actual coordinates of the abnormal solder joint and the actual coordinates of the abnormal component. The fatal defect is determined based on the actual position distance and the standard position distance.

[0022] Wherein, the actual coordinates of the abnormal solder joint are the actual coordinates of the solder joint in the abnormal area of ​​the image, and the actual coordinates of the abnormal component are the actual coordinates of the component in the abnormal area of ​​the image.

[0023] Furthermore, the process of determining the fatal flaw based on the actual location distance and the standard location distance includes:

[0024] If the actual location distance is less than the standard location distance, the defect type is a non-fatal defect.

[0025] If the actual location distance is greater than or equal to the standard location distance, the defect type is a fatal defect.

[0026] Furthermore, the process of obtaining the actual defect density of the circuit board based on the number of non-fatal defect categories and the reference area of ​​the circuit board includes:

[0027] The number of non-fatal defect categories is determined based on the number of component location defects and the number of solder joint connection defects, and the actual defect density is determined based on the number of non-fatal defect categories and the reference area of ​​the circuit board.

[0028] The reference area is the area of ​​a circuit board image unit.

[0029] Furthermore, the process of determining the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density range includes:

[0030] The actual positioning defect density is less than the minimum value of the standard positioning defect density range. The actual positioning defect impact value is determined based on the difference between the minimum value of the standard positioning defect density range and the actual positioning defect density.

[0031] Based on the fact that the actual positioning defect density of the component positioning defect is within the standard positioning defect density range, the first positioning defect influence value is determined as the actual positioning defect influence value.

[0032] The actual positioning defect density is greater than the maximum value of the standard positioning defect density range. The actual positioning defect impact value is determined based on the difference between the actual positioning defect density and the maximum value of the standard positioning defect density range.

[0033] Furthermore, the process of determining the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density range also includes:

[0034] The actual connection defect density is less than the minimum value of the standard connection defect density range. The actual connection defect impact value is determined based on the difference between the minimum value of the standard connection defect density range and the actual connection defect density.

[0035] Based on the fact that the actual connection defect density of the solder joint connection defect is within the standard connection defect density range, the influence value of the second location defect is determined as the influence value of the actual connection defect.

[0036] The actual connection defect density is greater than the maximum value of the standard connection defect density range, and the actual connection defect impact value is determined based on the difference between the actual connection defect density and the maximum value of the standard connection defect density range.

[0037] The impact value of the first positioning defect is greater than the impact value of the second positioning defect.

[0038] Furthermore, the process of determining the defect level of electronic products based on the defect impact value and its corresponding defect impact weight includes:

[0039] The defect level of electronic products is determined based on the actual location defect impact value and the actual location defect impact weight, as well as the actual connection defect impact value and the actual connection defect impact weight.

[0040] The defect impact value includes the actual location defect impact value and the actual connection defect impact value.

[0041] Compared with existing technologies, the advantages of this invention are as follows: In the image acquisition stage, this invention acquires three-dimensional images of the circuit board through an image sensor array. Compared with traditional two-dimensional images, it can completely restore the three-dimensional structure and clearly capture subtle defects such as component misalignment and solder joint abnormalities, avoiding missed detections from a planar perspective. At the same time, it segments the three-dimensional image according to the circuit board image unit, focusing on a single circuit board, reducing interference, and improving the accuracy of defect identification. After locking the abnormal area, it distinguishes between fatal and non-fatal defects, which can quickly eliminate failed products, avoid resource waste, and lay the foundation for subsequent evaluation of non-fatal defects, reducing blind detection. For non-fatal defects, it counts the number of categories, calculates the actual defect density by combining it with the benchmark area, and determines the impact value by comparing it with the standard range, getting rid of the subjective limitations of experience and ensuring consistent evaluation. Moreover, it calculates the impact value separately for component positioning and solder joint connection defects, accurately distinguishing the differences in impact and avoiding misjudgment. It determines three levels of defect levels through impact value and weight, and the production end can handle them according to level: Level 1 is released directly to reduce costs, Level 2 is reworked to reduce scrap, and Level 3 is scrapped in time to avoid ineffective consumption. The graded processing standardizes the process and can also locate production problems through defect level distribution, guiding process improvement. By reducing omissions and errors in the entire process, product quality is guaranteed. Defect data also helps companies optimize their supply chain and processes, reduce defect rates, and enhance market competitiveness.

[0042] Furthermore, this invention randomly selects finished circuit boards from the production line as inspection samples, which can truly reflect the overall production quality and avoid the deviation of results from reality caused by selective sampling. This makes subsequent defect analysis more valuable and provides a reliable basis for judging the quality of the entire production line. Three-dimensional scanning of the samples, compared to traditional two-dimensional scanning, can completely capture the three-dimensional structure of the circuit board, including key details such as the spatial position of components and the three-dimensional shape of solder joints, avoiding information loss from a planar perspective. Multi-angle synchronous scanning can also eliminate blind spots, leaving no room for potential defects to hide, providing a high-quality image foundation for anomaly identification. The three-dimensional image is segmented into individual functional circuit boards, breaking down the overall image of multiple boards into independent images of individual boards, completely eliminating inter-board interference, avoiding misjudgments, and significantly improving the accuracy of single-board inspection. Independent images support parallel inspection one by one or in batches, adapting to different rhythms. If a single board is found to be abnormal, only the image of that board needs to be reviewed, without processing the entire batch, significantly improving efficiency. Using a single board as the image unit ensures consistent processing standards for all samples, guaranteeing comparable test results. Furthermore, individual images can be linked to circuit board production information, enabling rapid tracing of original data when quality issues are subsequently discovered. This facilitates reviewing the causes of defects and provides precise clues for process optimization.

[0043] Furthermore, when analyzing abnormal areas in images, this invention uses a 3D image analysis tool to extract the actual 3D coordinates of components. Compared to 2D, which can only obtain planar information, this tool can completely capture the X, Y, and Z-axis positional states, avoiding the omission of height-direction offset details. Simultaneously, it retrieves the corresponding standard 3D coordinates of the circuit board for comparison, ensuring data consistency and providing an accurate basis for deviation calculation, reducing misjudgments of defects due to data errors. When calculating component coordinate deviations, it comprehensively considers the three-axis deviations to arrive at the overall degree of offset, rather than focusing on only a single direction. This accurately reflects the actual state of the component, avoiding the neglect of the potential impact of multi-directional offset superposition, making risk assessment more comprehensive, and preventing misjudgments of defect severity. When setting deviation thresholds, it does not adopt universal standards but combines component specifications and actual functions to clarify the functional problems that exceeding the threshold may cause, binding the threshold to the application scenario. This makes the classification of fatal and non-fatal defects more meaningful, avoiding judgment results detached from the impact of defects on product performance. Slight offsets are classified as non-fatal defects instead of being directly eliminated, avoiding product waste caused by excessive stringency and providing an accurate classification basis for subsequent defect density calculations and grade assessments. This ensures quality standards while optimizing resource utilization and provides a clear direction for improving production processes such as optimizing assembly precision.

[0044] Furthermore, this invention simultaneously acquires the correlation between solder joint area and conductivity stability and pin offset in its analysis, thus avoiding misjudgment based on a single feature. This prevents the risk of pin misalignment from being overlooked while only considering solder joint coverage, and also avoids overlooking conductivity faults due to insufficient solder joint area while only focusing on pin alignment. This ensures comprehensive coverage of solder joint anomalies and reduces the probability of misjudgment. Solder joint area directly determines conductivity efficiency; insufficient area will lead to signal interruption, thus it carries higher weight. Pin offset only affects stability; slight offset is unlikely to cause immediate failure, thus it carries lower weight. This approach allows outlier calculation to focus on core risks, preventing secondary anomalies from excessively interfering with the overall judgment. Ensure that the scoring matches the actual risk; convert the solder joint ratio to the notch ratio to reflect the difference from the ideal state, and the pin offset to the relative threshold ratio to reflect the distance from the risk threshold, forming a unified scoring index to get rid of the ambiguity of experience-based judgment and make the assessment objective and traceable; combine functional testing when making judgments, and do not mechanically compare abnormal values ​​with thresholds. If the abnormal value is close to the threshold but the conductivity is normal, it will not be misjudged. If the abnormal value does not exceed the standard but the function fluctuates, the risk should be investigated; at the same time, minor abnormal solder joints are classified as non-fatal defects to avoid excessive elimination and waste, and can also guide process improvement based on the type of abnormality: adjust welding parameters for area problems, and optimize assembly accuracy for offset problems.

[0045] Furthermore, this invention extracts the actual coordinates of solder joints and components and calculates the spacing, which can locate the risk of abnormal spacing in key areas such as power supply and charging of mobile phone circuit boards. Combined with power supply stability testing, it can verify whether it causes user-perceptible problems such as screen flickering and sudden shutdown, avoiding the risk of missing the judgment by looking at the data alone, and accurately screening out fatal defects that affect the use. Defects are categorized based on the comparison of spacing with standards: Circuit boards with slightly smaller spacing but normal function, such as those with smaller spacing between charging chip solder joints and resistors but stable power supply, are judged as non-fatal defects rather than being directly rejected. This allows for the retention of repairable circuit boards or those that do not affect core functions, minimizing resource waste. After a comprehensive evaluation of the defect level in conjunction with other defects, minor adjustments can be made before assembly, improving circuit board utilization. If a fatal defect is determined, the assembly process of the same batch of circuit boards can be traced, checking the positioning accuracy of the pick-and-place machine, post-soldering fixing processes, etc.: if the spacing of multiple circuit boards is too large, the pick-and-place machine parameters are adjusted; if the spacing fluctuations are irregular, the fixing process is optimized, addressing the problem at its source, improving production consistency, and ensuring quality. Rejecting fatally defective circuit boards prevents phones with abnormal power supply or easily broken wires from entering the market, preventing impact on user experience or data loss. Non-fatal defective circuit boards, after evaluation and minor adjustments, maintain stable core functions, ensuring user experience and data security, and protecting brand reputation.

[0046] Furthermore, this invention transforms scattered defect information into usable data, which is of significant value; it classifies and statistically analyzes component location defects and solder joint connection defects without omission or duplication, clearly distinguishing defect types and laying the foundation for subsequent cause analysis; it eliminates invalid areas using a benchmark area, using only the effective circuit area to ensure that the density accurately reflects the defect distribution in the functional area, avoiding data distortion; it quantifies the density and adapts it to industry units, making the number of defects intuitive and comparable, avoiding communication biases in qualitative descriptions; at the same time, it provides data support for subsequent defect impact value calculation and level determination, avoiding subjective misjudgments; it can also help the production end locate problems such as assembly or welding processes, optimizing processes in a targeted manner and reducing similar defects.

[0047] Furthermore, this invention calculates the impact value based on three relationships between the actual location defect density and the standard location defect density range: the lower the density, the smaller the impact value; and the higher the density, the larger the impact value. This directly reflects the actual risk of defects to the circuit board, avoiding misjudgment of risk. A preset first impact value and calculation logic ensure consistent judgment criteria for different circuit boards, eliminating subjective experience differences and ensuring comparable and reliable results. The actual location defect impact value directly guides operations: low impact values ​​require no additional processing, those meeting the standard proceed normally, and those too high require targeted fine-tuning, improving production efficiency. By quantifying the impact value, low-risk circuit boards are screened, and high-risk situations are addressed in advance, preventing the accumulation of defects from affecting subsequent assembly and functional stability.

[0048] Furthermore, this invention calculates the impact value based on three relationships between the actual connection defect density and the standard connection defect density range. This directly reflects the actual risk of solder joint connection defects to the circuit board, avoiding misjudgments of potential issues related to conductivity stability. The impact value of the second location defect is lower than that of the first location defect, highlighting that solder joint connection defects are subject to stricter control due to their direct association with conductivity, which aligns with their crucial role in the core performance of the circuit board and reflects a reasonable allocation of risk weights. The level of the impact value directly guides operations: extremely low risk requires no intervention, compliance with standards allows for normal operation, and higher risk requires targeted resoldering and fine-tuning, improving the processing efficiency of the production process. Through precise quantification and control of solder joint connection defects, problems such as poor conductivity are effectively avoided, ensuring the reliable conductivity of the circuit board and solidifying the foundation of the product's core performance.

[0049] Furthermore, this invention assigns weights based on the difference in impact of the two types of defects on core functions, with solder joint defects receiving a higher weight. This ensures that the comprehensive value prioritizes key risks and avoids secondary defects interfering with core quality assessment. The impact values ​​of the two types of defects are integrated into a comprehensive value using a formula, and then assigned to specific grade thresholds. This replaces subjective experience-based judgments, unifying the defect grade assessment standards for different circuit boards and making the results comparable, reducing human error. Different grades correspond to clear handling solutions: Grade 1 allows direct release, Grade 2 requires minor adjustments, and Grade 3 requires rework. The operational direction is clear without additional analysis, significantly improving defect handling efficiency in the production process. Low-risk circuit boards are quickly circulated to avoid resource waste, while high-risk circuit boards are reworked and repaired to ensure quality. This prevents unqualified products from flowing into subsequent stages without slowing down production due to excessive control, achieving a balance between quality and efficiency. Attached Figure Description

[0050] Figure 1 This is a flowchart of the electronic product defect detection method based on multi-dimensional data fusion in this embodiment;

[0051] Figure 2 This is a flowchart illustrating the process of determining fatal defects in this embodiment;

[0052] Figure 3 This is a flowchart illustrating the process of determining the actual impact value of the location defect in this embodiment;

[0053] Figure 4 This is a flowchart illustrating the process of determining the actual impact value of connection defects in this embodiment. Detailed Implementation

[0054] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0055] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0056] It should be noted that in the description of this invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc., which indicate directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. This is only for the convenience of description and is not intended to indicate or imply that the device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0057] Furthermore, it should be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0058] Please see Figure 1 As shown, it is a flowchart of the electronic product defect detection method based on multi-dimensional data fusion in this embodiment;

[0059] This embodiment provides a method for detecting defects in electronic products based on multi-dimensional data fusion, including:

[0060] Step S1: Select the circuit board within the target area, acquire a three-dimensional image of the circuit board based on the image sensor group, and segment the three-dimensional image based on the circuit board image unit to obtain a three-dimensional image of the region.

[0061] Step S2: Compare the three-dimensional image of the region with the standard three-dimensional image to obtain the abnormal image region, and determine whether it is a fatal defect or a non-fatal defect based on the analysis results of the defect characteristics of the abnormal image region.

[0062] Step S3: Determine the non-fatal defect category and the number of non-fatal defect categories based on the non-fatal defects; obtain the actual defect density of the circuit board based on the number of non-fatal defect categories and the reference area of ​​the circuit board; and determine the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density range.

[0063] Step S4: Determine the defect level of the electronic product based on the defect impact value and its corresponding defect impact weight;

[0064] The defect characteristics include the actual coordinate deviation of the component, the area ratio of the solder joint, the pin offset, and the actual positional distance between the solder joint and the component. The non-fatal defect categories include component positioning defects and solder joint connection defects.

[0065] During implementation, in the image acquisition phase, three-dimensional images of the circuit board are acquired through an image sensor array. Compared to traditional two-dimensional images, this method can completely restore the three-dimensional structure, clearly capture subtle defects such as component misalignment and solder joint anomalies, and avoid missed defects from a planar perspective. Simultaneously, the three-dimensional image is segmented into circuit board image units, focusing on individual circuit boards, reducing interference, and improving the accuracy of defect identification. After locating abnormal areas, fatal and non-fatal defects are distinguished, allowing for the rapid removal of failed products, avoiding resource waste, and laying the foundation for subsequent evaluation of non-fatal defects, reducing blind detection. For non-fatal defects, the number of categories is statistically analyzed, the actual defect density is calculated based on a benchmark area, and the impact value is determined by comparing with standard ranges, overcoming subjective limitations of experience and ensuring consistent evaluation. Furthermore, the impact value is calculated separately for component location and solder joint connection defects, accurately distinguishing impact differences and avoiding misjudgments. Three defect levels are determined through impact values ​​and weights, allowing production to handle defects according to their level: Level 1 allows direct release to reduce costs, Level 2 requires targeted rework to reduce scrap, and Level 3 requires timely scrapping to avoid unnecessary consumption. This tiered processing standardizes the process and can also locate production problems through defect level distribution, guiding process improvement. By reducing omissions and errors in the entire process, product quality is guaranteed. Defect data also helps companies optimize their supply chain and processes, reduce defect rates, and enhance market competitiveness.

[0066] Specifically, the process of segmenting the three-dimensional image based on circuit board image units to obtain a regional three-dimensional image includes:

[0067] Randomly select finished circuit boards from the production line, perform 3D scanning on the finished circuit boards to obtain 3D images of the circuit boards, and perform unit segmentation on the 3D images based on the area of ​​the circuit board image units to obtain regional 3D images of the circuit boards.

[0068] The area of ​​the circuit board image unit is the image area of ​​a single circuit board with product functions.

[0069] In this embodiment, a finished circuit board has multiple identical circuit board units;

[0070] In this embodiment, 20 circuit boards of a certain model of smartphone to be inspected are randomly selected from the production line as samples of the target inspection area. An image sensor group consisting of 3 industrial-grade depth cameras with a resolution of 2048×1536 and a scanning accuracy of 0.01mm is used to simultaneously scan from three angles: directly above, above left, and above right of the circuit board to obtain a complete three-dimensional image of each circuit board, which includes three-dimensional information such as component positions and solder joint shapes. Taking a single smartphone circuit board as the circuit board image unit, i.e., 1 image unit corresponds to 1 circuit board to be inspected, the acquired three-dimensional images are segmented to obtain 20 independent three-dimensional images of a single circuit board. Each three-dimensional image of a single circuit board contains only the three-dimensional data of one circuit board, which is convenient for individual inspection.

[0071] In practice, randomly selecting finished circuit boards from the production line as inspection samples accurately reflects the overall production quality, avoiding deviations from reality caused by selective sampling. This makes subsequent defect analysis more valuable and provides a reliable basis for judging the overall product quality. Three-dimensional scanning of the samples, compared to traditional two-dimensional scanning, can completely capture the three-dimensional structure of the circuit board, including key details such as component spatial positions and solder joint morphology, avoiding information loss from a planar perspective. Multi-angle synchronous scanning also eliminates blind spots, leaving no room for hidden potential defects and providing a high-quality image foundation for anomaly identification. Three-dimensional images are segmented into individual functional circuit boards, breaking down the overall image of multiple boards into independent images of each board, completely eliminating inter-board interference, avoiding misjudgments, and significantly improving the accuracy of single-board inspection. Independent images support sequential or batch parallel inspection, adapting to different paces; if a single board is found to be abnormal, only that board's image needs to be reviewed, eliminating the need to process the entire batch, significantly improving efficiency. Using a single board as the image unit ensures consistent processing standards for all samples, guaranteeing comparable test results. Furthermore, individual images can be linked to circuit board production information, enabling rapid tracing of original data when quality issues are subsequently discovered. This facilitates reviewing the causes of defects and provides precise clues for process optimization.

[0072] Specifically, the process of determining fatal defects based on the analysis results of the defect features of the abnormal regions in the image includes:

[0073] Select any abnormal region in the image and obtain the actual three-dimensional coordinates of the components in the abnormal region. Compare the actual three-dimensional coordinates of the components with the standard three-dimensional coordinates of the components to obtain the actual coordinate deviation value of the components. Based on the comparison result of the actual coordinate deviation value of the components and the component coordinate deviation value threshold, determine the fatal defect.

[0074] From the 20 individual circuit board area 3D images segmented in step S1, 3 circuit boards with preliminarily identified image anomaly areas were selected. Among them, the image anomaly area of ​​circuit board A is concentrated around the power management chip. The actual 3D coordinates (X=12.35mm, Y=8.62mm, Z=0.81mm) of a 0402 resistor in this area were extracted using a 3D image analysis tool. At the same time, the standard 3D image of the same circuit board model was retrieved, and the standard 3D coordinates of the resistor of the same specification were obtained (X=12.30mm, Y=8.60mm, Z=0.80mm). Using the spatial coordinate difference formula, the actual coordinate deviation value of the resistor was calculated: X-direction deviation 0.05mm, Y-direction deviation 0.02mm, Z-direction deviation 0.01mm, and the comprehensive deviation value is 0.05477, approximately equal to 0.06mm. The calculation process is existing technology and will not be elaborated here.

[0075] In this embodiment, the component coordinate deviation threshold is set to 0.1mm. For a 0402 specification resistor, if it exceeds this threshold, it may cause abnormal voltage division in the circuit and affect the power management function. Since the overall deviation value of the resistor in circuit board A is 0.06mm < 0.1mm, the defect corresponding to the abnormal area is determined to be a non-fatal defect.

[0076] During implementation, when analyzing abnormal areas in images, 3D image analysis tools are used to extract the actual 3D coordinates of components. Compared to 2D, which only provides planar information, this method can completely capture the X, Y, and Z-axis positional states, avoiding the omission of details related to height offsets. Simultaneously, the corresponding standard 3D coordinates of the circuit board are retrieved for comparison to ensure data consistency, providing an accurate basis for deviation calculation and reducing misjudgments of defects due to data errors. When calculating component coordinate deviations, the overall offset degree is derived by comprehensively considering the three-axis deviations, rather than focusing on a single direction. This accurately reflects the actual state of the component, avoiding the neglect of the potential impact of multi-directional offset superposition, making risk assessment more comprehensive, and preventing misjudgments of defect severity. When setting deviation thresholds, a universal standard is not adopted. Instead, the component specifications and actual functions are considered to clarify the functional problems that exceeding the threshold may cause. This binds the threshold to the application scenario, making the classification of fatal and non-fatal defects more meaningful and preventing judgments from being divorced from the impact of defects on product performance. Classifying minor deviations as non-fatal defects, rather than eliminating them outright, avoids product waste caused by excessive stringency, provides an accurate classification basis for subsequent defect density calculations and grade assessments, ensures the bottom line of quality while optimizing resource utilization, and also provides a clear direction for improving production processes such as optimizing assembly precision.

[0077] Specifically, the process of analyzing the abnormal regions of the image based on defect features to determine fatal defects also includes:

[0078] Select any abnormal region in the image and obtain the solder joint area ratio and pin offset in the abnormal region to determine the solder joint abnormal value. Determine the fatal defect based on the comparison result between the solder joint abnormal value and the solder joint abnormal threshold, or determine the fatal defect based on the actual position distance between the solder joint and the component.

[0079] Wherein, the solder joint area ratio is the ratio of the solder joint coverage area to the pad area; the pin offset is the offset between the actual coordinates and the standard coordinates of the pin.

[0080] From the abnormal area in the circuit board image, pinpoint BGA solder joint #1 of the power management chip was located. The actual coverage area of ​​this BGA solder joint was measured to be 0.42 mm², and the standard area of ​​the BGA pad for this model was retrieved to be 0.6 mm². The solder joint area ratio = (actual solder joint coverage area / pad area) × 100% = (0.42 / 0.6) × 100% = 70%; where the standard area of ​​the pad is determined based on the power management chip's datasheet.

[0081] The BGA solder joint corresponds to the power supply pin 1 of the chip. The actual three-dimensional coordinates of the pin (X=5.32mm, Y=7.85mm) and the standard coordinates of the pin (X=5.30mm, Y=7.80mm) are extracted. The pin offset is calculated to be approximately 0.053mm using the two-dimensional Euclidean distance formula.

[0082] In this embodiment, the weight of the solder joint area is set to 0.6, and the weight of the pin offset is set to 0.4. Since the solder joint coverage area directly affects conductivity stability, it has a higher weight. The solder joint anomaly value is set to a maximum score of 100 points; a higher score indicates a more severe anomaly.

[0083] The weld point accounts for 70% of the area, and the corresponding score is (100%-70%)×100×0.6=30×0.6=18 points;

[0084] The solder joint area ratio is an indicator of coverage adequacy. The higher the solder joint area ratio, the closer it is to 100%, the more stable the conductive contact, the lower the degree of abnormality, and the risk has an inverse linear relationship with the solder joint area ratio.

[0085] The difference value can be used to directly quantify the proportion of missing areas covered by the 100% area ratio. For example, if 70% of the area ratio corresponds to 30% of the missing areas, the missing area will directly lead to a decrease in conductivity stability. The larger the difference value, the more severe the anomaly.

[0086] The pin offset is 0.053mm. In this embodiment, the pin offset threshold is set to 0.08mm, and the corresponding score is (pin offset / pin offset threshold) × 100 × 0.4 = (0.053 / 0.08) × 100 × 0.4 = 26.5 points. The pin offset threshold is determined based on historical data. During the R&D phase, power supply tests are conducted on samples with different offsets: if the offset is 0.08mm, the pin and the pad can still make stable contact, and the power supply transmission is normal; if the offset exceeds 0.08mm, such as 0.1mm, the contact resistance increases significantly, and power supply fluctuations occur. Therefore, 0.08mm is set as the threshold, and exceeding it poses a risk of functional failure.

[0087] Pin offset is an indicator of critical risk. Risk is positively correlated with pin offset. Since the pin offset threshold is clearly defined as 0.08mm, the risk is low when the pin offset threshold is not exceeded, and the risk increases sharply when the pin offset threshold is approached or exceeded.

[0088] The purpose of the ratio is to quantify the proportion of the current pin offset to the safety threshold. This prevents offsets that do not exceed the pin offset threshold from receiving excessively high scores. For example, an offset of 0.053mm is only 66.25% of the threshold, corresponding to a score of 26.5 points, which is a small offset. However, if the pin offset is close to 0.08mm, such as 0.07mm, the offset will be 87.5% of the threshold, and the score will accumulate rapidly, leading to the test conclusion that exceeding the pin offset threshold poses a risk of functional failure.

[0089] The final solder joint anomaly score was 18 + 26.5 = 44.5 points. In this embodiment, the solder joint anomaly threshold was set to 80 points. Since the solder joint anomaly score of 44.5 points is less than 80 points, and the power transmission test showed that the solder joint was conductive, it was determined to be a non-fatal defect. The solder joint anomaly threshold was determined based on historical data. For samples with anomaly scores close to 80 points, such as 75-85 points, an aging test was conducted. Samples with anomaly scores above 80 points worked for 1000 hours in a high temperature and high humidity environment. After aging, 80% of the samples had solder joint cracks and lost their conductive function. Samples with anomaly scores below 80 points remained functionally stable after aging.

[0090] During implementation, the analysis simultaneously acquires data on the impact of solder joint area ratio on conductivity stability and pin offset on connection reliability. This avoids misjudgments based on a single feature, preventing both overlooking the risk of loose pins due to insufficient solder joint area while only considering solder joint coverage and neglecting conductivity faults due to insufficient solder joint area while focusing solely on pin alignment. This ensures comprehensive coverage of solder joint anomalies and reduces the probability of misjudgment. Solder joint area directly determines conductivity efficiency; insufficient area leads to signal interruption and thus carries higher weight. Pin offset only affects stability; slight offset is unlikely to cause immediate failure and carries lower weight. This approach allows outlier calculations to focus on core risks, preventing secondary anomalies from excessively interfering with overall judgment and ensuring that the score matches the actual risk. Solder joint ratio is converted to notch ratio to reflect the difference from the ideal state, and pin offset is converted to a relative threshold ratio to reflect the distance from the risk threshold, forming a unified scoring index that eliminates the ambiguity of experience-based judgments and makes the assessment objective and traceable. Judgment is combined with functional testing; outliers are not mechanically compared to thresholds. If an outlier is close to the threshold but conductivity is normal, it is not misjudged. If an outlier does not exceed the standard but functionality fluctuates, risk is investigated. At the same time, minor abnormal weld points are classified as non-fatal defects to avoid excessive waste and to guide process improvement based on the type of abnormality: adjusting welding parameters for area problems and optimizing assembly accuracy for offset problems.

[0091] Specifically, the process of determining fatal defects based on the actual distance between the solder joint and the component includes:

[0092] The actual position distance is obtained based on the actual coordinates of the abnormal solder joint and the actual coordinates of the abnormal component. The fatal defect is determined based on the actual position distance and the standard position distance.

[0093] Wherein, the actual coordinates of the abnormal solder joint are the actual coordinates of the solder joint in the abnormal area of ​​the image, and the actual coordinates of the abnormal component are the actual coordinates of the component in the abnormal area of ​​the image.

[0094] Please see Figure 2 As shown, it is a flowchart of the process of determining fatal defects in the electronic product defect detection method based on multi-dimensional data fusion in this embodiment.

[0095] Specifically, the process of determining a fatal flaw based on the actual location distance and the standard location distance includes:

[0096] If the actual location distance is less than the standard location distance, the defect type is a non-fatal defect.

[0097] If the actual location distance is greater than or equal to the standard location distance, the defect type is a fatal defect.

[0098] From the 3D image of the single electronic circuit board area segmented in step S1, an abnormal image area was identified, consisting of the No. 2 power supply solder joint of the safety control chip and the surrounding 0603 specification protection resistor. Preliminary observation revealed an abnormal spacing between the resistor and the solder joint. Using a high-precision 3D image measurement tool with an accuracy of 0.001mm, two types of coordinates were extracted. Because the assembly of electronic components has extremely high requirements for horizontal position, only the XY coordinates are needed to meet the calculation requirements.

[0099] Actual coordinates of the abnormal solder joint: The center coordinates of the No. 2 power supply solder joint are X=35.24mm and Y=28.63mm;

[0100] Actual coordinates of the abnormal component: The center coordinates of the protective resistor are X=35.58mm and Y=28.63mm;

[0101] The actual distance between the solder joint and the resistor was calculated to be 0.34 mm using the two-dimensional Euclidean distance formula.

[0102] Based on historical data, the standard distance between the No. 2 power supply solder joint and the protective resistor is determined to be 0.30mm.

[0103] The standard position distance is 0.30mm, and the actual position distance is 0.34mm. Since the actual position distance is greater than or equal to the standard position distance, the defect type is a fatal defect.

[0104] During implementation, a power supply stability test was conducted on the mobile phone circuit board. It was discovered that due to excessive spacing between the solder joints and resistors, the connecting wires were overstretched, causing the chip's power supply voltage to fluctuate by ±12%, far exceeding the ±5% allowable limit for mobile phone electronic components. This fluctuation directly leads to practical problems: in daily use, it may cause sudden screen flickering and frequent app crashes. If the fluctuation intensifies and causes wire breakage, it can also cause the phone to suddenly shut down and become unrestartable. Furthermore, abnormal power supply could damage core chips on the circuit board, such as the processor and memory chips, resulting in data loss. The final determination was that the defect corresponding to the abnormal image area was a fatal defect, and the circuit board needed to be immediately removed from the production line. Simultaneously, it is necessary to trace the component assembly process of the same batch of mobile phone circuit boards, focusing on checking the coordinate positioning accuracy of the pick-and-place machine and whether there are any deviations in the component fixing process after soldering, to avoid similar spacing abnormalities in subsequent circuit boards and ensure the stability and data security of the phones after they leave the factory.

[0105] If the actual distance between the charging chip's No. 1 power supply solder joint and the surrounding protection resistor on another circuit board of the same model is 0.28mm, which is less than the designed standard distance of 0.30mm:

[0106] The actual position distance meets the condition that the actual position distance is less than the standard position distance, which initially meets the criteria for non-fatal defects. A power supply stability test was conducted on this circuit board, and the results showed that the power supply voltage fluctuation of the charging chip was only ±3%, far below the ±5% upper limit allowed for mobile phone electronic components. Simultaneously, disassembly and observation revealed that the wires connecting the solder joints and resistors showed no compression deformation or wrinkling accumulation. Even after simulating scenarios such as frequent daily charging of a mobile phone and a drop from a height of 1.5 meters onto a table, the wires remained intact, indicating no risk of breakage or poor contact over long-term use. The defect corresponding to the abnormal area in the image is a non-fatal defect, and the circuit board does not need to be removed. It can proceed to the subsequent non-fatal defect density calculation stage. Combining the quantity and type of other non-fatal defects on the circuit board, such as slight component positioning misalignment and insufficient coverage of small solder joints, a comprehensive assessment of the final defect level of this mobile phone circuit board will be made to decide whether to release it directly for assembly or to make minor adjustments before putting it into production.

[0107] During implementation, extracting the actual coordinates of solder joints and components and calculating the spacing allows for the identification of abnormal spacing risks in critical areas of the mobile phone circuit board, such as power supply and charging. Combined with power supply stability testing, this verifies whether user-perceptible issues like screen flickering or sudden shutdowns occur, avoiding missed risks based solely on data and accurately identifying critical defects affecting usability. Defects are differentiated based on spacing comparison rules: circuit boards with slightly smaller spacing but normal function, such as those with smaller spacing between solder joints and resistors in the charging chip but stable power supply, are judged as non-critical defects rather than being directly rejected. This maximizes the retention of repairable circuit boards or those that do not affect core functions, reducing resource waste. After a comprehensive evaluation of other defects, minor adjustments can be made before assembly, improving circuit board utilization. If a critical defect is determined, the assembly process of the same batch of circuit boards can be traced to investigate the positioning accuracy of the pick-and-place machine and the post-soldering fixing process: if the spacing of multiple circuit boards is too large, the pick-and-place machine parameters are adjusted; if the spacing fluctuations are irregular, the fixing process is optimized, addressing the problem at its source, improving production consistency, and ensuring quality. Removing critically defective circuit boards prevents phones with abnormal power supply or easily broken wires from entering the market, thus avoiding impact on user experience or data loss. Non-critically defective circuit boards, after evaluation and fine-tuning, maintain stable core functions, ensuring user experience and data security, and protecting brand reputation.

[0108] Specifically, the process of obtaining the actual defect density of the circuit board based on the number of non-fatal defect categories and the reference area of ​​the circuit board includes:

[0109] The number of non-fatal defect categories is determined based on the number of component location defects and the number of solder joint connection defects, and the actual defect density is determined based on the number of non-fatal defect categories and the reference area of ​​the circuit board.

[0110] The reference area is the area of ​​a circuit board image unit.

[0111] The three-dimensional images of area E of circuit board and the previous defect judgment records were sorted out, and the number of defects were counted separately according to two categories: component location defects and solder joint connection defects, to ensure that there were no omissions and no duplicate classifications.

[0112] Component positioning defect count: Five components were identified with positional deviations that did not reach the fatal threshold. These included two 0402 surface mount resistors with coordinate deviations of 0.06mm and 0.07mm, both less than the fatal threshold of 0.1mm; two 0603 filter capacitors with coordinate deviations of 0.05mm and 0.08mm; and one miniature Bluetooth chip with a coordinate deviation of 0.09mm. All of these met the criteria for component positioning defects, resulting in a total of five component positioning defects.

[0113] Solder joint connection defect count: For cases of abnormal solder joints that did not reach the fatal threshold, a total of 3 were identified, including 1 BGA chip solder joint with an area of ​​78%, which is higher than the fatal threshold of 70%; 1 charging interface solder joint with a pin offset of 0.05mm, which is less than the fatal threshold of 0.08mm; and 1 RF antenna solder joint with an area of ​​82% and no pin offset. All of these are consistent with solder joint connection defects, so the number of solder joint connection defects is 3.

[0114] Add the number of the two types of defects together, that is, the total number of non-fatal defects = the number of component positioning defects + the number of solder joint connection defects = 8;

[0115] The reference area is the unit area of ​​the circuit board image. In this embodiment, the unit of the circuit board image is a single 5G smartphone circuit board. Therefore, the effective circuit area of ​​the circuit board is used as the reference area.

[0116] The shape parameters of circuit board E are read using a 3D image measurement tool: the overall length of the circuit board is 150mm and the width is 75mm, but there are mounting holes, positioning slots and blank non-circuit areas without components on the edge. The invalid areas need to be removed before calculating the effective area.

[0117] After precise measurement, the actual area of ​​the effective circuit area of ​​circuit board E where components and solder joints are laid out is 10500mm², which is equivalent to 105cm². This area is the reference area of ​​the circuit board.

[0118] The actual defect density is calculated as: total number of non-fatal defect categories / baseline area, with unit conversion to conform to common industry terminology.

[0119] Calculated per defect / mm²: Actual defect density = 8 defects / 10500mm² ≈ 0.00076 defects / mm²;

[0120] Based on the industry standard conversion of 1cm² = 100mm², the actual defect density is 0.00076 defects / mm² × 100 = 0.076 defects / cm².

[0121] In implementation, the transformation of scattered defect information into usable data is of significant value. Categorizing and statistically analyzing component location defects and solder joint defects ensures no omissions or duplications, clearly distinguishing defect types and laying the foundation for subsequent cause analysis. Eliminating invalid areas using a benchmark area, and using only the effective circuit area, ensures that density accurately reflects the defect distribution in functional areas, avoiding data distortion. Quantifying density and adapting it to industry units makes defect quantity intuitive and comparable, avoiding communication biases in qualitative descriptions. Simultaneously, it provides data support for subsequent defect impact value calculations and grade determinations, preventing subjective misjudgments. Furthermore, it helps production locate problems such as in assembly or welding processes, enabling targeted process optimization and reducing similar defects.

[0122] Please see Figure 3 The diagram shown is a flowchart illustrating the process of determining the actual location defect impact value in the electronic product defect detection method based on multi-dimensional data fusion in this embodiment.

[0123] The process of determining the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density range includes:

[0124] The actual positioning defect density is less than the minimum value of the standard positioning defect density range. The actual positioning defect impact value is determined based on the difference between the minimum value of the standard positioning defect density range and the actual positioning defect density.

[0125] Based on the fact that the actual positioning defect density of the component positioning defect is within the standard positioning defect density range, the first positioning defect influence value is determined as the actual positioning defect influence value.

[0126] The actual positioning defect density is greater than the maximum value of the standard positioning defect density range. The actual positioning defect impact value is determined based on the difference between the actual positioning defect density and the maximum value of the standard positioning defect density range.

[0127] In this embodiment, the standard positioning defect density range is set to 0.02-0.05 defects / cm², the first positioning defect influence value is set to 5 points, and the full score is 10 points. The lower the score, the smaller the influence, which means that the influence of defects within the range is controllable. The positioning influence value calculation coefficient is set to 30.

[0128] There are 2 component positioning defects, with a reference area of ​​120 cm². The actual positioning defect density is 2 / 120, which is approximately 0.017 defects / cm², less than the minimum value of 0.02 defects / cm².

[0129] The difference between the minimum standard location defect density range of 0.02 and the actual location defect density is 0.003 defects / cm². The actual location defect impact value is 5 - (0.003 × 30) = 4.91 points. The actual location defect impact value is slightly lower than the first location defect impact value, which means that the defect density is extremely low and has no substantial impact on circuit board assembly.

[0130] There are 5 component positioning defects with a base area of ​​120cm². The actual density is 5 / 120≈0.042 defects / cm², which is within the range of 0.02-0.05. The first positioning defect impact value is taken, that is, the actual positioning defect impact value is 5 points. The actual positioning defect impact value meets the standard. The defect has no significant interference with the functional stability of the circuit board and can be processed normally.

[0131] There are 8 component positioning defects with a reference area of ​​120cm². The actual positioning defect density is 8 / 120≈0.067 defects / cm², which is greater than the maximum value of the standard positioning defect density range of 0.05. The difference between the actual positioning defect density and the maximum value of the standard positioning defect density range is 0.017 defects / cm². The actual positioning defect impact value is 5 + (0.017 × 30) = 5.51 points. This indicates that the defect density is too high, and the offset component needs to be fine-tuned to avoid assembly interference.

[0132] In implementation, the impact value is calculated based on three relationships between the actual location defect density and the standard location defect density range: the lower the density, the smaller the impact value; the higher the density, the larger the impact value. This directly reflects the actual risk of defects to the circuit board, avoiding misjudgment of risk. A preset first impact value and calculation logic ensure consistent judgment criteria across different circuit boards, eliminating subjective experience differences and ensuring comparable and reliable results. The actual location defect impact value directly guides operations: low impact values ​​require no additional processing; values ​​meeting standards allow for normal flow; and high values ​​require targeted fine-tuning to improve production efficiency. By quantifying the impact value, low-risk circuit boards are screened, and high-risk situations are addressed in advance, preventing defect accumulation from affecting subsequent assembly and functional stability.

[0133] Please see Figure 4 As shown, it is a flowchart of the process of determining the actual connection defect impact value in the electronic product defect detection method based on multi-dimensional data fusion in this embodiment.

[0134] Specifically, the process of determining the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density range further includes:

[0135] The actual connection defect density is less than the minimum value of the standard connection defect density range. The actual connection defect impact value is determined based on the difference between the minimum value of the standard connection defect density range and the actual connection defect density.

[0136] Based on the fact that the actual connection defect density of the solder joint connection defect is within the standard connection defect density range, the influence value of the second location defect is determined as the influence value of the actual connection defect.

[0137] The actual connection defect density is greater than the maximum value of the standard connection defect density range, and the actual connection defect impact value is determined based on the difference between the actual connection defect density and the maximum value of the standard connection defect density range.

[0138] The impact value of the first positioning defect is greater than the impact value of the second positioning defect.

[0139] In this embodiment, the standard connection defect density range is set to 0.01-0.03 defects / cm², indicating a higher risk of solder joint connection defects and a stricter standard range. The second location defect impact value is set to 3 points out of 10, which is lower than the first location defect impact value of 5 points, meaning that the impact of solder joint connection defects is smaller when they are within the standard connection defect density range. The connection impact value calculation coefficient is set to 40 points, indicating that solder joint connection defects have a more direct impact on functionality, and the coefficient is higher than that of location defects.

[0140] One solder joint connection defect, such as a slight under-coverage of a BGA solder joint with a reference area of ​​120cm², has an actual connection defect density of 1 / 120 ≈ 0.008 defects / cm², which is less than the minimum value of the standard connection defect density range of 0.01. The difference between the minimum value of the standard connection defect density range and the actual connection defect density is 0.002 defects / cm². The actual connection defect impact value is 3 - (0.002 × 40) = 2.92 points, indicating that the solder joint connection defect is extremely rare, has no impact on conductivity stability, and requires no treatment.

[0141] There are 3 solder joint connection defects with a base area of ​​120cm². The actual connection defect density is 3 / 120 = 0.025 defects / cm², which is within the standard connection defect density range of 0.01-0.03. The second positioning defect influence value is directly taken, which is the actual connection defect influence value. The influence value meets the standard, the solder joint connection stability meets the standard, and the circuit board can proceed to the next process normally.

[0142] There are 5 weld joint defects with a base area of ​​120cm². The actual defect density is 5 / 120≈0.042 defects / cm², which is greater than the maximum value of the standard defect density range of 0.03. The difference between the actual defect density and the maximum value of the standard defect density range is 0.012 defects / cm². The actual defect impact value is 3 + (0.012 × 40) = 3.48 points, indicating that the weld joint defect density is too high. High-risk weld joints need to be repaired and fine-tuned to avoid poor conductivity.

[0143] Because the impact value of the first location defect is greater than that of the second location defect, it reflects the difference in risk weight between the two types of defects. Under the same density, the basic impact value of solder joint connection defects is lower, which means it is more stringent. Since it is directly related to the conductive function, it needs to be more precisely controlled to ensure the stability of the core performance of the circuit board.

[0144] In implementation, the impact value is calculated based on three relationships between the actual connection defect density and the standard connection defect density range. This directly reflects the actual risk of solder joint connection defects to the circuit board, avoiding misjudgments of potential conductive stability issues. The impact value of the second-position defect is lower than that of the first-position defect, highlighting the stricter control of solder joint connection defects due to their direct association with conductivity. This aligns with their crucial role in the core performance of the circuit board and reflects a reasonable allocation of risk weights. The impact value directly guides operations: extremely low risk requires no intervention, compliance with standards allows for normal processing, and higher risk requires targeted resoldering and fine-tuning, improving processing efficiency in the production process. Through precise quantification and control of solder joint connection defects, problems such as poor conductivity are effectively avoided, ensuring reliable conductivity of the circuit board and solidifying the foundation of the product's core performance.

[0145] Specifically, the process of determining the defect level of electronic products based on the defect impact value and its corresponding defect impact weight includes:

[0146] The defect level of electronic products is determined based on the actual location defect impact value and the actual location defect impact weight, as well as the actual connection defect impact value and the actual connection defect impact weight.

[0147] The defect impact value includes the actual location defect impact value and the actual connection defect impact value.

[0148] In this embodiment, the influence weight of actual positioning defects is set to 0.4. Component positioning offset only affects assembly and has little interference with core functions. The influence weight of actual connection defects is set to 0.6. Solder joint connection directly determines conductivity stability and is a key guarantee for the core functions of the circuit board, so it has a higher weight.

[0149] The threshold range of the comprehensive defect impact value is preset, and the corresponding relationship between levels is clearly defined. The smaller the value, the higher the level and the lower the defect risk.

[0150] First-level defect, with a comprehensive defect impact value of <4, indicates extremely low defect risk and can be directly released for assembly.

[0151] Second defect level, 4≤Comprehensive defect impact value≤5, medium defect risk, requires slight adjustments before assembly;

[0152] The third defect level, with a comprehensive defect impact value > 5, indicates a high defect risk and requires rework and repair followed by re-inspection.

[0153] Overall defect impact value = (actual location defect impact value × location defect impact weight) + (actual connection defect impact value × connection defect impact weight);

[0154] Scenario 1: The actual impact value of the positioning defect is 4.91 points; the actual impact value of the connection defect is 2.92 points.

[0155] The overall defect impact value is approximately 3.72 points (4.91 × 0.4) + (2.92 × 0.6). Since 3.71 is less than 4, it meets the first defect level standard. The circuit board defect risk is extremely low, and no adjustments are needed. It can directly proceed to the smartwatch assembly stage.

[0156] Scenario 2: The actual impact value of the positioning defect is 5 points; the actual impact value of the connection defect is 3.5 points.

[0157] The overall defect impact value = (6 × 0.4) + (4.5 × 0.6) = 2 + 2.1 = 4.1, which meets the second defect level standard. The circuit board has a slight defect risk. Only 1-2 components with large offset need to be mechanically fine-tuned. No rework is required. After adjustment, it can enter the assembly stage.

[0158] Scenario 3: The actual impact value of the location defect is 6 points, and the actual impact value of the connection defect is 4.5 points.

[0159] The overall defect impact value is (6×0.4) + (4.5×0.6) = 2.4 + 2.7 = 5.1 points, which meets the third defect level standard. The circuit board has a high defect risk and needs to be reworked. High-risk solder joints need to be re-soldered, and severely misaligned components need to be reassembled. After the repair, the overall defect impact value needs to be tested again. Only after it meets the standard can it proceed to the next stage.

[0160] In implementation, weights are allocated based on the difference in impact of the two types of defects on core functions, with solder joint defects receiving a higher weight. This ensures that the overall value prioritizes key risks and prevents secondary defects from interfering with core quality assessments. A formula integrates the impact values ​​of the two types of defects into a comprehensive value, which is then assigned a clear grade threshold. This replaces subjective experience-based judgments, unifying the defect grade assessment standards across different circuit boards and ensuring comparable results, thus reducing human error. Clear handling plans correspond to different grades: Grade 1 allows direct release, Grade 2 requires minor adjustments, and Grade 3 necessitates rework. The operational direction is clear without additional analysis, significantly improving defect handling efficiency in the production process. Low-risk circuit boards are swiftly circulated to avoid resource waste, while high-risk circuit boards are reworked and repaired to ensure quality. This approach prevents defective products from flowing into subsequent stages without slowing down production due to excessive control, achieving a balance between quality and efficiency.

[0161] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

[0162] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for detecting defects in electronic products based on multi-dimensional data fusion, characterized in that, include: The process of selecting a circuit board within a target area, acquiring a 3D image of the circuit board based on an image sensor array, and segmenting the 3D image based on circuit board image units to obtain a 3D image of the region includes: Randomly select finished circuit boards from the production line, perform 3D scanning on the finished circuit boards to obtain 3D images of the circuit boards, and perform unit segmentation on the 3D images based on the area of ​​the circuit board image units to obtain regional 3D images of the circuit boards. Wherein, the area of ​​the circuit board image unit is the image area of ​​a single circuit board with product functions; Compare the three-dimensional image of the region with a standard three-dimensional image to obtain the image anomaly region, and determine whether it is a fatal or non-fatal defect based on the analysis results of the defect characteristics of the image anomaly region; The process of determining the non-fatal defect category and the number of non-fatal defect categories based on the aforementioned non-fatal defects, and obtaining the actual defect density of the circuit board based on the number of non-fatal defect categories and the reference area of ​​the circuit board, includes: The number of non-fatal defect categories is determined based on the number of component location defects and the number of solder joint connection defects, and the actual defect density is determined based on the number of non-fatal defect categories and the reference area of ​​the circuit board. Wherein, the reference area is the area of ​​a circuit board image unit; The process of determining the defect impact value of the corresponding non-fatal defect category based on the actual defect density and the standard defect density range includes: The actual positioning defect density is less than the minimum value of the standard positioning defect density range. The actual positioning defect impact value is determined based on the difference between the minimum value of the standard positioning defect density range and the actual positioning defect density. Based on the fact that the actual positioning defect density of the component positioning defect is within the standard positioning defect density range, the first positioning defect influence value is determined as the actual positioning defect influence value. The actual positioning defect density is greater than the maximum value of the standard positioning defect density range. The actual positioning defect impact value is determined based on the difference between the actual positioning defect density and the maximum value of the standard positioning defect density range. The actual connection defect density is less than the minimum value of the standard connection defect density range. The actual connection defect impact value is determined based on the difference between the minimum value of the standard connection defect density range and the actual connection defect density. Based on the fact that the actual connection defect density of the solder joint connection defect is within the standard connection defect density range, the influence value of the second location defect is determined as the influence value of the actual connection defect. The actual connection defect density is greater than the maximum value of the standard connection defect density range, and the actual connection defect impact value is determined based on the difference between the actual connection defect density and the maximum value of the standard connection defect density range. Wherein, the impact value of the first positioning defect is greater than the impact value of the second positioning defect; The process of determining the defect level of electronic products based on the defect impact value and its corresponding defect impact weight includes: The defect level of electronic products is determined based on the actual location defect impact value and the actual location defect impact weight, as well as the actual connection defect impact value and the actual connection defect impact weight. The defect impact value includes the actual location defect impact value and the actual connection defect impact value; The defect features include the actual coordinate deviation of the component, the area ratio of the solder joint, the pin offset, and the actual positional distance between the solder joint and the component. The non-fatal defect categories include component positioning defects and solder joint connection defects.

2. The electronic product defect detection method based on multi-dimensional data fusion according to claim 1, characterized in that, The process of determining fatal defects based on the analysis results of the defect features of the abnormal regions in the image includes: Select any abnormal region in the image and obtain the actual three-dimensional coordinates of the components in the abnormal region. Compare the actual three-dimensional coordinates of the components with the standard three-dimensional coordinates of the components to obtain the actual coordinate deviation value of the components. Based on the comparison result of the actual coordinate deviation value of the components and the component coordinate deviation value threshold, determine the fatal defect.

3. The electronic product defect detection method based on multi-dimensional data fusion according to claim 2, characterized in that, The process of analyzing the abnormal regions of the image based on defect features to determine fatal defects also includes: Select any abnormal region in the image and obtain the solder joint area ratio and pin offset in the abnormal region to determine the solder joint abnormal value. Determine the fatal defect based on the comparison result between the solder joint abnormal value and the solder joint abnormal threshold, or determine the fatal defect based on the actual position distance between the solder joint and the component. Wherein, the solder joint area ratio is the ratio of the solder joint coverage area to the pad area; the pin offset is the offset between the actual coordinates and the standard coordinates of the pin.

4. The electronic product defect detection method based on multi-dimensional data fusion according to claim 3, characterized in that, The process of determining critical defects based on the actual distance between the solder joint and the component includes: The actual position distance is obtained based on the actual coordinates of the abnormal solder joint and the actual coordinates of the abnormal component. The fatal defect is determined based on the actual position distance and the standard position distance. Wherein, the actual coordinates of the abnormal solder joint are the actual coordinates of the solder joint in the abnormal area of ​​the image, and the actual coordinates of the abnormal component are the actual coordinates of the component in the abnormal area of ​​the image.

5. The electronic product defect detection method based on multi-dimensional data fusion according to claim 4, characterized in that, The process of determining fatal defects based on the actual location distance and the standard location distance includes: If the actual location distance is less than the standard location distance, the defect type is a non-fatal defect. If the actual location distance is greater than or equal to the standard location distance, the defect type is a fatal defect.

Images