Adjusting process method of grid work function of HKMG
By forming a lanthanum oxide layer in a high dielectric constant layer and annealing it, combined with adjusting the thickness of the TiN layer, the problem of unstable device performance caused by insufficient TiN film thickness was solved, and the threshold voltage was precisely adjusted and the device performance was improved.
Patent Information
- Application Number
- CN202511784122.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-02-27
AI Technical Summary
In the existing HKMG process, the small TiN film thickness leads to unstable device performance, making it difficult to balance the threshold voltages (VTSAT) at each stage to achieve the target value. Furthermore, the complex multiple photolithography/etching processes make it difficult to effectively adjust the gate work function.
A lanthanum oxide layer is formed in a high dielectric constant layer and annealed to advance the process, forming an electric dipole to reduce the gate work function. At the same time, combined with the adjustment of the TiN layer thickness, TiN layers of different thicknesses with different work functions are formed through multiple cycles of the process to adjust the gate work function of each region.
The threshold voltage adjustment process window has been expanded to ensure that the threshold voltage matches the target value to the greatest extent, thereby improving the stability and uniformity of device performance.
Smart Images
Figure CN121586283A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for semiconductor integrated circuits, and more particularly to a process method for adjusting the gate work function of a high dielectric constant (HK) metal gate (MG). Background Technology
[0002] As process nodes shrink and operating voltages decrease, the gate oxide thickness needs to be continuously reduced to improve gate capacitance and enhance channel control. This leads to a sharp increase in gate leakage current. In some processes, traditional SiO2 dielectric layers and doping-controlled threshold voltage techniques are no longer sufficient. Instead, the HKMG process technology, with its high-k HfO2, significantly suppresses dielectric tunneling and improves gate leakage current, while also effectively controlling the threshold voltage (VTSAT) of the metal gate.
[0003] In current HKMG processes, the most effective way to adjust VTSAT is by changing the TiN film thickness. The thicker the film, the greater its effective work function, which can increase the VTSAT of NMOS and decrease the VTSAT of PMOS. To achieve devices with different VTSAT, the process flow requires multiple photolithography (PH) / etching (ETch) / wet etching (WET) processes to fabricate the required thickness for different devices, thereby achieving the desired VTSAT.
[0004] In actual manufacturing processes, excessively thin TiN layers can negatively impact device performance, making it difficult to balance VTSAT values at each stage.
[0005] like Figure 1 The diagram shows schematic representations of various threshold voltage devices obtained using existing HKMG gate work function adjustment techniques; as shown... Figure 2 The diagram shown is a flowchart of the existing HKMG gate work function adjustment process; as shown... Figures 3A-3D The diagram shown is a schematic representation of the device structure in each step of the existing HKMG gate work function adjustment process. The existing HKMG gate work function adjustment process includes: Step S101, HK DEP, i.e., as Figure 3A As shown, an interface layer 101 and a high dielectric constant (HK) layer 102 are formed on a semiconductor substrate (not shown).
[0006] Step S102, Cap TiN & PMA, involves forming a cap TiN and performing post-metal annealing (PMA).
[0007] Step S103, A-Si dep / Ann / RM, depositing amorphous silicon (A-Si) layer and annealing to convert the TiN layer to TSN layer 103. The amorphous silicon layer is removed.
[0008] Step S104, TaN dep, as shown, forming TaN layer 104 on the top surface of the TSN layer 103. Figure 3A
[0009] The cycle process steps include: Step S105, TiN dep, as shown, depositing work function TiN layer 105a. Figure 3B Figure 3B The work function TiN layer 105a formed in the first cycle process step is taken as an example for illustration.
[0010] Step S106, PH, including depositing BARC layer and performing photo lithography (PH) process to define the patterned etching area of the work function TiN layer.
[0011] Step S107, Barc open ET, etching (ET) the BARC layer to form opening (open).
[0012] Step S108, TiN WET RM, etching the work function TiN layer 105a to achieve the patterned etching of the work function TiN layer 105a using the BARC layer as a mask. Generally, the etching of the work function TiN layer includes wet etching (wet).
[0013] Step S109, Asher & Wet strip, performing ashing (Asher) to remove the photoresist formed in the photo lithography process, and then performing wet strip (wet strip).
[0014] Figure 2 In the embodiment, the dashed line 202 represents that the steps S105 to S109 are repeated 5 times, and 5 layers of the work function TiN layer are formed. As shown, the size of the gate work function includes six, and the corresponding threshold voltages are NULVT, NLVT, NSVT, PSVT, PLVT and PULVT, and the corresponding areas are areas 101a, 101b, 101c, 101d, 101e and 101f. Figure 1
[0015] In the embodiment, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NSVT is the standard threshold voltage of NMOS.
[0016] PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PSVT is the standard threshold voltage of PMOS.
[0017] In the NULVT region, the work function TiN layer 105 is not formed.
[0018] In the NLVT region, the work function TiN layer 105 is composed of the work function TiN layer 105e of the fifth cycle process step.
[0019] In the NSVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 105d and 105e from the fourth and fifth cycle process steps.
[0020] In the PSVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 105c, 105d and 105e from the third to fifth cycle process steps.
[0021] In the PLVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 105b, 105c, 105d and 105e from the second to fifth cycle process steps.
[0022] In the PULVT region, the work function TiN layer 105 is formed by superimposing the work function TiN layers 05a, 05b, 105c, 105d and 105e from the first to the fifth cycle process steps.
[0023] This also includes: Step S110, TiAl dep. That is, as follows: Figure 3D As shown, the successful function TiAl layer 106 is formed. In Figure 5 In the preferred embodiment shown, this step is... Typically, after the TiAl layer with work function 106 is deposited, a top barrier (TBM) layer is also deposited, which includes a TiN layer.
[0024] Step S111, W deposition & CMP. That is, a metal conductive material layer 107 is formed, the material of which includes tungsten. After W deposition, CMP is performed.
[0025] The entire HKMG process is mainly designed to produce VTSAT for different devices by using multiple exposures to form TiN films of varying thicknesses. However, if the WF TiN film thickness is too small, the film quality will be greatly reduced, affecting the device's performance stability and uniformity. Therefore, it is difficult to control the VTSAT to lower requirements. Summary of the Invention
[0026] The technical problem solved by the present application is to provide a HKMG gate work function adjustment process method, which can expand the threshold voltage adjustment process window, make the threshold voltage match the target value to the maximum extent, and thereby improve the device performance.
[0027] To solve the above technical problem, the HKMG gate work function adjustment process method provided by the present application comprises: Step one, forming an interface layer and a high dielectric constant layer on a semiconductor substrate.
[0028] Step two, forming a lanthanum oxide (LaO) layer on the top surface of the high dielectric constant layer.
[0029] Step three, patterning and etching the lanthanum oxide layer to remove the lanthanum oxide layer outside the first region and retain the lanthanum oxide layer in the first region, where the first region outside is a region that does not need to reduce the gate work function.
[0030] Step four, performing annealing (ann) drive-in to push lanthanum into the high dielectric constant layer, and after the lanthanum is pushed into the high dielectric constant layer, an electric dipole is formed at the interface between the high dielectric constant layer and the interface layer, and the gate work function of the first region is reduced through the electric dipole.
[0031] Step five, removing the remaining lanthanum oxide layer.
[0032] Further improvement is that it further comprises: Step six, forming a silicon-doped TiN (TSN) layer on the top surface of the high dielectric constant layer.
[0033] Step seven, forming a TaN layer on the top surface of the TSN layer.
[0034] Step eight, forming a work function TiN layer with different thicknesses in different regions to adjust the gate work function of each region.
[0035] Step nine, forming a work function TiAl layer.
[0036] Step ten, forming a layer of metal conductive material.
[0037] Further improvement is that step six comprises the following sub-steps: Depositing a Cap TiN layer and performing metal post annealing (PMA).
[0038] Depositing an amorphous silicon layer (A-Si) and performing annealing to convert the silicon-doped TiN layer to the TSN layer.
[0039] Removing the amorphous silicon layer.
[0040] Further improvement is that step eight is implemented by repeating a plurality of cycle process steps, the cycle process steps comprising: depositing a work function (WF) TiN layer.
[0041] performing a patterned etching on the WF TiN layer.
[0042] Further improvement is that the WF TiN layer in each region is formed by stacking the WF TiN layers, and the WF TiN layer in each region is determined by the stacking thickness of the WF TiN layers included.
[0043] Further improvement is that before performing the patterned etching on the WF TiN layer, further comprising: depositing a BARC layer.
[0044] performing a photolithography process to define a patterned etching region of the WF TiN layer, and then etching the BARC layer.
[0045] Then, etching the WF TiN layer using the BARC layer as a mask to implement the patterned etching of the WF TiN layer.
[0046] Further improvement is that the etching of the WF TiN layer comprises a wet etching.
[0047] Further improvement is that in step eight, the number of repetitions of the cycle process steps is 5.
[0048] Further improvement is that the size of the gate work function includes six, and the corresponding threshold voltages are NULVT, NLVT, NSVT, PSVT, PLVT and PULVT.
[0049] NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NSVT is the standard threshold voltage of NMOS.
[0050] PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PSVT is the standard threshold voltage of PMOS.
[0051] In the NULVT region, the WF TiN layer is not formed.
[0052] In the NLVT region, the WF TiN layer is composed of the WF TiN layer of the fifth cycle process step.
[0053] In the region of NSVT, the work function TiN layer is formed by superimposition of the work function TiN layers of the fourth and fifth cycle process steps.
[0054] In the region of PSVT, the work function TiN layer is formed by superimposition of the work function TiN layers of the third to fifth cycle process steps.
[0055] In the region of PLVT, the work function TiN layer is formed by superimposition of the work function TiN layers of the second to fifth cycle process steps.
[0056] In the region of PULVT, the work function TiN layer is formed by superimposition of the work function TiN layers of the first to fifth cycle process steps.
[0057] A further improvement is that the thickness of the work function TiN layer is greater than or equal to a minimum limit value, the decrease of the gate work function by the electric dipole is used to compensate for the limitation of the minimum limit value on the decrease of the gate work function.
[0058] A further improvement is that the material of the metal conductive material layer includes tungsten.
[0059] A further improvement is that the gate work function is adjusted by adjusting the lanthanum doping concentration in the high dielectric constant layer, the greater the lanthanum doping concentration, the smaller the gate work function.
[0060] A further improvement is that the material of the high dielectric constant layer includes hafnium oxide.
[0061] The present application adds the step of forming a lanthanum oxide layer and annealing to incorporate lanthanum into the high dielectric constant layer after the formation of the high dielectric constant layer, and after the incorporation of lanthanum, an electric dipole is formed at the interface between the high dielectric constant layer and the interface layer, and the electric dipole reduces the gate work function, so the present application adds a process means for reducing the gate work function, and in particular, can break through the limitation of the minimum limit value of the thickness of the work function TiN layer on the reduction of the gate work function, so that the thickness of the work function TiN layer can still further reduce the gate work function below the gate work function limited by the minimum limit value under the condition of being greater than the minimum limit value. Since the gate work function can adjust the threshold voltage, the present application can expand the process window of the threshold voltage adjustment, make the threshold voltage match the target value to the greatest extent, and thus improve the device performance. BRIEF DESCRIPTION OF DRAWINGS
[0062] The present application will be further described in detail below in combination with the drawings and specific embodiments: Figure 1is a structure diagram of a plurality of threshold voltage devices obtained by a regulating process method of a gate work function of an existing HKMG; Figure 2 is a flow chart of a regulating process method of a gate work function of an existing HKMG; Figures 3A-3D is a structure diagram of a device in each step of a regulating process method of a gate work function of an existing HKMG; Figure 4 is a flow chart of a regulating process method of a gate work function of an HKMG of an embodiment of the present application; Figure 5 is a flow chart of a regulating process method of a gate work function of an HKMG of a preferred embodiment of the present application; Figures 6A-6E is a structure diagram of a device in each step of a regulating process method of a gate work function of an HKMG of a preferred embodiment of the present application; Figure 7 is a curve of a number of lanthanum atoms at an interface of a high dielectric constant layer and an interface layer and a flat band voltage of a device corresponding to a regulating process method of a gate work function of an HKMG of a preferred embodiment of the present application. DETAILED DESCRIPTION
[0063] As shown in Figure 4 , it is a flow chart of a regulating process method of a gate work function of an HKMG of an embodiment of the present application; as shown in Figure 5 , it is a flow chart of a regulating process method of a gate work function of an HKMG of a preferred embodiment of the present application; as shown in Figures 6A-6E , it is a structure diagram of a device in each step of a regulating process method of a gate work function of an HKMG of a preferred embodiment of the present application; the regulating process method of a gate work function of an HKMG of an embodiment of the present application comprises: Step one, as shown in Figure 6A , an interface layer 101 and a high dielectric constant (HK) layer 102 are formed on a semiconductor substrate (not shown).
[0064] In some preferred embodiments, the material of the high dielectric constant layer 102 includes hafnium oxide, which is formed by deposition.
[0065] In the preferred embodiment shown in Figure 5 , step one is step S101, HK DEP.
[0066] Step two, as shown in Figure 6A , a lanthanum oxide layer 301 is formed on the top surface of the high dielectric constant layer 102, and the molecular formula of the lanthanum oxide is La2O3.
[0067] In the preferred embodiment shown in Figure 5 , step two is step S201, LaO Dep, that is, depositing lanthanum oxide.
[0068] Step three, as shown in FIG. 3, the lanthanum oxide layer 301 is patterned and etched to remove the lanthanum oxide layer 301 outside the first region and keep the lanthanum oxide layer 301 in the first region, where the first region is a region where the gate work function does not need to be reduced. Figure 6B
[0069] In the preferred embodiment shown in FIG. 3, step three includes: Figure 5 Step S202, photolithography (PH) and etching (ET), i.e. PH / ET.
[0070] Step S203, LaO removal (RM), i.e. LaO RM.
[0071] Step four, as shown in FIG. 4, annealing is performed to drive lanthanum into the high dielectric constant layer 102, and after the lanthanum is driven into the high dielectric constant layer 102, an electric dipole 302 is formed at the interface between the high dielectric constant layer 102 and the interface layer 101, and the gate work function of the first region is reduced through the electric dipole 302. Figure 6C
[0072] In the preferred embodiment shown in FIG. 4, step four is step S204, La drive-in ann. Figure 6C
[0073] In the preferred embodiment shown in FIG. 4, step four is step S204, La drive-in ann. Figure 5 In the embodiment of the present application, the gate work function is adjusted by adjusting the lanthanum doping concentration in the high dielectric constant layer 102, and the greater the lanthanum doping concentration, the smaller the gate work function.
[0074] As shown in FIG. 5, it is a curve of the number of lanthanum atoms at the interface of the high dielectric constant layer and the interface layer and the flat band voltage of the device corresponding to the gate work function adjustment process method of the preferred embodiment of the present application HKMG;
[0075] In the preferred embodiment shown in FIG. 5, the vertical coordinate is the flat band voltage Vfb, and when other process conditions of the device are the same and only the number of lanthanum atoms is different, the change of the flat band voltage is the same as the change of the gate work function; the horizontal coordinate uses percentage (%) to represent the number of lanthanum atoms, and it can be seen that from 0 to 100, Vfb gradually decreases, indicating that the work function gradually decreases; wherein the values at the positions corresponding to the markers 401, 402 and 403 are respectively the Vfb values at the positions where the number of lanthanum atoms is 100%, 80% and 55%. When the number of lanthanum atoms is 100%, the HfO2 at the corresponding position is all converted into La2O3. Figure 7 Figure 7 Step five, as shown in FIG. 6, the high dielectric constant layer 102a doped with lanthanum is removed, and the high dielectric constant layer 102b without lanthanum is exposed.
[0076] Step five, as shown in FIG. 6, the high dielectric constant layer 102a doped with lanthanum is removed, and the high dielectric constant layer 102b without lanthanum is exposed.Figure 6D The remaining lanthanum oxide layer 301 is removed.
[0077] In Figure 5 In the preferred embodiment shown, step five is step S201, La RM2, which is a second removal of the lanthanum oxide layer 301.
[0078] Figure 5 In the preferred embodiment shown, step five is step S201, La RM2, which is a second removal of the lanthanum oxide layer 301. Figure 2 The subsequent steps of the present embodiment can use the same steps as the prior art method, which are described below: The subsequent steps of the present embodiment can use the same steps as the prior art method, which are described below: Step six, as shown in Figure 6E A TSN layer 103 is formed on the top surface of the high-k layer 102.
[0079] Step six includes the following sub-steps: A cap TiN layer is deposited and subjected to a metal post-anneal. In Figure 5 In the preferred embodiment shown, this step is step S102, Cap TiN & PMA.
[0080] An amorphous silicon layer is deposited and annealed to convert the TiN layer to the TSN layer 103 by doping with silicon. The amorphous silicon layer is removed. In Figure 5 In the preferred embodiment shown, these two steps are step S103, A-Si dep / Ann / RM.
[0081] Step seven, a TaN layer 104 is formed on the top surface of the TSN layer 103. In Figure 5 In the preferred embodiment shown, this step is step S104, TaN dep.
[0082] Step eight, a work function TiN layer 105 is formed in different regions to adjust the gate work function of each region.
[0083] In the present embodiment, step eight is achieved by repeating a plurality of cycle process steps, which include: A work function TiN layer is deposited. In Figure 5 In the preferred embodiment shown, this step is step S105, TiN dep.
[0084] The work function TiN layer is subjected to a patterned etch.
[0085] Before the work function TiN layer is subjected to a patterned etch, it further includes: A BARC layer is deposited.
[0086] A photo-lithography (PH) process is performed to define a patterned etching area of the work function TiN layer. Figure 5 In the preferred embodiment shown, this step is step S106, PH.
[0087] Then, the BARC layer is etched (ET) to form an opening (open). In Figure 5 In the preferred embodiment shown, this step is step S107, Barc open ET.
[0088] Then, the work function TiN layer is etched using the BARC layer as a mask to achieve the patterned etching of the work function TiN layer. Preferably, the etching of the work function TiN layer includes a wet etching (wet). In Figure 5 In the preferred embodiment shown, this step is step S108, TiN WET RM.
[0089] Then, it further includes an Asher to remove the photoresist formed by the photo-lithography process, and then a wet strip is performed. In Figure 5 In the preferred embodiment shown, this step is step S109, Asher & Wet strip.
[0090] The work function TiN layer 105 in each region is formed by the superposition of one or more work function TiN layers, and the thickness of the work function TiN layer 105 in each region is determined by the superposition thickness of the work function TiN layers included. Among them, the surface of the zero layer of the work function TiN layer does not form the work function TiN layer 105. In step eight, the number of repetitions of the cycle process step is 5 times. Figure 1 In the preferred embodiment shown, the dashed line 202 represents that steps S105 to S109 are repeated 5 times, and 5 layers of the work function TiN layer are formed.
[0091] The above-mentioned cycle process step is the same as the existing method, please refer to Figure 6E As shown, the size of the gate work function includes six, and the corresponding threshold voltages are NULVT, NLVT, NSVT, PSVT, PLVT and PULVT. The corresponding regions of the six threshold voltages are regions 101a, 101b, 101c, 101d, 101e and 101f, respectively.
[0092] Among them, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NSVT is the standard threshold voltage of NMOS.
[0093] PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PSVT is the standard threshold voltage of PMOS.
[0094] In the region of NULVT, the work function TiN layer 105 is not formed.
[0095] In the region of NLVT, the work function TiN layer 105 is composed of the work function TiN layer 105e of the fifth cycle process step.
[0096] In the region of NSVT, the work function TiN layer 105 is composed of the work function TiN layers 105d and 105e of the fourth and fifth cycle process steps.
[0097] In the region of PSVT, the work function TiN layer 105 is composed of the work function TiN layers 105c, 105d and 105e of the third to fifth cycle process steps.
[0098] In the region of PLVT, the work function TiN layer 105 is composed of the work function TiN layers 105b, 105c, 105d and 105e of the second to fifth cycle process steps.
[0099] In the region of PULVT, the work function TiN layer 105 is composed of the work function TiN layers 05a, 05b, 105c, 105d and 105e of the first to fifth cycle process steps.
[0100] In the embodiment of the present application, the thickness of the work function TiN layer is greater than or equal to a minimum limit value, the work function TiN layer limits the decrease of the gate work function by the minimum limit value, and the decrease of the gate work function by the electric dipole 302 compensates for the limitation of the decrease of the gate work function by the minimum limit value.
[0101] Step nine, as shown in FIG. 1, a work function TiAl layer 106 is formed. Figure 5 In the preferred embodiment shown in FIG. 1, this step is step S110, TiAl dep. Figure 6E Generally, after the work function TiAl layer 106 is deposited, a top barrier (TBM) layer is also deposited, and the TBM layer includes a TiN layer.
[0102] Step ten, as shown in FIG. 1, a metal conductive material layer 107 is formed. Preferably, the material of the metal conductive material layer 107 includes tungsten, and after W deposition, CMP is also performed.
[0103] In the preferred embodiment shown in FIG. 1, this step is step S111, W dep & CMP. Figure 5
[0104] The embodiment of the present application forms the lanthanum oxide layer 301 and carries out annealing to incorporate lanthanum into the high dielectric constant layer 102 after the high dielectric constant layer 102 is formed, and not directly forms the subsequent cap TiN layer, after the lanthanum is doped, the electric dipole 302 can be formed at the interface of the high dielectric constant layer 102 and the interface layer 101, the electric dipole 302 reduces the gate work function, therefore, the embodiment of the present application increases a process means for reducing the gate work function, in particular, can break through the limit of the minimum limit value of the thickness of the work function TiN layer 105 on the reduction of the gate work function, so that the thickness of the work function TiN layer 105 can still further reduce the gate work function below the gate work function limited by the minimum limit value under the condition of being greater than the minimum limit value, since the gate work function can adjust the threshold voltage, the embodiment of the present application can expand the threshold voltage adjustment process window, make the threshold voltage match the target value to the maximum extent and thereby improve the device performance.
[0105] In the embodiment of the present application, by pushing La into Hf2O3, the electric dipole is formed between the HK layer and the interface (IL), and the gate work function is reduced.
[0106] By PH / ET, the device area which does not need to reduce the work function is opened, the La2O3 film layer is removed by WET cleaning, and then the La in the area with the La2O3 film layer is diffused to HK by high temperature annealing, so as to generate the electric dipole and reduce the work function. The La doping technology combined with the TiN thickness adjustment can further expand the VTSAT adjustment window Compared with the prior art, the key of the embodiment of the present application is to add the La doping process, combine the existing TiN film thickness adjustment process, further expand the threshold voltage adjustment window (Window), make each level of threshold voltage match the target value to the maximum extent, and thereby improve the device performance.
[0107] The present application has been described in detail by specific embodiments, but these do not constitute limitations on the present application. Those skilled in the art can make many modifications and improvements without departing from the principle of the present application, and these should be considered as the protection scope of the present application.
Claims
1. A process method for adjusting the gate work function of an HKMG, characterized in that, include: Step 1: Form an interface layer and a high dielectric constant layer on a semiconductor substrate; Step 2: Form a lanthanum oxide layer on the top surface of the high dielectric constant layer; Step 3: Perform patterned etching on the lanthanum oxide layer to remove the lanthanum oxide layer outside the first region and retain the lanthanum oxide layer in the first region, wherein the region outside the first region is the region where it is not necessary to reduce the gate work function; Step 4: Annealing is performed to advance lanthanum into the high dielectric constant layer. After the lanthanum is advanced into the high dielectric constant layer, an electric dipole is formed at the interface between the high dielectric constant layer and the interface layer. The electric dipole reduces the gate work function of the first region. Step 5: Remove the remaining lanthanum oxide layer.
2. The method for adjusting the gate work function of an HKMG as described in claim 1, characterized in that, Also includes: Step 6: Form a TSN layer on the top surface of the high dielectric constant layer; Step 7: Form a TaN layer on the top surface of the TSN layer; Step 8: Form TiN layers of different thicknesses in different regions to adjust the gate work function in each region; Step 9: Form the functional TiAl layer; Step 10: Form a layer of conductive metallic material.
3. The method for adjusting the gate work function of an HKMG as described in claim 2, characterized in that, Step six includes the following sub-steps: Deposit a capping TiN layer and perform post-metal annealing; An amorphous silicon layer is deposited and annealed to convert the TiN layer into the TSN layer by silicon doping. Remove the amorphous silicon layer.
4. The method for adjusting the gate work function of an HKMG as described in claim 2, characterized in that, Step eight is achieved by repeating the cyclic process steps multiple times, the cyclic process steps including: Deposition work function TiN stratification; The work function TiN layers are patterned and etched.
5. The method for adjusting the gate work function of an HKMG as described in claim 4, characterized in that: The work function TiN layer in each region is formed by stacking work function TiN layers above the zero layer, and the work function TiN layer in each region is determined by the stacking thickness of each work function TiN layer included.
6. The process method for adjusting the gate work function of HKMG as described in claim 4, characterized in that: Before performing patterned etching on the work function TiN layer, the following steps are also included: Deposited BARC layer; A photolithography process is performed to define the patterned etching region of the work function TiN layer, and then the BARC layer is etched. Subsequently, the work function TiN layer is etched using the BARC layer as a mask to achieve patterned etching of the work function TiN layer.
7. The process method for adjusting the gate work function of HKMG as described in claim 6, characterized in that: The etching of the work function TiN layer includes wet etching.
8. The method for adjusting the gate work function of an HKMG as described in claim 4, characterized in that, In step eight, the cyclic process step is repeated 5 times.
9. The process method for adjusting the gate work function of an HKMG as described in claim 8, characterized in that: The gate work function includes six values, and the corresponding threshold voltages are: NULVT, NLVT, NSVT, PSVT, PLVT, and PULVT. Wherein, NULVT is the ultra-low threshold voltage of NMOS, NLVT is the low threshold voltage of NMOS, and NSVT is the standard threshold voltage of NMOS; PULVT is the ultra-low threshold voltage of PMOS, PLVT is the low threshold voltage of PMOS, and PSVT is the standard threshold voltage of PMOS. In the NULVT region, the work function TiN layer is not formed; In the NLVT region, the work function TiN layer is composed of the work function TiN layer of the fifth cycle process step; In the NSVT region, the work function TiN layer is formed by stacking the work function TiN layers from the fourth and fifth cycle process steps; In the PSVT region, the work function TiN layer is formed by stacking the work function TiN layers from the third to the fifth cycle process steps; In the PLVT region, the work function TiN layer is formed by stacking the work function TiN layers from the second to the fifth cycle process steps; In the PULVT region, the work function TiN layer is formed by stacking the work function TiN layers from the first to the fifth cycle process steps.
10. The process method for adjusting the gate work function of an HKMG as described in claim 4, characterized in that: The thickness of the TiN layer with work function is greater than or equal to the minimum limit value. The reduction of the gate work function by the TiN layer with work function is limited by the minimum limit value. The reduction of the gate work function by the electric dipole is compensated for by the limitation of the minimum limit value on the reduction of the gate work function.
11. The process method for adjusting the gate work function of an HKMG as described in claim 2, characterized in that: The material of the metallic conductive material layer includes tungsten.
12. The process method for adjusting the gate work function of an HKMG as described in claim 1, characterized in that: The gate work function is adjusted by regulating the lanthanum doping concentration in the high dielectric constant layer; the higher the lanthanum doping concentration, the lower the gate work function.
13. The process method for adjusting the gate work function of an HKMG as described in claim 1, characterized in that: The material of the high dielectric constant layer includes hafnium oxide.