Silicon through hole and manufacturing method thereof
By employing a gradually varying thermal expansion coefficient structure with alternating layers of insulators with different thermal expansion coefficients on the side of the through-silicon via (TSV) trench, the warping and breakage problems caused by the difference in thermal expansion coefficients during high-temperature processing of TSVs are solved, resulting in a more uniform stress distribution and improved electrical reliability.
Patent Information
- Application Number
- CN202511728310.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-02-27
AI Technical Summary
In existing through-silicon via (TSV) manufacturing methods, the large difference in thermal expansion coefficients between the insulating layer and the silicon substrate leads to problems such as silicon wafer warping and TSV breakage during high-temperature processes.
A gradually varying coefficient of thermal expansion matching insulation layer is adopted, which consists of multiple layers of insulators with different coefficients of thermal expansion arranged alternately to form a gradually varying coefficient of thermal expansion structure, thereby reducing thermal stress and improving electrical reliability.
By alternating multiple layers of insulators, thermal stress is buffered and balanced, preventing silicon wafer warping and TSV breakage, and improving the electrical reliability and heat resistance of through-silicon vias.
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Figure CN121586464A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a through-silicon via (TSV). This invention also relates to a method for manufacturing a through-silicon via. Background Technology
[0002] like Figure 1 The diagram shown is a schematic of the device structure in an existing through-silicon via (TSV) fabrication method. The main steps of the existing TSV fabrication method include:
[0003] 1. Etching of deep holes, i.e., through-silicon via trench 102:
[0004] The front-end silicon wafer, i.e., the silicon substrate 101, is flipped and its back side is thinned to a silicon thickness of 10-25 μm; then, through-silicon via trenches 102 are formed on the silicon substrate 101 by dry etching such as DRIE.
[0005] A semiconductor device is formed on the silicon substrate 101. A metal interconnect structure is formed on the front side of the silicon substrate 101. The metal interconnect structure includes multiple front metal layers 203, a front dielectric layer 204, and a via 205 passing through the front dielectric layer 204. The via 205 enables the connection of different front metal layers 203.
[0006] After forming the metal interconnect structure, the front side of the silicon substrate 101 and the wafer 201 need to be bonded. Then, the silicon substrate 101 is flipped, and the back side is thinned and etched to form the through-silicon via (TSV) trench 102. The etching process for the TSV trench 102 is typically dry etching. After etching through the silicon substrate 101, the front dielectric layer 204 also needs to be etched to expose the back side of the corresponding topmost front metal layer 203.
[0007] 2. Deposition of insulating layer / barrier layer / seed layer:
[0008] That is, an insulating layer 103 composed of SiO2, an adhesion barrier layer 105 composed of Ta and TaN layers and a Cu seed layer are deposited sequentially.
[0009] 3. Electroplating filling: Electroplated copper layer 104 fills silicon through-hole trench 102, and subsequent chemical mechanical polishing (CMP) achieves surface planarization.
[0010] The main drawback of existing through-silicon via (TSV) manufacturing methods is thermal stress, specifically: the large difference in the coefficient of thermal expansion (CTE) between the insulating layer 103 and the silicon substrate 101 can easily lead to silicon wafer warping or TSV breakage during high-temperature processes. Summary of the Invention
[0011] The technical problem solved by the present application is to provide a through silicon via, which can eliminate the problem of easy silicon substrate wafer warping and through silicon via fracture in high temperature process caused by the large difference in thermal expansion coefficient between the insulating layer on the side of the through silicon via trench and silicon.
[0012] To solve the above technical problem, the present application provides a through silicon via, which comprises:
[0013] A through silicon via trench penetrating through the silicon substrate.
[0014] A gradient thermal expansion coefficient matching insulating layer is formed on the side of the through silicon via trench.
[0015] A first metal layer is filled in the through silicon via trench to form a through silicon via.
[0016] The gradient thermal expansion coefficient matching insulating layer has a gradient thermal expansion coefficient structure, and the gradient thermal expansion coefficient structure is used to reduce the thermal stress between silicon and the first metal layer at the side of the through silicon via trench in the thermal process and thus improve the electrical reliability of the through silicon via.
[0017] Further improvement is that the gradient thermal expansion coefficient matching insulating layer is composed of multiple insulating sub-layers with different thermal expansion coefficients.
[0018] Further improvement is that the insulating sub-layers include a first insulating sub-layer and a second insulating sub-layer, and the materials of the first insulating sub-layer and the second insulating sub-layer are different.
[0019] The first insulating sub-layer and the second insulating sub-layer are alternately arranged to form the gradient thermal expansion coefficient matching insulating layer.
[0020] Further improvement is that the material of the first insulating sub-layer includes silicon dioxide, and the material of the second insulating sub-layer includes silicon nitride.
[0021] Further improvement is that in the gradient thermal expansion coefficient matching insulating layer, the repeating number of the superposition unit of the first insulating sub-layer and the second insulating sub-layer is 2 or more, so that the thickness of the gradient thermal expansion coefficient matching insulating layer meets the side insulation requirement of the through silicon via.
[0022] Further improvement is that in the gradient thermal expansion coefficient matching insulating layer, the repeating number of the superposition unit of the first insulating sub-layer and the second insulating sub-layer is 3.
[0023] Further improvement is that the first metal layer is a copper layer.
[0024] An adhesion barrier layer is further formed on the surface of the gradient thermal expansion coefficient matching insulating layer and the bottom surface of the through silicon via trench.
[0025] A copper seed layer is formed on the surface of the adhesion barrier layer.
[0026] Further improvement is that the adhesion barrier layer comprises a Ta layer and a TaN layer stacked in sequence.
[0027] To solve the above technical problems, the manufacturing method of the through silicon via provided by the present application comprises the following steps:
[0028] The silicon substrate is patterned and etched to form a through silicon via trench penetrating the silicon substrate.
[0029] A gradient thermal expansion coefficient matching insulating layer is formed on the side surface of the through silicon via trench.
[0030] A first metal layer is filled in the through silicon via trench to form a through silicon via.
[0031] The gradient thermal expansion coefficient matching insulating layer has a gradient thermal expansion coefficient structure and utilizes the gradient thermal expansion coefficient structure to reduce the thermal stress between the silicon and the first metal layer at the side surface of the through silicon via trench during a thermal process and thereby improve the electrical reliability of the through silicon via.
[0032] Further improvement is that the gradient thermal expansion coefficient matching insulating layer is stacked by multiple insulating sub-layers with different thermal expansion coefficients.
[0033] Further improvement is that the insulating sub-layers comprise a first insulating sub-layer and a second insulating sub-layer, and the materials of the first insulating sub-layer and the second insulating sub-layer are different.
[0034] The gradient thermal expansion coefficient matching insulating layer is formed by the first insulating sub-layer and the second insulating sub-layer arranged alternately.
[0035] Further improvement is that the material of the first insulating sub-layer comprises silicon dioxide; and the material of the second insulating sub-layer comprises silicon nitride.
[0036] The step of forming the gradient thermal expansion coefficient matching insulating layer comprises:
[0037] Silicon dioxide and silicon nitride are deposited alternately by CVD process to form the first insulating sub-layer and the second insulating sub-layer arranged alternately.
[0038] Further improvement is that in the gradient thermal expansion coefficient matching insulating layer, the repeating number of the stacked units of the first insulating sub-layer and the second insulating sub-layer is more than 2 times, so that the thickness of the gradient thermal expansion coefficient matching insulating layer meets the side surface insulation requirement of the through silicon via.
[0039] A further improvement is that, in the gradient thermal expansion coefficient matching insulation layer, the number of repetitions of the superposition unit of the first insulator layer and the second insulator layer is 3.
[0040] A further improvement is that the first metal layer is a copper layer, formed using an electroplating process; prior to forming the first metal layer, the following steps are also included:
[0041] An adhesion barrier layer is also formed on the surface of the insulating layer with the gradient thermal expansion coefficient and on the bottom surface of the through-silicon via trench.
[0042] A copper seed crystal layer is formed on the surface of the adhesive barrier layer.
[0043] A further improvement is that the adhesion barrier layer comprises a Ta layer and a TaN layer stacked sequentially.
[0044] A further improvement is that, after the electroplating process of the first metal layer is completed, the process further includes:
[0045] The silicon substrate surface is planarized by performing a chemical mechanical polishing process.
[0046] This invention features a specially designed insulating layer on the side of the through-silicon via (TSV) trench. The insulating layer is a gradient thermal expansion coefficient matching insulating layer. In the direction from the silicon on the side of the TSV trench to the first metal layer, the gradient thermal expansion coefficient matching insulating layer can achieve a gradual change in the thermal expansion coefficient. This can prevent the large stress caused by the large change in the thermal expansion coefficient between the silicon and the insulating layer, which is mainly a thermal stress problem generated in high-temperature processes. Therefore, this invention can eliminate the problem of silicon substrate warping and TSV breakage caused by the large difference in thermal expansion coefficient between the insulating layer and silicon on the side of the TSV trench during high-temperature processes.
[0047] In this invention, the gradually increasing thermal expansion coefficient matching insulation layer can be formed by stacking multiple layers of insulators with different thermal expansion coefficients, for example by alternating first and second insulator layers. The difference in thermal expansion coefficients between adjacent insulator layers creates a mutual restraint mechanism within the gradually increasing thermal expansion coefficient matching insulation layer, thereby buffering and balancing thermal stress.
[0048] The multilayer insulator layer of the present invention can also disperse stress when stress is generated. In this way, the deformation difference of each insulator layer is small when the temperature changes, and stress concentration will not occur. Therefore, compared with a single-layer insulator layer, the present invention can make the stress distribution more uniform, reduce the situation of excessive local stress, and reduce the defect risk of cracking of the film due to thermal stress.
[0049] In addition, a large number of interfaces are formed between the multilayer insulators of the present invention. These interfaces can effectively transfer and disperse stress, and the corresponding atomic stress adjustment at the interfaces can better adapt to the deformation of the substrate when the temperature changes, thereby reducing thermal stress. Attached Figure Description
[0050] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0051] Figure 1 This is a schematic diagram of the device structure in the existing through-silicon via (TSV) manufacturing method;
[0052] Figure 2 This is a schematic diagram of the structure of a through-silicon via according to an embodiment of the present invention;
[0053] Figures 3A-3C This is a schematic diagram of the device structure in each step of the manufacturing method of through-silicon vias according to an embodiment of the present invention. Detailed Implementation
[0054] like Figure 2 The diagram shown is a schematic representation of a through-silicon via (TSV) according to an embodiment of the present invention. The TSV in this embodiment includes:
[0055] Silicon via trench 302 penetrating silicon substrate 301.
[0056] A gradient thermal expansion coefficient matching insulating layer 303 is formed on the side of the through-silicon via trench 302.
[0057] A first metal layer 304 is filled in the through silicon via trench 302 to form a through silicon via.
[0058] The gradient thermal expansion coefficient matching insulating layer 303 has a gradient thermal expansion coefficient structure and utilizes the gradient thermal expansion coefficient structure to reduce the thermal stress between silicon and the first metal layer 304 at the side of the through silicon via trench 302 during thermal processes, thereby improving the electrical reliability of the through silicon via.
[0059] In this embodiment of the invention, the gradient thermal expansion coefficient matching insulation layer 303 is composed of multiple layers of insulators with different thermal expansion coefficients stacked together.
[0060] The insulator layer includes a first insulator layer 303a and a second insulator layer 303b, and the first insulator layer 303a and the second insulator layer 303b are made of different materials.
[0061] The gradually varying thermal expansion coefficient matching insulation layer 303 is formed by alternating arrangements of the first insulator layer 303a and the second insulator layer 303b.
[0062] Preferably, the material of the first insulator layer 303a includes silicon dioxide; and the material of the second insulator layer 303b includes silicon nitride.
[0063] In the gradient thermal expansion coefficient matching insulation layer 303, the number of repetitions of the superposition units of the first insulator layer 303a and the second insulator layer 303b is more than 2, so that the thickness of the gradient thermal expansion coefficient matching insulation layer 303 meets the side insulation requirements of the through silicon via.
[0064] In some embodiments, in the gradient thermal expansion coefficient matching insulation layer 303, the number of repetitions of the stacking units of the first insulator layer 303a and the second insulator layer 303b is 3. The total thickness of the gradient thermal expansion coefficient matching insulation layer 303 is approximately The thickness of each of the first insulator layers 303a is approximately The thickness of the second insulator layer 303b is approximately
[0065] In this embodiment of the invention, the first metal layer 304 is a copper layer, formed by an electroplating process.
[0066] An adhesion barrier layer 305 is also formed on the surface of the gradient thermal expansion coefficient matching insulating layer 303 and the bottom surface of the through-silicon via trench 302. Please refer to [reference needed for details] regarding the adhesion barrier layer 305. Figure 3C As shown. In some embodiments, the adhesion barrier layer 305 includes a Ta layer and a TaN layer stacked sequentially.
[0067] A copper seed crystal layer is formed on the surface of the adhesion barrier layer 305.
[0068] Same reference Figure 3C As shown, a semiconductor device is formed on the silicon substrate 301. A metal interconnect structure is formed on the front side of the silicon substrate 301. The metal interconnect structure includes multiple front metal layers 403, a front dielectric layer 404, and vias 405 passing through the front dielectric layer 404. The vias 405 connect the different front metal layers 403. The silicon vias also need to pass through the front dielectric layer 404 and contact the topmost front metal layer 403 in the metal interconnect structure.
[0069] In this embodiment of the invention, the insulating layer on the side of the through-silicon via trench 302 is specially designed. The insulating layer adopts a gradient thermal expansion coefficient matching insulating layer 303. In the direction from the silicon on the side of the through-silicon via trench 302 to the first metal layer 304, the gradient thermal expansion coefficient matching insulating layer 303 can achieve a gradual change in thermal expansion coefficient. This can prevent the large stress caused by the large change in thermal expansion coefficient between silicon and the insulating layer, which is mainly the thermal stress generated in the high-temperature process. Therefore, this embodiment of the invention can eliminate the problem of warping of silicon substrate 301 and breakage of through-silicon vias caused by the large difference in thermal expansion coefficient between the insulating layer and silicon on the side of the through-silicon via trench 302 in the high-temperature process.
[0070] In this embodiment of the invention, the gradient thermal expansion coefficient matching insulation layer 303 can be formed by stacking multiple layers of insulators with different thermal expansion coefficients, for example by alternating first insulator layer 303a and second insulator layer 303b. The difference in thermal expansion coefficient between adjacent insulator layers forms a mutual restraint mechanism inside the gradient thermal expansion coefficient matching insulation layer 303, thereby buffering and balancing thermal stress.
[0071] The multilayer insulator layer of this invention can also disperse stress when stress is generated. In this way, the deformation difference of each insulator layer is small when the temperature changes, and stress concentration will not occur. Therefore, compared with a single-layer insulator layer, this invention can make the stress distribution more uniform, reduce the situation of excessive local stress, and reduce the risk of cracks in the film due to thermal stress.
[0072] In addition, a large number of interfaces are formed between the multilayer insulators in this embodiment of the invention. These interfaces can effectively transfer and disperse stress, and the corresponding atomic stress adjustment at the interfaces can better adapt to the deformation of the substrate when the temperature changes, thereby reducing thermal stress.
[0073] like Figures 3A-3C The diagram shown is a schematic representation of the device structure in each step of the through-silicon via (TSV) manufacturing method according to an embodiment of the present invention. The TSV manufacturing method according to an embodiment of the present invention includes the following steps:
[0074] A silicon via trench 302 is formed by patterning and etching a silicon substrate 301.
[0075] like Figure 3AAs shown in the embodiment of the present invention, a semiconductor device is formed on the silicon substrate 301. A metal interconnect structure is formed on the front side of the silicon substrate 301. The metal interconnect structure includes multiple front metal layers 403, a front dielectric layer 404, and vias 405 passing through the front dielectric layer 404. The vias 405 connect different front metal layers 403. The vias also need to pass through the front dielectric layer 404 and contact the topmost front metal layer 403 in the metal interconnect structure. After forming the metal interconnect structure, the front side of the silicon substrate 301 and the wafer 401 need to be bonded. Then, the silicon substrate 301 is flipped, and the back side is thinned and etched to form the via trench 302. The etching process of the via trench 302 is usually dry etching. After etching through the silicon substrate 301, the front dielectric layer 404 also needs to be etched to expose the back side of the corresponding topmost front metal layer 403.
[0076] like Figure 3B As shown, a gradient thermal expansion coefficient matching insulating layer 303 is formed on the side of the through-silicon via trench 302. Figure 3B This is a partial enlarged view of the bottom region of the through-silicon via trench 302, that is, the region near the topmost front metal layer 403.
[0077] In the implementation method of this invention, the gradually varying thermal expansion coefficient matching insulation layer 303 is composed of multiple layers of insulators with different thermal expansion coefficients. Further, the insulator layers include a first insulator layer 303a and a second insulator layer 303b, wherein the first insulator layer 303a and the second insulator layer 303b are made of different materials.
[0078] The gradually varying thermal expansion coefficient matching insulation layer 303 is formed by alternating arrangements of the first insulator layer 303a and the second insulator layer 303b.
[0079] Preferably, the material of the first insulator layer 303a comprises silicon dioxide; and the material of the second insulator layer 303b comprises silicon nitride. The steps for forming the graded thermal expansion coefficient matching insulation layer 303 include:
[0080] Silicon dioxide and silicon nitride are deposited alternately in sequence using a CVD process to form an alternating structure of the first insulator layer 303a and the second insulator layer 303b. Preferably, the CVD process is a PECVD process.
[0081] In the gradient thermal expansion coefficient matching insulation layer 303, the number of repetitions of the superposition units of the first insulator layer 303a and the second insulator layer 303b is more than 2, so that the thickness of the gradient thermal expansion coefficient matching insulation layer 303 meets the side insulation requirements of the through silicon via.
[0082] In some embodiments, the overlapping units of the first insulator layer 303a and the second insulator layer 303b in the gradient thermal expansion coefficient matching insulation layer 303 are repeated three times. The total thickness of the gradient thermal expansion coefficient matching insulation layer 303 is approximately The thickness of each of the first insulator layers 303a is approximately The thickness of the second insulator layer 303b is approximately
[0083] like Figure 3C As shown, a first metal layer 304 is filled in the through silicon via trench 302 to form a through silicon via.
[0084] The gradient thermal expansion coefficient matching insulating layer 303 has a gradient thermal expansion coefficient structure and utilizes the gradient thermal expansion coefficient structure to reduce the thermal stress between silicon and the first metal layer 304 at the side of the through silicon via trench 302 during thermal processes, thereby improving the electrical reliability of the through silicon via.
[0085] In the method of this embodiment of the invention, the first metal layer 304 is a copper layer, formed by electroplating; before forming the first metal layer 304, the method further includes:
[0086] An adhesion barrier layer 305 is also formed on the surface of the gradient thermal expansion coefficient matching insulating layer 303 and the bottom surface of the through-silicon via trench 302. Preferably, the adhesion barrier layer 305 comprises a Ta layer and a TaN layer stacked sequentially.
[0087] A copper seed crystal layer is formed on the surface of the adhesion barrier layer 305.
[0088] After the electroplating process of the first metal layer 304 is completed, the process further includes:
[0089] The silicon substrate 301 is planarized by performing a chemical mechanical polishing process.
[0090] In this embodiment of the invention, a composite gradient insulating layer design is adopted, mainly using a SiO2-Si3N4 gradient composite layer. SiO2 and Si3N4 are alternately deposited by CVD to form a gradient coefficient of thermal expansion (CTE) matching layer from the silicon substrate 301 to the copper pillar, i.e., the first metal layer 304, thereby reducing thermal stress.
[0091] In the method of this invention, the existing method of depositing 250nm SiO2 on a silicon substrate is optimized to deposit SiO2 and Si3N4 alternately three times to form a gradient insulating layer design, which can reduce thermal stress and thus reduce silicon wafer warpage. The reasons include:
[0092] 1. Multilayer films with alternating SiO2 and Si3N4 deposits have different coefficients of thermal expansion, which create a mutual restraining effect within the film, thus buffering and balancing thermal stress.
[0093] 2. Multilayer films can disperse stress. When the temperature changes, the deformation difference between each layer is small, and there will be no excessive stress concentration. Compared with single-layer films, the stress distribution is more uniform, reducing the situation of excessive local stress and reducing the defect risk of cracks caused by thermal stress in the film.
[0094] 3. The formation of numerous interfaces in the multilayer film effectively transmits and disperses stress. The stress adjustment due to atomic interactions at the interfaces allows for better adaptation to substrate deformation during temperature changes, thereby reducing thermal stress.
[0095] In 3D integrated circuit (3D IC) manufacturing technology, the embodiments of the present invention achieve the following: TSV vias are deposited with alternating layers of SiO2 and Si3N4 three times, with each layer being relatively thin. This effectively transfers and disperses the thermal stress at the interface in subsequent high-temperature processes, preventing further concentration and accumulation of stress, reducing silicon wafer warping and cracks caused by thermal stress, and significantly improving product yield.
[0096] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A through-silicon via (TSV), characterized in that, include: Through-silicon via trenches penetrating a silicon substrate; A gradient thermal expansion coefficient matching insulating layer is formed on the side of the through-silicon via trench; A first metal layer is filled in the through-silicon via trench to form a through-silicon via; The gradient thermal expansion coefficient matching insulating layer has a gradient thermal expansion coefficient structure and utilizes the gradient thermal expansion coefficient structure to reduce the thermal stress between silicon and the first metal layer at the side of the through silicon via trench during thermal processes, thereby improving the electrical reliability of the through silicon via.
2. The through-silicon via as described in claim 1, characterized in that: The gradient thermal expansion coefficient matching insulation layer is composed of multiple layers of insulators with different thermal expansion coefficients stacked together.
3. The through-silicon via as described in claim 2, characterized in that: The insulator layer includes a first insulator layer and a second insulator layer, and the first insulator layer and the second insulator layer are made of different materials; The gradually varying coefficient of thermal expansion matching insulation layer is composed of alternating first and second insulator layers.
4. The through-silicon via as described in claim 3, characterized in that: The material of the first insulator layer includes silicon dioxide; the material of the second insulator layer includes silicon nitride.
5. The through-silicon via as described in claim 4, characterized in that: In the gradient thermal expansion coefficient matching insulation layer, the number of repetitions of the stacking units of the first insulator layer and the second insulator layer is more than 2, so that the thickness of the gradient thermal expansion coefficient matching insulation layer meets the side insulation requirements of the through silicon via.
6. The through-silicon via as described in claim 5, characterized in that: In the gradually varying thermal expansion coefficient matching insulation layer, the number of repetitions of the superposition unit of the first insulator layer and the second insulator layer is 3.
7. The through-silicon via as described in claim 1, characterized in that: The first metal layer is a copper layer; An adhesion barrier layer is also formed on the surface of the gradient thermal expansion coefficient matching insulating layer and the bottom surface of the through silicon via trench; A copper seed crystal layer is formed on the surface of the adhesive barrier layer.
8. The through-silicon via as described in claim 7, characterized in that: The adhesion barrier layer comprises a Ta layer and a TaN layer stacked sequentially.
9. A method for manufacturing a through-silicon via (TSV), characterized in that, Includes the following steps: A silicon via trench is formed by patterning and etching a silicon substrate. A gradient thermal expansion coefficient matching insulating layer is formed on the side of the through-silicon via trench; A first metal layer is filled into the through-silicon via trench to form a through-silicon via; The gradient thermal expansion coefficient matching insulating layer has a gradient thermal expansion coefficient structure and utilizes the gradient thermal expansion coefficient structure to reduce the thermal stress between silicon and the first metal layer at the side of the through silicon via trench during thermal processes, thereby improving the electrical reliability of the through silicon via.
10. The method for manufacturing through-silicon vias as described in claim 9, characterized in that: The gradient thermal expansion coefficient matching insulation layer is composed of multiple layers of insulators with different thermal expansion coefficients stacked together.
11. The method for manufacturing through-silicon vias as described in claim 10, characterized in that: The insulator layer includes a first insulator layer and a second insulator layer, and the first insulator layer and the second insulator layer are made of different materials; The gradually varying coefficient of thermal expansion matching insulation layer is composed of alternating first and second insulator layers.
12. The method for manufacturing through-silicon vias as described in claim 11, characterized in that: The material of the first insulator layer includes silicon dioxide; the material of the second insulator layer includes silicon nitride. The steps for forming the graded thermal expansion coefficient matching insulation layer include: Silicon dioxide and silicon nitride are deposited alternately in sequence using a CVD process to form an alternating arrangement of the first insulator layer and the second insulator layer.
13. The method for manufacturing through-silicon vias as described in claim 12, characterized in that: In the gradient thermal expansion coefficient matching insulation layer, the number of repetitions of the stacking units of the first insulator layer and the second insulator layer is more than 2, so that the thickness of the gradient thermal expansion coefficient matching insulation layer meets the side insulation requirements of the through silicon via.
14. The method for manufacturing through-silicon vias as described in claim 13, characterized in that: In the gradually varying thermal expansion coefficient matching insulation layer, the number of repetitions of the superposition unit of the first insulator layer and the second insulator layer is 3.
15. The method for manufacturing through-silicon vias as described in claim 9, characterized in that: The first metal layer is a copper layer, formed by electroplating; the process prior to forming the first metal layer includes: An adhesion barrier layer is also formed on the surface of the insulating layer with the gradient thermal expansion coefficient and on the bottom surface of the through-silicon via trench; A copper seed crystal layer is formed on the surface of the adhesive barrier layer.
16. The method for manufacturing through-silicon vias as described in claim 15, characterized in that: The adhesion barrier layer comprises a Ta layer and a TaN layer stacked sequentially.
17. The method for manufacturing through-silicon vias as described in claim 15, characterized in that: After the electroplating process of the first metal layer is completed, the process further includes: The silicon substrate surface is planarized by performing a chemical mechanical polishing process.