Support plate structure, preparation method of support plate structure and chip structure

Abstract

The embodiment of the invention provides a carrier plate structure, a preparation method of the carrier plate structure and a chip structure. The carrier plate structure comprises a substrate, a first insulating layer and a first conductive layer. The substrate is provided with a through hole penetrating through the substrate in the thickness direction of the carrier plate structure, and a conductive column is arranged in the through hole. The first insulating layer is located on at least one side of the substrate in the thickness direction of the carrier plate structure, the first insulating layer is provided with a first via hole, and the first insulating layer comprises 20-90 wt% of a resin material and 10-80 wt% of silicon-containing microspheres relative to the total weight of the first insulating layer. The first conductive layer is arranged on the first insulating layer and comprises a plurality of first wires arranged at intervals, and the first wires are electrically connected with the conductive columns through the first via holes. The thermal expansion coefficient of the first insulating layer is 0.9-1.1 times of the thermal expansion coefficient of the substrate, so that the thermal expansion coefficient of the first insulating layer is better matched with that of the adjacent film layer. Therefore, the problems of warping, deformation and unevenness of the first insulating layer and other film layers are reduced, and the yield of the carrier plate structure is further improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit equipment technology, and in particular to a substrate structure, a method for preparing the substrate structure, and a chip structure. Background Technology

[0002] The substrate structure of an integrated circuit (IC), also known as the IC packaging substrate, is used directly to mount the IC. It not only provides support and protection for the IC but also enables the connection between the IC and the printed circuit board (PCB). In short, the substrate structure is a core element that supports the IC and enables high-speed communication and effective heat dissipation between the IC and the external environment.

[0003] The existing carrier plate structure has poor insulation layer flatness, and the film layers are prone to warping and deformation, resulting in a low yield of the carrier plate structure. Summary of the Invention

[0004] This application provides a substrate structure, a method for fabricating the substrate structure, and a chip structure, aiming to improve the yield of the substrate structure.

[0005] An embodiment of the first aspect of this application provides a carrier structure, a substrate having a through-hole extending through the substrate along the thickness direction of the carrier structure, and a conductive post disposed within the through-hole. A first insulating layer is located on one side of the substrate along the thickness direction of the carrier structure, and the first insulating layer has a first via. The first insulating layer comprises: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer. A first conductive layer is disposed on the side of the first insulating layer opposite to the substrate and includes a plurality of first conductive lines spaced apart, the first conductive lines being electrically connected to the conductive post via the first via. The coefficient of thermal expansion of the first insulating layer is equal to 0.9-1.1 times the coefficient of thermal expansion of the substrate.

[0006] According to an embodiment of the first aspect of this application, the resin material comprises a cross-linked polymer.

[0007] According to any of the foregoing embodiments of the first aspect of this application, the diameter of the silicon-containing microspheres is 30nm-2000nm.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the coefficient of thermal expansion of the first insulating layer is 3ppm / °C - 60ppm / °.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the coefficient of thermal expansion of the resin material is less than or equal to 60 ppm / °C.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the number of layers of the first insulating layer is n, the number of layers of the first conductive layer is n-1 or n, where n is a natural number from 1 to 20, and the first insulating layer and the first conductive layer are alternately stacked.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the substrate is provided with the first insulating layer and the first conductive layer on both sides along the thickness direction of the carrier plate structure.

[0012] According to any of the foregoing embodiments of the first aspect of this application, a second conductive layer is further included, located between the substrate and the first insulating layer. The second conductive layer includes a plurality of second conductive wires spaced apart. One end of each second conductive wire is electrically connected to the first conductive wire via the first via, and the other end of each second conductive wire is used to connect to the conductive post.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the first insulating layer has a first sub-part and a second sub-part, the second sub-part is disposed around at least a portion of the first sub-part, the first via is located in the first sub-part, the orthographic projection of the first conductor on the substrate at least partially overlaps with the orthographic projection of the first sub-part on the substrate, wherein the proportion of silicon-containing microspheres in the first sub-part is greater than or equal to the proportion of silicon-containing microspheres in the second sub-part.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the first conductor on the substrate is within the orthographic projection of the first sub-part on the substrate.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the first conductor extends along a first direction, the second direction is the width direction of the first conductor, the minimum width of the first sub-part along the second direction is 5μm-100μm, the first direction intersects the second direction, and / or, along a direction parallel to the plane where the carrier plate structure is located, the minimum distance from the sidewall of the first sub-part to the sidewall of the first conductor is 0-5μm.

[0016] A second aspect of this application provides a method for preparing a carrier plate structure, comprising: A through-hole is formed in the substrate, and a conductive post is formed within the through-hole in the substrate.

[0017] A first insulating material is coated on one side of a substrate along its thickness direction and baked to form a first insulating layer, the first insulating layer having a first via. The first insulating material comprises: 5-20% by weight of resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent relative to the total weight of the first insulating material layer.

[0018] A first conductive material layer is prepared on the side of the first insulating layer away from the substrate, and the first conductive material layer is patterned to form the first conductive layer. The first conductive layer includes a plurality of first wires spaced apart, and one end of the first wire is electrically connected to the conductive post by the first via.

[0019] According to an embodiment of the second aspect of this application, a first insulating material is coated on one side of a substrate along its thickness direction and baked to form a first insulating layer, the first insulating layer having a first via. The first insulating material comprises, relative to the total weight of the first insulating material layer, 5-20% by weight of a resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent. The first insulating material layer is baked at a temperature of less than or equal to 300°C for less than or equal to 30 minutes to form the first insulating layer, the first insulating layer comprising: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer.

[0020] Alternatively, a first insulating material is coated onto one side of the substrate along its thickness direction and baked to form a first insulating layer, the first insulating layer having a first via. The first insulating material comprises, relative to the total weight of the first insulating material layer, 5-20% by weight of a resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent. Prior to this step, the method further includes: A solution to be treated is prepared, wherein the solvent of the solution to be treated includes N-methylpyrrolidone, and the solute of the solution to be treated includes polyimide.

[0021] Silicon-containing microspheres are added to the solution to be treated to form the first insulating material.

[0022] According to any of the foregoing embodiments of the second aspect of this application, the first insulating layer comprises: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer.

[0023] According to any of the foregoing embodiments of the second aspect of this application, the resin material comprises a cross-linked polymer.

[0024] According to any of the foregoing embodiments of the second aspect of this application, the resin material includes polyimide, and / or the preset solvent includes N-methylpyrrolidone.

[0025] According to any of the foregoing embodiments of the second aspect of this application, the first insulating layer comprises: 20-90% by weight of polyimide and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer, and / or the first insulating material comprises: 5-20% by weight of polyimide, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of N-methylpyrrolidone relative to the total weight of the first insulating material layer.

[0026] According to any of the foregoing embodiments of the second aspect of this application, the coefficient of thermal expansion of the first insulating layer is equal to 0.9-1.1 times the coefficient of thermal expansion of the substrate.

[0027] According to any of the foregoing embodiments of the second aspect of this application, in the first insulating material, the content of polyimide is a, the content of N-methylpyrrolidone is b, wherein a / (a+b)≤20%.

[0028] According to any of the foregoing embodiments of the second aspect of this application, the diameter of the silicon-containing microspheres is 30nm-2000nm.

[0029] According to any of the foregoing embodiments of the second aspect of this application, the coefficient of thermal expansion of the first insulating layer is 3ppm / °C - 60ppm / °C.

[0030] According to any of the foregoing embodiments of the second aspect of this application, a first insulating material is coated on one side of a substrate along its thickness direction and baked to form a first insulating layer, the first insulating layer having a first via. The first insulating material comprises, relative to the total weight of the first insulating material layer, 5-20% by weight of a resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent. Prior to this step, the method further includes: A second conductive material layer is prepared on the substrate, and the second conductive material layer is patterned to form a second conductive layer. The second conductive layer includes a plurality of second conductive lines spaced apart. One end of each second conductive line is electrically connected to the first conductive line via the first via, and the other end of each second conductive line is used to connect to the conductive post.

[0031] Alternatively, a first conductive material layer may be prepared on the side of the first insulating layer facing away from the substrate, and the first conductive material layer may be patterned to form the first conductive layer, wherein the first conductive layer includes a plurality of spaced first wires, and one end of each first wire is electrically connected to the conductive post via the first via. Following this step, the method may further include: A second insulating layer is prepared on the side of the first conductive layer opposite to the first insulating layer, the second insulating layer having a second via, at least a portion of the first conductive layer being exposed through the second via.

[0032] According to any of the foregoing embodiments of the second aspect of this application, the substrate is provided with the first insulating layer and the first conductive layer on both sides along the thickness direction of the carrier plate structure.

[0033] A third aspect of this application provides a chip structure, including a substrate structure as described in any of the preceding claims or a substrate structure prepared by a method for preparing a substrate structure as described in any of the preceding claims.

[0034] In the carrier structure, carrier structure fabrication method, and chip structure provided in this application embodiment, the carrier structure includes a substrate, a first insulating layer, and a first conductive layer. The substrate provides good support to the first insulating layer to improve the stability of the relative position between the first conductive layer and the first insulating layer. The substrate has a through-hole penetrating the substrate along the thickness direction of the carrier structure, and a conductive post is sleeved in the through-hole. The first insulating layer is used to provide insulation between adjacent metal traces. The first insulating layer is located on at least one side of the substrate along the thickness direction of the carrier structure, and the first insulating layer has a first via. The first insulating layer comprises: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer. The first conductive layer is disposed on the first insulating layer and includes a plurality of first conductive lines spaced apart. The first conductive lines are electrically connected to the conductive post by the first via. In this application embodiment, by adjusting the proportion of added resin material and silicon-containing microspheres, the thermal expansion coefficient of the first insulating layer can be made equal to 0.9-1.1 times the thermal expansion coefficient of the substrate, thereby making the thermal expansion coefficient of the first insulating layer more compatible with adjacent film layers. This reduces thermal stress between film layers, minimizes warping, deformation, and unevenness of the first insulating layer and other film layers, thereby further improving the yield of the carrier plate structure. Attached Figure Description

[0035] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0036] Figure 1 This is a cross-sectional view of a carrier plate structure provided in an embodiment of this application; Figure 2 This is a cross-sectional view of a carrier plate structure provided in another embodiment of this application; Figure 3 This is a schematic diagram of the structure of the first insulating layer of a carrier plate structure provided in an embodiment of this application; Figure 4 This is a cross-sectional view of a carrier plate structure provided in another embodiment of this application; Figure 5 yes Figure 2 A magnified view of a section at point M; Figure 6 yes Figure 1 A magnified view of a portion of point N in the middle; Figure 7 This is a schematic diagram of a method for preparing a carrier plate structure according to an embodiment of this application; Figures 8 to 9 This is a process diagram illustrating the fabrication of a carrier plate structure provided in an embodiment of this application; Figure 10 This is one of the schematic flowcharts of a method for preparing a carrier plate structure provided in another embodiment of this application; Figure 11 This is a second schematic diagram of a method for preparing a carrier plate structure according to another embodiment of this application; Figure 12 This is a process diagram of the fabrication of a carrier plate structure according to another embodiment of this application; Figure 13 This is a schematic flowchart of a method for preparing a carrier plate structure according to another embodiment of this application; Figure 14 This is a process diagram of the fabrication of a carrier plate structure provided in another embodiment of this application; Figure 15 This is a schematic flowchart of a method for preparing a carrier plate structure according to another embodiment of this application; Figure 16 This is a process diagram of the fabrication of a carrier plate structure provided in another embodiment of this application; Figure 17 This is a schematic diagram of a method for preparing a carrier plate structure according to another embodiment of this application.

[0037] Explanation of reference numerals in the attached figures: 10. Carrier structure; 20. Substrate; 21. Through-hole; 22. Conductive pillar; 30. Integrated circuit; 40. Encapsulation insulating layer; 100, First insulating layer; 110, First via; 120, First sub-section; 130, Second sub-section; 150, Silicon-containing microspheres; 200, First conductive layer; 201, First conductive material layer; 210, First wire; 300. Second insulating layer; 310. Second via; 400, Second conductive layer; 410, Second conductive wire; 500. Solder section; 510. Conductive plating; 600. Filling section; Y, second direction; Z, thickness direction. Detailed Implementation

[0038] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0039] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0041] Glass packaging substrates are key components connecting integrated circuits and external printed circuit boards. With the increasing technological demands for large chips due to high computing power and manpower requirements, the industry needs to develop large-size chip packaging substrates with high wiring density. During substrate fabrication, photoresist materials can be used for the intermetallic insulating layer; however, photoresist has poor leveling properties and cannot fill the height differences between metal lines.

[0042] Besides using photoresist materials, the insulating layer can also be made of polyimide. However, polyimide has a high coefficient of thermal expansion. During the use of the carrier board, the heat generated by the traces will be absorbed by the insulating layer, causing it to expand. This results in the insulating layer warping and deforming, and poor flatness, leading to a low yield of the carrier board structure.

[0043] To address the aforementioned problems, this application provides a carrier plate structure. The following is a detailed description... Figures 1 to 17 The carrier structure, the method for preparing the carrier structure, and the chip structure of the embodiments of this application are described in detail.

[0044] Please refer to the following: Figure 1 and Figure 3 , Figure 1 This is a cross-sectional view of a carrier plate structure provided in an embodiment of this application. Figure 2 This is a cross-sectional view of a carrier plate structure provided in another embodiment of this application. Figure 3 This is a schematic diagram of the structure of the first insulating layer of a carrier plate structure provided in an embodiment of this application.

[0045] like Figure 1 and Figure 3 As shown, an embodiment of the first aspect of this application provides a carrier structure 10 for connecting an integrated circuit 30 and a printed circuit board. The carrier structure 10 includes a substrate 20, a first insulating layer 100, and a first conductive layer 200. The substrate 20 has a through hole 21 extending through the substrate 20 along the thickness direction Z, and a conductive post 22 is disposed within the through hole 21. The first insulating layer 100 is located on at least one side of the substrate 20 along the thickness direction Z of the carrier structure 10, and the first insulating layer 100 has a first via 110. The first insulating layer 100 comprises: 20-90% by weight of resin material relative to the total weight of the first insulating layer 100, and 10-80% by weight of silicon-containing microspheres 150. The first conductive layer 200 is disposed on the first insulating layer 100 and includes a plurality of first conductive lines 210 spaced apart, the first conductive lines 210 being electrically connected to the conductive posts 22 via the first via 110. The coefficient of thermal expansion of the first insulating layer 100 is 0.9-1.1 times that of the substrate 20. The silicon-containing microspheres can be silicon microspheres or silicon oxide microspheres.

[0046] In the carrier structure 10 provided in the embodiments of this application, the carrier structure 10 includes a substrate 20, a first insulating layer 100 and a first conductive layer 200.

[0047] The substrate 20 can provide good support to the first insulating layer 100 to improve the stability of the relative position between the first conductive layer 200 and the first insulating layer 100.

[0048] Optionally, the substrate 20 includes at least one of a glass substrate, a silicon substrate, a ceramic substrate, a polymer substrate, etc.

[0049] Optionally, the substrate 20 can be a glass substrate. Exemplarily, the substrate 20 is at least one of borosilicate glass, aluminoborosilicate glass, quartz glass, alkali-free glass, and alkaline glass. Specifically, glass substrates not only possess advantages in material properties such as high modulus, high flatness, a wide coefficient of thermal expansion, and good chemical and high-temperature resistance, but also optical and mechanical advantages. This not only facilitates the smooth progress of laser processing but also meets the high-precision manufacturing requirements of semiconductor devices, reducing the impact on chip performance and packaging quality caused by dimensional deviations and / or damage to the carrier plate during chip stacking and other processes. The substrate 20 has a through-hole 21 extending through the substrate 20 along the thickness direction Z of the carrier plate structure 10, and a conductive post 22 is fitted inside the through-hole 21.

[0050] Optionally, when the substrate 20 is a glass substrate, the via 21 can also be a through-glass via (TGV). A through-glass via is a structure that achieves electrical interconnection through holes in a glass substrate, similar to a through-silicon via (TSV), and has the capability for three-dimensional interconnection. TGVs have advantages such as excellent electrical properties, optical properties, mechanical stability, and low cost, and have broad application prospects in advanced packaging, integrated passive devices, and optoelectronic device integration.

[0051] The first insulating layer 100 is used to provide insulation between adjacent metal traces. The first insulating layer 100 is located on at least one side of the substrate 20 along the thickness direction Z of the carrier structure 10, and the first insulating layer 100 has a first via 110.

[0052] The first conductive layer 200 is disposed on the first insulating layer 100 and includes a plurality of first wires 210 spaced apart. The first wires 210 are used to connect the conductive post 22 and the integrated circuit or printed circuit board. The first wires 210 are electrically connected to the conductive post 22 through the first via 110.

[0053] Optionally, the materials of the conductive post 22 and the first wire 210 include metallic materials, such as, but not limited to, at least one of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), tin (Sn), silver (Ag), etc.

[0054] Optionally, the material containing the silicon microspheres 150 includes silicon or silicon oxide.

[0055] The first insulating layer 100 comprises, relative to its total weight, 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres 150. For example, the first insulating layer 100 may comprise 10% by weight of silicon-containing microspheres 150 and 90% by weight of resin material, 35% by weight of silicon-containing microspheres 150 and 65% by weight of resin material, 50% by weight of silicon-containing microspheres 150 and 50% by weight of resin material, 65% by weight of silicon-containing microspheres 150 and 35% by weight of resin material, or 80% by weight of silicon-containing microspheres 150 and 20% by weight of resin material. The resin material includes polyimide, which has good flexibility, adhesion, and film-forming properties, as well as good insulating properties, while the silicon-containing microspheres 150 have a lower coefficient of thermal expansion than the resin material. This ratio allows the first insulating layer 100 to be easily processed and coated while also providing good heat dissipation and a low dielectric constant.

[0056] In this embodiment, by adjusting the ratio of added resin material and silicon-containing microspheres 150, the coefficient of thermal expansion of the first insulating layer 100 is made to be 0.9-1.1 times that of the substrate 20. For example, the coefficient of thermal expansion of the first insulating layer 100 is 0.9, 0.95, 1.0, 1.05, or 1.1 times that of the substrate 20. This allows the coefficient of thermal expansion of the first insulating layer 100 to better match that of adjacent film layers (such as silicon chips or ceramic substrates). This reduces thermal stress between film layers, minimizes warping, deformation, and unevenness of the first insulating layer 10 and other film layers, and further improves the yield of the substrate structure 10.

[0057] Optionally, the first conductor 210 may include a straight segment, which may extend along a first direction or a second direction Y. The first conductor 210 may also include an inclined segment, which extends at an angle relative to the first direction or the second direction Y. This application embodiment uses the extension of the first conductor 210 along the first direction as an example. This application does not limit the extension direction and shape of the first conductor 210.

[0058] In some alternative embodiments, such as Figure 3 As shown, the resin material includes cross-linked polymers.

[0059] In these optional embodiments, the resin material may include cross-linked polymers instead of non-cross-linked polymers. The molecular chains of cross-linked polymers are linked by covalent bonds into a three-dimensional network structure, resulting in better thermosetting and mechanical properties, while reducing the flow and thermal decomposition of the resin material at high temperatures. This can reduce large temperature fluctuations during the preparation and use of the carrier structure 10, reduce thermal stress and warpage between the insulating layer and other film layers, reduce energy consumption, and improve product yield. The resin material, including cross-linked polymers, has good film-forming properties and adhesion, facilitating the encapsulation of silicon-containing microspheres 150 while also promoting film formation. This allows the first insulating layer 100 to possess both good film-forming characteristics and thermal stability.

[0060] Optionally, the diameter of the silicon-containing microspheres 150 is 30nm-2000nm. For example, the diameter of the silicon-containing microspheres 150 can be 30nm, 500nm, 1000nm, 1500nm, or 2000nm. This can reduce the interlayer thermal stress of the first insulating layer 100 and help enhance the interfacial bonding between the silicon-containing microspheres 150 and the resin material, thereby further improving the flatness of the first insulating layer 100.

[0061] Optionally, the coefficient of thermal expansion of the first insulating layer 100 is 3ppm / °C to 60ppm / °C. Alternatively, the coefficient of thermal expansion of the first insulating layer 100 is 3ppm / °C to 10ppm / °C. For example, the coefficient of thermal expansion of the first insulating layer 100 can be 3ppm / °C, 5ppm / °C, 10ppm / °C, 15ppm / °C, 20ppm / °C, 40ppm / °C, or 60ppm / °C. Controlling the coefficient of thermal expansion of the first insulating layer 100 within a low range enables good thermal matching with key components such as semiconductor chips or glass substrates. This reduces the internal stress caused by thermal expansion mismatch between materials during temperature changes in the first insulating layer 100, thereby effectively improving the problems of cracking, warping, or interface peeling between the first insulating layer 100 and other film layers, and extending the service life of the carrier structure 10.

[0062] Optionally, the coefficient of thermal expansion of the silicon-containing microspheres 150 is less than or equal to 5 ppm / °C. For example, the coefficient of thermal expansion of the silicon-containing microspheres 150 can be 1 ppm / °C, 2 ppm / °C, 3 ppm / °C, 4 ppm / °C, or 5 ppm / °C. The silicon-containing microspheres 150 have a low coefficient of thermal expansion and high thermal stability, which can reduce the coefficient of thermal expansion of the first insulating layer 100, reduce the interlayer thermal stress between the first insulating layer 100 and other film layers, improve the degree of expansion of the first insulating layer 100 when heated, and improve the service life of the carrier structure 10.

[0063] Optionally, the resin material includes at least one of polyimide and epoxy resin, wherein polyimide and epoxy resin have high temperature resistance, high mechanical strength, and good film-forming processability.

[0064] Optionally, the coefficient of thermal expansion of the resin material is less than or equal to 60 ppm / °C. Alternatively, the coefficient of thermal expansion of the resin material is less than or equal to 20 ppm / °C. For example, the coefficient of thermal expansion of the resin material can be equal to 5 ppm / °C, 10 ppm / °C, 15 ppm / °C, 20 ppm / °C, 30 ppm / °C, 40 ppm / °C, or 60 ppm / °C. This satisfies the requirements for interfacial stability and internal structural integrity of the first insulating layer 100.

[0065] In some alternative embodiments, such as Figure 1 As shown, the first insulating layer 100 has n layers, and the first conductive layer 200 has n layers, where n is a natural number from 1 to 20.

[0066] In these optional embodiments, the number of layers of the first insulating layer 100 can be n, and the number of layers of the first conductive layer 200 can be n. For example, the number of layers of the first insulating layer 100 can be 1, 5, 10, 15, or 20, and the number of layers of the first conductive layer 200 can be 1, 5, 10, 15, or 20, respectively. The number of layers of the first insulating layer 100 and the number of layers of the first conductive layer 200 are set in a one-to-one correspondence to meet the insulation requirements of the first conductor 210.

[0067] Alternatively, in some other alternative embodiments, such as Figure 4 As shown, the first insulating layer 100 has n layers, and the first conductive layer 200 has n-1 layers, where n is a natural number from 1 to 20. For example, a second conductive layer 400 can also be disposed between the first insulating layer 100 and the substrate 20. In this case, the number of layers of the first insulating layer 100 can be 1, 5, 10, 15, or 20, and the number of layers of the first conductive layer 200 can be 0, 4, 9, 14, or 19, respectively. When the second conductive layer 400 is fabricated directly on the substrate 20, one less layer of the first insulating layer 100 can be fabricated to meet the insulation requirements of the first wire 210.

[0068] In some alternative embodiments, such as Figure 4 As shown, the second conductive layer 400 is located between the first insulating layer 100 and the substrate 20. The second conductive layer 400 includes a plurality of second wires 410 spaced apart. One end of the second wire 410 is electrically connected to the first wire 210 through the first via 110, and the other end of the second wire 410 is used to connect to the conductive post 22.

[0069] In these alternative embodiments, a metal layer can be prepared on the substrate 20 first, and then an insulating layer can be prepared on the metal layer. For example, in this embodiment, a second conductive layer 400 is first formed on the substrate 20, and then a first insulating layer 100 is prepared on the second conductive layer 400, which can reduce the number of first insulating layers 100 prepared.

[0070] In some alternative embodiments, such as Figure 1 and Figure 5 As shown, the first insulating layer 100 has a first sub-part 120 and a second sub-part 130. The second sub-part 130 is disposed around at least a portion of the first sub-part 120. A first via 110 is located in the first sub-part 120. The orthographic projection of the first conductor 210 on the substrate 20 overlaps at least partially with the orthographic projection of the first sub-part 120 on the substrate 20. The proportion of silicon-containing microspheres 150 in the first sub-part 120 is greater than or equal to the proportion of silicon-containing microspheres 150 in the second sub-part 130.

[0071] In this context, the proportion of silicon-containing microspheres 150 in the first sub-part 120 being greater than or equal to the proportion of silicon-containing microspheres 150 in the second sub-part 130 can be understood as follows: the density of silicon-containing microspheres 150 in the first sub-part 120 being greater than or equal to the density of silicon-containing microspheres 150 in the second sub-part 130; or, the diameter of silicon-containing microspheres 150 in the first sub-part 120 being greater than or equal to the diameter of silicon-containing microspheres 150 in the second sub-part 130. It is sufficient that the proportion of silicon-containing microspheres 150 in the first sub-part 120 is greater than or equal to the proportion of silicon-containing microspheres 150 in the second sub-part 130.

[0072] In these optional embodiments, the orthographic projection of the first conductive line 210 onto the substrate 20 at least partially overlaps with the orthographic projection of the first sub-part 120 onto the substrate 20. During use of the carrier structure 10, the heat received by the first sub-part 120 from the first conductive line 210 is greater than the heat received by the second sub-part 130 from the first conductive line 210. Therefore, the proportion of silicon-containing microspheres 150 in the first sub-part 120 is greater than or equal to the proportion of silicon-containing microspheres 150 in the second sub-part 130, resulting in better heat dissipation capacity and a lower coefficient of thermal expansion for the first sub-part 120, to match the higher thermal stress in the area where the first conductive line 210 is located, further reducing the possibility of warping of the first sub-part 120. Meanwhile, the second sub-part 130 can maintain a higher resin content to maintain overall adhesion and a certain degree of flexibility.

[0073] Optionally, the orthographic projection of the first conductor 210 onto the substrate 20 is within the orthographic projection of the first sub-part 120 onto the substrate 20. The first sub-part 120 can cover the first conductor 210 as much as possible to reduce the thermal stress in the area where the first conductor 210 is located.

[0074] Optionally, the first conductor 210 can extend along a first direction, and the second direction Y is the width direction of the first conductor 210. The minimum width of the first sub-part 120 along the second direction Y is 5μm-100μm. For example, the minimum width of the first sub-part 120 can be 5μm, 30μm, 50μm, 70μm, or 100μm. This can reduce the problem of insufficient coverage of the first trace caused by the minimum width of the first sub-part 120 being too small, and can also reduce the problem of difficult fabrication caused by the minimum width of the first sub-part 120 being too large.

[0075] Optionally, along a direction parallel to the plane of the carrier structure 10, the minimum distance from the sidewall of the first sub-part 120 to the sidewall of the first conductor 210 is 0-5 μm. For example, the minimum distance from the sidewall of the first sub-part 120 to the sidewall of the first conductor 210 is 0, 3.5 μm, 4 μm, 4.5 μm, or 5 μm. This can be understood as the first sub-part 120 covering the sidewall of the first conductor 210 to reduce thermal stress in the area where the first conductor 210 is located.

[0076] It should be noted that the minimum distance here can be the minimum distance from the side wall of the first sub-part 120 along the first direction to the side wall of the first conductor 210, or it can be the minimum distance from the side wall of the first sub-part 120 along the second direction Y to the side wall of the first conductor 210.

[0077] In some alternative embodiments, such as Figure 1 As shown, the carrier structure 10 also includes a second insulating layer 300, which is located on the side of the first conductive layer 200 away from the substrate 20. The second insulating layer 300 has a second via 310, through which at least a portion of the first conductor 210 is exposed.

[0078] Optionally, a solder section 500 is provided within the second via 310. This facilitates a stable connection between the first conductor 210 and the integrated circuit 30 via the solder section 500. The material of the solder section 500 may include solder or other welding materials, and the solder section 500 may be hemispherical.

[0079] Optional, such as Figure 6 As shown, a conductive plating layer 510 is provided between the first conductor 210 and the solder section 500, and at least a portion of the conductive plating layer 510 is located in the second via 310. By adding the conductive plating layer 510, the connection strength and connection stability between the solder section 500 and the first conductor 210 can be improved.

[0080] Optionally, the proportion of silicon-containing microspheres 150 in the first insulating layer 100 is greater than or equal to the proportion of silicon-containing microspheres 150 in the second insulating layer 300. This can be understood as follows: when the weight of the first insulating layer 100 is greater than or equal to the weight of the second insulating layer 300, or when the weight of the first insulating layer 100 is less than the weight of the second insulating layer 300, the proportion of silicon-containing microspheres 150 in the first insulating layer 100 is always greater than or equal to the proportion of silicon-containing microspheres 150 in the second insulating layer 300.

[0081] Optionally, the second insulating layer 300 has a third sub-part and a fourth sub-part 330. The fourth sub-part 330 is disposed around at least a portion of the third sub-part. The first via 110 is located in the third sub-part. The orthographic projection of the first conductor 210 on the substrate 20 at least partially overlaps with the orthographic projection of the third sub-part on the substrate 20. The proportion of silicon-containing microspheres 150 in the third sub-part is greater than or equal to the proportion of silicon-containing microspheres 150 in the fourth sub-part 330. During use of the carrier structure 10, the third sub-part receives more heat from the first conductor 210 than the fourth sub-part 330. Therefore, the weight of the silicon-containing microspheres 150 in the third sub-part is greater than or equal to the weight of the silicon-containing microspheres 150 in the fourth sub-part, resulting in better heat dissipation and a lower coefficient of thermal expansion in the third sub-part to match the higher thermal stress in the area where the first conductor 210 is located, further reducing the possibility of warping in the third sub-part. The fourth sub-part, on the other hand, can maintain a higher resin content to maintain the adhesion and a certain degree of flexibility of the first insulating layer 100.

[0082] Optionally, the orthographic projection of the first conductor 210 onto the substrate 20 is within the orthographic projection of the third sub-part onto the substrate 20. The third sub-part can cover the first conductor 210 as much as possible to reduce thermal stress in the area where the third conductor is located.

[0083] In this context, the proportion of silicon-containing microspheres 150 in the third sub-section being greater than or equal to the proportion of silicon-containing microspheres 150 in the fourth sub-section can be understood as either the density of silicon-containing microspheres 150 in the third sub-section being greater than or equal to the density of silicon-containing microspheres 150 in the fourth sub-section, or the diameter of silicon-containing microspheres 150 in the third sub-section being greater than or equal to the diameter of silicon-containing microspheres 150 in the fourth sub-section. As long as the proportion of silicon-containing microspheres 150 in the third sub-section is greater than or equal to the proportion of silicon-containing microspheres 150 in the fourth sub-section, the condition is met.

[0084] Optionally, the minimum width of the third sub-part along the second direction Y is 5μm-100μm. For example, the minimum width of the third sub-part can be 5μm, 30μm, 50μm, 70μm, or 100μm. This can reduce the problem of insufficient coverage of the first trace caused by the small minimum width of the first sub-part 120, and can also reduce the problem of difficult fabrication due to the large minimum width of the third sub-part.

[0085] Optionally, along a direction parallel to the plane of the carrier plate structure 10, the minimum distance from the sidewall of the third sub-part to the sidewall of the first conductor 210 is 0-5 μm. For example, the minimum distance from the sidewall of the third sub-part to the sidewall of the first conductor 210 is 0, 3.5 μm, 4 μm, 4.5 μm, or 5 μm. This can be understood as the third sub-part covering the sidewall of the first conductor 210 to reduce thermal stress in the area where the first conductor 210 is located.

[0086] It should be noted that the minimum distance here can be the minimum distance from the side wall of the third sub-part along the first direction to the side wall of the first conductor 210, or it can be the minimum distance from the side wall of the third sub-part along the second direction Y to the side wall of the first conductor 210.

[0087] A second aspect of this application provides a method for fabricating a carrier structure 10, which is used to connect an integrated circuit 30 and a printed circuit board, such as... Figure 7 As shown, the method includes: Step S000: A through hole 21 is formed in the substrate 20 and a conductive post 22 is formed in the through hole 21 of the substrate 20. Step S100: As Figure 8 As shown, a first insulating material is coated on one side of the substrate 20 along its thickness direction Z and baked to form a first insulating layer 100. The first insulating layer 100 has a first via 110. The first insulating material comprises: 5-20% by weight of resin material, 0.5-16% by weight of silicon-containing microspheres 150, and 64-94.5% by weight of a preset solvent relative to the total weight of the first insulating material.

[0088] Step S200: As Figure 9 As shown, a first conductive material layer 201 is disposed on the side of the first insulating layer 100 away from the substrate 20. The first conductive material layer 201 is patterned to form a first conductive layer 200. The first conductive layer 200 includes a plurality of first wires 210 spaced apart. One end of the first wire 210 is electrically connected to the conductive post 22 through a first via 110, and the other end of the first wire 210 is used to connect to the integrated circuit 30.

[0089] In the method for preparing the carrier structure 10 provided in the second aspect embodiment of this application, a substrate 20 is prepared in step S000, a first insulating layer 100 is prepared in step S100, and a first conductive layer 200 is prepared in step S200. The carrier structure 10 prepared according to the embodiments of this application, by adjusting the ratio of added resin material and silicon-containing microspheres 150, coats the substrate 20 along its thickness direction Z with a first insulating material and bakes it to form the first insulating layer 100. After baking, the preset solvent can evaporate, and the remaining resin material and silicon-containing microspheres 150 after baking have a higher proportion, which makes the thermal expansion coefficient of the formed first insulating layer 100 more compatible with adjacent layers. This reduces the thermal stress between film layers, reduces warping, deformation, and unevenness of the first insulating layer 100 and other film layers, thereby further improving the yield of the carrier structure 10.

[0090] Optionally, in step S000, the method for forming the via 21 includes at least one of laser-induced wet etching, laser ablation, focused discharge machining, plasma etching, electrochemical discharge machining, and sandblasting. In this embodiment, laser-induced wet etching is preferably used to form the via 21 on the substrate 20. Optionally, the cross-sectional shape of the via 21 parallel to the direction of the via 21 includes rectangular, trapezoidal, V-shaped, and X-shaped shapes, etc., and is not limited in this application.

[0091] Optionally, in step S100, the preset solvent can be N-methylpyrrolidone. For example, the first insulating material may comprise: 5-20% by weight of resin material, 0.5-16% by weight of silica-containing microspheres 150, and 64-94.5% by weight of N-methylpyrrolidone, relative to the total weight of the first insulating material. For instance, the first insulating material may comprise: 10% by weight of resin material, 16% by weight of silica-containing microspheres 150, and 74% by weight of N-methylpyrrolidone, relative to the total weight of the first insulating material; the first insulating material may comprise: 15% by weight of resin material, 10% by weight of silica-containing microspheres 150, and 75% by weight of N-methylpyrrolidone, relative to the total weight of the first insulating material; the first insulating material may comprise: 15% by weight of resin material, 15% by weight of silica-containing microspheres 150, and 70% by weight of N-methylpyrrolidone, relative to the total weight of the first insulating material. Nitromethylpyrrolidone is volatile, which facilitates the formation of the first insulating layer 100.

[0092] Optionally, in step S200, processes such as electroplating, vapor deposition, deposition, and coating can be used to deposit the first conductive material layer 201 on one side of the first insulating layer 100. Dry etching, wet etching, or other processes can be used to pattern the first conductive material layer 201 to form the first conductive layer 200.

[0093] Optionally, in the process of preparing the first conductive layer 200 in step S200, the method further includes: first preparing a seed material layer on the first insulating layer 100, and then preparing the first conductive layer 200 on the seed material layer. The first conductive layer 200 includes a plurality of spaced first wires 210, and the first wires 210 can be used as a mask to pattern the seed material layer to form the seed layer.

[0094] Optionally, methods for preparing the seed layer include, but are not limited to, physical vapor deposition (PVD), evaporation, and electroless plating.

[0095] Optionally, the seed layer may be made of at least one of copper, titanium, nickel, etc.

[0096] Optionally, in step S200, a first via 110 can be formed by laser etching, thereby exposing the underlying metal through the first via 110.

[0097] In some alternative embodiments, such as Figure 10 As shown, step S100 also includes: Step S110: Prepare the solution to be treated. The solvent of the solution to be treated includes N-methylpyrrolidone, and the solute of the solution to be treated includes polyimide.

[0098] Step S120: Add silicon-containing microspheres 150 to the solution to be treated to form a first insulating material.

[0099] In these optional embodiments, the solution to be treated is prepared by steps S110 and S120. Optionally, the solvent of the solution to be treated may include N-methylpyrrolidone to facilitate the coating of as many silicon-containing microspheres 150 as possible when preparing the first insulating material.

[0100] Nitrogen-methylpyrrolidone (NMP) is volatile. After baking, most of the NMP evaporates, while a relatively high proportion of the remaining resin material and silicon-containing microspheres 150 are retained, which facilitates the formation of the first insulating layer 100. Optionally, the solution to be treated is not limited, as long as it is volatile and the remaining content of the resin material and silicon-containing microspheres 150 after baking is relatively high.

[0101] Alternatively, in some other alternative embodiments, such as Figure 11 and Figure 12 As shown, step S100 further includes step S130: baking the first insulating material at a temperature of less than or equal to 300°C for less than or equal to 30 minutes to form a first insulating layer 100, the first insulating layer 100 comprising: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer 100.

[0102] In these optional embodiments, the first insulating material prepared by the above-described materials can be baked to form the first insulating layer 100 without high temperature, resulting in smaller process temperature fluctuations. Furthermore, the proportion of remaining resin material and silicon-containing microspheres 150 after baking is relatively high, leading to a more compatible coefficient of thermal expansion between the first insulating layer 100 and adjacent layers. This reduces thermal stress between film layers and minimizes warping, deformation, and unevenness of the first insulating layer 100 and other film layers.

[0103] Optionally, the baking temperature can be less than or equal to 300°C. Optionally, the baking temperature can be less than or equal to 230°C. For example, the baking temperature can be 50°C, 100°C, 150°C, 200°C, 250°C, or 300°C. Optionally, the baking time can be less than or equal to 30 minutes, for example, 10 minutes, 15 minutes, 20 minutes, 25 minutes, or 30 minutes. This can improve the problem of the first insulating material being difficult to form a film due to excessively low baking temperature or short baking time, and at the same time improve the problem of the first insulating layer 100 being easily deformed due to excessively high baking temperature or long baking time.

[0104] Optionally, in the first insulating material, the content of polyimide is a, and the content of N-methylpyrrolidone is b, wherein a / (a+b)≤20%.

[0105] Optionally, the arrangement of the resin material, the silicon-containing microspheres 150, and the first insulating layer 100 is as described above and will not be repeated here. For example, the first insulating layer 100 comprises: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres 150 relative to the total weight of the first insulating layer 100. For example, the resin material includes polyimide. For example, the coefficient of thermal expansion of the resin material is less than or equal to 60 ppm / °C. For example, the coefficient of thermal expansion of the resin material is less than or equal to 20 ppm / °C. For example, the diameter of the silicon-containing microspheres 150 is 30 nm-2000 nm. For example, the coefficient of thermal expansion of the first insulating layer 100 is 3 pm / °C - 60 ppm / °C. For example, the coefficient of thermal expansion of the first insulating layer 100 is 3 pm / °C - 10 ppm / °C. For example, the resin material includes cross-linked polymers.

[0106] This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0107] In some alternative embodiments, such as Figure 13 As shown, the procedure before step S100 also includes: Step S001: As Figure 14As shown, a second conductive material layer is prepared on the substrate 20, and the second conductive material layer is patterned to form a second conductive layer 400. The second conductive layer 400 includes a plurality of second wires 410 spaced apart. One end of the second wire 410 is electrically connected to the first wire 210 through the first via 110, and the other end of the second wire 410 is used to connect to the conductive post 22.

[0108] In these alternative embodiments, the second conductive layer 400 can be prepared first and then the first insulating layer 100 can be prepared, which can reduce the number of first insulating layers 100 prepared and save process time.

[0109] In some alternative embodiments, such as Figure 15 and Figure 16 As shown, step S100 also includes: Step S130: A first submaterial layer and a second sub-part 130 are prepared on the substrate 20, the second sub-part 130 being disposed around at least a portion of the first submaterial layer.

[0110] Step S140: The first sub-material layer is patterned to form a first sub-part 120. The first sub-part 120 has a first via 110. The orthographic projection of the first conductor 210 on the substrate 20 at least partially overlaps with the orthographic projection of the first sub-part 120 on the substrate 20. The weight of the silicon-containing microspheres 150 of the first sub-part 120 is greater than or equal to the weight of the silicon-containing microspheres 150 of the second sub-part 130.

[0111] Optionally, the fabrication order of the first sub-part 120, the first via 110, and the second sub-part 130 is not limited. For example, the first sub-part 120 and the first via 110 can be fabricated first, followed by the second sub-part 130; the second sub-part 130 can be fabricated first, followed by the first sub-part 120 and the first via 110; or the first sub-part 120 and the second sub-part 130 can be fabricated first, followed by the first via 110. The specific fabrication order depends on the specific process requirements.

[0112] In these optional embodiments, the first sub-part 120 and the second sub-part 130 prepared according to the embodiments of this application have at least partial overlap between the orthographic projection of the first conductive line 210 on the substrate 20 and the orthographic projection of the first sub-part 120 on the substrate 20. During use of the carrier structure 10, the heat received by the first sub-part 120 from the first conductive line 210 is greater than the heat received by the second sub-part 130 from the first conductive line 210. Therefore, the weight of the silicon-containing microspheres 150 in the first sub-part 120 is greater than or equal to the weight of the silicon-containing microspheres 150 in the second sub-part 130, resulting in better heat dissipation capacity and a lower coefficient of thermal expansion for the first sub-part 120, to match the higher thermal stress in the area where the first conductive line 210 is located, further reducing the possibility of warping of the first sub-part 120. The second sub-part 130 can maintain a higher resin content to maintain overall adhesion and a certain degree of flexibility.

[0113] Optionally, the arrangement of the first conductor 210 and the first sub-part 120 is as described above, and will not be repeated here. For example, the orthographic projection of the first conductor 210 onto the substrate 20 is within the orthographic projection of the first sub-part 120 onto the substrate 20.

[0114] Alternatively, in some other alternative embodiments, such as Figure 17 As shown, after step S200, the following steps are also included: Step S300: As Figure 2 As shown, a second insulating layer 300 is prepared on the side of the first conductive layer 200 opposite to the first insulating layer 100. The second insulating layer 300 has a second via 310, through which at least a portion of the first conductive layer 200 is exposed.

[0115] In these alternative embodiments, the second insulating layer 300 can provide protection for the first conductor 210, while at least a portion of the first conductive layer 200 is exposed through the second via 310 to facilitate improved alignment accuracy during soldering of the integrated circuit 30 and the printed circuit board.

[0116] Optionally, after step S300, the method may further include: Figure 1 As shown, a solder section 500 is prepared on the side of the second insulating layer 300 away from the first conductor 210. One end of the solder section 500 is electrically connected to the first trace through the second via 310, and the other end of the solder section 500 is electrically connected to the integrated circuit 30 or the printed circuit board.

[0117] Optionally, the solder portion 500 may protrude from the surface of the second insulating layer 300 away from the first conductive layer 200, so as to facilitate the alignment and connection of the integrated circuit 30 or printed circuit board with the solder portion 500.

[0118] Optionally, after step S300, such as Figure 1 and Figure 6 As shown, a conductive plating layer 510 can be first prepared on the side of the second insulating layer 300 opposite to the first conductor 210, with at least a portion of the conductive plating layer 510 located in the second via 310. Then, a solder portion 500 is prepared on the conductive plating layer 510. By adding the conductive plating layer 510, the connection strength and stability between the solder portion 500 and the first conductor 210 can be improved.

[0119] Optional, such as Figure 1 As shown, after the solder section 500 is prepared, the integrated circuit 30 is soldered on the solder section 500 corresponding to one side of the glass substrate 20, and the printed circuit board (not shown in the figure) is soldered on the solder section 500 corresponding to the other side of the glass substrate 20.

[0120] Optionally, after soldering the integrated circuit 30, insulating material can be filled into the gap between the integrated circuit 30 and the second insulating layer 300 to form a filling portion 600, and an encapsulation insulating layer 40 can be prepared on the side of the integrated circuit 30 facing away from the second insulating layer 300 to provide encapsulation protection for the carrier structure 10. Finally, the carrier structure 10 and the encapsulation insulating layer 40 can be cut and shaped as needed.

[0121] The third aspect of this application also provides a chip structure, including a carrier board structure 10 prepared by the methods of preparing the carrier board structure 10 of any of the first aspect embodiments and the carrier board structure 10 of any of the second aspect embodiments. Since the chip structure of the third aspect embodiment includes the aforementioned carrier board structure 10, it benefits from the advantages of any of the aforementioned carrier board structures 10.

[0122] Optionally, the chip structure in this application embodiment can be used in a mobile terminal, which includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablets, personal computers, desktop computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0123] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A carrier plate structure, characterized in that, include: A substrate has a through hole that penetrates the substrate along the thickness direction of the carrier plate structure, and a conductive post is provided in the through hole; A first insulating layer is located on one side of the substrate along the thickness direction of the carrier structure, and the first insulating layer has a first through hole. The first insulating layer comprises: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer. A first conductive layer is disposed on the side of the first insulating layer away from the substrate and includes a plurality of first wires spaced apart, wherein the first wires are electrically connected to the conductive pillars through the first vias; Wherein, the coefficient of thermal expansion of the first insulating layer is equal to 0.9-1.1 times that of the coefficient of thermal expansion of the substrate.

2. The carrier plate structure according to claim 1, characterized in that, The resin material includes cross-linked polymers; Preferably, the diameter of the silicon-containing microspheres is 30nm-2000nm; Preferably, the coefficient of thermal expansion of the first insulating layer is 3ppm / °C - 60ppm / °C; Preferably, the coefficient of thermal expansion of the resin material is less than or equal to 60 ppm / °C.

3. The carrier plate structure according to claim 1, characterized in that, The first insulating layer has n layers, and the first conductive layer has n-1 layers or n layers, where n is a natural number from 1 to 20. The first insulating layer and the first conductive layer are stacked alternately. Preferably, the substrate has the first insulating layer and the first conductive layer on both sides along the thickness direction of the carrier plate structure.

4. The carrier plate structure according to claim 1, characterized in that, It also includes a second conductive layer located between the substrate and the first insulating layer. The second conductive layer includes a plurality of second wires spaced apart. One end of the second wire is electrically connected to the first wire through the first via, and the other end of the second wire is used to connect to the conductive post.

5. The carrier plate structure according to claim 1, characterized in that, The first insulating layer has a first sub-part and a second sub-part, the second sub-part surrounding at least a portion of the first sub-part, the first via located in the first sub-part, and the orthographic projection of the first conductor on the substrate at least partially overlapping the orthographic projection of the first sub-part on the substrate. Wherein, the proportion of silicon-containing microspheres in the first sub-part is greater than or equal to the proportion of silicon-containing microspheres in the second sub-part; Preferably, the orthographic projection of the first wire onto the substrate lies within the orthographic projection of the first sub-part onto the substrate; Preferably, the first conductor extends along a first direction, the second direction is the width direction of the first conductor, the minimum width of the first sub-part along the second direction is 5μm-100μm, the first direction intersects the second direction, and / or, along a direction parallel to the plane of the carrier structure, the minimum distance from the sidewall of the first sub-part to the sidewall of the first conductor is 0-5μm.

6. A method for preparing a carrier plate structure, characterized in that, include: A through hole is formed in the substrate, and a conductive pillar is formed in the through hole of the substrate; A first insulating material is coated on one side of a substrate along its thickness direction and baked to form a first insulating layer, the first insulating layer having a first via; the first insulating material comprises: 5-20% by weight of resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent relative to the total weight of the first insulating material. A first conductive material layer is prepared on the side of the first insulating layer away from the substrate, and the first conductive material layer is patterned to form a first conductive layer. The first conductive layer includes a plurality of first wires spaced apart, and one end of the first wire is electrically connected to the conductive post by the first via.

7. The method for preparing the carrier plate structure according to claim 6, characterized in that, The step of coating a first insulating material onto one side of a substrate along its thickness direction and baking it to form a first insulating layer, the first insulating layer having a first via; the first insulating material comprising: 5-20% by weight of resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent relative to the total weight of the first insulating material layer, further comprising: The first insulating material layer is baked at a temperature of less than or equal to 300°C for less than or equal to 30 minutes to form the first insulating layer, the first insulating layer comprising: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer; Alternatively, a first insulating material may be coated onto one side of the substrate along its thickness direction and baked to form a first insulating layer, the first insulating layer having a first via; the first insulating material comprises, relative to the total weight of the first insulating material layer, 5-20% by weight of resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent, and the step prior to this step further includes: A solution to be treated is prepared, wherein the solvent of the solution to be treated includes N-methylpyrrolidone, and the solute of the solution to be treated includes polyimide; Silicon-containing microspheres are added to the solution to be treated to form the first insulating material.

8. The method for preparing the carrier plate structure according to claim 6, characterized in that, The first insulating layer comprises: 20-90% by weight of resin material and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer; Preferably, the resin material comprises a cross-linked polymer; Preferably, the resin material comprises polyimide, and / or the preset solvent comprises N-methylpyrrolidone; Preferably, the first insulating layer comprises: 20-90% by weight of polyimide and 10-80% by weight of silicon-containing microspheres relative to the total weight of the first insulating layer, and / or, the first insulating material comprises: 5-20% by weight of polyimide, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of N-methylpyrrolidone relative to the total weight of the first insulating material layer; Preferably, the coefficient of thermal expansion of the first insulating layer is 0.9-1.1 times that of the coefficient of thermal expansion of the substrate; Preferably, in the first insulating material, the content of polyimide is a, and the content of N-methylpyrrolidone is b, wherein a / (a+b)≤20%; Preferably, the diameter of the silicon-containing microspheres is 30nm-2000nm; Preferably, the coefficient of thermal expansion of the first insulating layer is 3ppm / °C - 60ppm / °C.

9. The method for preparing the carrier plate structure according to claim 6, characterized in that, The first insulating layer is formed by coating a first insulating material onto one side of a substrate along its thickness direction and baking it. The first insulating layer has a first via. The first insulating material comprises, relative to the total weight of the first insulating material layer, 5-20% by weight of resin material, 0.5-16% by weight of silicon-containing microspheres, and 64-94.5% by weight of a predetermined solvent. Prior to this step, the method further includes: A second conductive material layer is prepared on the substrate, and the second conductive material layer is patterned to form a second conductive layer. The second conductive layer includes a plurality of second wires spaced apart. One end of the second wire is electrically connected to the first wire through the first via, and the other end of the second wire is used to connect to the conductive post. Alternatively, a first conductive material layer may be prepared on the side of the first insulating layer facing away from the substrate, and the first conductive material layer may be patterned to form a first conductive layer. The first conductive layer includes a plurality of spaced first wires, and one end of each first wire is electrically connected to the conductive post via the first via. Following this step, the method may further include: A second insulating layer is prepared on the side of the first conductive layer opposite to the first insulating layer, and the second insulating layer has a second via, through which at least a portion of the first conductive layer is exposed. Preferably, the substrate has the first insulating layer and the first conductive layer on both sides along the thickness direction of the carrier plate structure.

10. A chip structure, characterized in that, include: The carrier plate structure prepared by the method of any one of claims 1-5 or claims 6-9.

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