Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method. The packaging method comprises the following steps of: 1, etching a silicon through hole blind hole in a silicon intermediate layer; 2, depositing an insulating layer in the through-silicon-via blind hole, depositing a barrier layer / seed layer on the insulating layer, and forming a copper column in the through-silicon-via blind hole; 3, manufacturing a re-wiring layer and a micro-bump on the surface of the silicon interposer; 4, preparing a chip or a chip and an intermediate chip; step 5, mounting the chip or the chip and the intermediate chip on the silicon intermediate layer; step 6, temporarily bonding the semi-finished product obtained in the step 5 on a carrier plate; 7, performing plastic packaging on the semi-finished product obtained in the step 6; step 8, carrying out de-bonding on the carrier plate, and manufacturing a re-wiring layer structure and a bump on the surface of the silicon intermediate layer; and ninthly, cutting is conducted. According to the invention, the low-cost and large-size silicon interposer is adopted to replace a prefabricated substrate or a printed circuit board, so that system-level integration with larger size and higher cost performance can be realized, and a technical scheme is provided for ultra-large single-chip or multi-chip system integration.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a packaging structure and packaging method. Background Technology

[0002] System-in-package (SIP) is an advanced semiconductor packaging technology that integrates multiple chips and passive devices with different functions into the same package housing to assemble a complete, independently functioning system or subsystem.

[0003] Existing system-in-package (SIP) technologies primarily rely on traditional organic packaging substrates or printed circuit boards (PCBs) as the core carriers for multi-chip integration and interconnection. A typical structure involves mounting multiple semiconductor chips and passive devices onto a pre-fabricated substrate or PCB via wire bonding or flip-chip bonding, electrically interconnecting them through internal circuitry layers, and finally encapsulating and protecting them with a molding compound.

[0004] However, this traditional system-level packaging structure has several inherent problems: 1) Traditional substrates or printed circuit boards are limited by subtractive manufacturing processes, making it difficult to achieve fine wiring below the micrometer level, which limits I / O density and interconnection capabilities, making it difficult to meet the growing demand for high-performance computing. 2) For packaging ultra-large chips, manufacturing a high-density, high-layer-count packaging substrate that matches it is very expensive. Summary of the Invention

[0005] To address the problems in the prior art, the present invention aims to provide a packaging structure and packaging method.

[0006] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: An encapsulation method includes the following steps: Step 1: Etch through-silicon vias and blind vias on the prepared silicon interposer; Step 2: Deposit an insulating layer on the inner wall of the through-silicon via blind hole, deposit a barrier layer / seed layer on the insulating layer, and form copper pillars in the through-silicon via blind hole by electrochemical plating; Step 3: Fabricate a redistribution layer and microbumps on the surface of the silicon interposer; Step 4: Prepare the chip, or the chip and intermediate chip; Step 5: Mount the chip, or the chip and intermediate chip, onto the silicon interposer; Step Six: Temporarily bond the semi-finished product obtained in Step Five onto the carrier board; Step 7: The semi-finished product obtained in Step 6 is encapsulated to form an encapsulated body; during the encapsulation stage, through-holes in the encapsulation material are selectively created; Step 8: Debond the carrier board and fabricate a redistribution layer structure and bumps on the surface of the silicon interposer; Step 9: Cutting.

[0007] Furthermore, in step two, after the copper pillars are formed, chemical mechanical polishing is used to grind away excess copper, insulating layer, and barrier / seed layer on the surface, so that the surface of the copper pillars in the through-silicon via blind holes is planarized with the surface of the silicon interposer.

[0008] Furthermore, in step two, the insulating layer material is silicon dioxide or silicon nitride, and the barrier layer material is titanium or tantalum.

[0009] Furthermore, in step three, the thickness of the redistribution layer is 2 to 6 micrometers.

[0010] Furthermore, in step four, the active layer of the chip is fabricated with a redistribution structure and a microbump structure, wherein the thickness of the redistribution structure is 2 to 6 micrometers.

[0011] Furthermore, step five, the step of mounting the chip onto the silicon interposer, includes: A high-precision pick-and-place machine is used to pick up the chip and precisely align the microbump structure on the chip with the microbumps on the silicon interposer. The mechanical and electrical connection between the chip and the silicon interposer is completed through a reflow soldering process, followed by underfill.

[0012] Furthermore, step five, the step of mounting the chip onto the silicon interposer, includes: Two chips are bonded together back to back using bonding adhesive, precisely aligning the microbump structure on the chip with the microbump on the silicon interposer, and completing the mechanical and electrical connection between the chip and the silicon interposer through a reflow soldering process.

[0013] Furthermore, in step five, the step of mounting the chip and the intermediate chip onto the silicon interposer includes: A high-precision pick-and-place machine is used to pick up the intermediate chip and precisely align the first microbump on the first wiring layer of one side of the chip with the microbump on the silicon interposer. The mechanical and electrical connection between the intermediate chip and the silicon interposer is completed through reflow soldering. The high-precision pick-and-place machine is then used to pick up the chip and precisely align the microbump structure on the chip with the second microbump on the second wiring layer on the other side of the intermediate chip. The mechanical and electrical connection between the chip and the intermediate chip is completed through reflow soldering. Finally, underfill is applied to complete the three-dimensional stacking and mounting.

[0014] This invention also discloses a packaging structure prepared by a packaging method, including a silicon interposer, on which through-silicon vias (TSVs) are etched, an insulating layer is deposited on the inner wall of the TSVs, a barrier layer / seed layer is deposited on the insulating layer, copper pillars are formed in the TSVs by electrochemical plating, a redistribution layer and microbumps are disposed on the silicon interposer, a molding compound is formed on the silicon interposer, a chip or a chip-molding via is encapsulated in the molding compound, and a redistribution layer structure and bumps are formed on the side of the silicon interposer away from the molding compound.

[0015] This invention also discloses a packaging structure prepared by a packaging method, including a silicon interposer, on which through-silicon vias (TSVs) are etched, an insulating layer is deposited on the inner wall of the TSVs, a barrier layer / seed layer is deposited on the insulating layer, copper pillars are formed in the TSVs by electrochemical plating, a redistribution layer and microbumps are disposed on the silicon interposer, a molding compound is formed on the silicon interposer, and a chip and an intermediate chip or a chip, an intermediate chip and a molding compound via are encapsulated in the molding compound, with a redistribution layer structure and bumps formed on the side of the silicon interposer away from the molding compound.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves larger-size, more cost-effective system-level integration by using a low-cost, large-size silicon interposer instead of a prefabricated substrate or printed circuit board. It significantly improves packaging efficiency and greatly reduces the manufacturing cost per unit area, breaking the limitations of traditional packaging architecture on integration area and providing a technical solution for ultra-large single-chip or multi-chip system integration. Attached Figure Description

[0017] Figure 1 This is a structural schematic diagram of step one of the present invention; Figure 2 This is a schematic diagram of the structure of step two of the present invention; Figure 3 This is a schematic diagram of step three of the present invention; Figure 4 This is a structural schematic diagram of step four of the present invention; Figure 5 This is a schematic diagram of step five in Embodiment 1 of the present invention; Figure 6 This is a structural schematic diagram of step five in Embodiment 2 of the present invention; Figure 7 This is a schematic diagram of step six in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of step seven of Embodiment 1 of the present invention; Figure 9 This is a schematic diagram of step eight in Embodiment 1 of the present invention; Figure 10 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 11 This is a schematic diagram of the structure of Embodiment 4 of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0019] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0020] like Figure 1-11 As shown, this invention discloses a packaging method, comprising the following steps: Step 1: As Figure 1 As shown, through-silicon vias 2 are etched on the prepared silicon interposer 1; Step Two: As Figure 2 As shown, an insulating layer is deposited on the inner wall of the through-silicon via (TSV) blind via 2. The insulating layer material includes, but is not limited to, silicon dioxide or silicon nitride. Then, a barrier layer / seed layer is deposited on the insulating layer. The barrier layer material includes, but is not limited to, titanium or tantalum, and the seed layer material includes, but is not limited to, copper. Copper is then filled into the TSV blind via 2 by electrochemical plating to form copper pillars. Excess copper, the insulating layer, and the barrier layer / seed layer are removed by chemical mechanical polishing, making the surface of the copper pillars inside the TSV blind via 2 planarized with the surface of the silicon interposer 1. Step 3: As Figure 3 As shown, a redistribution layer 3 is fabricated on the surface of a flat silicon interposer 1 using photolithography, electroplating, and other processes. The redistribution layer 3 consists of a dielectric layer and a metal layer; the dielectric layer material includes, but is not limited to, polymer or silicon dioxide. Multiple dielectric layers are fabricated repeatedly as needed. The thickness of the redistribution layer 3 is 2-6 micrometers, and its topmost layer contains microbumps 4 composed of copper and solder balls. Step 4: Prepare chip 5, or chip 5 and intermediate chip 9. like Figure 4 As shown, a redistribution structure 6 and a microbump structure 7 are fabricated on the active layer of chip 5 as needed. The redistribution structure 6 consists of a dielectric layer and a metal layer with a thickness of 2-6 micrometers. The topmost layer is fabricated with a microbump structure 7, which is composed of copper and solder balls. Chip 5 can be a chip or functional module with different process technology, different materials, and different functions, such as: advanced digital logic chips, analog / RF chips, memory, MEMS sensors, or passive devices; Step 5: As Figure 5 As shown, chip mounting and reflow soldering are performed. A high-precision pick-and-place machine picks up a known, qualified chip 5, precisely aligns the microbump structure 7 onto the microbumps 4 of the silicon interposer 1, and completes the mechanical and electrical connection between the chip 5 and the silicon interposer 1 through a reflow soldering process. Then, underfill adhesive 8 is applied, and the silicon interposer 1 is ground to the appropriate thickness; or... like Figure 6 As shown, a high-precision pick-and-place machine picks up a known qualified intermediate chip 9, precisely aligns the first microbump on the first multi-wiring layer 91 on one side of the intermediate chip 9 with the microbump 4 on the silicon interposer 1, and completes the mechanical and electrical connection between the intermediate chip 9 and the silicon interposer 1 through reflow soldering. A high-precision pick-and-place machine then picks up a known qualified chip 5, precisely aligning the microbump structure 7 with the second microbump on the second multi-wiring layer 92 on the other side of the intermediate chip 9, and completes the mechanical and electrical connection between the chip 5 and the intermediate chip 9 through reflow soldering. Underfill is then applied, and the silicon interposer 1 is ground to a suitable thickness to complete the three-dimensional stack-up mounting; or... Two chips 5 are directly bonded back to back with bonding adhesive, and the microbump structure 7 on the chip 5 is precisely aligned with the microbump 4 on the silicon interposer 1. The mechanical and electrical connection between the chip 5 and the silicon interposer 1 is completed by reflow soldering process. Underfill materials include, but are not limited to, epoxy resin; Step Six: As Figure 7 As shown, the chip-silicon interposer assembly is cut along the dicing groove to obtain an independent and complete chip-silicon interposer assembly, and then temporarily bonded to the carrier plate 10 by temporary bonding adhesive 101. The carrier plate 10 can be a glass carrier plate or a steel plate, etc. Step Seven: As Figure 8 As shown, molding and polishing are performed. The assembly is molded to form a molded body 11. After molding, chemical mechanical polishing is used to reduce the thickness of the molded body 11 until the silicon surface is exposed. Alternatively, the following steps can be designed according to requirements: after laser drilling in the molding stage, electroplating metal is used to create molding compound through-holes 111, or the copper pillar structure is molded together with the chip in the molding stage to form molding compound through-holes 111 to supply power to the top chip; this step is optional. Step 8: As Figure 9 As shown, the carrier 10 is debonded, and the surface of the silicon interposer 1 is polished by chemical mechanical polishing to reduce the thickness of the silicon interposer 1 to the target thickness. Then, the redistribution layer structure 12 and bump 13 are fabricated. The bump 13 can be a copper pillar bump + solder ball, or an array of solder balls. Step 9: Cutting. Cut the duplicate package into individual subsystem units.

[0021] The present invention also discloses a packaging structure prepared by a packaging method, including a silicon interposer 1, through-silicon vias (TSVs) 2 etched on the silicon interposer 1, an insulating layer deposited on the inner wall of the TSVs 2, a barrier layer / seed layer deposited on the insulating layer, copper pillars formed in the TSVs 2 by electrochemical electroplating, a redistribution layer 3 and microbumps 4 disposed on the silicon interposer 1, a molding compound 11 formed on the silicon interposer 1, a chip 5 encapsulated in the molding compound 11, or the chip 5 and the molding compound via 111, or the chip 5 and the intermediate chip 9, or the chip 5, the intermediate chip 9 and the molding compound via 111, and a redistribution layer structure 12 and bumps 13 formed on the side of the silicon interposer 1 away from the molding compound 11.

[0022] Example 1 like Figure 1-5 , Figure 7-9 As shown, an encapsulation method includes the following steps: Step 1: As Figure 1 As shown, through-silicon vias 2 are etched on the prepared silicon interposer 1; Step Two: As Figure 2 As shown, an insulating layer made of silicon dioxide is deposited on the inner wall of the through-silicon via (TSV) blind via 2. A seed layer made of copper is then deposited on the insulating layer. Copper is then filled into the TSV blind via 2 through electrochemical plating to form copper pillars. Excess copper, the insulating layer, and the seed layer are removed by chemical mechanical polishing, making the surface of the copper pillars inside the TSV blind via 2 planar with the surface of the silicon interposer 1. Step 3: As Figure 3 As shown, a redistribution layer 3 is fabricated on the surface of a flat silicon interposer 1 using photolithography, electroplating, and other processes. The redistribution layer 3 consists of a dielectric layer and a metal layer, with silicon dioxide as the dielectric material. Multiple dielectric layers are fabricated repeatedly as needed. The redistribution layer 3 has a thickness of 5 micrometers, and a microbump 4 is fabricated on its top layer, consisting of copper and solder balls. Step Four: As Figure 4 As shown, the chip is prepared. A redistribution structure 6 and a microbump structure 7 are fabricated on the active layer of chip 5 as needed. The redistribution structure 6 consists of a dielectric layer and a metal layer, with a thickness of 5 micrometers. The topmost layer of this structure is the microbump structure 7, composed of copper and solder balls. In this embodiment, chip 5 is a MEMS sensor; Step 5: As Figure 5 As shown, chip 5 is mounted and reflow soldered. A high-precision pick-and-place machine picks up known qualified chips 5, precisely aligns the microbump structure 7 onto the microbumps 4 of the silicon interposer 1, completes the mechanical and electrical connection between chip 5 and silicon interposer 1 through reflow soldering, then applies underfill 8, and finally grinds the silicon interposer 1 to the appropriate thickness; The underfill material is made of epoxy resin; Step Six: As Figure 7 As shown, the chip-silicon interposer assembly is cut along the dicing groove to obtain an independent and complete chip-silicon interposer assembly, and then temporarily bonded to the carrier plate 10 by temporary bonding adhesive 101. The carrier plate 10 is a glass carrier plate. Step Seven: As Figure 8 As shown, molding and polishing are performed. The assembly is molded to form a molded body 11. After molding, chemical mechanical polishing is used to reduce the thickness of the molded body 11 until the silicon surface is exposed. Step 8: As Figure 9 As shown, the carrier 10 is debonded, and the surface of the silicon interposer 1 is polished by chemical mechanical polishing to reduce the thickness of the silicon interposer 1 to the target thickness. Then, the redistribution layer structure 12 and bump 13 are fabricated. The bump 13 is a copper pillar bump + solder ball. Step 9: Cutting. Cut the duplicate package into individual subsystem units.

[0023] This embodiment also discloses a packaging structure prepared by a packaging method, including a silicon interposer 1, through-silicon vias (TSVs) 2 etched on the silicon interposer 1, an insulating layer deposited on the inner wall of the TSVs 2, a barrier layer / seed layer deposited on the insulating layer, copper pillars formed in the TSVs 2 by electrochemical plating, a redistribution layer 3 and microbumps 4 disposed on the silicon interposer 1, a molding compound 11 formed on the silicon interposer 1, a chip 5 encapsulated in the molding compound 11, and a redistribution layer structure 12 and bumps 13 fabricated on the side of the silicon interposer 1 away from the molding compound 11.

[0024] Example 2 like Figure 1-4 , Figure 6 As shown, an encapsulation method includes the following steps: Step 1: As Figure 1 As shown, through-silicon vias 2 are etched on the prepared silicon interposer 1; Step Two: As Figure 2 As shown, an insulating layer is deposited on the inner wall of the through-silicon via (TSV) blind via 2, and the insulating layer material is silicon nitride. Then, a barrier layer is deposited on the insulating layer, and the barrier layer material is tantalum. Next, copper is filled into the TSV blind via 2 through electrochemical plating to form copper pillars. Chemical mechanical polishing is used to grind away excess copper, the insulating layer, and the barrier layer, making the surface of the copper pillars inside the TSV blind via 2 planar with the surface of the silicon interposer 1. Step 3: As Figure 3 As shown, a redistribution layer 3 is fabricated on the surface of a flat silicon interposer 1 using photolithography, electroplating, and other processes. The redistribution layer 3 consists of a dielectric layer and a metal layer; the dielectric layer material includes, but is not limited to, polymer or silicon dioxide. Multiple dielectric layers are fabricated repeatedly as needed. The redistribution layer 3 has a thickness of 6 micrometers, and its topmost layer contains microbumps 4 composed of copper and solder balls. Step Four: As Figure 4 As shown, the chip is prepared. A redistribution structure 6 and a microbump structure 7 are fabricated on the active layer of chip 5 as needed. The redistribution structure 6 consists of a dielectric layer and a metal layer, with a thickness of 6 micrometers. The topmost layer of this structure is the microbump structure 7, composed of copper and solder balls. Step 5: As Figure 6 As shown, a high-precision pick-and-place machine is used to pick up a known qualified intermediate chip 9, and the first microbump on the first super-wiring layer 91 on one side of the chip is precisely aligned with the microbump 4 on the silicon interposer 1. The mechanical and electrical connection between the intermediate chip 9 and the silicon interposer 1 is completed through reflow soldering. A high-precision pick-and-place machine is used to pick up a known qualified chip 5, and the microbump structure 7 is precisely aligned with the second microbump on the second super-wiring layer 92 on the other side of the intermediate chip 9. The mechanical and electrical connection between the chip 5 and the intermediate chip 9 is completed through reflow soldering. Then, underfill adhesive 8 is applied, and the silicon interposer 1 is ground to a suitable thickness to complete the three-dimensional stack-up mounting. In this embodiment, epoxy resin is used as the filler material; Step 6: Cut along the dicing groove to obtain an independent and complete chip-silicon interposer assembly, and then temporarily bond it to the carrier plate 10 with temporary bonding adhesive 101. The carrier plate 10 can be a glass carrier plate or a steel plate, etc. Step 7: Molding and Polishing. The assembly is molded to form a molded body 11. After molding, the thickness of the molded body 11 is reduced by chemical mechanical polishing until the silicon surface is exposed. Step 8: Debond the carrier 10, grind the surface of the silicon interposer 1 using chemical mechanical polishing, reduce the thickness of the silicon interposer 1 to the target thickness, and then fabricate the redistribution layer structure 12 and bumps 13. The bumps 13 can be copper pillar bumps + solder balls, or an array of solder balls. Step 9: Cutting. Cut the duplicate package into individual subsystem units.

[0025] This embodiment also discloses a packaging structure prepared by a packaging method, including a silicon interposer 1, through-silicon vias (TSVs) 2 etched on the silicon interposer 1, an insulating layer deposited on the inner wall of the TSVs 2, a barrier layer / seed layer deposited on the insulating layer, copper pillars formed in the TSVs 2 by electrochemical plating, a redistribution layer 3 and microbumps 4 disposed on the silicon interposer 1, a molding compound 11 formed on the silicon interposer 1, a chip 5 and an intermediate chip 9 encapsulated in the molding compound 11, and a redistribution layer structure 12 and bumps 13 fabricated on the side of the silicon interposer 1 away from the molding compound 11.

[0026] The rest is the same as in Example 1.

[0027] Example 3 like Figure 1-4 , Figure 6 , Figure 10As shown, an encapsulation method includes the following steps: Step 1: As Figure 1 As shown, through-silicon vias 2 are etched on the prepared silicon interposer 1; Step Two: As Figure 2 As shown, an insulating layer made of silicon nitride is deposited on the inner wall of the through-silicon via (TSV) blind via 2. A seed layer made of copper is then deposited on the insulating layer. Copper is then filled into the TSV blind via 2 by electrochemical plating to form copper pillars. Excess copper, the insulating layer, and the seed layer are removed by chemical mechanical polishing, making the surface of the copper pillars inside the TSV blind via 2 planar with the surface of the silicon interposer 1. Step 3: As Figure 3 As shown, a redistribution layer 3 is fabricated on the surface of a flat silicon interposer 1 using photolithography, electroplating, and other processes. The redistribution layer 3 consists of a dielectric layer and a metal layer; the dielectric layer material includes, but is not limited to, polymer or silicon dioxide. Multiple dielectric layers are fabricated repeatedly as needed. The redistribution layer 3 has a thickness of 2 micrometers, and its topmost layer contains microbumps 4 composed of copper and solder balls. Step 4: Prepare chip 5 and intermediate chip 9. (For example...) Figure 4 As shown, a redistribution structure 6 and a microbump structure 7 are fabricated on the active layer of chip 5 as needed. The redistribution structure 6 consists of a dielectric layer and a metal layer, with a thickness of 2 micrometers. The topmost layer is fabricated with a microbump structure 7, which is composed of copper and solder balls. Step 5: Chip mounting and reflow soldering. (e.g., chip placement and reflow soldering) Figure 6 As shown, a high-precision pick-and-place machine is used to pick up a known qualified intermediate chip 9, and the first microbump on the first super-wiring layer 91 on one side of the chip is precisely aligned with the microbump 4 on the silicon interposer 1. The mechanical and electrical connection between the intermediate chip 9 and the silicon interposer 1 is completed through reflow soldering. A high-precision pick-and-place machine is used to pick up a known qualified chip 5, and the microbump structure 7 is precisely aligned with the second microbump on the second super-wiring layer 92 on the other side of the intermediate chip 9. The mechanical and electrical connection between the chip 5 and the intermediate chip 9 is completed through reflow soldering. Then, underfill adhesive 8 is applied, and the silicon interposer 1 is ground to a suitable thickness to complete the three-dimensional stack-up mounting. Step 6: Cut along the dicing groove to obtain an independent and complete chip-silicon interposer assembly, and then temporarily bond it to the carrier plate 10 using temporary bonding adhesive 101. The carrier plate 10 is a glass carrier plate. Step 7: Molding and Polishing. The assembly is molded to form a molded body 11. After molding, the thickness of the molded body 11 is reduced by chemical mechanical polishing until the silicon surface is exposed. Laser drilling is performed during the molding process, followed by electroplating with metal to create through-holes 111 in the molding compound. Step 8: Debond the carrier 10, grind the surface of the silicon interposer 1 using chemical mechanical polishing, reduce the thickness of the silicon interposer 1 to the target thickness, and then fabricate the redistribution layer structure 12 and bumps 13. The bumps 13 can be copper pillar bumps + solder balls. Step 9: Cutting. Cut the duplicate package into individual subsystem units.

[0028] A packaging structure prepared by a packaging method includes a silicon interposer 1, through-silicon vias (TSVs) 2 etched on the silicon interposer 1, an insulating layer deposited on the inner wall of the TSVs 2, a seed layer deposited on the insulating layer, copper pillars formed in the TSVs 2 by electrochemical plating, a redistribution layer 3 and microbumps 4 disposed on the silicon interposer 1, a molding compound 11 formed on the silicon interposer 1, a chip 5, an intermediate chip 9 and molding compound vias 111 encapsulated within the molding compound 11, and a redistribution layer structure 12 and bumps 13 fabricated on the side of the silicon interposer 1 away from the molding compound 11.

[0029] The rest is the same as in Example 2.

[0030] Example 4 like Figure 1-4 , Figure 11 As shown, an encapsulation method includes the following steps: Step 1: As Figure 1 As shown, through-silicon vias 2 are etched on the prepared silicon interposer 1; Step Two: As Figure 2 As shown, an insulating layer made of silicon dioxide is deposited on the inner wall of the through-silicon via (TSV) blind via 2. A barrier layer made of titanium is then deposited on the insulating layer. Copper is then electrochemically plated into the TSV blind via 2 to form copper pillars. Excess copper, the insulating layer, and the barrier layer are removed using chemical mechanical polishing, making the surface of the copper pillars inside the TSV blind via 2 planar with the surface of the silicon interposer 1. Step 3: As Figure 3 As shown, a redistribution layer 3 is fabricated on the surface of a flat silicon interposer 1 using photolithography, electroplating, and other processes. The redistribution layer 3 consists of a dielectric layer and a metal layer, with silicon dioxide as the dielectric material. Multiple dielectric layers are fabricated repeatedly as needed. The redistribution layer 3 has a thickness of 6 micrometers, and a microbump 4 is fabricated on its top layer, consisting of copper and solder balls. Step 4: Prepare chip 5. (e.g.) Figure 4 As shown, a redistribution structure 6 and a microbump structure 7 are fabricated on the active layer of chip 5 as needed. The redistribution structure 6 consists of a dielectric layer and a metal layer, with a thickness of 6 micrometers. The topmost layer is fabricated with a microbump structure 7, which is composed of copper and solder balls. Step 5: Chip mounting and reflow soldering. Two chips 5 are directly bonded back to back using bonding adhesive 51. The microbump structure 7 on the chip 5 is precisely aligned with the microbump 4 on the silicon interposer 1. The mechanical and electrical connection between the chip 5 and the silicon interposer 1 is completed through the reflow soldering process. Underfill materials include, but are not limited to, epoxy resin; Step 6: Cut along the dicing groove to obtain an independent and complete chip-silicon interposer assembly, and then temporarily bond it to the carrier plate 10 using temporary bonding adhesive 101. The carrier plate 10 is a glass carrier plate. Step 7: Molding and Polishing. The assembly is molded to form a molded body 11. After molding, the thickness of the molded body 11 is reduced by chemical mechanical polishing until the silicon surface is exposed. After laser drilling during the molding process, metal is electroplated to create molding compound through-holes 111; the molding compound through-holes 111 are bonded to the redistribution structure 6 of the chip 5 via leads 14. Step 8: Debond the carrier 10, grind the surface of the silicon interposer 1 using chemical mechanical polishing, reduce the thickness of the silicon interposer 1 to the target thickness, and then fabricate the redistribution layer structure 12 and bumps 13. The bumps 13 can be copper pillar bumps + solder balls. Step 9: Cutting. Cut the duplicate package into individual subsystem units.

[0031] This embodiment also discloses a packaging structure prepared by a packaging method, including a silicon interposer 1, through-silicon vias (TSVs) 2 etched on the silicon interposer 1, an insulating layer deposited on the inner wall of the TSVs 2, a barrier layer / seed layer deposited on the insulating layer, copper pillars formed in the TSVs 2 by electrochemical plating, a redistribution layer 3 and microbumps 4 disposed on the silicon interposer 1, a molding compound 11 formed on the silicon interposer 1, a chip 5 and molding compound vias 111 encapsulated in the molding compound 11, and a redistribution layer structure 12 and bumps 13 fabricated on the side of the silicon interposer 1 away from the molding compound 11.

[0032] The rest is the same as in Example 2.

[0033] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0034] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A packaging method, characterized in that, Includes the following steps: Step 1: Etch through-silicon vias and blind vias on the prepared silicon interposer; Step 2: Deposit an insulating layer on the inner wall of the through-silicon via blind hole, deposit a barrier layer / seed layer on the insulating layer, and form copper pillars in the through-silicon via blind hole by electrochemical plating; Step 3: Fabricate a redistribution layer and microbumps on the surface of the silicon interposer; Step 4: Prepare the chip, or the chip and intermediate chip; Step 5: Mount the chip, or the chip and intermediate chip, onto the silicon interposer; Step Six: Temporarily bond the semi-finished product obtained in Step Five onto the carrier board; Step 7: The semi-finished product obtained in Step 6 is encapsulated to form an encapsulated body; during the encapsulation stage, through-holes in the encapsulation material are selectively created; Step 8: Debond the carrier board and fabricate a redistribution layer structure and bumps on the surface of the silicon interposer; Step 9: Cutting.

2. The packaging method according to claim 1, characterized in that, In step two, after the copper pillars are formed, chemical mechanical polishing is used to grind away excess copper, insulating layer, and barrier / seed layer on the surface, so that the surface of the copper pillars in the through-silicon via blind holes is planarized with the surface of the silicon interposer.

3. The packaging method according to claim 1, characterized in that, In step two, the insulating layer material is silicon dioxide or silicon nitride, and the barrier layer material is titanium or tantalum.

4. The packaging method according to claim 1, characterized in that, In step three, the thickness of the redistribution layer is 2 to 6 micrometers.

5. The packaging method according to claim 1, characterized in that, In step four, the active layer of the chip is fabricated with a redistribution structure and a microbump structure, and the thickness of the redistribution structure is 2 to 6 micrometers.

6. The packaging method according to claim 1, characterized in that, Step five, the step of mounting the chip onto the silicon interposer, includes: A high-precision pick-and-place machine is used to pick up the chip and precisely align the microbump structure on the chip with the microbumps on the silicon interposer. The mechanical and electrical connection between the chip and the silicon interposer is completed through a reflow soldering process, followed by underfill.

7. The packaging method according to claim 1, characterized in that, Step five, the step of mounting the chip onto the silicon interposer, includes: Two chips are bonded together back to back using bonding adhesive, precisely aligning the microbump structure on the chip with the microbump on the silicon interposer, and completing the mechanical and electrical connection between the chip and the silicon interposer through a reflow soldering process.

8. The packaging method according to claim 1, characterized in that, Step five, which involves mounting the chip and intermediate chip onto the silicon interposer, includes: A high-precision pick-and-place machine is used to pick up the intermediate chip and precisely align the first microbump on the first wiring layer of one side of the chip with the microbump on the silicon interposer. The mechanical and electrical connection between the intermediate chip and the silicon interposer is completed through reflow soldering. The high-precision pick-and-place machine is then used to pick up the chip and precisely align the microbump structure on the chip with the second microbump on the second wiring layer on the other side of the intermediate chip. The mechanical and electrical connection between the chip and the intermediate chip is completed through reflow soldering. Finally, underfill is applied to complete the three-dimensional stacking and mounting.

9. A packaging structure prepared by any one of the packaging methods according to claims 1-7, characterized in that, The device includes a silicon interposer, on which through-silicon vias (TSVs) are etched. An insulating layer is deposited on the inner wall of the TSVs. A barrier layer / seed layer is deposited on the insulating layer. Copper pillars are formed in the TSVs through electrochemical plating. A redistribution layer and microbumps are disposed on the silicon interposer. A molding compound is formed on the silicon interposer. A chip or a chip-molding via is encapsulated in the molding compound. A redistribution layer structure and bumps are fabricated on the side of the silicon interposer away from the molding compound.

10. A packaging structure prepared by any one of the packaging methods according to claims 1-5 and 8, characterized in that, The device includes a silicon interposer, on which through-silicon vias (TSVs) are etched. An insulating layer is deposited on the inner wall of the TSVs. A barrier layer / seed layer is deposited on the insulating layer. Copper pillars are formed in the TSVs through electrochemical plating. A redistribution layer and microbumps are disposed on the silicon interposer. A molding compound is formed on the silicon interposer. The molding compound encapsulates a chip and an intermediate chip or a chip, an intermediate chip, and a through-hole of the molding compound. A redistribution layer structure and bumps are fabricated on the side of the silicon interposer away from the molding compound.

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