Henting in data processing device

Abstract

An apparatus has processing circuitry to perform processing operations specified by program instructions; and a loop control circuit to identify a program loop specified by the program instruction. Upon identification of a program loop, the loop control circuitry stores loop control data indicating a program loop body that excludes any program flow control instructions specifying the program loop. The loop control circuitry controls the processing circuitry to perform loop iterations of the program loop volume indicated by the loop control data. The processing circuitry causes loop control data for a given program loop to exclude a hint instruction from the modified program loop body in response to the hint instruction occurring at the beginning of the given program loop body, and performs a performance modification operation process specified by the hint instruction while performing a loop iteration of the modified program loop body.

Description

BACKGROUND

[0001] The present technology relates to the field of data processing. More specifically, the present technology relates to processing hints in a data processing apparatus.

[0002] A hint instruction can be used within a sequence of program instructions to be executed by processing circuitry in order to indicate to the processing circuitry an opportunity to perform a performance modification operation. For example, the hint instruction can indicate certain properties of data to be operated on or certain properties of an upcoming sequence of instructions to be executed, where the processing circuitry can make use of these properties to modify the way in which data compression operations are performed in order to improve the performance of these operations. SUMMARY

[0003] In one example arrangement, there is provided an apparatus comprising: processing circuitry to perform processing operations specified by program instructions; and loop control circuitry to identify a program loop specified by the program instructions, and to store loop control data indicative of a program loop body of the program loop, the program loop body excluding any program flow control instructions that specify the program loop; wherein the loop control circuitry is to control the processing circuitry to perform loop iterations of the program loop body indicated by the loop control data; and wherein the processing circuitry is responsive to a hint instruction occurring at the start of a given program loop body, the hint instruction indicating a performance modification operation procedure to be used for one or more subsequent program instructions, such that: the loop control data for the given program loop excludes the hint instruction from the modified program loop body by identifying instructions following the hint instruction as the start of the modified program loop body, and the processing circuitry is to perform the performance modification operation procedure specified by the hint instruction when performing loop iterations of the modified program loop body.

[0004] In another example arrangement, there is provided a system comprising: the apparatus described above, implemented in at least one package chip; at least one system component; and a board; wherein the at least one package chip and the at least one system component are assembled on the board.

[0005] In a further example arrangement, there is provided a chip-in product comprising the system described above, assembled with at least one other product component on a further board.

[0006] In yet another example arrangement, there is provided a computer readable medium for storing computer readable code for manufacturing an apparatus comprising: processing circuitry for performing processing operations specified by program instructions; and loop control circuitry for identifying a program loop specified by the program instructions, and for storing loop control data indicative of a program loop body of the program loop, the program loop body excluding any program flow control instructions specifying the program loop; wherein the loop control circuitry is for controlling the processing circuitry to perform loop iterations of the program loop body indicated by the loop control data; and wherein, in response to a hint instruction occurring at the start of a given program loop body, the hint instruction indicating a performance modification operation process to be used for one or more subsequent program instructions, the loop control data for the given program loop is caused to exclude the hint instruction from a modified program loop body by identifying instructions following the hint instruction as the start of the modified program loop body, and the processing circuitry is caused to perform the performance modification operation process specified by the hint instruction when performing loop iterations of the modified program loop body.

[0007] In another example arrangement, there is provided a method comprising: performing processing operations specified by program instructions; identifying a program loop specified by the program instructions, and storing loop control data indicative of a program loop body of the program loop, the program loop body excluding any program flow control instructions specifying the program loop; controlling performance of loop iterations of the program loop body indicated by the loop control data; and in response to a hint instruction occurring at the start of a given program loop body, the hint instruction indicating a performance modification operation process to be used for one or more subsequent program instructions, the loop control data for the given program loop is caused to exclude the hint instruction from a modified program loop body by identifying instructions following the hint instruction as the start of the modified program loop body, and the performance modification operation process specified by the hint instruction is performed when performing loop iterations of the modified program loop body. BRIEF DESCRIPTION OF DRAWINGS

[0008] Further aspects, features, and advantages of the present technology will become apparent from the following description of examples, read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 An example of a data processing apparatus is schematically illustrated;

[0010] Figure 2 A loop control data item is exemplified;

[0011] Figure 3 Zero-overhead loop behaviour is schematically illustrated;

[0012] Figure 4Loop behavior is illustratively exemplified in which a hint instruction is excluded from the modified program loop body of a zero-overhead loop;

[0013] Figure 5 Loop behavior is illustratively exemplified in which a hint instruction is excluded from the modified program loop body of a zero-overhead loop with a loop start instruction;

[0014] Figure 6 Loop behavior is illustratively exemplified in which two hint instructions are excluded from the modified program loop body;

[0015] Figure 7 Loop behavior is illustratively exemplified in which a hint instruction is excluded from the modified program loop body of a loop;

[0016] Figure 8 is a flowchart illustrating the operation of a data processing apparatus in one example;

[0017] Figure 9 is a flowchart illustrating the operation of a data processing apparatus in another example; and

[0018] Figure 10 A system including a package chip is illustratively exemplified. DETAILED DESCRIPTION

[0019] The following description of examples provides details to make such examples understandable. Nevertheless, the description is given only by way of example and without limitation to the particulars described.

[0020] Program code typically includes instructions that set up a program loop, causing a series of program instructions forming a program loop body to be repeatedly executed. A program loop can be controlled using a branch instruction at the end of the program loop, which when executed causes program flow to be transferred back to the start of the loop; or can be controlled, for example, using a dedicated loop instruction that defines the program loop.

[0021] According to the techniques described herein, there is provided an apparatus having processing circuitry to perform processing operations specified by program instructions. The apparatus also has loop control circuitry capable of identifying a program loop specified by the program instructions. On detecting such a program loop, the loop control circuitry stores loop control data identifying the program loop body of the program loop. In the case where the program loop is specified using a program flow control instruction, such as the branch instruction or the dedicated loop instruction discussed above, these program flow control instructions are excluded from the program loop body. The program loop body therefore only includes instructions to be repeatedly executed as part of the loop.

[0022] The loop control circuitry then controls the processing circuitry to only perform loop iterations of the program loop body when executing program instructions, and in doing so, prevents the program flow control instructions from being executed in at least some executions of the loop. By controlling the processing circuitry to perform loop iterations in this way, the loop control circuitry is able to reduce the overhead involved in controlling the program loop, which would otherwise arise from repeatedly executing the program flow control instructions in each iteration of the program loop. Conversely, by storing the loop control data identifying the program loop body separately from the program flow control instructions, the loop control circuitry is able to ensure that the program loop behaviour defined by the program flow control instructions is observed, whilst preventing the program flow control instructions themselves from being executed in at least some iterations of the loop.

[0023] In the case where an apparatus comprising such loop control circuitry is used, and a programmer wishes to include one or more hint instructions indicating a performance modification operation process to be used for instructions in a program loop, a number of possible locations for the hint instructions can be considered.

[0024] Firstly, the hint instruction can be included within the program loop body, for example, as the first instruction in the program loop body. The hint would thus apply to subsequent instructions occurring in the program loop body (until the hint instruction is cleared, replaced by another hint instruction, or ceases to apply for other reasons). The hint instruction would be executed in each iteration of the program loop, allowing the performance modification operation process to be performed. However, this approach requires the hint instruction to be executed in each iteration of the program loop, which can impact performance, and in some cases can negate any performance benefits provided by the performance modification operation process.

[0025] To address this, another approach involves locating the hint instruction outside of the program loop body (for example, before the first instruction in the program loop body, or before a program flow control instruction marking the start of the program loop). This approach means that the hint instruction is executed before the first iteration of the program loop, but not in subsequent iterations of the program loop. Since the instruction does not form part of the program loop body, the performance impact associated with repeatedly executing the hint instruction is thereby reduced.

[0026] The hint information associated with the hint instruction can be cached and used to instruct the performance modification operation process that should be performed when executing one or more subsequent instructions. When an interrupt or other type of exception occurs causing the processing circuitry to perform a context switch to handle the interrupt, the cached hint instruction is flushed to avoid using the performance modification operation process in the context of handling the interrupt, which can inadvertently degrade performance. However, the flushing of the hint information means that if the interrupt occurs while the processing circuitry is executing a loop, when the program flow returns to the loop after handling the interrupt, the hint information will no longer be cached. In the case where the hint instruction is positioned outside of the program loop body, the hint instruction will not form part of the program flow when returning to the program loop, and so the subsequent iteration of the program loop will be executed without employing the performance modification operation process specified by the hint instruction. This can itself cause a performance impact as any performance benefits associated with the performance modification operation process will no longer be obtained.

[0027] According to the techniques described herein, therefore, the processing circuitry, in response to the hint instruction occurring at the start of a given program loop body, causes the loop control data for the given program loop to exclude the hint instruction from the modified program loop body. This is done by identifying the instruction following the hint instruction as the start of the modified program loop body. By excluding the hint instruction from the modified program loop body, the processing circuitry is then able to prevent the hint instruction being executed in subsequent iterations of the program loop. During iterations of the modified program loop body, the processing circuitry performs the performance modification operation process specified by the hint instruction.

[0028] The apparatus is therefore able to benefit from any performance gains associated with the performance modification operation process, whilst also avoiding the need to execute the hint instruction in every iteration of the program loop.

[0029] In response to an interrupt occurring while the processing circuitry is executing an iteration of the program loop, both the loop control data and the hint control data will be flushed. The loop control data will therefore no longer define a modified program loop body that excludes the hint instruction when the program loop is returned to after handling the interrupt. The first full iteration of the program loop performed after returning from the interrupt will therefore result in the re-execution of the hint instruction (as the loop control data no longer excludes the hint instruction from the modified program loop body). Execution of the hint instruction will therefore enable the performance modification operation process to be performed for subsequent program instructions (e.g. subsequent iterations of the program loop). The re-execution of the hint instruction can also cause the processing circuitry to exclude the hint instruction from the modified program loop body again, so that the processing circuitry will perform loop iterations of the modified program loop body whilst employing the performance modification operation process.

[0030] In this way, the present technology can optimize the execution of a program loop containing hint instructions by preventing the hint instructions from being repeatedly executed on each iteration of the program loop, while ensuring that any performance benefits of the performance modification operation process are not lost in the event of an interrupt occurring while the processing circuitry is executing an iteration of the program loop.

[0031] It is important to appreciate that the above instructions are "hint" instructions, and thus the present technology is not concerned with functionally altering the data processing operations performed in response to the sequence of data processing instructions, i.e. altering the data processing results produced by the data processing operations. Rather, the present technology is concerned with modifying the manner in which the data processing operations are performed (in terms of "performance"), such that the data processing operations can be performed, for example, in a manner in which efficiency, power consumption, latency, etc. can be varied relative to the manner in which they would be performed without the hint instructions. The apparatus is arranged to produce the same data processing results whether the sequence of data processing instructions is executed according to the operational process (i.e. without the register-identifying hint instructions preceding them) or according to the modified operational process (i.e. with the hint instructions preceding them). Both processes produce the same results, but the manner in which those results are produced can vary in a range of ways between the operational process and the modified operational process.

[0032] The present technology thus provides a mechanism for a programmer, indeed an instruction set architect, to modify the manner in which an apparatus responds to one or more data processing instructions forming a sequence of data processing instructions, without having to redefine the plurality of data processing instructions as part of the instruction set of the apparatus to implement the modification.

[0033] There are many different types of performance measurement that can be implemented. For example, in one example use case, the hint instructions can be used to apply a non-temporal behaviour to memory operations. Non-temporal memory operations are variants of normal load and store operations in which the accessed data is not expected to be accessed again soon, and so does not need to be retained in a cache. Thus, if certain accesses can be marked as non-temporal, then the cache allocation / eviction policy of one or more caches can take this information into account in order to aim to more optimally use the cache resources, thereby improving performance, reducing energy consumption, etc.

[0034] As another illustrative example use case, the hint instructions can be used to mark the prefetch behaviour in respect of certain instructions. For example, the hint instructions can be used to trigger prefetch behaviour to occur, or indeed in some cases to disable prefetch behaviour in association with certain instructions that reference the registers indicated by the hint instructions, with the aim being to improve the overall performance of the apparatus.

[0035] The point in time at which any given performance measurement is implemented based on the hint instruction can vary depending on various factors, such as the type of hint instruction. In one example implementation, at least one of the one or more performance measurements is implemented in association with performing one or more data processing operations defined by one or more given instructions in the instruction sequence that access the given register identified by the hint instruction. Thus, in such implementations, the performance measurement can be implemented in connection with the performance of at least some type of data processing operation that accesses the given register identified by the hint instruction. As a particular example where such an approach can be applicable, this approach can be used when the hint instruction provides a non-temporary hint in association with data stored in the given register. For example, a memory access operation can be used to load data from memory into the given register, or to store data from the given register to memory, and when that memory access activity causes the data to be cached within a cache structure of the apparatus, marking the data as non-temporary can enable more efficient implementation of the cache structure, for example by marking the data as able to be evicted faster than would otherwise be the case, thereby freeing up space for data that is in fact going to be reused.

[0036] In one example implementation, the one or more given instructions can be instructions that use the value held in the given register in a predetermined manner. Thus, the use of the hint instruction to trigger the performance measurement can depend on the manner in which the value in the given register is used. As one particular example, the performance measurement can be decided to be triggered when the value held in the given register is used as a pointer by a memory access instruction. This can be considered to be a use case that is suitable for marking accesses as non-temporary, for example.

[0037] Similarly, the one or more given instructions can be instructions of a predetermined type, so that the hint only has an effect and causes the associated performance measurement to be implemented when the instruction is of that predetermined type and optionally also uses the data held in the given register in a particular manner. As an example, the use of the hint instruction to trigger the performance measurement can be limited to memory access instructions.

[0038] While in the above examples the performance measurements are triggered in association with the execution of a data processing operation defined by a particular instruction, additionally or alternatively one or more performance measurements can be implemented in response to the execution of a hint instruction. In particular, for certain types of hint instructions, once the hint instruction has been executed, the hint instruction can be acted upon to trigger one or more performance measurements without waiting for one or more subsequent instructions to access a register identified by the hint instruction. As a specific example, when a prefetch is performed, a hint instruction can be used to flag that data to be used by one or more subsequent instructions that reference a given register identified by the hint instruction should be prefetched into the cache to improve performance when the one or more subsequent instructions are actually executed, and thus the prefetch activity can be implemented prior to the execution of the instructions. In some examples, a subsequent instruction that modifies the value of a register that has been flagged using a hint instruction will trigger further prefetching, improving the performance of further subsequent instructions that use the flagged register as a pointer. Thus, it will be appreciated that in some examples one or more performance measurements can be triggered in response to the generation of a hint instruction and in response to a subsequent instruction that modifies a value stored in a register referenced by the hint instruction. As another example, a hint instruction can be used to disable prefetch training for a given load event. For example, pointer chasing workloads are known to be detrimental to prefetching, and can pollute the prefetch training structure. Thus, bypassing training for these load events can improve overall prefetch performance.

[0039] As described above, the processing circuitry maintains hint control data indicative of a performance modification operation process that has been specified by an instruction encountered by the processing circuitry. The processing circuitry then references the hint control data in order to determine the performance modification operation process to be performed. This control data is in addition to loop control data maintained by the loop control circuitry, which identifies the (modified) program loop body of a program loop.

[0040] In response to an exception (e.g. an interrupt), the processing circuitry flushes at least some of the loop control data and at least some of the hint control data. Flushing the loop control data and / or the hint control data can comprise deleting the data from the storage structure, or invalidating the data, for example by clearing a respective enable bit associated with a hint control and / or loop control data entry.

[0041] Because the loop control data identifies the modified program body (excluding prompt instructions), refreshing the loop control data upon exception will re-enable the execution of prompt instructions upon returning from the exception. Therefore, when this prompt instruction is encountered during the execution of the program loop, its re-execution will cause the prompt control data to be repopulated (thus re-enabling the performance modification process), and the loop control data will be set to exclude the prompt instruction from the modified program loop body (thus preventing the prompt instruction from being executed in subsequent iterations of the program loop unless another exception occurs). It should also be understood that if an exception occurs in the last iteration of the program loop, the prompt instruction will not be executed again even if it is re-enabling, because the program flow will not return to the top of the loop.

[0042] Processing circuitry can detect prompt instructions occurring at the beginning of a program loop in several ways. In some examples, the processing circuitry, in response to the execution of a prompt instruction, references loop control data and determines whether the loop control data marks the executed prompt instruction as the beginning of a program loop. This can be done by comparing the program counter (which indicates the address of the current instruction) with the indication in the loop control data of the address of the beginning of the program loop. If the loop control data does indeed mark a prompt instruction at the beginning of the program loop, the processing circuitry can modify the loop control data to exclude the prompt instruction from the modified program loop. Another way to detect instructions occurring at the beginning of a program loop is by setting a flag at the beginning of the loop, which is cleared when subsequent instructions are executed. Therefore, if a flag is set when a prompt instruction is executed, the processing circuitry can determine that an instruction has occurred at the beginning of the program loop.

[0043] It should be understood that when a prompt instruction is first encountered at the beginning of the program loop body, the loop control data may not yet have been updated to exclude the prompt instruction from the modified program loop body within the loop control data. This might be the case, for example, if the loop control data is filled at the end of the program loop (e.g., if the program flow control instruction specifying the program loop occurs at the end of the program loop). However, in the second iteration of the program loop, the loop control data used for the loop will be filled, so the processing circuit will detect that the loop control data identifies a prompt instruction at the beginning of the program loop body, and will therefore modify the loop control data to exclude the prompt instruction from the modified program body. Therefore, for subsequent iterations of the program loop, the prompt instruction will not be executed, and thus the overhead of that instruction will no longer be incurred.

[0044] In some cases, there may be more than one prompt instruction at the beginning of a program loop. Therefore, the processing circuitry can identify an additional prompt instruction occurring at the beginning of a modified program loop body in response to the execution of such an instruction (i.e., after the initial prompt instruction). That is, after the initial prompt instruction is executed and the loop control data excludes the prompt instruction from the modified program loop body, the additional prompt instruction forms the beginning of the modified program loop body. The processing circuitry can detect this, for example, by comparing the program counter of the additional prompt instruction with the loop control data or by referencing the aforementioned flag (where the processing circuitry is configured not to clear the flag when the prompt instruction is executed). In response to identifying the additional prompt instruction, the processing circuitry can further modify the loop control data to exclude the additional prompt instruction from the modified program loop body. The processing circuitry can then execute the loop iteration of the modified program loop body while employing the performance modification operation process specified by both the initial prompt instruction and the additional prompt instruction. In this way, the processing circuitry can benefit from any performance advantages associated with cue instructions while avoiding the overhead associated with executing cue instructions in each iteration of the program loop. The method can also be extended to further instances of cue instructions, enabling the processing circuitry to typically handle multiple cue instructions occurring at the beginning of the program loop body.

[0045] Another way the processing circuit can detect prompt instructions occurring at the beginning of a program loop is based on a loop start instruction. This loop start instruction is a program flow control instruction that occurs before the program loop body and identifies the start of the program loop. Therefore, when the processing circuit encounters a loop start instruction followed by one or more prompt instructions, it can instruct the loop control circuit to modify the loop control data by providing loop modification information that identifies the instruction following one or more prompt instructions as the start of a modified program loop body. Then, when a subsequent loop end instruction is encountered (at which point the range of the loop body is known), the loop control circuit can utilize the loop modification information by storing loop control data based on the received loop modification information, which identifies the start of the modified program loop body. In this way, the loop control circuit can set the loop control data to exclude one or more prompt instructions from the modified program loop body. Notably, this method allows the loop control data to be set so that prompt instructions can be excluded from the modified program loop body during the second iteration of the program loop.

[0046] Program loops can be identified by loop control circuitry in several ways. In some examples, the loop control circuitry identifies a program loop based on a loop termination instruction that occurs at the end of the program loop, specifying the scope of the loop body. For example, the loop termination instruction could identify the address of the first instruction in the program loop, such that the loop body includes instructions occurring between the first instruction and the instructions preceding the loop termination instruction. The loop termination instruction may or may not be conditional and / or identify the number of loop iterations to be performed.

[0047] In some examples, the loop control circuit is configured to additionally define the program loop based on a loop start instruction, which controls the number of times the program loop body is executed. The loop start instruction can directly specify the number of iterations the program loop will perform, or it can specify a condition for continuing the loop. In this sense, the loop start instruction can represent the start instruction of a do or while loop.

[0048] Therefore, a program loop can be represented as a zero-overhead loop (also known as a low-overhead loop). Executing the program flow control instructions that define a loop incurs overhead because it requires executing program flow control instructions that occupy a place in the processing pipeline. This can be particularly impactful for workloads involving a large number of small loop iterations, where a larger proportion of the executed instructions will be program flow control instructions. To address this, a zero-overhead loop can be used, where the information defined in the program flow control instructions that control the loop (such as loop start and loop end instructions) is cached, and the program loop body (excluding loop control instructions) is executed based on the cached information. In this way, the overhead associated with executing the program flow control instructions themselves is reduced. Such zero-overhead loops provide an opportunity to implement this technique, where hint instructions can be used to enable performance modification procedures, while caching of loop control information prevents repeated execution of hint instructions and reduces the impact of their execution.

[0049] In addition to explicitly invoking loop control circuitry to store loop control data and exclude zero-overhead loops from the execution of program flow control instructions, or instead of such zero-overhead loops, loop control circuitry can also implicitly detect the presence of loops in program code and thus identify opportunities to avoid executing program flow control instructions that define these loops. Therefore, loop control circuitry may include loop detection circuitry to detect program loops defined by one or more branch instructions (where branch instructions represent program flow control instructions). In response to detecting a program loop, loop detection circuitry may store loop control data indicating the loop body of the detected program loop in order to perform loop performance modification operations aimed at improving the performance of subsequent iterations of the detected program loop. This performance modification operation may, for example, aim to reduce power consumption during the execution of the program loop or improve the performance of the program loop (e.g., by avoiding the execution of branch instructions).

[0050] In this scenario, the loop control circuitry may include a loop buffer circuitry for storing loop control data indicating at least some of the instructions in the program loop body. Alternatively, the loop control circuitry may include loop metadata circuitry for storing loop control data indicating the address of the start of the program loop body. In both cases, the loop control data can then be modified upon detection of a prompt instruction occurring at the beginning of the program loop as described herein.

[0051] In this scenario, the processing circuitry can respond to multiple prompting instructions occurring at the beginning of a given program loop body by excluding multiple prompting instructions from the modified program loop body. This is accomplished by identifying the instructions following the multiple prompting instructions at the beginning of the modified program loop body. The processing circuitry can then execute loop iterations of the modified program loop body excluding these prompting instructions, while employing the performance modification operation process specified by the corresponding prompting instruction among the multiple prompting instructions.

[0052] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0053] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0054] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0055] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0056] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductors, magnetic disks, or optical disks. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0057] A specific example will now be described with reference to the accompanying drawings.

[0058] Figure 1 An example of a data processing apparatus 2 is illustrated schematically. The data processing apparatus has a processing pipeline 4 comprising multiple pipeline stages, each implemented by corresponding circuitry. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; a release stage 12 for checking if the operands required for the micro-operation are available in a register file 14, and releasing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 for performing the data processing operation corresponding to the micro-operation by processing the operands read from the register file 14 to generate a result value; and a write-back stage 18 for writing the processed result back to the register file 14. It should be understood that this is merely one example of a possible pipeline architecture, and other systems may have different numbers of stages or different configurations of stages. For example, in an out-of-order processor, an additional register renaming level may be included, which is used to map the architecture registers specified by program instructions or micro-operations to physical register specifiers in the identifier register file 14.

[0059] Execution phase 16 includes multiple processing units for performing different categories of processing operations. For example, the execution units may include: an arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations; a floating-point unit 22 for performing operations on floating-point values; a branching unit 24 for evaluating the results of branching operations and adjusting the program counter representing the current execution point accordingly; and a load / store unit 28 for performing load / store operations to access data in memory systems 8, 30, 32, and 34. In this example, the memory system includes a Level 1 data cache 30, a Level 1 instruction cache 8, a shared Level 2 cache 32, and main system memory 34. It should be understood that this is only one example of a possible memory hierarchy, and other arrangements including different cache organizations are also possible. The specific types of processing units 20 to 28 shown in execution phase 16 are only one example, and other specific implementations may have different sets of processing units or may include multiple instances of the same type of processing units, allowing multiple micro-operations of the same type to be processed in parallel. It should be understood that... Figure 1 This is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not illustrated for the sake of brevity, such as branch prediction mechanisms, address translation, or memory management mechanisms.

[0060] Device 2 also includes loop control circuitry 40, which is arranged to assist in controlling the execution of program loops under certain conditions. Loop control circuitry 40 is arranged to detect the presence of certain types of program loops, such as zero-overhead loops defined by dedicated loop instructions (e.g., loop start and loop end instructions). Loop control circuitry stores loop control data in loop control cache 42 (also called loop control storage circuitry). Referring to this loop control data, loop control circuitry 40 can control device 2 to execute loops in a more efficient manner. For example, using zero-overhead loops, loop control circuitry 40 can cause device 2 to execute only the loop body in at least some iterations of the loop, thereby avoiding repeated execution of the loop instructions themselves. Loop control circuitry 40 can also respond to other forms of loops by detecting the presence of such loops and implementing loop performance modification operations (e.g., by disabling the execution of control flow change instructions defining the loop, instead relying on loop control data, or by using a more efficient performance mode to execute loop iterations).

[0061] Device 2 supports one or more performance modification procedures that can be employed to improve the performance of device 2 (e.g., by executing workloads faster and / or consuming less power). The device implements these performance modification procedures based on prompts included in program code, which may signal the opportunity to execute such procedures based on, for example, the expected access frequency to certain data locations, the data type to be executed, or the expected value of the data item. The modified procedure differs from the normal operation procedure in that it performs one or more performance measurements based on the prompts.

[0062] In response to a prompting instruction executed by device 2, prompting control circuit 50 populates prompting control cache 52 (also called prompting control storage circuit) with prompting control data that identifies the performance modification operation to be performed. Device 2 can then use this performance measurement to operate accordingly.

[0063] A wide variety of performance measurements can be implemented, and in fact, the timing of these measurements can vary depending on the type of performance measurement being implemented. However, as an illustrative example only, one form of hint that can be generated is called a non-temporary hint, and if such a non-temporary hint is associated with a given register, this can trigger the implementation of a performance measurement when the data held in that register is used in a particular manner. In a specific example implementation, when data held in a given register is used as a pointer for a memory access operation, the accessed data can be marked as non-temporary. This allows for improved overall device performance by allowing for more efficient use of the data cache, as such data marked as non-temporary can be evicted from the cache more quickly than would otherwise be, increasing the likelihood that other data to be reused will remain in the cache.

[0064] As another example of a generateable hint, a prefetch hint can be generated in association with a given register to indicate that data to be used by one or more subsequent instructions that reference that given register should be prefetched into the cache to improve performance when those instructions are actually executed. Such prefetching activity can be performed before these instructions are executed. As a result of such prefetching, an improvement in the overall performance of the device is expected.

[0065] As another example of a supported hint type, a data value hint can be generated to be associated with a given register, thus providing a hint about the value that might be stored in that given register. Such data value hints can be used in various ways. As an example only, such data value hints could affect branch prediction mechanisms, for example, by making more likely branch paths distinguishable from less likely branch paths (e.g., if which path is taken depends on whether the value in the given register matches a specific value (e.g., the value 0), and the hint metadata indicates that the expected value in that given register is indeed 0).

[0066] As another example of a supported hint type, branch hints can be generated to be associated with a given register. This can be used, for example, to indicate that the value stored in the given register contains a function pointer, i.e., the address that will be used to identify the function to which a subsequent indirect branch instruction might branch. By using such branch hints, a prompt is provided to the branch prediction circuitry so that instructions are prefetched starting from the address identified in the given register. If, when appropriate, an indirect branch instruction is encountered that identifies the given register as containing an address indication for the branch destination, these prefetched instructions can be used if the branch predictor predicts that the branch will be taken, thereby improving performance.

[0067] A key point to understand here is that the presence or absence of prompts, and therefore the use of one or more performance modification procedures (which can modify how the data processing operations defined by the data processing instructions are executed), do not change the data processing results of these data processing operations. In other words, the data processing results generated as a result of the data processing instructions (other than prompt instructions) received by the decoding circuit do not change based on whether prompts are used. Therefore, the data processing results remain the same (depending only on the received data processing instructions and the data values ​​referenced by those instructions).

[0068] In addition to the previously mentioned prompt instructions, the instruction sequence may also include one or more instances of register prompt clear instructions. This can result in the generation of a control signal that is sent to the prompt control circuitry 50 to update the prompt control data stored in the prompt control cache 52, specifically by clearing one or more existing entries of the prompt control data. The register prompt clear instruction may, for example, identify one or more registers, causing the prompt metadata associated with those registers to be cleared, or alternatively, it may take the form of a "clear all" prompt clear instruction, which may, for example, cause all existing prompt control data stored in the prompt control cache 52 to be cleared. Where multiple different types of prompts are supported, the register prompt clear instruction may identify type information, thus restricting the clearing activity to one or more of a given type of prompt.

[0069] When an exception occurs, the hint control cache 52 will also be cleared. When an exception occurs (e.g., due to triggering an interrupt / to process external input), device 2 performs a context switch to replace the contents of at least some registers (e.g., the program counter register) in register 14 with data relevant to the new context associated with handling the exception. To avoid using performance modification procedures that might be appropriate when executing program code in a context for handling exceptions (where such performance modification procedures might be inappropriate), the hint control circuitry 50 is configured to refresh the hint control cache 52 when an exception occurs.

[0070] Figure 2 Example 60 loop control data items are shown. Loop control data 60 is stored in loop control cache 42 and is used by loop control circuitry 40 to represent loop details when a program loop is detected in the program code. Loop control data 60 can then be used to control the execution of loop iterations, ensuring that only the program loop body is executed and preventing further execution of the program flow control instructions defining the loop. Figure 2As shown, loop control data 60 includes a loop start field 62 that identifies the start of a program loop and a loop end field 64 that identifies the end of a program loop. The loop start and loop end can be directly identified by specifying the addresses of the instructions that form the loop start and loop end. In other examples, the loop end can be identified as an offset from the loop start address, or by the number of instructions in the loop body, to reduce the size of loop control data 60. The loop control data 60 item depicted also includes a valid bit 68 to indicate whether the loop control data 60 item is valid. Thus, the valid bit 68 provides a way to quickly invalidate the loop control data 60 item by switching the valid bit 68 from a valid state to an invalid state. In some examples, loop control data 60 may also include a count field 70 to identify the expected number of further iterations of the loop to be executed. However, since loop control data can be flushed from loop control cache 42 when an exception occurs, loop count data is usually also stored separately in such a way that loop count data is maintained even when an exception occurs, to ensure that the loop is executed the expected number of times even when an exception occurs during the execution of such a loop.

[0071] Figure 3 The zero-overhead loop behavior is illustrated schematically. Figure 3 The instruction sequence is shown, where instructions 05, 06, and 07 (representing load, load, and multiplication instructions, respectively) are instructions to be repeatedly executed. Including the loop termination instruction as instruction 08, which instructs the program flow to be transferred to the position marked "loop start." Therefore, this instruction sequence forms a program loop, whereby at least instructions 05, 06, and 07 will be repeatedly executed. The execution of the prompt instructions at instructions 03 and 04 is discussed below.

[0072] The loop termination instruction is a specific type of instruction used to define a zero-overhead loop (also known as a low-overhead loop). The loop control circuit 40 identifies the zero-overhead loop and stores loop control data that indicates that loop. Figure 3 The loop control data used for this overhead loop is depicted, where instruction 04 is identified as the start of the loop body and instruction 07 is identified as the end of the loop body. The valid bit is set to 1 to indicate that the loop control data item is valid. The loop control circuit then controls the processing circuit to iterate only on the program loop body, thus omitting the execution of the loop end instruction itself.

[0073] It should be understood that zero-overhead program loop behavior does not mean that there is no overhead associated with supporting loop behavior, but rather that the overhead is reduced. For example, loop control program instructions (such as loop end instructions) will occupy a slot in the pipeline during the first pass through the program loop, but will be omitted in subsequent passes, where the loop behavior is controlled by loop control circuit 40.

[0074] Therefore, using zero-overhead loops in this way reduces the overhead associated with repeated execution of loop termination instructions. This can be achieved... Figure 3 As seen on the right-hand side, this diagram schematically illustrates the program flow through a sequence of instructions. For example... Figure 3 As can be seen, in the first iteration of the loop, all instructions from instruction 03 to instruction 08 are executed. Then, the presence of the loop termination instruction causes the program flow to shift to the beginning of the loop body at instruction 04. However, in the next iteration of the loop, the loop termination instruction is omitted, and the program flow proceeds directly from instruction 07 to the next iteration of the loop at instruction 04.

[0075] In the third iteration of the loop, an exception occurs, as illustrated by the asterisk. Device 2 then handles this exception. However, when switching to the exception handler, the loop control cache 42 is cleared. Therefore, upon returning from the exception, although loop execution continues, the loop control circuit 40 cannot prevent the execution of the loop termination instruction. Instead, the loop termination instruction is re-executed, at which point the loop control data is refilled, preventing the loop termination instruction from being executed in further iterations.

[0076] To indicate to the processing circuitry that a performance modification procedure should be applied, a cue instruction can be included in the instruction sequence. When a cue instruction is used to indicate a performance modification procedure to be applied to an instruction forming part of a loop, the cue instruction can be placed inside or outside the loop. Figure 3 Examples of each method are shown, where instruction 03 is placed before the "loop start" position (and therefore outside the loop), and prompt instruction 04 is placed after the "loop start" position (and therefore inside the loop).

[0077] Hint 03 will be executed before the first iteration of the loop. Hint control data corresponding to hint 03 will be stored, and the performance modification procedure will be applied as specified. However, in the event of an exception, the hint control data will be cleared. If an exception occurs during an iteration of the program loop, hint 03 will not be re-executed upon returning from the exception, and the remaining loop iterations will be performed without using the performance modification procedure specified by hint 03. Therefore, any performance benefits associated with using the performance modification procedure will be lost.

[0078] For prompt instruction 04, even if an exception occurs during the execution of the loop iteration, prompt instruction 04 will be re-executed in the next iteration of the loop because it forms part of the loop body, and therefore the performance modification operation will still be performed. However, since prompt instruction 04 is included in the program loop body and executed in each iteration, device 2 produces performance effects associated with the repeated execution of this instruction.

[0079] The performance impact caused by repeated execution of prompt instructions can be mitigated by the techniques described herein, while ensuring that prompt instructions are executed after an exception, thereby allowing for performance modification procedures for iterations of the program loop after an exception.

[0080] Figure 4 The loop behavior based on the example is illustrated schematically, where prompt instructions are excluded from the modified program loop body of the zero-overhead loop.

[0081] exist Figure 4 The diagram illustrates a similar program loop body involving two load instructions 04-05, a multiplication instruction 06, and a loop end instruction 07. Here, a prompt instruction 03 is included as part of the program loop body following the "loop start" position. The program flow when this sequence of instructions is executed on an apparatus incorporating the technology of this disclosure, according to an example, will now be described.

[0082] During the first loop pass, cue instruction 03 is executed, causing cue control cache 52 to be filled with cue control data indicating performance modification procedures to be performed for one or more subsequent instructions. In this example, instructions 04 through 06 are then executed, followed by loop termination instruction 07. As in the previous example, the loop termination instruction causes loop control data to be filled into loop control cache 42. In this example, during the first loop pass, the loop control data (not shown) identifies cue instruction 03 as the first instruction in the program loop body and multiplication instruction 06 as the last instruction in the program loop body.

[0083] Therefore, the next iteration of the loop begins with cue instruction 03. Since the cue control cache 52 has already been filled based on cue instruction 03, the cue instruction has no cueing effect here. However, in this example, the processing circuitry detects the cue instruction at the beginning of the program loop body and therefore modifies the loop control data accordingly. Figure 4 The form depicted is such that the instruction following the prompt instruction is marked as the beginning of the modified program loop body, where instruction 04 is now marked as the first instruction in the loop body. Then, the program flow advances to the last instruction (instruction 07) of the modified program loop body, and then loops back to the beginning of the modified program loop body based on the modified loop control data.

[0084] Therefore, the third iteration of the loop begins with load instruction 04. In this way, the execution of cue instructions can be excluded from subsequent iterations of the loop, and the loop will only iterate on the instructions of the modified program loop body, while the already filled cue control data will enable the performance modification process to be performed.

[0085] If an exception occurs (e.g., an interrupt), the prompt control data and loop control data will be cleared / invalidated. Therefore, the first iteration of the loop after the exception will involve re-execution of the loop end instruction 07, resulting in the refilling of the loop control data, thus identifying the prompt instruction 03 (as specified by the loop end instruction) as the first instruction of the program loop body. In the next iteration of the loop, the prompt instruction 03 will be executed again. The processing circuitry can detect that the prompt instruction is the first instruction in the program loop body (e.g., by comparing the program counter with the loop control data, or by monitoring a flag set at the beginning of the loop and cleared when an instruction that is not a prompt instruction is executed). The loop control data is then modified to remove the prompt instruction 03 from the modified program loop body again, such that further iterations of the program loop involve only the execution of instructions 04 through 06.

[0086] Therefore, this method reduces the number of times prompt instructions need to be executed, while still ensuring that prompt instructions are executed after an exception occurs, so as to restore the prompt control data that was cleared when the exception occurred.

[0087] However, utilizing Figure 4 The method executes prompts in both the first and second iterations of the loop. Figure 5 The loop behavior is illustrated schematically, in which prompt instructions are excluded from the modified loop body during the first iteration of the program loop, thereby preventing them from being executed in the second iteration.

[0088] In this example, the instruction sequence includes a loop start instruction 03. This loop start instruction may, for example, specify the conditions for executing further iterations of the program loop, or specify the number of iterations to be executed. In response to the execution of the loop start instruction, followed by the execution of a prompt instruction, the processing circuitry indicates that modified loop control data can be used once a loop end instruction is encountered, in order to prevent future execution of the prompt instruction 04. Therefore, loop modification information is provided to the loop control circuitry 40. When a loop end instruction is encountered, modified loop control data can be populated, which excludes the prompt instruction 04 from the modified program loop body. Thus, the prompt instruction can be excluded in the second iteration of the program loop.

[0089] When an exception occurs (such as an interrupt), the loop control data is cleared, causing the program flow to proceed to the prompt instruction. The processing circuitry can then detect the prompt instruction occurring at the beginning of the program loop and cause the newly filled loop control data to exclude the prompt instruction from the modified program loop body.

[0090] Figure 6 The loop behavior is illustrated schematically, where two prompt instructions are excluded from the modified program loop body. It should be understood that these techniques are generally applicable to situations using multiple prompt instructions. Here, the loop control data is modified in a manner similar to that discussed above; however, the presence of two prompt instructions occurring at the beginning of the program loop is detected, and modified loop control data is stored that identifies instruction 05 following the last prompt instruction as the start of the modified program loop body. Therefore, in the first iteration of the loop, the program flow will proceed through the instruction sequence from instruction 03 to the loop end instruction 08.

[0091] Although not depicted, this could be used here if a loop start instruction exists. Figure 5 The method is to provide loop modification information to the loop control circuit 40 when a prompt instruction is detected at the beginning of the loop.

[0092] Conversely, the prompt instruction is executed a second time in the second iteration of the program loop. At this point, a prompt instruction occurring at the beginning of the program loop body will be detected. (This can be done by comparing the program counter with loop control data when the prompt instruction is executed, or by comparing a flag that is set at the beginning of the loop and cleared when any instruction other than the prompt instruction is executed. Therefore, if the flag is set when the prompt instruction is executed, the prompt instruction occurs at the beginning of the program loop body.) If the prompt instruction is excluded from the modified program loop body, subsequent iterations of the loop will continue without re-executing the prompt instruction.

[0093] This technique can also be applied to situations where zero-overhead loop instructions are not used. Figure 7 The loop behavior is illustrated schematically, in which prompt instructions are excluded from the modified program loop body of a loop that does not use zero-overhead loop instructions. In this example, instruction 08 is a conditional branch instruction, for which program flow is transferred to instruction 03 if a branch is taken. The loop control circuit 40 may include a loop detection circuit capable of detecting loops such as... Figure 7The loop control circuit 40 can perform loop performance modification operations, such as storing loop control data that identifies the program loop body for the loop. The loop control circuit 40 can then use this loop control data to execute only the program loop body (instead of establishing the loop's branch instructions). Therefore, in a similar manner to zero-overhead loops, the loop control circuit 40 can utilize the loop detection circuit to execute only the loop body.

[0094] In such cases, the processing circuitry can detect the prompt instruction 03 occurring at the beginning of the program loop body and exclude the prompt instruction from the modified program loop body executed in subsequent iterations of the loop. Therefore, once the prompt control data associated with the prompt instruction has been stored, further execution of the prompt instruction can be prevented.

[0095] Figure 8 This is a flowchart illustrating the operation of a data processing apparatus according to the first method. At step 802, it is determined whether a program loop has been identified. As discussed above, the program loop may be a zero-overhead loop identified using loop control instructions (such as loop start / loop end instructions), or the program loop may be identified separately based on the sequence of instructions to be executed.

[0096] Once a program loop is identified, loop control data identifying the loop body is stored at step 804. This loop control data can be stored in loop control cache 42, and can cause further iterations of the loop to execute only the loop body (rather than any program flow control instructions that define the loop).

[0097] If one or more prompt instructions are subsequently identified at the beginning of the loop body at step 806, the loop control data is modified at step 810 to exclude one or more prompt instructions from the modified loop body, and then the modified loop body is executed in subsequent iterations of the program loop. Therefore, this method prevents further execution of prompt instructions when the prompt control data has already been populated based on them. However, if an exception (such as an interrupt) occurs, causing the prompt control data and loop control data to be cleared, the prompt instructions will be executed again, allowing for the implementation of performance modification procedures associated with the prompt instructions and realizing any associated performance benefits.

[0098] Figure 9This is a flowchart illustrating the operation of a data processing apparatus according to the second method. In this second method, the processing circuitry is arranged to detect one or more prompting instructions occurring after a loop start instruction at step 902. Since the prompting instructions occur after the loop start instruction, it is known that they will occur at the beginning of the program loop body. Therefore, after these prompting instructions have been executed, they can be excluded from the program loop body. Therefore, at step 904, loop modification information is provided to the loop control circuitry 40. When it is determined at step 906 that a loop end instruction has been reached, loop control information is stored, which identifies the modified loop body that has excluded one or more prompting instructions based on the provided loop modification information. Therefore, the modified loop body can be represented in the loop control data without first filling the loop control data with an unmodified loop body. This method avoids executing the prompting instructions in the second iteration of the program loop, thereby further improving the overhead caused by the prompting instructions.

[0099] The concepts described herein can be specifically embodied in a system comprising at least one packaged chip. The previously described apparatus is implemented in this at least one packaged chip (either in a specific chip of the system or distributed across more than one packaged chip). The at least one packaged chip is assembled on a board along with at least one system component. Chip-containing products may include systems assembled on another board having at least one other product component. The system or chip-containing product may be assembled into a housing or onto a structural support (such as a frame or blade).

[0100] like Figure 10 As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the devices described above are implemented on one chip or distributed across two or more chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package, which includes a protective housing (e.g., made of metal, plastic, glass, or ceramic) housing the semiconductor device implementing the above-described devices, and connectors such as pads, solder balls, or pins for connecting the semiconductor device to the external environment. Where more than one chip 400 is provided, these chips may be provided as individual integrated circuits (provided as separate packages), or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., using interposers, or by using three-dimensional integration to provide a multilayer chip product comprising two or more vertically stacked integrated circuit layers).

[0101] In some examples, a collection of chiplets (i.e., small modular chips with specific functionalities) may be referred to as a chip in itself. Chipslets may be individually packaged in semiconductor packages and / or packaged together with other chiplets in multi-chiplet semiconductor packages (e.g., using interpolators, or by using three-dimensional integration to provide multi-layer chiplet products comprising two or more vertically stacked integrated circuit layers).

[0102] One or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or flexible substrate materials such as paper, plastic, or textile materials. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include any one or more of the following: another packaged chip (e.g., supplied by a different manufacturer or manufactured at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0103] A chip-containing product 416 is manufactured, comprising a system 406 (including a board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product components 412 include one or more additional components that are not part of system 406. As an example, in a non-exhaustive list, one or more product components 412 may include user input / output devices such as keyboards, touchscreens, microphones, speakers, displays, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on an additional board 414.

[0104] Plate 402 or another plate 414 may be disposed on or within the equipment housing or other structural support (e.g., frame or blade) to provide a product that can be disposed of by a user and / or intended for operational use by personnel or company.

[0105] System 406 or chip-containing product 416 can be at least one of the following: end-user product, machine, medical device, computing or telecommunications infrastructure product, or automated control system. For example, as a non-exhaustive list, a chip-containing product can be any of the following: telecommunications equipment, mobile phone, tablet computer, laptop computer, computer, server (e.g., rack server or blade server), infrastructure equipment, networking equipment, vehicle or other automotive product, industrial machine, consumer device, smart card, credit card, smart glasses, avionics equipment, robotic equipment, camera, television, smart TV, DVD player, set-top box, wearable device, home appliance, smart meter, medical device, heating / lighting control equipment, sensor, and / or control system for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0106] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0107] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features may be provided individually or in combination. For example, “at least one of the following: [A], [B], and [C]” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0108] While exemplary examples of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise examples, and various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims.

Claims

1. An apparatus, the apparatus comprising: A processing circuit, the processing circuit being used to execute a processing operation specified by program instructions; and A loop control circuit, the loop control circuit being used to identify a program loop specified by the program instructions, and to store loop control data for storing a program loop body indicating the program loop, the program loop body excluding any program flow control instructions specifying the program loop; The loop control circuit is used to control the processing circuit to execute the loop iteration of the program loop body indicated by the loop control data; and The processing circuitry therein responds to a prompt instruction occurring at the beginning of a given program loop body, the prompt instruction indicating a performance modification operation to be performed for one or more subsequent program instructions, such that: Loop control data for a given program loop excludes the prompt instruction from the modified program loop body by identifying the instruction following the prompt instruction as the start of the modified program loop body, and The processing circuit executes the performance modification operation specified by the prompt instruction during the iterative execution of the modified program loop body.

2. The apparatus of claim 1, wherein excluding the prompt instruction from the modified program loop body prevents the prompt instruction from being executed in subsequent loop iterations of the given program loop.

3. The apparatus according to claim 1 or claim 2, wherein: The processing circuit is configured to maintain prompt control data, which indicates the performance modification operation process indicated by one or more prompt instructions; and The processing circuit refreshes at least some loop control data and at least some prompt control data in response to an anomaly.

4. The apparatus of claim 3, wherein refreshing the at least some of the loop control data re-enables the execution of the prompting instruction upon returning from the exception.

5. The apparatus according to any of the preceding claims, wherein: The processing circuit, in response to the execution of the prompt instruction, determines whether the loop control data identifies the prompt instruction as the start of the given program loop body; and In response to the loop control data identifying the prompt instruction as the start of the given program loop, the processing circuitry is configured to modify the loop control data to exclude the prompt instruction from the modified program loop.

6. The apparatus according to any of the preceding claims, wherein: The processing circuit, in response to the execution of an additional prompt instruction, determines whether the loop control data identifies the additional prompt instruction as the start of the modified program loop body; and In response to the loop control data identifying the additional prompt instruction as the start of the modified program loop, the processing circuit is configured to further modify the loop control data to exclude the additional prompt instruction from the modified program loop.

7. The apparatus according to any preceding claim, wherein the loop control circuit is configured to identify the program loop based on a loop end instruction, the loop end instruction specifying the program loop body of the program loop.

8. The apparatus of claim 7, wherein the loop control circuit is configured to identify a loop start instruction, the loop start instruction controlling the number of times the program loop body is to be executed.

9. The apparatus of claim 7 or claim 8, wherein the program loop is a zero-overhead loop.

10. The apparatus according to any of the preceding claims, wherein: The processing circuit, in response to a loop start instruction followed by one or more prompt instructions, provides loop modification information to the loop control circuit, the loop modification information identifying the instruction following the one or more prompt instructions as the start of a modified program loop body; and The loop control circuit is configured to utilize the received loop modification information by adjusting the stored loop control data based on the received loop modification information when storing loop control data in response to a loop end instruction. The stored loop control data identifies the start of the modified program loop body.

11. The apparatus according to any of the preceding claims, wherein: The loop control circuit includes a loop detection circuit configured to detect program loops defined by one or more branch instructions. and The loop detection circuit stores loop control data indicating the loop body of the detected program loop in response to the detection of a program loop, so as to perform loop performance modification operations aimed at improving the performance of subsequent iterations of the detected program loop.

12. The apparatus according to claim 11, wherein: The loop control circuit further includes a loop buffer circuit for storing loop instruction data, which indicates at least some instructions in the program loop body; and The loop buffer circuit is configured to store the loop instruction data in response to the loop detection circuit detecting a program loop.

13. The apparatus according to any of the preceding claims, wherein: The processing circuit responds to a plurality of prompting instructions occurring at the beginning of the given program loop body such that: The loop control data for the given program loop excludes the plurality of prompts from the modified program loop body by identifying the instruction following the plurality of prompts as the beginning of the modified program loop body, and The processing circuit performs the corresponding performance modification operation process specified by the plurality of prompt instructions during the loop iteration of the modified program loop body.

14. The apparatus according to any preceding claim, the apparatus comprising a loop control data storage circuit for storing the loop control data.

15. A computer-readable medium for storing computer-readable code for manufacturing an apparatus, the apparatus comprising: A processing circuit, the processing circuit being used to execute a processing operation specified by program instructions; and A loop control circuit, the loop control circuit being used to identify a program loop specified by the program instructions, and to store loop control data for storing a program loop body indicating the program loop, the program loop body excluding any program flow control instructions specifying the program loop; The loop control circuit is used to control the processing circuit to execute the loop iteration of the program loop body indicated by the loop control data; and The processing circuitry therein responds to a prompt instruction occurring at the beginning of a given program loop body, the prompt instruction indicating a performance modification operation to be performed for one or more subsequent program instructions, such that: Loop control data for a given program loop excludes the prompt instruction from the modified program loop body by identifying the instruction following the prompt instruction as the start of the modified program loop body, and The processing circuit executes the performance modification operation specified by the prompt instruction during the iterative execution of the modified program loop body.

16. A system comprising: The apparatus according to any one of claims 1 to 14, wherein the apparatus is implemented in at least one packaged chip; At least one system component; and plate; The at least one packaged chip and the at least one system component are assembled on the board.

17. A chip-containing product, the chip-containing product comprising the system of claim 16, the system being assembled on an additional board together with at least one other product component.

18. A method, the method comprising: Execute the processing operations specified by the program instructions; Identify the program loop specified by the program instructions, and store loop control data that indicates the program loop body, the program loop body excluding any program flow control instructions that specify the program loop; Control the execution of the loop iterations of the program loop body as indicated by the loop control data; as well as In response to a prompt instruction occurring at the beginning of a given program loop body, the prompt instruction indicating a performance modification procedure for one or more subsequent program instructions, such that: Loop control data for a given program loop excludes the prompt instruction from the modified program loop body by identifying the instruction following the prompt instruction as the start of the modified program loop body, and The performance modification operation process specified by the prompt instruction is executed during the loop iteration of the modified program loop body.

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