Method for improving success rate of grinding and layer removing before chip failure analysis

Abstract

The invention provides a method for improving the success rate of grinding and layer removal before chip failure analysis. The method comprises the following steps: step 1, preparing a gasket; 2, slotting in the central area of the gasket according to the size of the target chip; step 3, filling the groove with glue; and step 4, after the target chip is placed in the groove, the glue is cured. According to the method and the device, the delamination flatness of the target chip can be improved, so that the efficiency and the success rate of failure analysis are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for improving the success rate of chip failure analysis before grinding and delamination. Background Technology

[0002] In the field of semiconductor failure analysis, layer-by-layer peeling is a commonly used sample processing method. However, if the chip is too small (approximately 1mm*1mm) or the failure location is close to the chip edge, it will pose a significant challenge to the chip grinding and delamination process, mainly due to the problem of maintaining the flatness of the chip surface during the delamination process. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method to improve the success rate of chip failure analysis by grinding and delamination, in order to solve the problem of poor chip surface flatness after grinding and delamination in the prior art.

[0004] To achieve the above and other related objectives, this application provides a method for improving the success rate of chip failure analysis before grinding and delamination, comprising:

[0005] Step 1: Prepare the gasket;

[0006] Step 2: Cut a groove in the central area of ​​the pad according to the size of the target chip;

[0007] Step 3: Fill the tank with adhesive;

[0008] Step four: After placing the target chip into the slot, cure the adhesive.

[0009] Preferably, in step one, a wafer fragment with a metal layer is selected and its bevel is ground to a size of 1cm*1cm to serve as a spacer.

[0010] Preferably, in step two, a laser or ion beam is used to create a groove in the central region of the gasket.

[0011] Preferably, the size of the slot is larger than the size of the target chip.

[0012] Preferably, in step three, the adhesive used includes hot melt adhesive or A / B adhesive.

[0013] Preferably, in step four, before curing the adhesive, the target chip and the surface of the pad are adjusted to be on the same horizontal plane.

[0014] Preferably, if it is a hot melt adhesive, it is cured by cooling; if it is an A / B adhesive, it is cured by heating.

[0015] Preferably, the temperature for heat curing is 200℃-220℃.

[0016] Preferably, after step four, the target chip is subjected to grinding and delamination treatment before failure analysis.

[0017] As described above, the method for improving the success rate of pre-grinding delamination in chip failure analysis provided in this application has the following beneficial effects: a groove is cut on the pad according to the size of the target chip, and then the target chip is embedded in the groove and bonded and cured by hot melt adhesive or A / B adhesive. During the curing process, the surface of the target chip and the surface of the pad are adjusted to be on the same horizontal plane to improve the flatness of the delamination of the target chip, thereby improving the efficiency and success rate of failure analysis. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 The diagram shows an existing method of using pads and pseudo-wafers to assist in polishing.

[0020] Figure 2 The flowchart shown is a method for improving the success rate of chip failure analysis before grinding and delamination according to an embodiment of this application.

[0021] Figure 3 The diagram shown is a schematic representation of the device structure formed after each step in the method for improving the success rate of chip failure analysis before grinding and delamination provided in this application embodiment. Detailed Implementation

[0022] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0023] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0027] In chip failure analysis, delamination through grinding is a fundamental and crucial step in sample preparation. The smoothness and accuracy of the grinding process directly impact the failure analysis results. This is especially challenging for small samples after cutting or packaging.

[0028] The problems currently encountered include:

[0029] (1) For ultra-small samples (approximately 1mm*1mm), the grinding rate is relatively fast and the grinding gradient is large, making it difficult to accurately control the grinding to stay at the target layer.

[0030] (2) The target address is close to the edge of the wafer (distance from the edge < 1mm). The grinding gradient at the edge of the wafer is large, making it difficult to accurately control the dwell time on the target layer.

[0031] Existing methods for improving grinding smoothness and their limitations:

[0032] like Figure 1 As shown, using a shim and a dummy die to assist in polishing is suitable for polishing uneven samples where the target location is at the chip edge. During the polishing process, a layer of hot melt adhesive is applied to areas with higher polishing rates to aid in the polishing. The thickness of the dummy die needs to be the same as the thickness of the target wafer; generally, it needs to be a product wafer used as a dummy die.

[0033] To address this issue, this application provides a method for improving the success rate of chip failure analysis before grinding and delamination.

[0034] Please see Figure 2 This illustrates a method for improving the success rate of chip failure analysis before grinding and delamination, provided by an embodiment of this application.

[0035] like Figure 2 As shown, the method for improving the success rate of chip failure analysis through grinding and delamination includes the following steps:

[0036] Step 1: Prepare the gasket;

[0037] Step 2: Cut a groove in the central area of ​​the pad according to the size of the target chip;

[0038] Step 3: Fill the tank with adhesive;

[0039] Step four: After placing the target chip into the slot, cure the adhesive.

[0040] Please see Figure 3 It shows a three-dimensional schematic diagram and a cross-sectional schematic diagram of the device structure formed after each step in the method for improving the success rate of chip failure analysis before grinding and delamination provided in the embodiments of this application.

[0041] In step one, select a wafer fragment with a metal layer, chamfer it and grind it to a size of about 1cm*1cm to use as a spacer.

[0042] In step two, a groove is created in the central region of the pad using a laser or ion beam. The size of the groove is slightly larger than the size of the target chip.

[0043] In step three, the adhesive used includes hot melt adhesive or A / B adhesive.

[0044] In step four, before curing the adhesive, adjust the target chip and the pad surface to be on the same horizontal plane. If it is a hot melt adhesive, cool and cure it; if it is an A / B adhesive, heat and cure it at a temperature of 200℃-220℃.

[0045] After step four is completed, the target chip undergoes grinding and delamination treatment before failure analysis.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] In summary, the method for improving the success rate of pre-grinding delamination in chip failure analysis provided in this application involves creating grooves on a spacer according to the size of the target chip, embedding the target chip into the grooves, and then bonding and curing it with hot melt adhesive or A / B adhesive. During the curing process, the surface of the target chip and the surface of the spacer are adjusted to be on the same horizontal plane to improve the flatness of the target chip after delamination, thereby improving the efficiency and success rate of failure analysis. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0048] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for improving the success rate of chip polishing and delamination before failure analysis, characterized in that, The method includes: Step 1: Prepare the gasket; Step 2: Cut a groove in the central area of ​​the pad according to the size of the target chip; Step 3: Fill the groove with adhesive; Step four: After placing the target chip into the groove, cure the adhesive.

2. The method according to claim 1, characterized in that, In step one, a wafer fragment with a metal layer is selected and its chamfered and ground to a size of 1cm*1cm to serve as the spacer.

3. The method according to claim 1, characterized in that, In step two, a laser or ion beam is used to create a groove in the central region of the pad.

4. The method according to claim 1 or 3, characterized in that, The size of the slot is larger than the size of the target chip.

5. The method according to claim 1, characterized in that, In step three, the adhesive includes hot melt adhesive or A / B adhesive.

6. The method according to claim 1, characterized in that, In step four, before curing the adhesive, the target chip and the surface of the pad are adjusted to be on the same horizontal plane.

7. The method according to claim 5, characterized in that, If the adhesive is a hot melt adhesive, it is cured by cooling; if the adhesive is an A / B adhesive, it is cured by heating.

8. The method according to claim 7, characterized in that, The temperature for heat curing is 200℃-220℃.

9. The method according to claim 1, characterized in that, After step four is completed, the target chip undergoes grinding and delamination treatment before failure analysis.

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