Silicon-based carrier web structure and method of making the same

Abstract

The application discloses a silicon-based support net structure and a preparation method thereof. The silicon-based support net structure comprises a support film, a substrate and a heating assembly. The support film is provided with an imaging window, and the imaging window comprises a hollow observation window used for carrying a sample. The substrate is used for supporting the support film and is provided with a first hollow part. The projection of the observation window on the substrate is located within the range of the first hollow part. The heating assembly comprises a heating layer. The heating layer is arranged on the side of the support film away from the substrate and is used for heating the sample carried in the observation window. The heating layer in the heating assembly can heat the sample in the imaging window, so that the thickness of the sample liquid layer is controlled. The silicon-based support net structure matches a pipeline type cryogenic data collection, so that the collection efficiency of cryogenic electron microscope image data is improved. The substrate can ensure the flatness of the support film and save the time spent in a cryogenic electron microscope focusing process. The support net structure is convenient for batch production, manual operation for pasting the support film on the support net is not needed, and the processing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of cryo-electron microscopy, and in particular to a silicon-based network structure and its fabrication method. Background Technology

[0002] The grid structure is the carrier that supports the sample during cryo-electron microscopy sample preparation. The traditional grid structure uses a metal grid sheet as a base and is covered with a porous support membrane.

[0003] With the widespread application of cryo-electron microscopy, traditional support nets have gradually revealed many problems. Firstly, they are difficult to produce. In related technologies, the prepared support membrane is first floated on the water surface, and then retrieved using a support net, allowing the support membrane to adhere to the net. Individual support membranes are thin and fragile, and the retrieval process requires manual operation, which is difficult and costly, hindering mass production of support membranes. Furthermore, manual operation suffers from inconsistent results and is prone to contamination.

[0004] Secondly, sample preparation is difficult, mainly due to the excessive thickness of the mesh and the difficulty in reproducing the preparation method. The metal mesh of the mesh provides support for the supporting film on it, and the thickness of traditional meshes is generally tens of micrometers. Samples tend to adsorb at the edges of the metal mesh, and the thicker the supporting mesh, the more sample is adsorbed, leading to sample preparation failure. Furthermore, traditional sample preparation methods use filter paper adsorption, which is difficult to reproduce and has poor operability.

[0005] Secondly, the efficiency is low. When imaging cryo-electron microscopy samples in an electron microscope, the underfocus needs to be controlled between -1 and -3 μm. Due to insufficient flatness of the grid, refocusing is required every 5 to 16 images, and the total refocusing takes up about 30% of the time, resulting in low efficiency.

[0006] Furthermore, electron microscopes require electron beams emitted from pole shoes to capture sample information. In related technologies, the observation window used to support the sample in the carrier structure is relatively wide. When the electron beam is focused on the observation window, the carrier structure needs to be displaced in multiple dimensions to ensure comprehensive observation of the sample. On the one hand, this is not conducive to the motion control of the carrier structure. On the other hand, interference between the pole shoes and the structure on top of the support membrane is likely to occur during the multi-dimensional displacement of the carrier structure, affecting the sample observation process.

[0007] In addition, the finished network structure of the related technology includes a silicon oxide layer. When silicon oxide is used in cryo-electron microscopy, electron beam tremor will occur, which will affect the imaging quality.

[0008] Meanwhile, while platinum is used to make electrodes in related technologies, large power is required to adjust the temperature of the grid structure in cryo-electron microscopy. Platinum electrodes are difficult to adapt to large power, making it difficult to apply this type of grid structure to cryo-electron microscopy. Summary of the Invention

[0009] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a silicon-based network structure and a method for its fabrication.

[0010] This application also proposes a method for preparing a silicon-based mesh structure applicable to the above-mentioned silicon-based mesh structure.

[0011] According to a first aspect embodiment of the silicon-based mesh structure of this application, the silicon-based mesh structure includes a support film, a substrate, and a heating assembly. The support film has an imaging window, which includes a perforated observation window for holding a sample. The substrate supports the support film and has a first perforation. The projection of the observation window onto the substrate is located within the area of ​​the first perforation. The heating assembly includes a heating layer disposed on the side of the support film facing away from the substrate, and the heating layer is used to heat the sample held within the observation window.

[0012] The silicon-based network structure according to the embodiments of this application has at least the following beneficial effects:

[0013] 1. The heating layer in the heating assembly can heat the sample within the imaging window, ensuring that the sample is in a liquid state. This facilitates control of the sample liquid layer thickness and improves the imaging effect. Once the liquid layer thickness is controlled, the heating layer stops heating the sample, thereby achieving rapid freezing of the sample.

[0014] 2. The observation window used to hold the sample facilitates the passage of the electron beam, meets the needs of data collection, and is compatible with pipelined cryogenic data collection, thereby improving the efficiency of cryo-electron microscopy image data collection;

[0015] 3. The substrate can ensure the flatness of the supporting film, so that the cryo-electron microscope can meet the observation requirements with a single focusing during the data collection process, saving the time spent in the focusing process of the cryo-electron microscope and improving work efficiency;

[0016] 4. The carrier mesh structure facilitates mass production, eliminating the need for manual application of support film to the carrier mesh and improving processing efficiency.

[0017] According to some embodiments of this application, the imaging window includes a plurality of observation windows, the observation windows extending linearly, and each observation window being arranged within the range of the imaging window.

[0018] According to some embodiments of this application, the length of the imaging window is 1.5-3 mm, and the width of the observation window is 0.6-2.5 μm.

[0019] According to some embodiments of this application, a support beam is provided between adjacent observation windows, the support beam being used to support the support membrane.

[0020] According to some embodiments of this application, the support film is made of silicon nitride.

[0021] According to some embodiments of this application, a support layer is provided on the side of the substrate facing away from the support film, and the support layer is provided with a second hollow portion, wherein the projection of the first hollow portion on the support layer is located within the range of the second hollow portion.

[0022] According to some embodiments of this application, the heating layer includes a first metal layer and a second metal layer stacked together, wherein the first metal layer is located between the second metal layer and the support film.

[0023] According to some embodiments of this application, the first metal layer is made of tungsten, and the thickness of the first metal layer is 70-120 nm.

[0024] According to some embodiments of this application, the second metal layer is made of gold, and the thickness of the second metal layer is 10-60 nm.

[0025] According to some embodiments of this application, the support membrane includes a first support portion for carrying a sample and a support portion surrounding the first support portion, the observation window is disposed on the first support portion, and the thickness of the support portion is greater than the thickness of the first support portion.

[0026] According to some embodiments of this application, the support beam and the support membrane are integrally formed.

[0027] According to some embodiments of this application, the thickness of the first carrier portion is 34 nm to 46 nm.

[0028] According to some embodiments of this application, the thickness of the support portion is 195 nm to 205 nm.

[0029] According to some embodiments of this application, the first carrier portion is flush with the side of the support portion connected to the substrate.

[0030] According to some embodiments of this application, the first bearing portion is flush with the side of the support portion connected to the heating layer.

[0031] According to some embodiments of this application, the silicon-based carrier structure further includes an ion implantation layer located between the support film and the substrate, and the ion implantation layer is in ohmic contact with the heating layer.

[0032] According to some embodiments of this application, the ion implantation layer is made by implanting boron ions into polycrystalline silicon.

[0033] According to some embodiments of this application, the thickness of the ion implantation layer is 195 nm to 205 nm.

[0034] According to some embodiments of this application, the thickness of the support film is 34 nm to 46 nm.

[0035] According to some embodiments of this application, the support film covers the surface of the ion implantation layer, the ion implantation layer is provided with a third hollow portion, and the observation window is disposed within the range of the third hollow portion.

[0036] According to some embodiments of this application, the support film includes a lateral bonding portion, a longitudinal bonding portion, and a second carrier portion. The lateral bonding portion is bonded to the side of the ion implantation layer facing away from the substrate, the longitudinal bonding portion is bonded to the sidewall of the third hollow portion, the second carrier portion is flush with the side of the ion implantation layer connected to the substrate, and the observation window is disposed on the second carrier portion.

[0037] According to some embodiments of this application, the lateral bonding portion is provided with an ohmic contact area, the heating layer passes through the ohmic contact area, and makes ohmic contact with the ion implantation layer.

[0038] According to some embodiments of this application, the heating assembly further includes an electrical connection assembly connected to the heating layer. The electrical connection assembly includes a plurality of first pins and a plurality of second pins, each of the first pins and each of the second pins being used for electrical connection with an external circuit.

[0039] According to some embodiments of this application, the electrical connection assembly further includes a first connection portion, a second connection portion, a first extension portion, and a second extension portion. The first connection portion and the second connection portion are respectively connected to the heating layers on opposite sides in the linear extension direction of the imaging window. The first connection portion is connected to each of the first pins through the first extension portion, and the second connection portion is connected to each of the second pins through the second extension portion.

[0040] According to some embodiments of this application, the first extension and the second extension are parallel, each first pin is perpendicular to the first extension, each second pin is perpendicular to the second extension, and each first pin and each second pin are arranged side by side.

[0041] According to some embodiments of this application, the electrical connection assembly further includes a third connection portion, a fourth connection portion, a third extension portion, and a fourth extension portion. The third connection portion and the fourth connection portion are connected to the heating layer on the same side of the linear extension direction of the imaging window. The third connection portion is connected to each of the first pins through the third extension portion, and the fourth connection portion is connected to each of the second pins through the fourth extension portion.

[0042] According to some embodiments of this application, the third connecting portion gradually increases in size in the direction close to the third extension portion, and the fourth connecting portion gradually increases in size in the direction close to the fourth extension portion.

[0043] According to some embodiments of this application, the third extension and the fourth extension are collinear, each first pin is perpendicular to the third extension, each second pin is perpendicular to the second extension, and each first pin and each second pin are arranged side by side.

[0044] According to some embodiments of this application, the heating layer has an outwardly extending bent connecting portion on the opposite side connecting the third connecting portion and the fourth connecting portion.

[0045] According to the second aspect of this application, the method for fabricating a silicon-based network structure includes:

[0046] Substrate preparation;

[0047] Clean the substrate;

[0048] Silicon oxide is grown and etched on the surface of the substrate;

[0049] A support film is deposited on top of the substrate, and the support film is photolithographically etched and etched.

[0050] The support film is photolithographically etched, and a heating layer is deposited on the surface of the support film;

[0051] The substrate is etched.

[0052] The silicon-based network structure fabrication method according to the embodiments of this application has at least the following beneficial effects:

[0053] 1. By growing and etching silicon oxide on the surface of the substrate to enhance the chemical stability of the grid, the mechanical properties of the grid can be improved and the surface state of the grid can be adjusted, thereby improving the observation effect of cryo-electron microscopy;

[0054] 2. The support film is deposited on top of the substrate, eliminating the need for manual application of the support film on the mesh, thus improving processing efficiency;

[0055] 3. A heating layer is deposited on the surface of the supporting membrane. The heating layer can heat the sample within the imaging window to ensure that the sample is in a liquid state, which makes it easier to control the thickness of the liquid layer and improve the imaging effect. After the liquid layer thickness is controlled, the heating layer no longer heats the sample, thereby achieving rapid freezing of the sample.

[0056] According to some embodiments of this application, cleaning the substrate includes:

[0057] The substrate was cleaned using the RCA process.

[0058] According to some embodiments of this application, silicon oxide is grown and etched on the surface of the substrate, including:

[0059] The silicon oxide was etched using BOE for 60 to 100 seconds.

[0060] According to some embodiments of this application, photolithography is performed on the support film, and a heating layer is deposited on the surface of the support film, including:

[0061] Metal is deposited on the surface of the support film to form the heating layer.

[0062] According to some embodiments of this application, a support film is deposited on top of the substrate, including:

[0063] A support layer is deposited at the bottom of the substrate.

[0064] According to some embodiments of this application, after photolithography of the support film and deposition of a heating layer on the surface of the support film, the method further includes:

[0065] The support layer is photolithographically etched and etched.

[0066] According to some embodiments of this application, the photolithography and etching of the support layer includes:

[0067] The depth of etching the support layer is 250 nm to 270 nm.

[0068] According to some embodiments of this application, a support film is deposited on top of the substrate, and the support film is photolithographically etched and etched, including:

[0069] A first layer of silicon nitride is deposited on top of the substrate to initially form the support film;

[0070] A second layer of silicon nitride is deposited on top of the substrate to form the support film;

[0071] A second layer of silicon nitride is photolithographically etched to form an observation window.

[0072] According to some embodiments of this application, a first layer of silicon nitride is deposited on top of the substrate, comprising:

[0073] The first layer of silicon nitride was deposited using LPCVD, with a thickness of 195 nm to 205 nm.

[0074] According to some embodiments of this application, a second layer of silicon nitride is deposited on top of the substrate, including:

[0075] A second silicon nitride layer was deposited using LPCVD, with a thickness of 34 nm to 46 nm.

[0076] According to some embodiments of this application, the photolithography and etching of the second layer of silicon nitride includes:

[0077] The depth of the second silicon nitride layer is 42nm to 48nm.

[0078] According to some embodiments of this application, etching the substrate includes:

[0079] The substrate was etched using a KOH wet etching process.

[0080] According to some embodiments of this application, after depositing a first layer of silicon nitride on top of the substrate to initially form the support film, the method further includes:

[0081] The first layer of silicon nitride is photolithographically etched and etched to a depth of 204 nm to 216 nm to form an imaging window.

[0082] According to some embodiments of this application, after photolithography and etching of the support layer, the method further includes:

[0083] Photoresist is coated onto the surface of the support film and photolithography is performed. The thickness of the photoresist is greater than the thickness of the heating layer. The process of coating the photoresist and photolithography avoids the imaging window.

[0084] After photolithography is completed, support beams are deposited on the surface of the photoresist and at the imaging window;

[0085] NMP was used to remove the photoresist and the support beams on the photoresist surface.

[0086] According to some embodiments of this application, after the substrate is prepared, the process further includes:

[0087] The substrate is photolithographically etched and etched to form silicon pillars, with the etching depth of the substrate ranging from 490 nm to 510 nm.

[0088] According to some embodiments of this application, after depositing a first layer of silicon nitride on top of the substrate to initially form the support film, the method further includes:

[0089] The silicon pillar and the first layer of silicon nitride are ground.

[0090] According to some embodiments of this application, grinding the silicon pillar and the first layer of silicon nitride includes:

[0091] The silicon pillars were polished using CMP.

[0092] According to some embodiments of this application, a support film is deposited on top of the substrate, and the support film is photolithographically etched and etched, including:

[0093] Polycrystalline silicon is deposited on top of the substrate;

[0094] The polycrystalline silicon was implanted with boron ions.

[0095] Anneal the carrier structure;

[0096] Photolithography and etching of the polysilicon;

[0097] The support film is deposited on the surface of the polycrystalline silicon.

[0098] The support film is photolithographically etched and etched to form the observation window and the ohmic contact area.

[0099] According to some embodiments of this application, polycrystalline silicon is deposited on top of the substrate, including:

[0100] The polycrystalline silicon was deposited using LPCVD, and the thickness of the deposited polycrystalline silicon was 195 nm to 205 nm.

[0101] According to some embodiments of this application, the photolithography and etching of the polycrystalline silicon includes:

[0102] The depth of etching the polysilicon is 200 nm to 210 nm.

[0103] According to some embodiments of this application, the support film is deposited on the surface of the polycrystalline silicon, including:

[0104] The thickness of the support film is 34 nm to 46 nm, deposited by LPCVD.

[0105] According to some embodiments of this application, the photolithography and etching of the support film to form the observation window and the ohmic contact area includes:

[0106] The depth of etching the support film is 42 nm to 48 nm.

[0107] According to some embodiments of this application, after depositing polycrystalline silicon on top of the substrate, the method further includes:

[0108] Silicon oxide is grown and photolithographically etched on top of the polycrystalline silicon.

[0109] According to some embodiments of this application, growing and photolithographically etching silicon oxide on top of the polycrystalline silicon includes:

[0110] Silica was grown using PECVD.

[0111] According to some embodiments of this application, after annealing the carrier network structure, the process further includes:

[0112] BOE was used to remove silica.

[0113] According to some embodiments of this application, etching the substrate includes:

[0114] The substrate was etched using a suspended film method.

[0115] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0116] The present application will be further illustrated below with reference to the accompanying drawings and embodiments. It should be noted that the embodiments illustrated in the following drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0117] Figure 1 This is a schematic diagram of the silicon-based carrier network structure according to the first embodiment of this application;

[0118] Figure 2 This is a schematic diagram of the silicon-based carrier network structure according to the second embodiment of this application;

[0119] Figure 3 This is a schematic diagram of the silicon-based carrier network structure according to the third embodiment of this application;

[0120] Figure 4 This is a top view of a portion of the imaging window in the silicon-based carrier structure of this application;

[0121] Figure 5 This is a schematic diagram of the substrate structure in the silicon-based carrier network structure of this application;

[0122] Figure 6 This is a schematic diagram of the structure after depositing the first layer of silicon nitride in the silicon-based carrier network structure of the first embodiment of this application;

[0123] Figure 7 This is a schematic diagram of the structure after etching the first layer of silicon nitride in the silicon-based carrier network structure of the first embodiment of this application;

[0124] Figure 8 This is a schematic diagram of the structure after depositing the second layer of silicon nitride in the silicon-based carrier network structure of the first embodiment of this application;

[0125] Figure 9 This is a schematic diagram of the structure after etching the second layer of silicon nitride in the silicon-based carrier network structure of the first embodiment of this application;

[0126] Figure 10 This is a schematic diagram of the structure after the heating layer is deposited in the silicon-based carrier network structure of the first embodiment of this application;

[0127] Figure 11 This is a schematic diagram of the structure after etching the support layer in the silicon-based carrier network structure of the first embodiment of this application;

[0128] Figure 12 This is a schematic diagram of the structure after etching the substrate in the silicon-based mesh structure of the first embodiment of this application;

[0129] Figure 13 This is a schematic diagram of the silicon-based carrier network structure coated with photovoltaic material and subjected to photolithography in the first embodiment of this application;

[0130] Figure 14 This is a schematic diagram of the structure after silicon nitride deposition at the photoresist and imaging window in the silicon-based carrier structure of the first embodiment of this application;

[0131] Figure 15 This is a schematic diagram of the silicon-based mesh structure after removing the photoresist in the first embodiment of this application;

[0132] Figure 16 This is a schematic diagram of the structure after etching the substrate in the silicon-based mesh structure of the second embodiment of this application;

[0133] Figure 17 This is a schematic diagram of the structure after depositing the first layer of silicon nitride in the silicon-based carrier network structure of the second embodiment of this application;

[0134] Figure 18 This is a schematic diagram of the structure of the silicon-based carrier network structure after grinding the silicon pillars and the first layer of silicon nitride in the second embodiment of this application;

[0135] Figure 19 This is a schematic diagram of the structure after depositing the second layer of silicon nitride in the silicon-based carrier network structure of the second embodiment of this application;

[0136] Figure 20 This is a schematic diagram of the structure after etching the second layer of silicon nitride in the silicon-based carrier network structure of the second embodiment of this application;

[0137] Figure 21 This is a schematic diagram of the structure after the heating layer is deposited in the silicon-based carrier network structure of the second embodiment of this application;

[0138] Figure 22 This is a schematic diagram of the structure after etching the support layer in the silicon-based carrier network structure of the second embodiment of this application;

[0139] Figure 23 This is a schematic diagram of the structure after etching the substrate in the silicon-based mesh structure of the second embodiment of this application;

[0140] Figure 24 This is a schematic diagram of the structure after polycrystalline silicon deposition in the silicon-based carrier network structure of the third embodiment of this application;

[0141] Figure 25 This is a schematic diagram of the structure after silicon oxide growth in the silicon-based carrier network structure of the third embodiment of this application;

[0142] Figure 26 This is a schematic diagram of the structure of the silicon-based carrier network structure after boron ion implantation into polycrystalline silicon according to the third embodiment of this application;

[0143] Figure 27 This is a schematic diagram of the structure after etching polysilicon in the silicon-based carrier network structure of the third embodiment of this application;

[0144] Figure 28 This is a schematic diagram of the structure after silicon nitride deposition in the silicon-based carrier network structure of the third embodiment of this application;

[0145] Figure 29 This is a schematic diagram of the structure after the heating layer is deposited in the silicon-based carrier network structure of the third embodiment of this application;

[0146] Figure 30 This is a schematic diagram of the structure after etching the support layer in the silicon-based carrier network structure of the third embodiment of this application;

[0147] Figure 31 This is a schematic diagram of the silicon-based carrier network structure after the substrate has been etched, according to the third embodiment of this application.

[0148] Figure 32 This is a top view of the first heating component in the silicon-based mesh structure of this application embodiment;

[0149] Figure 33 This is a silicon-based carrier network structure according to an embodiment of this application. Figure 32 A magnified view of part A in the middle;

[0150] Figure 34 This is a top view of the second heating component in the silicon-based mesh structure of this application embodiment;

[0151] Figure 35 This is a silicon-based carrier network structure according to an embodiment of this application. Figure 34 A magnified view of part B in the middle section.

[0152] Figure label:

[0153] 101. Support film; 102. Imaging window; 103. Observation window; 104. Substrate; 105. First cutout portion; 106. Heating layer; 107. First metal layer; 108. Second metal layer; 109. Support layer; 110. Second cutout portion; 111. First carrier portion; 112. Support portion; 113. Support beam; 114. Photoresist;

[0154] 201. Support film; 202. Imaging window; 203. Observation window; 204. Substrate; 205. First cutout portion; 206. Heating layer; 207. First metal layer; 208. Second metal layer; 209. Support layer; 210. Second cutout portion; 211. First bearing portion; 212. Support portion; 213. Support beam;

[0155] 301. Support film; 302. Imaging window; 303. Observation window; 304. Substrate; 305. First cutout portion; 306. Heating layer; 307. First metal layer; 308. Second metal layer; 309. Support layer; 310. Second cutout portion; 311. Support beam; 313. Ion implantation layer; 314. Lateral bonding portion; 315. Longitudinal bonding portion; 316. Second carrier portion; 317. Silicon oxide layer; 318. Polycrystalline silicon; 319. Ohmic contact area;

[0156] 401. First pin; 402. Second pin; 403. First connection portion; 404. Second connection portion; 405. First extension portion; 406. Second extension portion;

[0157] 501. First pin; 502. Second pin; 503. Third connecting part; 504. Fourth connecting part; 505. Third extension part; 506. Fourth extension part; 507. Bend connecting part; 508. Supporting component. Detailed Implementation

[0158] The embodiments of this application are described in detail below with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0159] In the description of this application, it should be understood that the terms "center", "middle", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0160] In the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0161] In the description of this application, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0162] In the description of this application, the use of terms such as "one embodiment," "some embodiments," "an example," "some instances," "some embodiments," "illustrative embodiment," "example," "specific example," and "some examples" indicates that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0163] like Figure 1 , Figure 2 and Figure 3 The present application provides a silicon-based mesh structure, which includes a support film, a substrate, and a heating component.

[0164] The support film is located on top of the substrate, which supports it. The support film also carries the sample. The electron beam emitted by the cryo-electron microscope first propagates to the sample carried by the support film. After acquiring information from the sample, the electron beam passes through the sample and propagates to the electron receiving equipment in the cryo-electron microscope to obtain more information and ultimately achieve imaging. Specifically, the support film is made of silicon nitride.

[0165] like Figure 1 As shown, in the first embodiment, the substrate is substrate 104, and in the first embodiment, the support film is support film 101; as Figure 2 As shown, in the second embodiment, the substrate is substrate 204, and the support film is support film 201; as Figure 3 As shown, the substrate in the third embodiment is substrate 304, and the support film in the third embodiment is support film 301.

[0166] Furthermore, the support membrane is equipped with an imaging window, which includes an observation window formed by a perforated structure. Understandably, the sample is supported by the observation window, facilitating the electron beam, after acquiring sample information, to pass through the support membrane along the observation window, ensuring electron beam propagation. Specifically, the perforation area of ​​the observation window meets the data collection requirements of cryo-electron microscopy and is compatible with automated cryo-data collection, improving the efficiency of electron microscopy image data collection.

[0167] like Figure 1 As shown, the imaging window in the first embodiment is imaging window 102, and the observation window in the first embodiment is observation window 103; as Figure 2 As shown, the imaging window in the second embodiment is imaging window 202, and the observation window in the second embodiment is observation window 203; as Figure 3 As shown, the imaging window is imaging window 302 in the third embodiment, and the observation window is observation window 303 in the third embodiment.

[0168] Specifically, conventional cryo-electron microscopy spends approximately one-third of its time on focusing during data collection. The support film flatness of this application is better than 1 μm, allowing the cryo-electron microscope to focus only once during data collection, thus saving time spent on focusing.

[0169] Furthermore, the substrate is located at the bottom of the support film, and a first cutout is provided on the substrate to facilitate the electron beam's passage through the mesh structure. After the electron beam passes through the support film, it travels along the first cutout through the mesh structure, thus ensuring the propagation of the electron beam. It is understood that the projection of the observation window onto the substrate lies within the area of ​​the first cutout.

[0170] like Figure 1 As shown, the first hollow portion in the first embodiment is the first hollow portion 105; as Figure 2 As shown, in the second embodiment, the first hollow portion is the first hollow portion 205; as Figure 3 As shown, the first hollow part is the first hollow part 305 in the third embodiment.

[0171] Furthermore, the heating component is located on top of the support membrane, and the heating component includes a heating layer that surrounds the imaging window to uniformly heat the sample at various locations within the imaging window.

[0172] like Figure 1 As shown, the heating layer in the first embodiment is heating layer 106; as Figure 2 As shown, in the second embodiment, the heating layer is heating layer 206; as Figure 3 As shown, the heating layer in the third embodiment is heating layer 306.

[0173] When a sample is supported on a supporting membrane, the liquid layer may become too thick, affecting cryo-electron microscopy imaging. If the liquid layer freezes into a solid ice layer when it becomes too thick, it is difficult to further reduce the thickness of the ice layer. Therefore, the heating element can heat the sample, keeping it in a liquid state, which facilitates the reduction of the liquid layer thickness. When the liquid layer thickness is reduced to the target value, the heating element stops heating the sample, thus achieving rapid freezing of the sample.

[0174] The sample liquid layer thinning methods can include natural evaporation thinning, plasma wind thinning, and electrospray printing. Specifically, in the plasma wind thinning method, plasma wind can accelerate the gas flow rate on the surface of the sample liquid layer, thereby increasing the evaporation rate of the sample liquid layer and achieving thinning of the sample liquid layer.

[0175] In some examples, such as Figure 4 As shown, the imaging window includes several observation windows, with support beams between adjacent observation windows, and each observation window can support the sample.

[0176] In each of these embodiments, the observation windows extend linearly. In some embodiments, the imaging window extends in a straight line, and the observation windows are arranged linearly within the area of ​​the imaging window, with the arrangement direction of the observation windows being the same as the extension direction of the observation windows. In other embodiments, the imaging window consists of several windows arranged side by side, with each window connected end to end, forming a zigzag shape, and the observation windows are arranged within the area of ​​the imaging window.

[0177] Furthermore, in existing cryo-electron microscopy observations, the observation window of a traditional grid structure has certain width and length dimensions. To ensure comprehensive observation, the grid structure needs to be moved in both the length and width directions, making the movement process of the grid structure relatively complex and affecting the efficiency of observation. In contrast, the observation window of the grid structure in this application extends linearly, meaning that the width of the observation window is smaller and the length dimension is larger. The grid structure only needs to be moved in the length direction to ensure comprehensive observation, which is beneficial for the movement control of the grid structure and can also avoid interference between the grid structure and the pole pieces of the electron microscope.

[0178] Specifically, the electron microscope is equipped with pole pieces for emitting and receiving electron beams. The electron beam emitted by the pole pieces can be focused onto the observation window to acquire information about the sample within the window, and then the sample information is transmitted back to the pole pieces, thus enabling sample observation. In actual implementation, as the grid structure moves along the length of the observation window, the electron beam continuously acquires information about the sample, ensuring comprehensive observation.

[0179] Therefore, the grid structure can perform linear, pipeline-style cryogenic data collection, improving the efficiency of electron microscope image data collection.

[0180] In some examples, the imaging window length is 1.5-3 mm, where the length can be set to any value between 1.5 mm and 3 mm. Specifically, the imaging window length can be set to 2 mm or 2.5 mm. Meanwhile, the observation window width is 0.6-2.5 μm, where the width can be set to any value between 0.6 μm and 2.5 μm. Specifically, the observation window width can be set to 1 μm or 2 μm. It is evident that the area of ​​the observation window is approximately 10 times the area required for data collection, facilitating pipelined cryogenic data collection while meeting data collection needs.

[0181] In some examples, there is a certain gap between adjacent observation windows. A support beam is provided in this gap area to support the support membrane, thereby ensuring the structural strength of the support membrane and preventing deformation of the support membrane during observation, which would lead to a decrease in observation accuracy.

[0182] In addition, the specific form of the support beam can be set according to the actual situation. For example, the support beam can include a main support beam and a secondary beam. The width of the main support beam can be set to 50-90μm, and the width of the secondary beam can be set to 5-15μm.

[0183] In the first embodiment, the support beam is support beam 113; in the second embodiment, the support beam is support beam 213; and in the third embodiment, the support beam is support beam 311.

[0184] In some examples, a support layer is provided at the bottom of the substrate. On the one hand, the support layer can improve the strength of the carrier structure; on the other hand, the support layer can ensure the flatness of the bottom surface of the carrier structure.

[0185] like Figure 1 As shown, in the first embodiment, the support layer is support layer 109; as Figure 2 As shown, in the second embodiment, the support layer is support layer 209; as Figure 3 As shown, the support layer in the third embodiment is support layer 309.

[0186] The support layer, located at the bottom of the electron microscope grid, enhances the thermal stability of the grid structure. Made of a material with a low coefficient of thermal expansion, the support layer ensures the dimensional stability of the grid structure during temperature changes. During cryo-electron microscopy observation, the sample needs to be frozen. The support layer prevents the grid structure from bending, twisting, or deforming due to temperature changes, avoiding sample displacement or image blurring caused by grid deformation, thus providing a stable observation environment for the experiment.

[0187] Meanwhile, with the support layer in place, the carrier structure can be placed flat within the cryo-electron microscope, ensuring its positional stability within the microscope.

[0188] Furthermore, to ensure the propagation of the electron beam, the support layer is provided with a second hollow section. After acquiring information from the sample, the electron beam first passes through the substrate along the first hollow section, then passes through the support layer along the second hollow section, and finally reaches the equipment in the cryo-electron microscope used to receive the electron beam.

[0189] like Figure 1 As shown, in the first embodiment, the second hollow portion is the second hollow portion 110; as Figure 2 As shown, in the second embodiment, the second hollow portion is the second hollow portion 210; as Figure 3 As shown, the second hollow portion is the second hollow portion 310 in the third embodiment.

[0190] In some examples, the heating layer is a two-layer metal structure, comprising a first metal layer and a second metal layer stacked together. The first metal layer is disposed on the surface of the support film, and the second metal layer is stacked on the surface of the first metal layer, i.e., the first metal layer is located between the second metal layer and the support film. Alternatively, the heating layer is a single-layer metal structure.

[0191] like Figure 1 As shown, the first metal layer in the first embodiment is a first metal layer 107, and the second metal layer in the first embodiment is a second metal layer 108; as Figure 2 As shown, in the second embodiment, the first metal layer is a first metal layer 207, and in the second embodiment, the second metal layer is a second metal layer 208; as Figure 3 As shown, the first metal layer in the third embodiment is the first metal layer 307, and the second metal layer in the third embodiment is the second metal layer 308.

[0192] The heating layer conducts heat to the sample held within the observation window, thereby raising the sample temperature and keeping it in a liquid state. Understandably, having the sample in a liquid state makes it easier to reduce the thickness of the liquid layer, thus improving the observational accuracy of cryo-electron microscopy.

[0193] An adhesive layer is used to connect the heating layer and the support film. The adhesive layer can be made of materials such as Ti, TiN, TiW, Cr, Ni, Ta, and TaN.

[0194] The electrode in this application has a relatively high current cross-sectional density, specifically 5 × 10⁻⁶. 5 A / cm 2When the heating layer uses a single-layer metal structure, the electrode metal can be W, Au, Ta, or Cu; when the heating layer uses a two-layer metal structure, the electrode metal can be a combination of W, Au, Ta, and Cu. Specifically, in some embodiments where the heating layer uses a two-layer metal structure, the first metal layer is made of tungsten, and the second metal layer is made of gold. In cryo-electron microscopy, since the entire grid structure is in a low-temperature environment, the heating layer needs to withstand a large heating power to achieve the sample heating process. Therefore, tungsten and gold, which can withstand a large heating power, are used to make the first and second metal layers.

[0195] Meanwhile, both tungsten and gold have good thermal conductivity, facilitating heat transfer from the heating layer to the sample. The thickness of the first metal layer is 70-120 nm, where the thickness can be set to any value between 70 nm and 120 nm; specifically, the thickness of the first metal layer can be set to 90 nm or 100 nm. Furthermore, the thickness of the second metal layer is 10-60 nm, where the thickness of the first metal layer can be set to any value between 10 nm and 60 nm; specifically, the thickness of the first metal layer can be set to 25 nm or 30 nm.

[0196] In the first and second embodiments, the support membrane includes a first carrier portion and a support portion, wherein the thickness of the first carrier portion is smaller and the thickness of the support portion is larger.

[0197] like Figure 1 As shown, in the first embodiment, the first bearing part is the first bearing part 111, and in the first embodiment, the support part is the support part 112; as Figure 2 As shown, in the second embodiment, the first bearing part is the first bearing part 211, and the support part is the support part 212; in addition, as Figure 3 As shown, in the third embodiment, since the thickness of the support membrane 301 is approximately the same at all locations, the first bearing portion and support portion are not provided.

[0198] The first support portion carries the sample, and the supporting portion surrounds the first support portion to ensure the strength of the supporting membrane. It is understood that the observation window is located in the first support portion, while the heating layer is located in the supporting portion, facilitating the heating layer to surround the imaging window.

[0199] Specifically, the thickness of the first carrier portion is 34nm to 46nm, and the thickness of the support portion is 195nm to 205nm.

[0200] In some examples, the support beam and the support membrane are integrally formed. During the fabrication process, observation windows are formed by photolithography, etching, and other processes on the support membrane, while the areas between adjacent observation windows are not etched, thus forming the support beam.

[0201] like Figure 1 As shown, in the first embodiment, the support beam is support beam 113; as Figure 2 As shown, in the second embodiment, the support beam is support beam 213; as Figure 3 As shown, the support beam in the third embodiment is support beam 311.

[0202] In the first and second embodiments, the position of the first support portion differs to some extent. Specifically, in the first embodiment, the first support portion 111 and the support portion 112 are flush with the side of the substrate 104 connected to it. In this case, the sample preparation operation is relatively difficult, but it is convenient for the fabrication of the mesh structure. In the second embodiment, the first support portion 211 and the support portion 212 are flush with the side of the heating layer 206 connected to it. In this case, the sample preparation operation is relatively simple, but the fabrication of the mesh structure is relatively complex, and the position and size of the imaging window are relatively difficult to control.

[0203] In the third embodiment, the silicon-based carrier network structure further includes an ion implantation layer 313, which is located between the support film 301 and the substrate 304, and the ion implantation layer 313 is in ohmic contact with the heating layer 306 on top of the support film 301.

[0204] Specifically, the ion implantation layer 313 is formed by implanting boron ions into polycrystalline silicon 318. Compared to metal heating, the sheet resistance of the ion-implanted polycrystalline silicon 318 is more uniform, and the temperature uniformity is better.

[0205] In the third embodiment, the thickness of the ion implantation layer 313 is 195 nm to 205 nm, and the thickness of the support film 301 is 34 nm to 46 nm.

[0206] In the third embodiment, a support film 301 covers the surface of the ion implantation layer 313. The ion implantation layer 313 forms a third hollow portion through processes such as photolithography and etching, facilitating the electron beam to pass through the ion implantation layer 313 along the third hollow portion. It is understood that the observation window 303 on the support film 301 is disposed within the area of ​​the third hollow portion.

[0207] In the third embodiment, the support film 301 includes a transverse bonding portion 314, a longitudinal bonding portion 315, and a second carrier portion 316. When the support film 301 is disposed on the surface of the ion implantation layer 313, the transverse bonding portion 314 is located at a position where the ion implantation layer 313 does not have a third perforation, and the longitudinal bonding portion 315 is naturally formed on the inner wall of the third perforation of the support film 301. It is understood that the transverse bonding portion 314 is bonded to the top of the ion implantation layer 313, and the heating layer 306 is disposed on the top of the transverse bonding portion 314. Meanwhile, the second carrier portion 316, which has an observation window 303, is located within the area of ​​the third perforation and is used to carry the sample.

[0208] Specifically, the second support portion 316 is flush with the bottom of the ion implantation layer 313.

[0209] In the third embodiment, the lateral bonding portion 314 is provided with an ohmic contact area 319, and the heating layer 306 passes through the ohmic contact area 319 and forms an ohmic contact with the ion implantation layer 313, so that the heating layer 306 can transfer heat to the ion implantation layer 313, and the ion implantation layer 313 surrounding the imaging window 302 and the heating layer 306 together heat the sample.

[0210] In some examples, the heating assembly also includes an electrical connection component that ensures that the heating assembly is electrically connected to an external circuit.

[0211] The electrical connection component is connected to the heating layer and includes several first pins and several second pins. It is understood that each first pin and each second pin is used for electrical connection to an external circuit.

[0212] This application relates to two structural forms of electrical connection components, such as Figure 32 As shown, the first pin in the first heating assembly is the first pin 401, and the second pin in the first heating assembly is the second pin 402; as Figure 34 As shown, the first pin in the second heating component is the first pin 501, and the second pin in the second heating component is the second pin 502.

[0213] In the first type of electrical connection assembly, the electrical connection assembly includes a first connection portion 403, a second connection portion 404, a first extension portion 405, and a second extension portion 406.

[0214] Each first pin 401 is connected to the first extension 405, the first connecting part 403 is used to connect the heating layer and the first extension 405, and the first connecting part 403 is connected to the heating layer on one side of the linear extension direction of the imaging window.

[0215] Meanwhile, each second pin 402 is connected to the second extension 406, the second connection 404 is used to connect the heating layer and the second extension 406, and the second connection 404 is connected to the heating layer on the other side of the linear extension direction of the imaging window.

[0216] Since the first connecting part 403 and the second connecting part 404 are respectively connected to the heating layers on opposite sides, the heating layer and the electrical connection assembly form a circuit, which facilitates the external circuit to energize the heating layer through the electrical connection assembly.

[0217] Furthermore, in the extension direction, the first extension 405 and the second extension 406 are parallel. Each first pin 401 extends perpendicularly to the first extension 405 and outwards from the carrier structure, and each second pin extends perpendicularly to the second extension 406 and outwards from the carrier structure, such that each first pin 401 and each second pin 402 are arranged side by side. Specifically, in the mutually parallel first extension 405 and second extension 406, the first extension 405 is closer to the heating layer, so when the ends of each first pin 401 and each second pin 402 are aligned, the length of the first pin 401 is greater than the length of the second pin 402.

[0218] In the second type of electrical connection assembly, the electrical connection assembly includes a third connection portion 503, a fourth connection portion 504, a third extension portion 505, and a fourth extension portion 506.

[0219] Each first pin 501 is connected to the third extension 505, the third connection 503 is used to connect the heating layer and the third extension 505, and the third connection 503 is connected to the heating layer on one side of the linear extension direction of the imaging window.

[0220] Meanwhile, each second pin 502 is connected to the fourth extension 506, and the fourth connection 504 is used to connect the heating layer and the fourth extension 506, and the fourth connection 504 is connected to the heating layer on one side of the linear extension direction of the imaging window. It is worth noting that the third connection 503 and the fourth connection 504 are connected to the heating layer on the same side of the imaging window.

[0221] Furthermore, the third connecting portion 503 gradually increases in size in the direction close to the third extension portion 505, and the fourth connecting portion 504 gradually increases in size in the direction close to the fourth extension portion 506.

[0222] The third extension 505 and the fourth extension 506 are collinear in the extension direction. Specifically, the third connecting portion 503, the third extension 505, the fourth connecting portion 504, and the fourth extension 506 are symmetrical. Each first lead is perpendicular to the third extension 505 and extends outward from the carrier structure, and each second lead 502 is perpendicular to the fourth extension 506 and extends outward from the carrier structure, such that each first lead 501 and each second lead 502 are arranged side by side. In addition, the heating layer has an outwardly extending bent connecting portion 507 on the opposite side connecting the third connecting portion 503 and the fourth connecting portion 504.

[0223] In some examples, the electrical connection assembly also includes a support member 508, which connects the heating layers on both sides of the linear extension direction of the imaging window, thereby improving the overall structural strength of the electrical connection assembly. The support member 508 can be made of materials such as SiN, SiON, or amorphous silicon, and there is at least one support member 508. Specifically, the number of support members 508 is set to three.

[0224] Based on the above-described silicon-based network structure, the following are various embodiments of the silicon-based network structure fabrication method of this application.

[0225] The method for fabricating this silicon-based network structure can be applied to the aforementioned silicon-based network structure, and the method includes, but is not limited to, the following steps:

[0226] Step S1: Prepare the substrate;

[0227] Step S2: Clean the substrate;

[0228] Step S3: Grow and etch silicon oxide on the surface of the substrate;

[0229] Step S4: Deposit a support film on top of the substrate, and then photolithographically etch and etch the support film;

[0230] Step S5: Photolithography is performed on the support film, and a heating layer is deposited on the surface of the support film;

[0231] Step S6: Etch the substrate.

[0232] In the first embodiment, the substrate is substrate 104, the support film is support film 101, and the heating layer is heating layer 106; in the second embodiment, the substrate is substrate 204, the support film is support film 201, and the heating layer is heating layer 206; in the third embodiment, the substrate is substrate 304, the support film is support film 301, and the heating layer is heating layer 306.

[0233] In some examples, a substrate is first prepared and cleaned, where the substrate is made of an ultra-flat silicon wafer, which facilitates control over the flatness of the finished mesh structure. When an ultra-flat silicon wafer is used as the substrate to ensure the flatness of the mesh structure, the cryo-electron microscope only needs to focus once during data collection, thus saving microscope time.

[0234] Furthermore, during the use of cryo-electron microscopy, the presence of silicon oxide in the substrate structure can easily lead to electron beam tremor, which in turn degrades image quality. Therefore, the silicon oxide grown on the substrate surface is completely or nearly completely removed during the etching process, resulting in a finished substrate structure with almost no silicon oxide, thus avoiding the problem of electron beam tremor.

[0235] Meanwhile, a support film is deposited on top of the substrate, eliminating the need for manual application of the support film to the grid, thus improving processing efficiency and facilitating mass production of the grid structure. Understandably, the support film needs to be etched after deposition to form the observation window.

[0236] In the first embodiment, the observation window is observation window 103; in the second embodiment, it is observation window 203; and in the third embodiment, it is observation window 303.

[0237] In addition, a heating layer is formed on the surface of the support membrane by deposition. This heating layer can heat the sample, thereby keeping the sample in a liquid state and making it easier to reduce the thickness of the liquid sample layer, thus ensuring imaging quality.

[0238] Furthermore, after the support film and heating layer are prepared, the substrate needs to be etched to form the first hollow part, which facilitates the electron beam to pass through the carrier structure and complete the imaging process.

[0239] In the first embodiment, the first hollow part is the first hollow part 105; in the second embodiment, the first hollow part is the first hollow part 205; and in the third embodiment, the first hollow part is the first hollow part 305.

[0240] Additionally, step S2: cleaning the substrate may include, but is not limited to, the following steps:

[0241] Step S21: Clean the substrate using the RCA process.

[0242] In some examples, the RCA cleaning process is a classic wet chemical cleaning process used in semiconductor manufacturing and other fields to remove impurities and contaminants from the surface of silicon wafers. In the RCA cleaning process, the chemical properties of different reagents are used to target and remove different types of contaminants from the silicon wafer surface. Through chemical reactions, contaminants are transformed into substances soluble in the cleaning solution or easily removed, while avoiding excessive damage to the silicon wafer surface.

[0243] Furthermore, the RCA cleaning process includes steps such as SC-1 cleaning, DI water rinsing, HF cleaning, and SC-2 cleaning.

[0244] Additionally, step S3: growing and etching silicon oxide on the surface of the substrate includes:

[0245] Step S31: Etch silicon oxide with BOE for 60 to 100 seconds.

[0246] In some examples, BOE, or buffered oxide etchant, is used to etch silicon oxide. BOE is an etching solution widely used in semiconductor manufacturing and other fields, mainly for etching oxide films such as silicon oxide.

[0247] BOE (Bodied fluoride) is typically a buffer solution composed of hydrofluoric acid and ammonium fluoride in a specific ratio, such as 6:1 or 7:1. Hydrofluoric acid provides the fluoride ions required for etching, while ammonium fluoride acts as a buffer. Compared to pure hydrofluoric acid, BOE has buffering capacity, maintaining a relatively stable fluoride ion concentration in the solution. This results in a more uniform and controllable etching rate, reduces excessive erosion of other materials during the etching process, and improves etching selectivity.

[0248] Meanwhile, BOE's etching time is 60 to 100 seconds, which ensures sufficient etching of silicon oxide while avoiding damage to the substrate.

[0249] Additionally, step S5: photolithography of the support film and deposition of a heating layer on the surface of the support film, including:

[0250] Step S51: Deposit metal on the surface of the support film to form the heating layer.

[0251] In some examples, a heating layer is used to achieve the heating process of the sample. The heating layer can be a single-layer metal structure or a multi-layer metal structure. Tungsten and gold have good electrical conductivity, facilitating electrical connection with external circuits. When the heating layer is a two-layer metal structure, the two layers are made of tungsten and gold, respectively. Furthermore, in cryo-electron microscopy, the support structure is in a low-temperature environment, and the heating layer needs to withstand a large electrical heating power to achieve sample heating. Therefore, tungsten and gold, which can withstand high electrical power, are used for the heating layer.

[0252] Additionally, step S4: after depositing a support film on top of the substrate, further includes:

[0253] Step S41: Deposit a support layer at the bottom of the substrate.

[0254] In the first embodiment, the support layer is support layer 109; in the second embodiment, the support layer is support layer 209; and in the third embodiment, the support layer is support layer 309.

[0255] In some examples, a support layer is deposited at the bottom of the substrate. The support layer is used to improve the strength of the mesh structure and the flatness of the bottom of the mesh structure.

[0256] In addition, after step S5: photolithography of the support film and deposition of a heating layer on the surface of the support film, the method further includes:

[0257] Step S52: Photolithography and etching of the support layer.

[0258] In some examples, to ensure that the electron beam can pass through the carrier structure, the support layer is formed with second cutouts 110, 210, and 310 by photolithography.

[0259] In the first embodiment, the second hollow part is the second hollow part 110; in the second embodiment, the second hollow part is the second hollow part 210; and in the third embodiment, the second hollow part is the second hollow part 310.

[0260] After the electron beam passes through the support film, it passes through the substrate along the first cutout, then through the support layer along the second cutout, and finally reaches the device in the cryo-electron microscope used to receive the electron beam, thus completing the imaging process.

[0261] Additionally, step S52: the photolithography and etching of the support layer includes:

[0262] Step S521: The depth of etching the support layer is 250nm to 270nm.

[0263] In some examples, when etching the support layer, it is necessary to ensure that the etching depth is greater than the thickness of the support layer, thereby forming a second cutout that penetrates the support layer. It is understood that the etching depth of the support layer can be set according to the thickness of the support layer. Specifically, in this application, the etching depth of the support layer is 250 nm to 270 nm.

[0264] In addition, in the first and second embodiments, step S4: depositing a support film on top of the substrate, photolithographically etching the support film, includes:

[0265] Step S42: Deposit a first layer of silicon nitride on top of the substrate to initially form the support film;

[0266] Step S43: Deposit a second layer of silicon nitride on top of the substrate to form the support film;

[0267] Step S44: Photolithography and etching of the second layer of silicon nitride to form an observation window.

[0268] In some examples, silicon nitride is deposited on both sides of the top portion of the substrate to form a support film. The first silicon nitride deposition mainly forms the thicker portion around the observation window; this portion serves as the support and ensures the structural strength of the support film. Simultaneously, the second silicon nitride deposition mainly forms the portion of the support film used to house the observation window; this portion serves as the first carrier portion.

[0269] In the first embodiment, the first support part is the first support part 111, and in the second embodiment, the first support part is the first support part 211.

[0270] Furthermore, etching is performed on the first support portion to form an observation window for supporting the sample.

[0271] In addition, in the first and second embodiments, step S42: depositing a first layer of silicon nitride on top of the substrate includes:

[0272] Step S421: Deposit the first layer of silicon nitride using LPCVD, with a thickness of 195nm to 205nm.

[0273] In some examples, the first silicon nitride layer used to form the support has a large thickness to ensure structural strength. Specifically, the thickness of the deposited first silicon nitride layer is 195 nm to 205 nm.

[0274] In the first embodiment, the support part is support part 112, and in the second embodiment, the support part is support part 212.

[0275] Furthermore, LPCVD involves introducing a gaseous precursor into a reaction chamber under a pressure environment below atmospheric pressure. The precursor undergoes a chemical reaction under high temperature and low pressure conditions, and the resulting solid product is deposited on the surface of a substrate such as a silicon wafer, thereby forming a silicon nitride thin film.

[0276] In addition, in the first and second embodiments, step S43: the photolithography and etching of the second layer of silicon nitride includes:

[0277] Step S431: The depth of etching the second layer of silicon nitride is 42nm to 48nm.

[0278] In some examples, the second silicon nitride layer used to form the first support portion has a small thickness, which facilitates sample support. Since the observation window is located in the first support portion, the smaller thickness of the first support portion helps to reduce the thickness of the sample liquid layer, especially the thickness of the portion of the sample liquid layer in contact with the inner wall of the observation window, thus ensuring imaging accuracy.

[0279] Specifically, the thickness of the second silicon nitride layer is 42nm to 48nm, which is significantly less than the thickness of the first silicon nitride layer.

[0280] In addition, in the first and second embodiments, step S6: etching the substrate includes:

[0281] Step S61: Etch the substrate using KOH wet etching.

[0282] In some examples, after the support film and heating layer are fabricated, the substrate needs to be etched to form the final shape of the carrier network structure. In this case, the substrate of the carrier network structure is etched using the KOH wet etching method.

[0283] KOH wet etching is a process that uses potassium hydroxide solution as an etchant to selectively etch semiconductor materials.

[0284] In addition, in the first embodiment, after depositing a first layer of silicon nitride on top of the substrate 104 to initially form the support film 101, step S42 further includes:

[0285] Step S422: Photolithography and etching of the first layer of silicon nitride, the depth of which is 204nm to 216nm, to form imaging window 102.

[0286] In the first embodiment, after the first layer of silicon nitride is deposited, an area for setting the first support portion 111, i.e., the imaging window 102, needs to be etched in the middle of the first layer of silicon nitride so that the first support portion 111 can be formed when the second layer of silicon nitride is deposited.

[0287] The thickness of the first silicon nitride layer is 195nm to 205nm. The etching depth of 204nm to 216nm ensures that the etching area penetrates the first silicon nitride layer, avoiding the presence of residual first silicon nitride in the etching area. This is beneficial for controlling the thickness of the first support portion 111 when depositing the second silicon nitride layer.

[0288] In addition, such as Figure 13 , Figure 14 and Figure 15 As shown, in some examples, step S52: after the photolithography and etching of the support layer, includes:

[0289] Step 53: Coat the surface of the support film 101 with photoresist 114 and perform photolithography. The thickness of the photoresist 114 is greater than the thickness of the heating layer 106. The process of coating the photoresist 114 and performing photolithography avoids the imaging window 102.

[0290] Step 54: After photolithography is completed, a support beam is deposited on the surface of the photoresist 114 and at the imaging window 102;

[0291] Step 55: Use NMP to remove photoresist 114 and silicon nitride on the photoresist surface.

[0292] In this process, photoresist 114 is coated on the surface of the support film 101, excluding the imaging window 102. It is understood that, since the heating layer 106 protrudes from the surface of the support film 101, to ensure the flatness of the photoresist 114, the thickness of the photoresist 114 is greater than the thickness of the heating layer 106, so that the photoresist 114 completely encapsulates the heating layer 106. After the photoresist 114 is coated, etching is performed.

[0293] Furthermore, after photolithography, support beams are deposited on top of the photoresist 114 and at the imaging window 102. These support beams can be made of materials such as silicon nitride or amorphous silicon. Since no photoresist 114 is placed at the imaging window 102, the silicon nitride is directly deposited inside the imaging window 102. Specifically, the support beams are deposited using ICP-VD, and the thickness of the deposited support beams is between 150 nm and 500 nm.

[0294] Furthermore, after the support beam is deposited, the photoresist 114 needs to be removed by NMP. Since silicon nitride and other materials are deposited on the surface of the photoresist 114, the silicon nitride and other materials deposited on the surface of the photoresist 114 will also be removed during the removal process, while the support beam containing silicon nitride and other materials within the imaging window 102 is retained. After the photoresist 114 and the silicon nitride and other materials deposited on the surface of the photoresist 114 are removed, the heating layer 106 is exposed, facilitating subsequent heating operations on the heating layer 106.

[0295] This process method can retain a portion of the support beam formed by materials such as silicon nitride at the imaging window 102, thereby improving the strength of the carrier structure, making the thin film at the imaging window 102 less prone to breakage, and increasing the success rate of sample preparation.

[0296] In addition, in the second embodiment, after step S1: the preparation of substrate 204, the method further includes:

[0297] Step S11: Photolithography and etching of the substrate 204 to form silicon pillars, wherein the depth of etching of the substrate 204 is 490nm to 510nm.

[0298] In the second embodiment, after the substrate 204 is prepared, but before the first layer of silicon nitride is deposited, the substrate 204 needs to be etched, and a silicon pillar is formed in the middle of the substrate 204. The silicon pillar is beneficial for constructing the shape of the support film 201.

[0299] The etching depth is 490nm to 510nm, meaning the thickness of the silicon pillar is 490nm to 510nm.

[0300] In addition, in the second embodiment, after depositing a first layer of silicon nitride on top of the substrate 204 to initially form the support film 201, step S42 further includes:

[0301] Step S423: Grind the silicon pillar and the first layer of silicon nitride.

[0302] In the second embodiment, the first layer of silicon nitride at the top of the silicon pillar is first ground until no silicon nitride remains at the top of the silicon pillar. Then, the silicon pillar is ground until it is flush with the surrounding first layer of silicon nitride.

[0303] It is understood that during the deposition of the second silicon nitride layer, the second silicon nitride layer at the top of the silicon pillar forms the first support portion 211. Since the first silicon nitride layer is not present at the top of the silicon pillar during the deposition of the second silicon nitride layer, the thickness of the second silicon nitride layer is the thickness of the first support portion 211. This method is advantageous for controlling the thickness of the first support portion 211 in the second embodiment.

[0304] In addition, in the second embodiment, step S423: grinding the silicon pillar and the first layer of silicon nitride includes:

[0305] Step S4231: Grind the silicon pillar using CMP.

[0306] In the second embodiment, CMP, or chemical mechanical polishing, is a polishing method that combines chemical corrosion and mechanical polishing to achieve surface planarization of materials.

[0307] In this process, the chemical reagents in the polishing slurry react with the surface of the material being polished, forming a softer reaction layer that reduces the surface hardness and makes subsequent mechanical polishing easier. Simultaneously, the relative movement between the polishing pad and the material being polished utilizes the mechanical friction of the abrasive particles to remove the reaction layer and some of the material from the surface, thus achieving planarization.

[0308] Additionally, in the third embodiment, step S4: depositing a support film 301 on top of the substrate 304, and photolithographically etching the support film 301, includes:

[0309] Step S45: Deposit polysilicon 318 on top of the substrate 304;

[0310] Step S46: Boron ions are implanted into the polycrystalline silicon 318;

[0311] Step S47: Anneal the carrier network structure;

[0312] Step S48: Photolithography and etching of the polysilicon 318;

[0313] Step S49: Deposit the support film 301 on the surface of the polycrystalline silicon 318;

[0314] Step S50: Photolithography and etching of the support film 301 to form the observation window 303 and the ohmic contact area 319.

[0315] In the third embodiment, compared to metal heating, the sheet resistance of the ion-implanted polycrystalline silicon 318 is more uniform, and the temperature uniformity is also better. The third embodiment of this application uses boron ion implantation into the polycrystalline silicon 318 to form the ion-implanted layer 313.

[0316] In this process, polycrystalline silicon 318 is deposited on top of the substrate 304 before the support film 301 is deposited. Furthermore, after boron ions are implanted into the polycrystalline silicon 318, the carrier structure needs to be annealed. The annealing process can repair lattice damage, reduce impurity diffusion inhomogeneity, and reduce surface damage and stress.

[0317] Meanwhile, after the annealing process is completed, a support film 301 is deposited on the surface of the ion implantation layer 313, and an observation window 303 and an ohmic contact area 319 are etched to facilitate ohmic contact between the heating layer 306 and the ion implantation layer 313.

[0318] Additionally, in the third embodiment, step S45: depositing polysilicon 318 on top of the substrate 304 includes:

[0319] Step S451: Deposit the polysilicon 318 using LPCVD, with the thickness of the deposited polysilicon 318 being 195nm to 205nm.

[0320] Additionally, in the third embodiment, step S48: the photolithography and etching of the polysilicon 318 includes:

[0321] Step S481: The polysilicon 318 is etched to a depth of 200 nm to 210 nm.

[0322] In the third embodiment, the etched area of ​​polysilicon 318 is used to set the second carrier portion 316 of the support film 301. When polysilicon 318 is not present in the etched area, the thickness of silicon nitride deposited in the etched area is the thickness of the second carrier portion 316.

[0323] Therefore, in order to control the thickness of the second carrier portion 316, the thickness of the polysilicon 318 deposited is 195nm to 205nm, and the depth of the etched polysilicon 318 is 200nm to 210nm, that is, the etched area of ​​the polysilicon 318 penetrates the layered structure formed by the polysilicon 318.

[0324] Additionally, in the third embodiment, step S49: depositing the support film 301 on the surface of the polycrystalline silicon 318 includes:

[0325] Step S491: Deposit the support film 301 with a thickness of 34 nm to 46 nm using LPCVD.

[0326] Additionally, in the third embodiment, step S50: photolithography and etching of the support film 301 to form the observation window 303 and the ohmic contact area 319, includes:

[0327] Step S501: The depth of etching the support film 301 is 42nm to 48nm.

[0328] In the third embodiment, the depth of etching the support film 301 is greater than the thickness of depositing the support film 301, that is, the etched area of ​​the support film 301 penetrates the support film 301, thereby forming a hollow observation window 303.

[0329] Additionally, in the third embodiment, step S45, after depositing polysilicon 318 on top of the substrate 304, further includes:

[0330] Step S452: Silicon oxide is grown and photolithographically etched on top of the polysilicon 318.

[0331] In the third embodiment, after polysilicon 318 is deposited on top of substrate 304, silicon oxide needs to be grown on top of polysilicon 318 to form silicon oxide layer 317. This silicon oxide layer 317 can serve as a buffer layer to protect the wafer and subsequent processes.

[0332] PECVD utilizes plasma to enhance chemical reactions. Under low pressure, a high-frequency electromagnetic field ionizes the reactant gases to form plasma. The plasma contains a large number of high-energy electrons, ions, and active groups; these active particles lower the activation energy of the chemical reaction, allowing the reaction to proceed rapidly at lower temperatures. Under the influence of the plasma, the reactant gases decompose into active atoms or molecules, which react with each other and deposit on the surface of a 304 substrate to form a solid thin film.

[0333] Additionally, in the third embodiment, after annealing the carrier network structure, step S47 further includes:

[0334] Step S471: Remove silicon oxide using BOE.

[0335] In the third embodiment, BOE is used to precisely remove the silicon oxide grown in the previous stage, ensuring that the polysilicon 318 is in direct contact with the wafer.

[0336] Additionally, in the third embodiment, step S6: etching the substrate 304 includes:

[0337] Step S62: Etch the substrate 304 using a suspended film.

[0338] In the third embodiment, a suspended film etching substrate 304 is used to form the first hollow portion 305. Suspended film etching refers to removing a portion of a thin film of material through a specific process, leaving a portion of it suspended to form a suspended structure.

[0339] During the process, based on micro-nano fabrication technologies such as photolithography and etching, a thin film of the required material is first deposited on the substrate, then a pattern is defined using photoresist, and finally, the unwanted parts are removed through etching, leaving a suspended structure. Etching is divided into dry etching and wet etching. Dry etching commonly uses plasma etching, which has high precision and good anisotropy; wet etching uses chemical solutions to react with the material to achieve etching, which is low-cost and fast.

[0340] In the specific implementation of the preparation method, regarding the first embodiment:

[0341] like Figure 5 As shown, a 4, 6, or 8-inch ultra-flat silicon wafer is selected and first subjected to RCA cleaning. After the cleaning process, a silicon oxide film is grown on the surface of the ultra-flat silicon wafer. The grown silicon oxide film is etched using a BOE solution, with the etching time strictly controlled within the range of 60 to 100 seconds.

[0342] like Figure 6 As shown, a low-stress silicon nitride thin film with a thickness of is deposited on the surface of the processed wafer using the LPCVD process.

[0343] like Figure 7 As shown, the first layer of pattern photolithography is carried out, and after the photolithography operation is completed, the silicon nitride thin film is etched.

[0344] like Figure 8 As shown, the LPCVD process is used again to deposit a low-stress silicon nitride thin film on the wafer surface.

[0345] like Figure 9 As shown, a second-layer patterning photolithography process is performed, followed by etching of the silicon nitride thin film to form the observation window 103.

[0346] like Figure 10 As shown, a tungsten and gold heating layer 106 is deposited to form the heating layer 106.

[0347] like Figure 11 As shown, the fourth layer of patterning photolithography is carried out. After the photolithography is completed, the silicon nitride thin film is etched to form the support layer 109.

[0348] like Figure 12 As shown, the KOH wet etching process is used to complete the entire semiconductor manufacturing process.

[0349] Regarding the second embodiment:

[0350] Use 4, 6 or 8-inch ultraflat wafers as the initial material and perform the first layer of patterning photolithography.

[0351] like Figure 16As shown, substrate 204 is etched to form silicon pillars. After etching, the substrate is cleaned with RCA, followed by silicon oxide growth, and then BOE etching is used to etch the silicon oxide.

[0352] like Figure 17 As shown, low-stress silicon nitride is grown using the LPCVD process.

[0353] like Figure 18 As shown, silicon pillars and silicon nitride thin layers were polished using CMP.

[0354] like Figure 19 As shown, low-stress silicon nitride is grown again using the LPCVD process.

[0355] like Figure 20 As shown, a second layer of patterning photolithography is performed, followed by etching of silicon nitride to form the observation window 203.

[0356] like Figure 21 As shown, a third layer of patterning photolithography is performed to deposit tungsten and gold to form a heating layer 206.

[0357] like Figure 22 As shown, a fourth layer of patterning photolithography is performed to etch silicon nitride to form a support layer 209.

[0358] like Figure 23 As shown, the substrate 204 was etched using KOH wet etching to complete the entire process.

[0359] Regarding the third embodiment:

[0360] 4, 6, or 8-inch ultra-flat silicon wafers are selected as the wafer substrate. RCA cleaning technology is used to thoroughly remove particles, organic matter, and metallic contaminants from the wafer surface. A layer of silicon oxide is then grown on the wafer surface using a thermal oxidation process. BOE is used to precisely remove the previously grown silicon oxide, ensuring direct contact between the polysilicon 318 and the wafer.

[0361] like Figure 24 As shown, a low-stress polysilicon 318 layer is deposited on the cleaned wafer using the LPCVD process. This polysilicon 318 layer will serve as a key semiconductor active layer material.

[0362] like Figure 25 As shown, silicon oxide is grown on polysilicon layer 318 using PECVD process. This silicon oxide layer 317 is mainly used to reduce the damage of high-energy ions to polysilicon layer 318 during subsequent ion implantation, and can also be used as a mask layer for subsequent photolithography process.

[0363] like Figure 26As shown, photolithography is used to complete the first layer patterning, precisely transferring the designed circuit pattern onto the silicon oxide layer 317 on the wafer surface. Boron ions are implanted at a high concentration into the area defined by the photolithographic pattern to alter the electrical properties of the semiconductor. After implantation, a rapid annealing process is performed, using instantaneous high temperature to activate and uniformly diffuse the implanted boron ions. After annealing, BOE is used to remove the silicon oxide layer 317 generated during photolithography and implantation, preparing for subsequent processes.

[0364] like Figure 27 As shown, a second layer of patterning photolithography is performed to precisely transfer the circuit pattern onto the wafer surface again. After photolithography, polysilicon 318 etching is immediately performed to form the desired polysilicon 318 structure.

[0365] like Figure 28 As shown, a low-stress silicon nitride layer is grown on the wafer surface using the LPCVD process. Silicon nitride possesses good chemical stability and mechanical properties, and can be used as a protective and masking layer for subsequent processes.

[0366] like Figure 29 As shown, a third layer of patterning lithography is performed to transfer the pattern onto the silicon nitride layer. The silicon nitride is then etched to form the observation window 303 and the ohmic contact region 319. Further, a fourth layer of patterning lithography is performed to precisely define the area for metal deposition. Simultaneously, tungsten and gold are deposited to form the heating layer 306.

[0367] like Figure 30 As shown, a fifth layer of patterning photolithography is performed to further define the circuit pattern. After photolithography, silicon nitride is etched to expose the required underlying structure.

[0368] like Figure 31 As shown, the suspended film etching substrate 304 selectively etches specific areas of the wafer by precisely controlling the etching conditions, removing unwanted materials, forming a suspended thin film structure, and finally completing the entire semiconductor process to obtain a semiconductor device that meets the design requirements.

[0369] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application. Furthermore, unless otherwise specified, the embodiments and features described in the embodiments of this application can be combined with each other.

Claims

1. A silicon-based network structure, characterized in that, include: A support membrane is provided with an imaging window, the imaging window including a perforated observation window for holding a sample; A substrate for supporting the support film, the substrate having a first cutout portion, and the projection of the observation window onto the substrate being located within the range of the first cutout portion; A heating assembly, comprising a heating layer disposed on the side of the support film facing away from the substrate, the heating layer being used to heat the sample carried within the observation window; An ion implantation layer is located between the support film and the substrate, and the ion implantation layer is in ohmic contact with the heating layer. The support film covers the surface of the ion implantation layer, and the ion implantation layer has a third cutout portion. An observation window is disposed within the area of ​​the third cutout portion. The support film includes a lateral bonding portion, a longitudinal bonding portion, and a second carrier portion. The lateral bonding portion is bonded to the side of the ion implantation layer facing away from the substrate, the longitudinal bonding portion is bonded to the sidewall of the third cutout portion, and the second carrier portion is flush with the side of the ion implantation layer connected to the substrate. The observation window is disposed in the second carrier portion. The lateral bonding portion has an ohmic contact area, through which the heating layer passes and is in ohmic contact with the ion implantation layer.

2. The silicon-based carrier network structure according to claim 1, characterized in that, The imaging window includes a plurality of observation windows, which extend linearly and are arranged within the range of the imaging window.

3. The silicon-based carrier network structure according to claim 2, characterized in that, The imaging window has a length of 1.5-3 mm and the observation window has a width of 0.6-2.5 μm.

4. The silicon-based carrier network structure according to claim 2, characterized in that, A support beam is provided between adjacent observation windows, and the support beam is used to support the support membrane.

5. The silicon-based carrier network structure according to claim 1, characterized in that, The support film is made of silicon nitride.

6. The silicon-based carrier network structure according to claim 1, characterized in that, The substrate has a support layer on the side opposite to the support film, and the support layer has a second hollow portion, the projection of the first hollow portion on the support layer being within the range of the second hollow portion.

7. The silicon-based carrier network structure according to claim 1, characterized in that, The heating layer includes a first metal layer and a second metal layer stacked together, with the first metal layer located between the second metal layer and the support film.

8. The silicon-based carrier network structure according to claim 7, characterized in that, The first metal layer is made of tungsten and has a thickness of 70-120 nm.

9. The silicon-based carrier network structure according to claim 7, characterized in that, The second metal layer is made of gold and has a thickness of 10-60 nm.

10. The silicon-based carrier network structure according to claim 4, characterized in that, The support membrane includes a first support portion for carrying the sample and a support portion surrounding the first support portion. The observation window is disposed on the first support portion, and the thickness of the support portion is greater than the thickness of the first support portion.

11. The silicon-based carrier network structure according to claim 10, characterized in that, The support beam and the support membrane are integrally formed.

12. The silicon-based carrier network structure according to claim 10, characterized in that, The thickness of the first carrier portion is 34 nm to 46 nm.

13. The silicon-based carrier network structure according to claim 10, characterized in that, The thickness of the support portion is 195nm to 205nm.

14. The silicon-based carrier network structure according to claim 10, characterized in that, The first carrier portion is flush with the side of the support portion that connects to the substrate.

15. The silicon-based carrier network structure according to claim 10, characterized in that, The first bearing portion is flush with the side of the support portion that connects to the heating layer.

16. The silicon-based carrier network structure according to claim 1, characterized in that, The ion implantation layer is made by implanting boron ions into polycrystalline silicon.

17. The silicon-based carrier network structure according to claim 1, characterized in that, The thickness of the ion implantation layer is 195 nm to 205 nm.

18. The silicon-based carrier network structure according to claim 1, characterized in that, The thickness of the support film is 34 nm to 46 nm.

19. The silicon-based carrier network structure according to claim 1, characterized in that, The heating assembly further includes an electrical connection assembly connected to the heating layer. The electrical connection assembly includes a plurality of first pins and a plurality of second pins, each of the first pins and each of the second pins being used for electrical connection with an external circuit.

20. The silicon-based network structure according to claim 19, characterized in that, The electrical connection assembly further includes a first connection portion, a second connection portion, a first extension portion, and a second extension portion. The first connection portion and the second connection portion are respectively connected to the heating layers on opposite sides of the linear extension direction of the imaging window. The first connection portion is connected to each of the first pins through the first extension portion, and the second connection portion is connected to each of the second pins through the second extension portion.

21. The silicon-based carrier network structure according to claim 20, characterized in that, The first extension and the second extension are parallel, each first pin is perpendicular to the first extension, each second pin is perpendicular to the second extension, and each first pin and each second pin are arranged side by side.

22. The silicon-based carrier network structure according to claim 20, characterized in that, The electrical connection assembly further includes a third connection portion, a fourth connection portion, a third extension portion, and a fourth extension portion. The third connection portion and the fourth connection portion are connected to the heating layer on the same side of the linear extension direction of the imaging window. The third connection portion is connected to each of the first pins through the third extension portion, and the fourth connection portion is connected to each of the second pins through the fourth extension portion.

23. The silicon-based network structure according to claim 22, characterized in that, The third connecting portion gradually increases in size in the direction close to the third extension portion, and the fourth connecting portion gradually increases in size in the direction close to the fourth extension portion.

24. The silicon-based carrier network structure according to claim 22, characterized in that, The third extension and the fourth extension are collinear, each first pin is perpendicular to the third extension, each second pin is perpendicular to the second extension, and each first pin and each second pin are arranged side by side.

25. The silicon-based carrier network structure according to claim 22, characterized in that, The heating layer has an outwardly extending bent connection on the opposite side of the connection between the third connection and the fourth connection.

26. A method for fabricating a silicon-based network structure, used to fabricate the silicon-based network structure as described in any one of claims 1-25, characterized in that, include: Substrate preparation; Clean the substrate; Silicon oxide is grown and etched on the surface of the substrate; A support film is deposited on top of the substrate, and the support film is photolithographically etched and etched. Polycrystalline silicon is deposited on top of the substrate; The polysilicon is implanted with boron ions; the carrier structure is annealed; the polysilicon is photolithographically etched and etched; the support film is deposited on the surface of the polysilicon; the support film is photolithographically etched and etched to form an observation window and an ohmic contact area. The support film is photolithographically etched, and a heating layer is deposited on the surface of the support film; The substrate is etched.

27. The method for preparing a silicon-based network structure according to claim 26, characterized in that, Cleaning the substrate includes: The substrate was cleaned using the RCA process.

28. The method for preparing a silicon-based network structure according to claim 26, characterized in that, Growing and etching silicon oxide on the surface of the substrate includes: The silicon oxide was etched using BOE for 60 to 100 seconds.

29. The method for preparing a silicon-based network structure according to claim 26, characterized in that, Photolithography of the support film and deposition of a heating layer on the surface of the support film include: Metal is deposited on the surface of the support film to form the heating layer.

30. The method for preparing a silicon-based network structure according to claim 26, characterized in that, After depositing a support film on top of the substrate, the method further includes: A support layer is deposited at the bottom of the substrate.

31. The method for preparing a silicon-based network structure according to claim 30, characterized in that, After photolithography of the support film and deposition of a heating layer on the surface of the support film, the process further includes: The support layer is photolithographically etched and etched.

32. The method for preparing a silicon-based network structure according to claim 31, characterized in that, The photolithography and etching of the support layer includes: The depth of etching the support layer is 250 nm to 270 nm.

33. The method for preparing a silicon-based network structure according to claim 31, characterized in that, Depositing a support film on top of the substrate, photolithographically lithographically etching the support film, includes: A first layer of silicon nitride is deposited on top of the substrate to initially form the support film; A second layer of silicon nitride is deposited on top of the substrate to form the support film; A second layer of silicon nitride is photolithographically etched to form an observation window.

34. The method for preparing a silicon-based network structure according to claim 33, characterized in that, A first layer of silicon nitride is deposited on top of the substrate, comprising: The first layer of silicon nitride was deposited using LPCVD, with a thickness of 195 nm to 205 nm.

35. The method for preparing a silicon-based network structure according to claim 33, characterized in that, A second layer of silicon nitride is deposited on top of the substrate, comprising: A second silicon nitride layer was deposited using LPCVD, with a thickness of 34 nm to 46 nm.

36. The method for preparing a silicon-based network structure according to claim 33, characterized in that, The photolithography and etching of the second layer of silicon nitride includes: The depth of the second silicon nitride layer is 42nm to 48nm.

37. The method for preparing a silicon-based network structure according to claim 33, characterized in that, Etching the substrate includes: The substrate was etched using a KOH wet etching process.

38. The method for preparing a silicon-based network structure according to claim 33, characterized in that, After depositing a first layer of silicon nitride on top of the substrate to initially form the support film, the method further includes: The first layer of silicon nitride is photolithographically etched and etched to a depth of 204 nm to 216 nm to form an imaging window.

39. The method for preparing a silicon-based network structure according to claim 38, characterized in that, After photolithography and etching of the support layer, the method further includes: Photoresist is coated onto the surface of the support film and photolithography is performed. The thickness of the photoresist is greater than the thickness of the heating layer. The process of coating the photoresist and photolithography avoids the imaging window. After photolithography is completed, support beams are deposited on the surface of the photoresist and at the imaging window; NMP was used to remove the photoresist and the silicon nitride on the photoresist surface.

40. The method for preparing a silicon-based network structure according to claim 33, characterized in that, After the substrate is prepared, the process further includes: The substrate is photolithographically etched and etched to form silicon pillars, with the etching depth of the substrate ranging from 490 nm to 510 nm.

41. The method for preparing a silicon-based network structure according to claim 40, characterized in that, After depositing a first layer of silicon nitride on top of the substrate to initially form the support film, the method further includes: The silicon pillar and the first layer of silicon nitride are ground.

42. The method for preparing a silicon-based network structure according to claim 41, characterized in that, Grinding the silicon pillar and the first layer of silicon nitride includes: The silicon pillars were polished using CMP.

43. The method for preparing a silicon-based network structure according to claim 26, characterized in that, Depositing polycrystalline silicon on top of the substrate includes: The polycrystalline silicon was deposited using LPCVD, and the thickness of the deposited polycrystalline silicon was 195 nm to 205 nm.

44. The method for preparing a silicon-based network structure according to claim 26, characterized in that, The photolithography and etching of the polysilicon includes: The depth of etching the polysilicon is 200 nm to 210 nm.

45. The method for preparing a silicon-based network structure according to claim 26, characterized in that, Depositing the support film on the surface of the polycrystalline silicon includes: The thickness of the support film is 34 nm to 46 nm, deposited by LPCVD.

46. ​​The method for preparing a silicon-based network structure according to claim 26, characterized in that, The photolithography and etching of the support film to form the observation window and ohmic contact area includes: The depth of etching the support film is 42 nm to 48 nm.

47. The method for preparing a silicon-based network structure according to claim 26, characterized in that, After depositing polycrystalline silicon on top of the substrate, the process further includes: Silicon oxide is grown and photolithographically etched on top of the polycrystalline silicon.

48. The method for preparing a silicon-based network structure according to claim 47, characterized in that, Growing and photolithographically etching silicon oxide on top of the polycrystalline silicon includes: Silica was grown using PECVD.

49. The method for preparing a silicon-based network structure according to claim 47, characterized in that, After annealing the carrier network structure, the process also includes: BOE was used to remove silica.

50. The method for preparing a silicon-based network structure according to claim 26, characterized in that, Etching the substrate includes: The substrate was etched using a suspended film method.

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