Miniature electrochemical three-electrode test chip and preparation method thereof
By integrating the working electrode, reference electrode, and counter electrode into a micro electrochemical three-electrode test chip, the problem of high internal resistance caused by the large size difference between the working electrode and the traditional reference electrode is solved, realizing efficient parallel electrochemical testing and accurate experimental results.
Patent Information
- Application Number
- CN202411140783.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2026-03-03
AI Technical Summary
In existing microelectrode array devices, the size difference between the working electrode and the traditional reference electrode is too large, which leads to increased internal resistance and affects the test sensitivity and the accuracy of experimental results.
The working electrode, reference electrode, and counter electrode are integrated into the site region of the micro electrochemical three-electrode test chip. Through ingenious electrode layout design, each site region becomes a complete electrochemical three-electrode system. The working electrode and the reference electrode are adjacent, and the area of the counter electrode is at least ten times that of the working electrode.
This approach enables efficient parallel electrochemical testing of each site region, improving test sensitivity and the accuracy of experimental results while avoiding the influence of electrode reactions on the measurement signal.
Smart Images
Figure CN121595671A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of test chips, and particularly relates to a micro electrochemical three-electrode test chip and its preparation method. Background Technology
[0002] The electrochemical three-electrode system is the most common setup in various electrochemical detection environments. It typically includes a working electrode (WE), a reference electrode (RE), and a counter electrode (CE), along with a sensing element (S) connected to the working electrode for signal collection. Under operating conditions (current flowing through the working and counter electrodes), although the potential difference between the working and counter electrodes cannot be directly measured, the potential difference between the working electrode and the adjacent reference electrode can be controlled and measured through the element S because the working electrode is connected to and always grounded (potential stable). This three-electrode configuration can be used to study various phenomena occurring at the electrochemical interface when the potential of the working electrode changes relative to the reference electrode (e.g., redox reactions, reaction reversibility, resistance changes, etc.). Therefore, this technology is widely used in various scenarios requiring precise electrochemical detection of the working electrode (e.g., materials testing, non-destructive testing, and bioelectronics).
[0003] In the field of bioelectronics, microelectrode arrays (MEAs) are a commonly used detection tool. Their core component utilizes micro- and nanofabrication techniques to create a large number of conductive micro- and nanoelectrodes arranged according to specific rules within an extremely small area on a chip. These are used for various electrochemical applications, such as in vitro cell monitoring (capable of simultaneously recording and stimulating multiple sites) and electrochemical DNA synthesis (characterized by high-throughput and parallel synthesis). With the development of microelectromechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) fabrication technologies, detection devices are becoming increasingly miniaturized and integrated, making the miniaturization of electrochemical testing systems an inevitable trend. However, currently common microelectrode array devices often only miniaturize the working electrode using micro- and nanofabrication techniques, while the counter electrode, especially the reference electrode, is not integrated into the microelectrode array. In electrochemical experiments, a traditional reference electrode (e.g., Ag / AgCl, Hg / HgO, and Ag / AgNO3) with three parts—a metal electrode (platinum, gold, mercury, silver, etc.), an internal electrolyte solution, and a liquid junction (ceramic, ion-permeable porous glass, etc.)—is still required, along with a relatively large counter electrode (platinum, graphite). Due to the significant size difference between the working electrode and the traditional reference electrode on the microelectrode array, the distance between them is large, resulting in increased internal resistance. This leads to decreased test sensitivity and negatively impacts the accuracy of experimental results. Summary of the Invention
[0004] This invention provides a micro electrochemical three-electrode test chip and its fabrication method, wherein the working electrode, reference electrode and counter electrode are fabricated at the site, and each site region can be used for independent and parallel chemical testing.
[0005] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.
[0006] To achieve one, some, or all of the above objectives or other objectives, the present invention provides a method for fabricating a micro electrochemical three-electrode test chip, comprising the following steps: Step 1: Substrate preparation, depositing a first insulating layer on the substrate surface, sputtering a metal lead layer on the first insulating layer, and performing photolithography and etching on the metal lead layer to form a metal lead layer pattern; Step 2: Depositing a second insulating layer on the metal lead layer, and performing aperture treatment on the second insulating layer; depositing a first metal electrode layer communicating with the working electrode metal lead layer and a second metal electrode layer communicating with the counter electrode metal lead layer on the second insulating layer. Second metal electrode layer; Step 3: Pattern the second metal electrode layer to expose the reference electrode metal lead layer; Deposit a third insulating layer on the first and second metal electrode layers, and after opening holes in the third metal insulating layer, deposit a third metal electrode layer communicating with the reference electrode metal lead layer on the third insulating layer; Step 4: Pattern the third metal electrode layer to form circular sites; Deposit a fourth insulating layer on the third metal electrode layer, and open through holes in the fourth insulating layer to expose the conductive surfaces of the first, second, and third metal electrode layers. The beneficial effect of this technical solution is that, through the ingenious design of the electrode layout, the working electrode, reference electrode, and counter electrode are integrated into the circular sites, making each site a complete electrochemical three-electrode system.
[0007] The substrate is a single-crystal silicon, glass, a flexible polymer substrate, or a CMOS chip that has undergone front-end processing.
[0008] The first insulating layer, the second insulating layer, and the third insulating layer are silicon oxide layers, and the fourth insulating layer is any one of a silicon oxide layer, a silicon nitride layer, or a polyimide layer.
[0009] The working electrode metal lead layer, reference electrode metal lead layer, and counter electrode metal lead layer formed in step one are array electrodes; the central region of the array electrode is the working electrode metal lead layer, which includes a square array of multiple metal dots; the reference electrode metal lead layer and the counter electrode metal lead layer are square metal dot arrays formed outside the working electrode metal lead layer.
[0010] In step one, the patterning of the metal lead layer also includes forming metal interconnects connecting the working electrode metal lead layer, the reference electrode metal lead layer, and the counter electrode metal lead layer to the chip pads.
[0011] The circular sites expose the first and second metal electrode layers, and the circular sites are arranged in an array; the fourth insulating layer has through holes at the sites to expose the conductive surfaces of the first, second, and third metal electrode layers.
[0012] Another embodiment of the present invention provides a micro electrochemical three-electrode test chip, comprising a substrate and a first insulating layer formed on the substrate. The first insulating layer has a working electrode metal lead layer, a reference electrode metal lead layer, a counter electrode metal lead layer, and metal connecting wires. It also includes a first metal electrode layer connected to the working electrode metal lead layer and a second metal electrode layer connected to the counter electrode metal lead layer. The working electrode metal lead layer and the counter electrode metal lead layer are separated from the first metal electrode layer and the second metal electrode layer by a second insulating layer. A third metal electrode layer is connected to the reference electrode metal lead layer. The reference electrode metal lead layer and the third metal electrode layer are separated by a third insulating layer. A fourth insulating layer is also disposed on the third metal electrode layer.
[0013] The second and third insulating layers are provided with through holes for connection; the fourth insulating layer is provided with through holes for forming electrodes.
[0014] The third metal electrode layer has a plurality of sites, which form a square array and expose the first metal electrode layer and the second metal electrode layer.
[0015] The fourth insulating layer covers the site. After the fourth insulating layer is opened, a working electrode and a counter electrode are formed at the site, and a reference electrode is formed adjacent to the site.
[0016] The working electrode metal lead layer, the reference electrode metal lead layer, and the counter electrode metal lead layer are arrayed electrodes; the central region of the arrayed electrode is the working electrode metal lead layer, which includes a square array of multiple metal dots; the reference electrode metal lead layer and the counter electrode metal lead layer are square metal dot arrays formed outside the working electrode metal lead layer.
[0017] The working electrode metal lead layer, the reference electrode metal lead layer, and the counter electrode metal lead layer are connected to the chip pads via metal interconnects.
[0018] The working electrode is adjacent to the reference electrode, and the area of the counter electrode is at least ten times the area of the working electrode.
[0019] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. By cleverly designing the electrode layout, the working electrode, reference electrode and counter electrode are integrated into the circular site region, so that each site region is a complete electrochemical three-electrode system. The center of the site is arranged in an array according to a certain spacing rule, and electrochemical tests can be performed in parallel.
[0020] 2. At each site region, the working electrode is adjacent to the reference electrode, and the area of the counter electrode is at least ten times that of the working electrode to ensure that the counter electrode reaction rate is higher than that of the working electrode, thus avoiding the influence of the counter electrode reaction on the measurement signal.
[0021] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the cross-section of the chip site in the micro electrochemical three-electrode testing system of the present invention.
[0024] Figure 2 This is a detailed process flow diagram of the micro electrochemical three-electrode testing system chip in Example 1.
[0025] In the figure: 1. Substrate; 2. First insulating layer; 3. Reference electrode metal lead layer; 4. Second insulating layer; 5. Working electrode metal lead layer; 6. First metal electrode layer; 7. Second metal electrode layer; 8. Counter electrode metal lead layer; 9. Metal connecting wire; 10. Reference electrode; 11. Working electrode; 12. Counter electrode; 13. Third insulating layer; 14. Third metal electrode layer; 15. Fourth insulating layer. Detailed Implementation
[0026] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.
[0027] Example 1
[0028] Example 1 provides a method for fabricating a micro electrochemical three-electrode test chip. For the specific fabrication process, please refer to [link to details]. Figure 2 Specifically, it includes the following steps:
[0029] Step 1: Select substrate 1. Substrate 1 can be made of single-crystal silicon, glass, polymer, or other flexible substrates, or a CMOS chip that has completed the front-end processing. Here, "front-end processing" refers to all processes before metal thin film deposition. Processes following metal thin film deposition refer to back-end processes. A first insulating layer 2 is deposited on substrate 1 using thermal oxidation deposition or plasma-enhanced chemical vapor deposition (PECVD). After depositing the first insulating layer 2, a metal lead layer of a certain thickness is deposited on its surface. The metal lead layer can be made of any one of gold, platinum, aluminum, copper, doped silicon, titanium, or titanium nitride. After depositing the metal lead layer on the surface of the first insulating layer 2, the metal lead layer is patterned. Specifically, photoresist is spin-coated onto the metal lead layer, followed by photolithography and development, and then dry etching to create the pattern. The patterned metal lead layer after etching is shown below. Figure 2 As shown in Figure a, the structure includes a working electrode metal lead layer 5 in the central region, and a reference electrode metal lead layer 3 and a counter electrode metal lead layer 8 located outside the working electrode metal lead layer 5. The working electrode metal lead layer 5 in the central region is composed of multiple metal dots with circular cross-sections. The reference electrode metal lead layer 3 and the counter electrode metal lead layer 8 outside the central region are also metal dots, which together form a square array. Figure 2 The metal dots of the reference electrode metal lead layer 3 and the counter electrode metal lead layer 8 in layer a are symmetrically arranged along the diagonal of the central region. In the actual fabrication process, there are no restrictions on the position of the reference electrode metal lead layer 3 and the counter electrode metal lead layer 8, as long as they are outside the central region and form a square array. The spacing between the metal dots (distance between their centers) must be at least greater than the diameter of a single metal dot, meaning that the metal dots cannot overlap each other.
[0030] Meanwhile, the metal lead layer patterning in step one also includes etching metal interconnect lines 9, which connect the working electrode metal lead layer 5, the reference electrode metal lead layer 3, and the counter electrode metal lead layer 8 to the chip's pads.
[0031] In Example 1, the working electrode metal lead layer is a microelectrode array, specifically a 2×2 array. In actual manufacturing, there is no limitation on the size of the microelectrode array; it can be set as needed. The larger the array size, the greater the chip throughput.
[0032] Step 2: Deposit a second insulating layer 4 on the patterned metal lead layer. Perform photolithography and etching on the second insulating layer 4 to expose the working electrode metal lead layer 5 and the counter electrode metal lead layer 8. For details, see [link to details]. Figure 2 b, for ease of representation Figure 2In diagram b, the second insulating layer 4 is made transparent (i.e., it is not shown in the figure), but the positions of the openings are indicated by a grid pattern (that is, the positions of the working electrode metal lead layer 5 and the counter electrode metal lead layer 8 at the center). The first metal electrode layer 6 and the second metal electrode layer 7 are deposited using sputtering. The first metal electrode layer 6 is connected to the working electrode metal lead layer 5, and the second metal electrode layer 7 is connected to the counter electrode metal lead layer 8.
[0033] Step 3: After depositing the first metal electrode layer 6 and the second metal electrode layer 7, the second metal electrode layer 7 is patterned to expose the position of the reference electrode metal lead layer 3, while ensuring that the first metal electrode layer 6 and the second metal electrode layer 7 are separated from each other (this separation can also be controlled during the deposition of the first metal electrode layer 6 and the second metal electrode layer 7). The thickness of the first metal electrode layer 6 and the second metal electrode layer 7 is the same as the thickness of the second insulating layer 4. See the process for Step 3. Figure 2 c.
[0034] A third insulating layer 13 is deposited on the first metal electrode layer 6 and the second metal electrode layer 7 using PECVD technology. The third insulating layer is then photolithographically and etched to create openings to expose the reference electrode positions. Afterwards, a third metal electrode layer 14 is deposited on the third insulating layer using sputtering. For details, see [link to detailed process]. Figure 2 d and Figure 2 e. Figure 2 The third insulating layer deposited in d is shown in blank form for simplicity in the figure, but the location of the opening is indicated by a gray grid. The location of the opening is the location of the reference electrode metal lead layer 3. At the same time, the third insulating layer 13 also serves to separate the first metal electrode layer 6 and the second metal electrode layer 7.
[0035] Step 4: Perform patterning on the formed third metal electrode layer 14, see [link to relevant documentation]. Figure 2 e, forming four arrayed sites, each site being linearly circular. Each site is formed by etching to expose the first metal electrode layer 6 and the second electrode layer 7. Simultaneously, each circular site has a notch that is not etched; this notch is used for... Figure 2 The fourth insulating layer is etched in f to expose the location of the third metal electrode layer 14. This notch location is etched through... Figure 2 The process of f is used to form the reference electrode 10.
[0036] A fourth insulating layer 15 is deposited on the third metal electrode layer 14, and the fourth insulating layer 15 is patterned. Specifically, the fourth insulating layer 15 is perforated to expose the conductive surfaces of the first metal electrode layer 6, the second metal electrode layer 7, and the third metal electrode layer 14. These exposed conductive surfaces are the working electrode 11, the counter electrode 12, and the reference electrode 10, respectively. See [link to specific structure] for details. Figure 2 f, Figure 2 The fourth insulating layer 15 in f is not shown in the figure; the opening location is indicated by a gray patterned illustration. In actual manufactured chips, because the fourth insulating layer is relatively thin, the site area can still be seen through the fourth insulating layer.
[0037] The first insulating layer 2, the second insulating layer 4, and the third insulating layer 13 are silicon oxide layers, and the fourth insulating layer 15 is any one of a silicon oxide layer, a silicon nitride layer, or a polyimide layer. The first, second, and third insulating layers are silicon oxide insulating layers to prevent short circuits. The fourth insulating layer can be silicon oxide, but in certain applications (such as fluorescent staining of the electrode), silicon oxide may have its own background fluorescence, which may hinder the observation of the fluorescence of the electrode portion. Using titanium nitride or polyimide may avoid this. Therefore, the last insulating layer can be selected according to the application.
[0038] The thickness of the insulating layer is selected based on the actual application, ensuring adequate insulation without creating excessively deep wells in the electrodes that would hinder liquid wetting. The micro-electrochemical three-electrode test chip prepared by the method in Example 1 is shown in the schematic diagram of the cross-sectional test of the chip's sites. Figure 1 As shown.
[0039] Example 2
[0040] Example 2 provides a micro electrochemical three-electrode test chip, which is prepared using the method of Example 1.
[0041] Miniature electrochemical three-electrode test chip, see Figure 1 as well as Figure 2The system includes a substrate 1 and a first insulating layer 2 formed on the substrate 1. A working electrode metal lead layer 5, a reference electrode metal lead layer 3, a counter electrode metal lead layer 8, and metal interconnects 9 are deposited on the first insulating layer 2. The metal interconnects 9 connect the working electrode metal lead layer 5, the reference electrode metal lead layer 3, and the counter electrode metal lead layer 8 to chip pads. The working electrode metal lead layer 5 is connected to a first metal electrode layer 6, and the counter electrode metal lead layer 8 is connected to a second metal electrode layer 7. The first metal electrode layer 6 and the second metal electrode layer 7 are separated from each other during deposition. The working electrode metal lead layer 5 is separated from the first metal electrode layer 6, and the counter electrode metal lead layer 8 is separated from the second metal electrode layer 7 by a second insulating layer 4.
[0042] A third metal electrode layer 14, which is connected to the reference electrode metal lead layer 3, is also provided on the first metal electrode layer 6 and the second metal electrode layer 7. The reference electrode metal lead layer 3 and the third metal electrode layer 14 are separated by a third insulating layer 13. The third insulating layer 13 is also used to separate the first metal electrode layer 6 and the second metal electrode layer 7.
[0043] A fourth insulating layer 15 is also disposed on the third metal electrode layer 14. The second, third, and fourth insulating layers are all patterned to form through holes for connection. For specific steps, please refer to Embodiment 1 and... Figure 2 a.
[0044] The working electrode metal lead layer 5, the reference electrode metal lead layer 3, and the counter electrode metal lead layer 8 are arrayed electrodes; the working electrode metal lead layer 5 is located in the central region of the arrayed electrodes, and the working electrode metal lead layer 5 is formed by a square array of multiple metal dots; the reference electrode metal lead layer 3 and the counter electrode metal lead layer 8 are square metal dot arrays formed outside the working electrode metal lead layer 5.
[0045] The third metal electrode layer 14 has several sites. Each site is formed into a circular groove (or through hole) by etching, and the circular site has a missing corner. The several sites form a square array, and the several sites expose the first metal electrode layer 6 and the second metal electrode layer 7. At the same time, when the first metal electrode layer 6 and the second metal electrode layer 7 are exposed, the third insulating layer 13 between the first metal electrode layer 6 and the second metal electrode layer 7 will not be damaged.
[0046] A fourth insulating layer 15 covers the site and forms a working electrode 11, a reference electrode 10, and a counter electrode 12 through openings. The working electrode 11 is adjacent to the reference electrode 10, and the area of the counter electrode 12 is at least ten times that of the working electrode 11, ensuring that the counter electrode reaction rate is higher than that of the working electrode and avoiding the influence of the counter electrode reaction on the measurement signal.
[0047] By designing the electrode layout as described above, the working electrode, reference electrode, and counter electrode are integrated into the circular site region, making each site region a complete electrochemical three-electrode system. The center of the sites is arranged in an array at a certain interval, allowing for parallel electrochemical testing.
[0048] The present invention provides a detailed description of a miniature electrochemical three-electrode test chip and its fabrication method. Specific examples have been used to illustrate the structure and working principle of the invention. The descriptions of the embodiments are merely for the purpose of helping to understand the method and core ideas of the invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.
Claims
1. A method for fabricating a micro electrochemical three-electrode test chip, characterized in that, Includes the following steps: Step 1: Substrate preparation. A first insulating layer is deposited on the substrate surface, and a metal lead layer is sputtered on the first insulating layer. The metal lead layer is then photolithographically and etched to form a metal lead layer pattern. Step 2: Deposit a second insulating layer on top of the metal lead layer, and perform aperture treatment on the second insulating layer; A first metal electrode layer communicating with the working electrode metal lead layer and a second metal electrode layer communicating with the counter electrode metal lead layer are respectively deposited on the second insulating layer. Step 3: Pattern the second metal electrode layer to expose the reference electrode metal lead layer; A third insulating layer is deposited on the first metal electrode layer and the second metal electrode layer, and after the third metal insulating layer is made into an opening, a third metal electrode layer communicating with the reference electrode metal lead layer is deposited on the third insulating layer. Step 4: Pattern the third metal electrode layer to form circular sites; deposit a fourth insulating layer on the third metal electrode layer, and open through holes in the fourth insulating layer to expose the conductive surfaces of the first, second, and third metal electrode layers.
2. The method for fabricating a micro electrochemical three-electrode test chip according to claim 1, characterized in that, The substrate is a single-crystal silicon, glass, a flexible polymer substrate, or a CMOS chip that has undergone front-end processing.
3. The method for fabricating a micro electrochemical three-electrode test chip according to claim 1, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are silicon oxide layers, and the fourth insulating layer is any one of a silicon oxide layer, a silicon nitride layer, or a polyimide layer.
4. The method for fabricating a micro electrochemical three-electrode test chip according to claim 1, characterized in that, The working electrode metal lead layer, reference electrode metal lead layer, and counter electrode metal lead layer formed in step one are array electrodes; The central region of the array electrode is a working electrode metal lead layer, which comprises a square array of multiple metal dots. The reference electrode metal lead layer and the counter electrode metal lead layer are square metal dot arrays formed outside the working electrode metal lead layer.
5. The method for fabricating a micro electrochemical three-electrode test chip according to claim 3, characterized in that, In step one, the patterning of the metal lead layer also includes forming metal interconnects connecting the working electrode metal lead layer, the reference electrode metal lead layer, and the counter electrode metal lead layer to the chip pads.
6. The method for fabricating a micro electrochemical three-electrode test chip according to claim 1, characterized in that, The circular sites expose the first and second metal electrode layers, and the circular sites are arranged in an array. The fourth insulating layer has through holes at the sites to expose the conductive surfaces of the first, second, and third metal electrode layers.
7. A miniature electrochemical three-electrode test chip, comprising a substrate and a first insulating layer formed on the substrate, characterized in that, The first insulating layer has a working electrode metal lead layer, a reference electrode metal lead layer, a counter electrode metal lead layer, and metal connecting wires, respectively. It also includes a first metal electrode layer connected to the working electrode metal lead layer, and a second metal electrode layer connected to the counter electrode metal lead layer, wherein the working electrode metal lead layer, the counter electrode metal lead layer, the first metal electrode layer, and the second metal electrode layer are separated by a second insulating layer; A third metal electrode layer is connected to the reference electrode metal lead layer, and the reference electrode metal lead layer and the third metal electrode layer are separated by a third insulating layer; A fourth insulating layer is also provided on the third metal electrode layer.
8. A miniature electrochemical three-electrode test chip according to claim 7, characterized in that, The second and third insulating layers are provided with through holes for connection; the fourth insulating layer is provided with through holes for forming electrodes.
9. A miniature electrochemical three-electrode test chip according to claim 8, characterized in that, The third metal electrode layer has a plurality of sites, which form a square array and expose the first metal electrode layer and the second metal electrode layer.
10. A miniature electrochemical three-electrode test chip according to claim 9, characterized in that, The fourth insulating layer covers the site. After the fourth insulating layer is opened, a working electrode and a counter electrode are formed at the site, and a reference electrode is formed adjacent to the site.
11. A miniature electrochemical three-electrode test chip according to claim 7, characterized in that, The working electrode metal lead layer, the reference electrode metal lead layer, and the counter electrode metal lead layer are arrayed electrodes; The central region of the array electrode is a working electrode metal lead layer, which comprises a square array of multiple metal dots. The reference electrode metal lead layer and the counter electrode metal lead layer are square metal dot arrays formed outside the working electrode metal lead layer.
12. A miniature electrochemical three-electrode test chip according to claim 11, characterized in that, The working electrode metal lead layer, the reference electrode metal lead layer, and the counter electrode metal lead layer are connected to the chip pads via metal interconnects.
13. A miniature electrochemical three-electrode test chip according to claim 7, characterized in that, The working electrode is adjacent to the reference electrode, and the area of the counter electrode is at least ten times the area of the working electrode.