Fault detection circuit, circuit fault detection method and fault detection system

Abstract

The embodiment of the invention discloses a fault detection circuit, a circuit fault detection method and a fault detection system, and the circuit comprises a test data generation unit which is used for generating test data; the data distribution unit is used for sending test data to at least one first target tested unit in the tested circuit; each first target tested unit is used for processing the test data and obtaining output data; the operation summarization unit is used for receiving the output data of each first target tested unit and processing the output data of each first target tested unit based on preset operation to obtain target output data; each first target tested unit is determined after dividing at least one tested unit based on a preset grouping mode, and the preset grouping mode is determined based on the type of the tested circuit; and the verification unit is used for determining a fault detection result based on the standard output data and the target output data corresponding to the test data. According to the invention, the fault detection efficiency of the circuit can be improved while the hardware design complexity is reduced.

Description

Technical Field

[0001] This application relates to circuit testing technology, and more particularly to a fault detection circuit, a circuit fault detection method, and a fault detection system. Background Technology

[0002] In fields such as automotive electronics, industrial control, the Internet of Things (IoT), and high-performance computing, functional safety (FuSa) has become a core consideration in chip design and system integration due to increasing system complexity and increasingly stringent safety requirements. For example, the automotive electronics functional safety standard ISO 26262 requires that electronic systems related to functional safety must have the ability to detect internal circuit faults to prevent system failures from causing hazards. Furthermore, for security chips involved in data encryption and authentication (such as smart cards and in-vehicle communication modules), the reliability of their core cryptographic algorithm circuits is particularly important. To ensure that cryptographic algorithm circuits do not malfunction due to transistor aging, single-event upsets, manufacturing defects, or other reasons during operation, effective fault detection is necessary.

[0003] Typically, the Known Answer Test (KAT) method can be used to detect faults in the circuit under test (such as a cryptographic algorithm circuit). The principle is to input a set of pre-determined test vectors into the circuit under test and compare the output of the circuit under test with the pre-determined correct result; if they do not match, it indicates a fault in the circuit under test. However, traditional hardware KAT implementations often suffer from high hardware complexity and low detection efficiency. Summary of the Invention

[0004] This application provides a fault detection circuit, a circuit fault detection method, and a fault detection system, which can reduce the hardware complexity of circuit fault detection and improve fault detection efficiency.

[0005] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a fault detection circuit for detecting faults in a circuit under test. The fault detection circuit includes: a test data generation unit for generating test data, wherein the test data is determined based on a preset seed value stored in the fault detection circuit; a data distribution unit for sending the test data to at least one first target unit under test in the circuit under test, wherein each first target unit under test processes the test data and obtains output data; a calculation and summarization unit for receiving the output data of each first target unit under test and processing the output data of each first target unit under test based on a preset calculation to obtain target output data corresponding to at least one first target unit under test; wherein each first target unit under test is determined after dividing at least one unit under test in the circuit under test based on a preset grouping method, the preset grouping method being determined based on the type of the circuit under test; and a verification unit for determining the fault detection result corresponding to at least one first target unit under test based on the standard output data and target output data corresponding to the test data.

[0006] In this embodiment, at least one unit under test in the circuit under test can be grouped and tested based on a cryptographic protocol. At least one first target unit under test in the same test combination can be tested in parallel using the same test data. The output data of at least one first target unit under test is processed by a unified calculation and summary unit and a verification unit. Therefore, it is not necessary to send test data to each first target unit under test one by one and compare the output data one by one. That is, no serial processing is required, thus improving the efficiency of fault detection. Moreover, it is not necessary to configure an independent verification unit for each unit under test, thus reducing power consumption and circuit design complexity.

[0007] In some implementations, the fault detection circuit further includes: a seed storage unit for storing a preset seed value; a test data generation unit for: obtaining the preset seed value from the seed storage unit; and generating test data based on the preset seed value; wherein the test data is a pseudo-random sequence; and a data distribution unit for: broadcasting the test data to each first target unit under test.

[0008] In this embodiment, by storing a preset seed value in the fault detection circuit and generating test data based on the preset seed value, the storage requirement for test data can be reduced from KB or MB to byte level, thereby reducing hardware storage overhead. Furthermore, generating pseudo-random test data ensures the determinism and repeatability of fault testing.

[0009] In some implementations, the test data generation unit is used to: increment a first counter value according to a preset step to obtain a second counter value corresponding to the current clock cycle; wherein the first counter value is an initial counter value or a counter value corresponding to the previous clock cycle of the current clock cycle; perform a first preset processing on a preset seed value, a first key, and the second counter value corresponding to the current clock cycle to obtain a second key corresponding to the current clock cycle; wherein the first key is an initial key or a key corresponding to the previous clock cycle of the current clock cycle; the first preset processing includes XOR operation and / or shift operation; and perform an operation on the second key corresponding to the current clock cycle based on a preset cryptographic algorithm to generate test data corresponding to the current clock cycle.

[0010] In this embodiment, since the preset seed value of the external input is fixed, the test data generated by the test data generation unit is the same each time. Furthermore, even if the counter value changes by only 1 bit, the test data generated after processing by the preset cryptographic algorithm will undergo drastic changes, thus generating an unpredictable pseudo-random bit stream in each clock cycle.

[0011] In some implementations, the calculation and summarization unit is used to: perform XOR or XNOR operations on the output data of each first target tested unit to obtain target output data; wherein, the preset operation includes XOR or XNOR operation.

[0012] In this embodiment, the XOR and NAND operations do not mask the output errors of the unit under test, nor do they cause result overflow or bit width expansion, thus ensuring the accuracy of the fault test results.

[0013] In some implementations, the verification unit is used to: convert target output data into first mapping data based on a preset mapping rule; wherein the mapping data obtained by converting the same data based on the preset mapping rule are the same, and the mapping data obtained by converting multiple data with at least one different bit based on the preset mapping rule are different; acquire second mapping data stored in the fault detection circuit; wherein the second mapping data is obtained by converting the standard output data corresponding to the test data based on the preset mapping rule; and compare the second mapping data and the first mapping data to determine the fault detection result corresponding to at least one first target unit under test.

[0014] In this embodiment, when the data is the same, the mapping data obtained based on the preset mapping rule is the same, while when the data is different (even if there is only a 1-bit difference), the mapping data obtained based on the preset mapping rule will be different, thereby ensuring high coverage and reliability of fault detection.

[0015] In some embodiments, the circuit under test further includes a data processing unit; wherein the data distribution unit is configured to: send test data to the data processing unit; wherein the data processing unit is configured to perform a second preset processing on the test data to obtain target test data, and send the target test data to each first target unit under test; each first target unit under test is configured to perform calculations on the target test data to obtain first output data; the second preset processing includes data format conversion and / or data concatenation processing; the calculation and summarization unit is configured to: receive the first output data of each first target unit under test, and process the first output data of each first target unit under test based on preset calculations to obtain second output data corresponding to at least one first target unit under test; and send the second output data to the data processing unit; wherein the data processing unit is configured to perform a second preset processing on the second output data to obtain target output data, and send the target output data to the verification unit.

[0016] In this embodiment of the application, the circuit under test may further include a data processing unit that performs conventional data processing. Thus, if the data processing unit makes an error in processing the test data or output data, it can also determine that the circuit under test has failed based on the target output data, so that fault detection can cover the entire data path from test data generation to result output.

[0017] In some implementations, the test data generation unit is used to: generate test data corresponding to each clock cycle; the calculation and summarization unit is used to: receive output data from the second target test unit corresponding to each clock cycle for the test data corresponding to each clock cycle; wherein, the second target test unit corresponding to each clock cycle is a first target test unit capable of processing the test data of the corresponding clock cycle; perform data summarization processing on each bit of the output data corresponding to each clock cycle to obtain the summarization data corresponding to each clock cycle; perform data summarization processing on each bit of the summarization data corresponding to multiple clock cycles to obtain target output data corresponding to at least one second target test unit; wherein, the standard output data is determined based on the output data generated by the fault-free second target test unit corresponding to each clock cycle.

[0018] In this embodiment, output data is generated by simulating the test unit without reverse voltage in each clock cycle and determining the standard output data, so that fault detection of the test circuit can still be achieved even when the test unit has reverse voltage.

[0019] In some embodiments, the fault detection circuit further includes a selector; the selector is used to: in response to a first signal, open a path between the fault detection circuit and the circuit under test; or, in response to a second signal, close the path between the fault detection circuit and the circuit under test, and open a path between a preset memory and the circuit under test; wherein the circuit under test is used to write or read data to the preset memory.

[0020] In this embodiment, the selector enables switching between fault detection mode and normal operation mode (i.e., non-fault detection mode), thereby improving the usability of the fault detection circuit and ensuring that it does not affect the normal operation mode of the circuit.

[0021] On the other hand, embodiments of this application provide a circuit fault detection method applied to a fault detection circuit. The fault detection circuit is used to detect faults in a circuit under test. The method includes: a test data generation unit generating test data; wherein the test data is determined based on a preset seed value stored in the fault detection circuit; a data distribution unit sending the test data to at least one first target unit under test in the circuit under test; wherein each first target unit under test processes the test data and obtains output data; a calculation and summarization unit receiving the output data of each first target unit under test and processing the output data of each first target unit under test based on a preset calculation to obtain target output data corresponding to at least one first target unit under test; wherein each first target unit under test is determined after dividing at least one unit under test in the circuit under test based on a preset grouping method, the preset grouping method being determined based on the type of the circuit under test; and a verification unit determining the fault detection result corresponding to at least one first target unit under test based on the standard output data and target output data corresponding to the test data.

[0022] In this embodiment, at least one unit under test in the circuit under test can be grouped and tested based on a cryptographic protocol. At least one first target unit under test in the same test combination can be tested in parallel using the same test data. The output data of at least one first target unit under test is processed by a unified calculation and summary unit and a verification unit. Therefore, it is not necessary to send test data to each first target unit under test one by one and compare the output data one by one. That is, no serial processing is required, thus improving the efficiency of fault detection. Moreover, it is not necessary to configure an independent verification unit for each unit under test, thus reducing power consumption and circuit design complexity.

[0023] On the other hand, embodiments of this application provide a fault detection system, which includes a fault detection circuit and a circuit under test; wherein, the fault detection circuit is used to perform fault detection on the circuit under test to obtain a fault detection result.

[0024] On the other hand, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a fault detection circuit, implements some or all of the steps in the above-described circuit fault detection method.

[0025] On the other hand, embodiments of this application provide a program product, which includes a computer program or instructions. When the computer program or instructions are executed by a fault detection circuit, they implement some or all of the steps in the above-described circuit fault detection method.

[0026] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0027] Figure 1 A schematic diagram of a circuit fault detection method provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating a fault detection circuit sending test data to the unit under test, as provided in an embodiment of this application. Figure 3 This is a schematic diagram of a fault detection circuit receiving output data from a unit under test, provided in an embodiment of this application. Figure 4 A schematic diagram illustrating another circuit fault detection method provided in an embodiment of this application; Figure 5 A schematic diagram illustrating another circuit fault detection method provided in an embodiment of this application; Figure 6 This is a schematic diagram illustrating the implementation process of a circuit fault detection method provided in an embodiment of this application.

[0028] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0032] In related technologies, traditional hardware KAT implementations typically embed a large amount of complete test data (i.e., test vectors) and their corresponding standard output data into the chip's read-only memory (ROM) or flash memory during the chip design phase. However, with the increasing complexity of cryptographic algorithms (such as post-quantum cryptography (PQC), which has many computational units and long data paths), and the surge in the number of transistors brought about by the evolution of chip manufacturing processes, traditional KAT implementations suffer from the following problems: (1) Large storage resource consumption: It is necessary to store a large amount of complete test data, especially for complex algorithm circuits. The amount of test data surges, requiring a large amount of silicon wafer area for storage (usually reaching KB or even MB level), which significantly increases the manufacturing cost and power consumption of the chip, resulting in high hardware storage cost and large area. (2) High hardware complexity: Each circuit under test needs to be configured with an independent verification circuit, which will double the size of the verification circuit in the case of multiple circuits under test, thus increasing power consumption and design difficulty; (3) Low verification efficiency: It can only perform serial testing on each circuit under test, resulting in a long self-test time.

[0033] Based on the above-mentioned technical problems, this application provides a fault detection circuit, a circuit fault detection method, and a fault detection system to reduce hardware storage resources, lower hardware design complexity, and improve circuit fault detection efficiency.

[0034] Figure 1 This is a schematic diagram of a circuit fault detection method provided in an embodiment of this application, such as... Figure 1 As shown, the fault detection circuit 100 is used to perform fault detection on the circuit under test 110. The fault detection circuit 100 includes a test data generation unit 10, a data distribution unit 11, a calculation and summarization unit 12, and a verification unit 13. The fault detection circuit 100 can be a KAT module. The circuit under test 110 includes at least one test unit 14, and each test unit 14 can be a transistor. Exemplarily, the fault detection circuit 100 can perform fault detection on the circuit under test 110 during initialization, or it can perform fault detection during normal operation of the circuit under test 110. That is, the fault detection circuit 100 can perform fault detection at any time after the circuit under test 110 is started. In this embodiment, the timing of fault detection by the fault detection circuit 100 is not limited.

[0035] In some examples, at least one tested unit 14 in the circuit under test 110 can be a cryptographic operation circuit, an artificial intelligence (AI) operation circuit, a general signal processing circuit, a graphics processing circuit, etc. The specific type of the circuit under test 110 is not limited in this embodiment; any digital logic circuit with a deterministic input-output mapping relationship can be used as the circuit under test 110. For example, at least one tested unit 14 can be an operator module in an arithmetic and Logic Unit (ALU). Specifically, at least one tested unit 14 can be a cryptographic operator module in the arithmetic logic unit (e.g., a pqc_alu module) of a cryptographic module (e.g., a post-quantum cryptography algorithm pqc module) to perform encryption and decryption operations on the test data; or, at least one tested unit 14 can also be a cryptographic operator module in the arithmetic logic unit of an AI module to perform AI operations on the test data. The fault detection circuit 100 (which may be referred to as pqc_alu_kat) can perform fault detection on at least one of the tested units 14 in the arithmetic logic unit (such as the pqc_alu module).

[0036] In some implementations, based on the requirements of the Functional Safety Standard (FuSa), since it is usually only necessary to detect whether a fault has occurred and trigger a safety mechanism to enter a safe state, without needing to accurately locate the specific fault source at the first moment, fault detection can be performed on all the units 14 under test in the circuit under test 110 as a whole to determine whether the circuit under test 110 as a whole has failed.

[0037] For example, at least one unit under test 14 can be divided into at least one different test combination according to different business needs, and fault tests can be performed on at least one unit under test 14 in each test combination to determine whether each test combination has failed. In some examples, a preset grouping method can be determined based on the type of the circuit under test 110, and at least one unit under test 14 in the circuit under test 110 can be divided based on the preset grouping method to obtain at least one test combination, each test combination including at least one unit under test 14 (hereinafter referred to as the first target unit under test 14). The preset grouping method may include grouping methods such as the test units having the same cryptographic protocol, the test units implementing the same function, or the test units having a higher usage frequency than a preset frequency, etc., which are not limited in this embodiment.

[0038] For example, when the circuit under test 110 is a cryptographic operation circuit, in practical applications, computing devices (such as mobile phones, computers, vehicle terminals, etc.) that deploy the circuit under test 110 can call the corresponding combination of test units (i.e., cryptographic operator modules) 14 to perform cryptographic operations on input data (such as user data) based on different cryptographic protocols at corresponding cryptographic security levels. Therefore, according to the test units 14 required by the cryptographic protocols corresponding to different cryptographic security levels, at least one first target test unit 14 corresponding to at least one cryptographic protocol can be divided into the same test combination. Each first target test unit 14 can correspond to one or more cryptographic protocols, and the cryptographic protocol is related to the cryptographic security level. For example, in the post-quantum cryptography algorithm pqc module, at least one test unit 14 can include a key generation unit (pqc_gen_unit), a key decapsulation unit (pqc_kd_unit), a sampling unit (pqc_smp_unit), a modular arithmetic unit (pqc_mcal_unit), a hash function unit (pqc_hash_unit), etc. Specifically, the key generation unit, key decapsulation unit, and modular arithmetic unit called by the 203 protocol in the post-quantum cryptography algorithm PQC can be grouped into the same test combination; similarly, the key generation unit, key decapsulation unit, modular arithmetic unit, and sampling unit called by the 204 protocol (which has a higher security level than the 203 protocol) in the post-quantum cryptography algorithm PQC can be grouped into the same test combination, and so on. It is understood that the above method of dividing test combinations is merely an example, and this application does not limit the scope of the embodiments.

[0039] For example, when the type of the circuit under test 110 is an AI operation circuit, at least one target test unit 14 that performs the same function can be divided into the same test group based on the function implemented by the test unit. For example, the first target test unit 14 used to implement multiply-add operation (such as a multiply-adder) 14 can be divided into the same test group, and the first target test unit 14 used to implement nonlinear transformation (such as an activation function unit) 14 can be divided into the same test group.

[0040] For example, the number of first target test units 14 in each test combination can be one or more. When there is only one first target test unit 14, it is possible to detect whether the first target test unit 14 has failed, that is, the faulty circuit can be accurately located; when there are multiple first target test units 14 in the test combination, it is possible to detect whether there is a faulty circuit in the test combination.

[0041] In some embodiments, the test data generation unit 10 generates test data based on a preset seed value stored in the fault detection circuit 100, i.e., the preset seed value is fixed in the fault detection circuit 100, and sends the test data to the data distribution unit 11. The test data can be a pseudo-random sequence, i.e., the test data is deterministic and reproducible. The test data generation unit 10 can be a hardware module such as a pseudo-random number generator (PRNG) or a linear feedback shift register (LFSR), etc., and this embodiment is not limited to this.

[0042] For example, a pseudo-random number generator (PRNG) can employ a preset cryptographic algorithm and a counter (CTR) mode, using the input preset seed value as the key to encrypt continuously increasing counter values ​​(such as 0, 1, 2, 3...). The preset cryptographic algorithm can be a lightweight block cipher algorithm (such as the PRESENT algorithm).

[0043] A pseudo-random number generator can generate pseudo-random sequences (i.e., test data) for multiple clock cycles. In circuit implementation, for each clock cycle, an iterative architecture can be used to generate the pseudo-random sequence. For example, the counter value corresponding to the previous clock cycle (i.e., the first counter value) can be incremented by a preset step (e.g., by 1) to obtain the counter value for the current clock cycle (i.e., the second counter value). A first preset processing is then performed on a preset seed value, the key from the previous clock cycle (i.e., the first key), and the second counter value for the current clock cycle to obtain the key for the current clock cycle (i.e., the second key); where the first preset processing may include XOR and / or shift operations. Then, based on a preset cryptographic algorithm and the second key for the current clock cycle, calculations are performed to generate the pseudo-random sequence for the current clock cycle. The above process is repeated for each clock cycle (similar to a linear feedback shift register), thus generating different pseudo-random sequences for each clock cycle.

[0044] In some examples, an initial key and initial vector (or initial counter value 1) can be internally stored in the pseudo-random number generator; where initial counter value 1 is the initial counter value. During the first clock cycle (i.e., the first clock cycle), the pseudo-random number generator obtains a preset seed value and performs an XOR and shift operation on this preset seed value with the initial key and initial vector to generate a new key (hereinafter referred to as key 1); then, it operates on key 1 based on the PRESENT algorithm to generate the pseudo-random sequence for the first clock cycle. In the second clock cycle, the pseudo-random number generator increments the initial counter value 1 by a preset step to obtain counter value 2, and performs an XOR and shift operation on the preset seed value, key 1 from the first clock cycle, and counter value 2 to generate a new key (hereinafter referred to as key 2); then, it operates on key 2 based on the PRESENT algorithm to generate the pseudo-random sequence for the second clock cycle. In the third clock cycle, the pseudo-random number generator increments the counter value 2 by a preset step to obtain the counter value 3. It then performs an XOR operation and shift operation on the preset seed value, the key 2 from the second clock cycle, and the counter value 3 to generate a new key (hereinafter referred to as key 3). Next, it operates on key 3 based on the PRESENT algorithm to generate the pseudo-random sequence for the third clock cycle. This process continues until a preset number of pseudo-random sequences are generated.

[0045] Since the preset seed value of the external input is fixed, the pseudo-random sequence generated by the pseudo-random number generator is the same every time it restarts. Furthermore, due to the strong avalanche effect of the PRESENT algorithm, even a 1-bit change in the counter value will cause a drastic jump in the pseudo-random sequence generated after PRESENT processing, thus producing an unpredictable pseudo-random bit stream in each clock cycle.

[0046] The data distribution unit 11 receives test data sent by the test data generation unit 10 and simultaneously broadcasts the test data to each of the first target test units 14 in the target combination to be tested, so that the test data received by each first target test unit 14 is the same. After receiving the test data, each first target test unit 14 processes the test data and obtains output data; and sends the output data to the calculation and summarization unit 12. The at least one test combination mentioned above includes a target combination.

[0047] refer to Figure 2 The diagram shown illustrates a fault detection circuit sending test data to the unit under test. Figure 2As shown, the data distribution unit 11 in the fault detection circuit 100 (pqc_alu_kat) can simultaneously broadcast test data to each first target unit under test 14 (pqc_*_unit). Each first target unit under test 14 may further include one or more functional subunits 15, such as a key decapsulation unit (pqc_kd_unit) which may include a compression function (pqc_kyber_compress); and a key generation unit (pqc_gen_unit) which may include direct memory access (gen_dma). Therefore, the data distribution unit 11 can simultaneously broadcast test data to each functional subunit 15 in each unit under test 14, allowing each functional subunit 15 to process the test data and obtain corresponding output data.

[0048] refer to Figure 3 The diagram shown illustrates a fault detection circuit receiving output data from a first target unit under test. Figure 3 As shown, the calculation and summarization unit 12 is used to receive the output data of each functional subunit 15 in each first target tested unit 14, and perform data summarization processing on each bit of the output data of each functional subunit 15 to obtain the summarized output data (hereinafter referred to as target output data) corresponding to at least one first target tested unit 14; and send the target output data to the verification unit 13. The data summarization processing can be performed on the corresponding bits of each output data based on a preset operation; the preset operation is a logical operation that will not mask the output errors of each first target tested unit 14 (or each functional subunit 15); for example, if an AND operation is used, then if the output data of one first target tested unit 14 is 0 in a certain bit, then regardless of whether other first target tested units 14 are correct in that bit, that bit in the summarization result will be fixed as 0, which will cause the fault of that first target tested unit 14 to be masked, and thus cause a significant decrease in the detection accuracy. For example, the preset operation can be an XOR operation (i.e., performing an XOR operation on the corresponding bits of each output data), or it can be an NNXOR operation (i.e., performing an NNXOR operation on the corresponding bits of each output data). Neither the XOR nor the NNXOR operation will mask output errors of the first target test unit 14, nor will it cause result overflow or bit width expansion. In some examples, if there is only one first target test unit 14 in the target combination, then there is no need to process the output data of the first target test unit 14 based on the preset operation; that is, the output data of the first target test unit 14 is the target output data.

[0049] The verification unit 13 is used to determine the fault detection result of the target combination in the circuit under test 110 based on the target output data and the standard output data (golden value) corresponding to the test data of the target combination, thereby completing the fault detection of the target combination in the circuit under test 110. For example, if the target output data of the target combination is inconsistent with the standard output data of the target combination, the fault detection result of the target combination is output as "0", "fail", etc., to indicate that the target combination has failed; if the target output data of the target combination is consistent with the standard output data, the fault detection result of the circuit under test 110 is output as "1", "pass", etc., to indicate that the target combination has not failed. The standard output data of the target combination can be the summarized data obtained in advance in the simulation environment by processing the test data of each fault-free first target unit under test in the target combination, and processing the output data of each first target unit under test based on preset calculations; the standard output data of the target combination can be stored in advance in the memory of the fault detection circuit 100. It is understood that the test data input during fault testing is the same as the test data input during simulation.

[0050] In this embodiment, at least one unit under test (DUT) in the circuit under test can be grouped and tested based on a cryptographic protocol. At least one first target DUT in the same test combination can be tested in parallel using the same test data. The output data of at least one first target DUT is processed by a unified computation and verification unit. This eliminates the need to send test data to each first target DUT individually and compare the output data one by one, i.e., no serial processing is required, thus improving fault detection efficiency. Furthermore, it eliminates the need to configure an independent verification unit for each first target DUT, thereby reducing power consumption and circuit design complexity. In addition, generating pseudo-random test data ensures the determinism and repeatability of fault testing.

[0051] In some implementations, reference Figure 4 Another schematic diagram of circuit fault detection is shown, such as Figure 4 As shown, the fault detection circuit 100 also includes a seed storage unit 16, which stores the aforementioned preset seed value. At the start of the test, the test data generation unit 10 can retrieve the preset seed value from the seed storage unit 16 and generate pseudo-random test data based on the preset seed value. The seed storage unit 16 may have a read / write protection mechanism, such as being a one-time programmable (OTP) memory, to prevent the preset seed value from being tampered with or reverse-engineered.

[0052] In this embodiment, by storing a preset seed value in the fault detection circuit and generating test data based on the preset seed value, the storage requirement for test data can be reduced from KB or MB to byte level, thereby reducing hardware storage overhead. Furthermore, the storage area of ​​the fault detection circuit (i.e., the seed storage unit) has a read / write protection mechanism, allowing only internal reading and no external access interface, thus preventing the preset seed value from being tampered with or reverse-derived, meeting the functional safety requirements for test data integrity.

[0053] In some implementations, reference continues. Figure 4 The fault detection result (e.g., CRC status) of the circuit under test 110 is determined based on the standard output data and target output data corresponding to the test data. This can include mapping data (hereinafter referred to as first mapping data) corresponding to the target output data of each test combination and mapping data (hereinafter referred to as second mapping data) corresponding to the standard output data of each test combination, thereby determining the fault detection result of the circuit under test 110. The mapping data can be generated based on preset mapping rules, which can be cyclic redundancy check (CRC), hash algorithm, parity check algorithm, etc. This application does not limit the specific type of preset mapping rules.

[0054] For example, after pre-determining the standard output data for each test combination, second mapping data corresponding to the standard output data of each test combination can be determined based on a preset mapping rule, and the second mapping data corresponding to each test combination can be stored in the memory 16 (such as a read-only memory) of the fault detection circuit 100. During the fault detection process, after receiving the target output data of the target combination, the verification unit 13 in the fault detection circuit 100 can generate first mapping data corresponding to the target output data of the target combination based on the preset mapping rule, and obtain the second mapping data corresponding to the target combination from the second mapping data corresponding to at least one test combination stored in the memory 16. The preset mapping rule used to generate the second mapping data is the same as the preset mapping rule used to generate the first mapping data; the first mapping data and the second mapping data can be CRC checksums, hash checksums, etc.; the data lengths of the first mapping data and the second mapping data generated based on the preset mapping rule can be less than the lengths of the target output data and the standard output data, respectively.

[0055] Next, the verification unit 13 can compare the second mapping data and the first mapping data to determine the fault detection result corresponding to at least one first target unit under test 14 of the target combination. For example, if the first mapping data is inconsistent with the second mapping data, the fault detection result of the target combination in the circuit under test 110 is output as "0", "fail", etc., to indicate that the target combination has a fault, that is, there is a faulty unit under test in the target combination; if the first mapping data is consistent with the second mapping data, the fault detection result of the target combination in the circuit under test 110 is output as "1", "pass", etc., to indicate that the target combination has not a fault, that is, there is no faulty unit under test in the target combination.

[0056] In this embodiment, when the data is the same, the mapped data obtained based on the preset mapping rule is the same; when the data is different (even if there is only a 1-bit difference), the mapped data obtained based on the preset mapping rule will be different, thereby ensuring high coverage and reliability of fault detection. Furthermore, the preset mapping rule can transform complex output data comparisons into comparisons between mapped data with shorter data lengths, thus greatly simplifying the comparison logic; and by storing the mapped data corresponding to the standard output data instead of the standard output data itself, hardware storage overhead can be further reduced.

[0057] In some implementations, reference continues. Figure 4 After obtaining the fault detection result, the verification unit 13 can send the fault detection result to the processor 120. The fault detection circuit 100, the circuit under test 110 and the processor 120 can be configured in a computing device (such as a mobile phone, computer, vehicle terminal, etc.).

[0058] For example, a functional safety management module (CMP) may be deployed in the processor 120. The processor 120 can process fault detection results through the CMP, and when the fault detection results indicate that the circuit under test 110 has a fault, it can generate corresponding control instructions (such as a module reset instruction) and perform safety responses such as safety alarm reporting. The processor 120 can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field-programmable gate array (FPGA), etc., and is not limited in this embodiment. The architecture adopted by the processor 120 can be a fifth-generation reduced instruction set computer (RISC-V) architecture.

[0059] Optionally, the second mapping data can also be stored in the processor 120. After generating the first mapping data based on the target output data, the verification unit 13 can directly send the first mapping data to the processor 120 so that the processor 120 can compare the first mapping data and the second mapping data and obtain the fault detection result.

[0060] In this embodiment, the fault detection result is reported to the processor so that the functional safety management module in the processor can trigger subsequent safety response events, thereby meeting the full-process requirements of functional safety standards (such as ISO 26262) for fault detection and handling.

[0061] In some embodiments, when performing fault detection on the circuit under test 110, fault detection can be performed on the circuit under test 110 based on the output data corresponding to at least one first target unit under test 14 in a preset number of clock cycles (hereinafter referred to as the preset number of clock cycles). For example, the test data generation unit 10 can generate corresponding test data based on a preset seed value in each clock cycle, and broadcast the test data corresponding to each clock cycle to each first target unit under test 14 via the data distribution unit 11. The test data corresponding to each clock cycle can be the same or different. Each first target unit under test 14 processes the corresponding test data in each clock cycle to obtain the output data of each first target unit under test 14 in each clock cycle, and sends the output data corresponding to each first target unit under test 14 to the calculation and summarization unit 12 in each clock cycle. Then, the calculation and summarization unit 12 performs data summarization processing on each bit of the output data corresponding to each first target tested unit 14 based on preset calculations in each clock cycle to obtain the summary data corresponding to each clock cycle. Then, based on preset calculations, the summary data corresponding to each clock cycle is further summarized. After the number of clock cycles elapsed during the test reaches a preset number of clock cycles, the output data of the summarized multiple clock cycles is determined as the target output data corresponding to at least one first target tested unit 14. Thus, the verification unit 13 determines the fault detection result based on the target output data and standard output data of at least one first target tested unit 14 in multiple clock cycles. For example, it can be set that when the number of elapsed clock cycles reaches a preset number of clock cycles, the first target tested unit 14 with the longest calculation time (i.e., the first target tested unit 14 that generates the last output data) generates a flag bit at the same time as generating the output data to indicate that the clock cycle has reached the preset number of clock cycles, that is, the calculation of the test data for all clock cycles has been completed. Thus, the fault detection circuit 100 can respond to the flag bit and stop sending test data to the tested circuit 110.

[0062] For example, since the first target unit under test 14 may experience back pressure, meaning that after receiving the test data corresponding to the current clock cycle, the first target unit under test 14 cannot complete the processing of the test data in the current clock cycle, but needs to wait for several clock cycles before obtaining the output data, the first target unit under test 14 cannot generate output data in the current clock cycle. Therefore, the standard output data can be determined in a simulation environment by simulating a fault-free first target unit under test (hereinafter referred to as the second target unit under test) 14 that can process the test data in each clock cycle, and based on the output data generated by the second target unit under test in each clock cycle. Therefore, after each unit under test 14 receives the corresponding test data in each clock cycle, the second target unit under test 14, which does not have back pressure in each clock cycle, processes the test data and obtains the output data of the second target unit under test 14 in each clock cycle, and sends the output data to the calculation and summarization unit 12 in each clock cycle. The calculation and summarization unit 12 receives the output data of the second target test unit 14 corresponding to each clock cycle, and performs data summarization processing on each bit of the output data of the second target test unit 14 in each clock cycle based on preset calculations to obtain the summarization data corresponding to each clock cycle; and performs data summarization processing on each bit of the summarization data corresponding to multiple clock cycles based on preset calculations to finally obtain at least one target output data corresponding to the second target test unit 14.

[0063] Taking a preset multiple clock cycles as an example of two clock cycles. In the first clock cycle, if the output data of the second target tested unit A is 0x12345678, the output data of the second target tested unit B is 0x9ABCDEF0, and the second target tested unit C has reverse voltage and no output, then the target second tested units corresponding to the first clock cycle are the second target tested unit A and the second target tested unit B. The calculation and summarization unit 12 calculates the summarization data corresponding to the first clock cycle based on a preset operation (such as XOR operation): 0x12345678 XOR 0x9ABCDEF0 = 0x88888888.

[0064] In the second clock cycle, if the output data of the second target test unit A is 0x2468ACE0, the output data of the second target test unit B is 0x13579BDF, and the output data of the second target test unit C is 0xFEDCBA98, then the target second test units corresponding to the second clock cycle are second target test unit A, second target test unit B, and second target test unit C. The calculation and summarization unit 12 calculates the summarization data corresponding to the second clock cycle based on a preset calculation: 0x2468ACE0 XOR 0x13579BDF XOR 0xFEDCBA98 = 0xC9E38DA7. Finally, the calculation and summarization unit 12 processes the summarization data corresponding to the first and second clock cycles based on a preset calculation to obtain the target output data: 0x88888888 XOR 0xC9E38DA7 = 0x416B052F.

[0065] In this embodiment, output data is generated by simulating the test unit without reverse voltage in each clock cycle and determining the standard output data, so that fault detection of the test circuit can still be achieved even when the test unit has reverse voltage.

[0066] In some implementations, reference Figure 5 Another schematic diagram of circuit fault detection is shown, such as Figure 5 As shown, the circuit under test 110 may further include at least one data processing unit 142. Each first target unit under test 14 may be a cryptographic operation unit, an AI operation unit, etc. The specific type of each first target unit under test 14 is not limited in this embodiment. For example, each first target unit under test 14 may be a key generation unit (pqc_gen_unit) 1410, a key decapsulation unit (pqc_kd_unit) 1411, a sampling unit (pqc_smp_unit) 1412, a modulo operation unit (pqc_mcal_unit) 1413, a hash function unit (pqc_hash_unit) 1414, etc.

[0067] The data processing unit 142 can be a unit used to implement functions such as data format conversion and data concatenation. For example, the data processing unit 142 may include a first data processing unit (such as a random access memory controller (RAM ctrl)) 142 and a second data processing unit (such as a data concatenation unit (pack_core_mux)) 142. For instance, during normal data processing, the RAM controller 142 processes the data between each first target unit under test 14 and the memory (RAM 0 / 1) 20; during fault testing, the RAM controller 142 sends the data to the data concatenation unit (pack_core_mux) 142 or the fault detection circuit 100 according to a preset timing and preset format. The data concatenation unit (pack_core_mux) 142 performs data concatenation processing according to a preset bit width and sends the processed data to each first target unit under test 14 or the RAM controller 142. The subsequent quantum cryptography module may contain multiple first target test units 14 of different types (such as polynomial multiplication, number theory transformation, etc.), and each first target test unit 14 may require test data with different bit widths (64 bits, 128 bits, 256 bits) or different arrangements.

[0068] For example, the data distribution unit 11 can send test data to the first data processing unit 142 via the read data path (rdata). After receiving the test data, the first data processing unit 142 can perform second preset processing such as data format conversion on the test data to obtain first test data, and then send the first test data to the second data processing unit 142. After receiving the first test data, the second data processing unit 142 can perform second preset processing such as data concatenation on the first test data to obtain target test data, and then send the target test data to each first target tested unit 14. Thus, each first target tested unit 14 can perform calculations on the target test data to obtain first output data.

[0069] After receiving the target test data, the second data processing unit 142 can send the target test data to the direct memory access controller (ahb_dma) 19 through the read data path (rdata), so that the direct memory access controller (ahb_dma) 19 can send the target test data to the direct memory access subunit (gen_dma) 15 through the read data path (rdata); at the same time, the second data processing unit 142 sends the target test data to the functional subunits 15 other than the direct memory access subunit (gen_dma) 15.

[0070] Next, each first target test unit 14 can send its first output data to the calculation and summarization unit 12. The calculation and summarization unit 12 receives the first output data of each first target test unit 14 and processes the first output data of each first target test unit 14 based on a preset calculation to obtain second output data corresponding to at least one first target test unit 14; then it sends the summarized second output data to the second data processing unit 141. Among them, after the direct memory access subunit (gen_dma) 15 obtains the first output data, it can send the first output data to the direct memory access controller (ahb_dma) 19 through the write data path (wdata), and then the direct memory access controller (ahb_dma) 19 sends the first output data to the calculation and summarization unit 12 through the write data path (wdata).

[0071] The second data processing unit 141 can perform second preset processing such as data splicing on the second output data, and then send the processed second output data to the first data processing unit 141. The first data processing unit 141 then performs second preset processing such as data format conversion on the received second output data to obtain the target output data, and sends the target output data to the verification unit 13 through the write data path (wdata).

[0072] In this embodiment, the circuit under test may include not only a first target unit for performing cryptographic operations, AI operations, etc., but also a data processing unit for performing conventional data processing. Thus, if the data processing unit makes a mistake in processing the test data or output data, it can also determine that the circuit under test has failed based on the target output data, so that fault detection can cover the entire data path from test data generation to result output.

[0073] In some implementations, reference continues. Figure 5 After obtaining the fault detection result, the verification unit 13 in the fault detection circuit 100 can send the fault detection result to the execution unit (pqc_op_exe) 130; and send the fault detection result to the processor 120 through the execution unit 130.

[0074] For example, the fault detection circuit 100 may further include selectors (such as a first selector and a second selector) 18. The processor 120 may send a detection instruction to the execution unit 130, which may be a fault detection start instruction (such as katstart) or a fault detection stop instruction (such as katstop). The processor 120 may divide at least one unit 14 in the circuit under test 110 based on a preset grouping method to obtain at least one test combination. When performing fault detection, the processor 120 may determine the target combination to be detected in at least one test combination and send a fault detection start instruction for the target combination to the execution unit 130. In response to the fault detection start instruction, the execution unit 130 sends an enable signal (hereinafter referred to as the first signal, kat enable) to the first selector 18 to trigger the first selector 18 to open the path between the fault detection circuit 100 and the circuit under test 110, and close the path between the memory 20 and the circuit under test 110. Furthermore, the execution unit 130 can send an enable signal (i.e., a third signal) to the second selector 18 to trigger the second selector 18 to open the path between the Advanced High Performance Bus (AHB) and the Direct Memory Access Controller (ahb_dma) 19. Additionally, the execution unit 130 can send a fault detection enable command for the target combination to the fault detection circuit 100 and the circuit under test 110, causing the fault detection circuit 100 and the circuit under test 110 to respond to the fault detection enable command. The fault detection circuit 100 generates test data and sends it to each of the first target units under test 14 in the target combination. Each first target unit under test 14 receives the test data and generates output data.

[0075] Alternatively, when fault detection is not required, processor 120 can send a fault detection stop instruction to execution unit 130. In response to this instruction, execution unit 130 sends a second signal to first selector 18 to trigger it to close the path between the fault detection circuit and the circuit under test, and to open the path between memory 20 and the circuit under test. This allows the circuit under test 110 to write or read data from memory 20 without receiving test data from fault detection circuit 100. Furthermore, execution unit 130 can send a fourth signal to second selector 18 to trigger it to open the path between the Advanced High Performance Bus (AHB) and the Direct Memory Access Controller (ahb_dma) 19. This allows the Direct Memory Access Subunit (gen_dma) 15 to read input data from the AHB via the read data path (rdata). In addition, the execution unit 130 can send a fault detection stop command to the fault detection circuit 100 and the circuit under test 110, so that the fault detection circuit 100 stops generating and outputting test data in response to the fault detection stop command, and the circuit under test 110 can read data from the memory 20 and AHB and write data to the memory 20.

[0076] In this embodiment, the execution unit (pqc_op_exe) and the selector enable switching between the fault detection mode and the normal operation mode (i.e., the non-fault detection mode), thereby improving the usability of the fault detection circuit and ensuring that the normal operation mode of the circuit is not affected.

[0077] This application provides a circuit fault detection method, which can be executed by the fault detection circuit shown in the above embodiments. Figure 6 This is a schematic diagram illustrating the implementation process of a circuit fault detection method provided in an embodiment of this application, as shown below. Figure 6 As shown, the method includes steps S601 to S604: S601, the test data generation unit generates test data.

[0078] S602, the data distribution unit sends test data to each first target unit under test in the circuit under test.

[0079] S603, the calculation and summarization unit receives the output data of each first target tested unit, and processes the output data of each first target tested unit based on a preset calculation to obtain target output data corresponding to at least one first target tested unit.

[0080] S604, the verification unit determines the fault detection result corresponding to at least one first target unit under test based on the standard output data and target output data corresponding to the test data.

[0081] It is understood that the implementation of S601 to S604 can be referred to the description of the above embodiments, and will not be repeated here.

[0082] Based on the foregoing embodiments, this application proposes a circuit fault self-testing method. This method utilizes a combination of a fixed seed, pseudo-random number generation, and CRC / HASH verification to achieve fault self-testing of transistors in an algorithm circuit. Exemplarily, this application uses a pseudo-random number generator (PRNG) or a linear feedback shift register (LFSR) to generate the input test vector (or test data) for self-testing. The calculation results (i.e., output data) output from the circuit (e.g., the circuit under test) or the arithmetic unit (e.g., the unit under test) are used to generate a Cyclic Redundancy Check (CRC) code or a HASH code. The comparison results are then used to check whether the arithmetic unit (or verification unit) has experienced a fault. Specifically, this includes: 1. Input data is generated by using a pseudo-random number generator (PRNG) or a linear feedback shift register (LFSR). The seed (i.e., preset seed value) stored in the circuit is used as the input of the PRNG / LFSR to generate a fixed set of test data. This allows most circuit fault detection to be completed with a small amount of hardware storage (seed), greatly reducing the consumption of hardware storage resources. 2. Test data is broadcast to each circuit under test, meaning that the input to each operator or sub-module under test (i.e., the unit under test) is consistent; 3. The calculation results (i.e., output data) output by the circuit under test (i.e., the unit under test) are summed by XOR; 4. After summarizing, input the data into the CRC / HASH unit to generate a CRC checksum or a HASH checksum as the self-test result (i.e., the target output data), and compare it with the standard result (i.e., the standard output data). If the self-test result is inconsistent with the standard result, it indicates that the circuit under test has failed.

[0083] In some implementations, the product-side technical solution can take the Functional Safety (FuSa) standard ISO 26262 as the core constraint, and achieve full-process safety assurance of "power-on self-test - periodic inspection - fault response" for the KAT testing requirements of cryptographic algorithm-related products. For specific deployment and implementation, please refer to the following: The KAT module (i.e., fault detection circuit) includes a seed storage unit, a PRNG / LFSR generation unit, a broadcast distribution unit, an XOR summarization unit, a CRC / HASH verification unit, and a comparison and fault output unit.

[0084] Interface adaptation: The KAT module connects to the cryptographic module via a standard AHB bus and supports input of trigger signals for KAT testing (power-on trigger, timed trigger, external command trigger).

[0085] The fault detection results are fed back to the Functional Safety Management Unit (CMP), triggering a safety response compliant with the FuSa standard (such as module reset or safety alarm reporting).

[0086] The storage area is configured with a read-write protection mechanism, allowing only internal reading by the BIST module and no external access interface, thus preventing the seed from being tampered with or reverse-engineered, and meeting the functional safety requirement of "test data integrity".

[0087] In some implementations, such as Figure 4 As shown, KAT uses a fixed seed embedded in the circuit, which is input into the PRNG module (i.e., the test data generation unit) to generate a pseudo-random number sequence as test data, which is then sent to each operator (i.e., the unit under test). The operator output is input into the CRC Gen module (i.e., the verification unit) to generate the corresponding CRC checksum, which is compared with the checksum embedded in the circuit. If they do not match, a fail alarm is output. Figure 2 As shown, the same test input data is generated by the KAT module and broadcast to each operator module. Figure 3 As shown, the results of each operator's output operation are XORed and then output to the KAT module.

[0088] like Figure 5 The diagram shows the operator architecture of the PQC cryptographic module. The ALU module contains various operator modules, such as PQC_Gen_Unit and PQC_KD_Unit. The KAT module, PQC_Alu_KAT, is used to generate random data, receive results, generate CRC checksums, and output them to the CMP module for result comparison. It can be seen that... Figure 5 The two selectors (such as the first selector and the second selector) select the KAT test path when KAT testing is enabled (KAT enable); and select the data path in normal working mode when KAT testing is disabled.

[0089] When a KAT test is initiated, all operators simultaneously receive the same test data and begin computation, outputting results. During the test, the data passes through the `ram ctrl` and `pack_core_mux` modules (these are data processing modules, not cryptographic operators; the `ram ctrl` module handles data between RAM and operators, and the `pack_core_mux` module handles data concatenation according to specific widths). Fault detection can also be performed on these two data processing modules during the KAT test. The specific detection process is as follows: 1. The processor initiates a KAT self-test through its software (such as the functional safety management module) to trigger KAT start (enable) through pqc_op_exe (i.e., the execution module).

[0090] 2. The fixed seed input is fed into the lfsr / prng module to generate a pseudo-random sequence. The rdata path of ram ctrl receives the pseudo-random sequence of pqc_alu_kat as the input of the operator. After passing through the pack module, it is broadcast to each operator.

[0091] 3. The results of each operator operation are summed together by XOR and output to the pqc_alu_kat module through the wdata path of the pqc_pack_mux and ramctrl modules. The pqc_alu_kat module generates a checksum (such as a 32-bit CRC checksum) based on the XOR result.

[0092] 4. It should be noted that some operators have backpressure during rdata, meaning that the input data cannot be continuous. However, the input of the pseudo-random sequence is continuous and cannot be backpressured. When setting golden, it is important to note that the input data of these operator modules is not a continuous input of the pseudo-random sequence, but rather a sequence spaced apart by a certain number of cycles.

[0093] 5. KAT detection can include the detection of DMA operators. By adding a selector (mux) between AHB DMA and AHB, the DMA operator can interact with the KAT module through the AHB DMA data path when KAT detection is performed.

[0094] Furthermore, in this embodiment, different combinations of operators can be tested according to business needs. The input test vector remains unchanged, and only the checksum of the stored test operation is added, increasing the flexibility of the test. That is to say, multiple operator combinations can be tested, each operator combination can be tested in parallel based on the scheme described in this embodiment, and serial testing can be performed between operator combinations, while keeping the test vector input to each combination unchanged.

[0095] In this embodiment, by generating test data using "fixed seed + PRNG / LFSR", only one seed (byte level) needs to be stored, replacing the original KB or even MB level complete test vector, greatly reducing hardware storage resources. Furthermore, by using "broadcast input + XOR aggregation", all modules under test share one CRC / HASH verification unit, eliminating the need for separate configuration for each module and significantly reducing hardware complexity. In addition, by broadcasting, all modules synchronously receive test data, and each module under test can perform detection operations simultaneously and independently in parallel. The output of multiple modules is integrated through XOR aggregation, avoiding serial processing. This enables efficient circuit fault detection of at least one operator with minimal resources.

[0096] It should be noted that, in the embodiments of this application, if the above-mentioned circuit fault detection method or circuit fault self-test method is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0097] This application provides a fault detection system. The fault detection system includes the fault detection circuit and the circuit under test as described in the above embodiments. The fault detection circuit is used to detect faults in the circuit under test and obtain fault detection results.

[0098] This application provides a computer-readable storage medium storing a computer program thereon. When executed by a fault detection circuit, the computer program implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0099] This application provides a computer program including computer-readable code, wherein when the computer-readable code is run in a fault detection circuit, the fault detection circuit performs some or all of the steps in the above method.

[0100] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a fault detection circuit, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0101] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0102] This application provides a computer storage medium that stores one or more programs, which can be executed by a fault detection circuit to implement the steps of the circuit fault detection method or circuit fault self-test method in the above embodiments.

[0103] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0104] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0105] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A fault detection circuit, characterized in that, The fault detection circuit is used for fault detection in the circuit under test, and the fault detection circuit includes: A test data generation unit is used to generate test data; wherein the test data is determined based on a preset seed value stored in the fault detection circuit. A data distribution unit is configured to send the test data to at least one first target unit under test in the circuit under test; wherein each first target unit under test is configured to process the test data and obtain output data; The calculation and summarization unit is used to receive the output data of each of the first target tested units and process the output data of each of the first target tested units based on a preset calculation to obtain target output data corresponding to at least one of the first target tested units; wherein, each of the first target tested units is determined after dividing at least one tested unit in the tested circuit based on a preset grouping method, and the preset grouping method is determined based on the type of the tested circuit. The verification unit is used to determine at least one fault detection result corresponding to the first target tested unit based on the standard output data corresponding to the test data and the target output data.

2. The fault detection circuit according to claim 1, characterized in that, The fault detection circuit also includes: Seed storage unit, used to store the preset seed value; The test data generation unit is used to obtain the preset seed value from the seed storage unit; The test data is generated based on the preset seed value; wherein the test data is a pseudo-random sequence. The data distribution unit is used to send the test data to each of the first target test units in a broadcast manner.

3. The fault detection circuit according to claim 2, characterized in that, The test data generation unit is used for: The first counter value is incremented according to a preset step to obtain the second counter value corresponding to the current clock cycle; wherein, the first counter value is the initial counter value, or the counter value corresponding to the previous clock cycle of the current clock cycle; The preset seed value, the first key, and the second counter value corresponding to the current clock cycle are subjected to a first preset process to obtain the second key corresponding to the current clock cycle; wherein, the first key is the initial key, or the key corresponding to the previous clock cycle of the current clock cycle; the first preset process includes XOR operation and / or shift operation; The second key corresponding to the current clock cycle is calculated based on a preset cryptographic algorithm to generate test data corresponding to the current clock cycle.

4. The fault detection circuit according to claim 1, characterized in that, The calculation and summarization unit is used for: The output data of each of the first target tested units are subjected to an XOR operation or a XNOR operation to obtain the target output data; wherein, the preset operation includes an XOR operation or a XNOR operation.

5. The fault detection circuit according to claim 1, characterized in that, The verification unit is used for: The target output data is converted into first mapped data based on a preset mapping rule; wherein, the mapped data obtained by converting the same data based on the preset mapping rule are the same, and the mapped data obtained by converting multiple data with at least one different bit based on the preset mapping rule are different. Obtain the second mapping data stored in the fault detection circuit; wherein the second mapping data is obtained by converting the standard output data corresponding to the test data based on the preset mapping rule; The second mapping data and the first mapping data are compared to determine the fault detection result corresponding to at least one of the first target tested units.

6. The fault detection circuit according to any one of claims 1-5, characterized in that, The circuit under test further includes a data processing unit; wherein... The data distribution unit is used to: send the test data to the data processing unit; The data processing unit is used to perform a second preset processing on the test data to obtain target test data, and send the target test data to each of the first target test units; each of the first target test units is used to perform calculations on the target test data to obtain first output data; the second preset processing includes data format conversion and / or data splicing processing; The calculation and aggregation unit is used to: receive the first output data of each of the first target tested units, and process the first output data of each of the first target tested units based on the preset calculation to obtain the second output data corresponding to at least one of the first target tested units; and send the second output data to the data processing unit. The data processing unit is used to perform a second preset processing on the second output data to obtain the target output data, and send the target output data to the verification unit.

7. The fault detection circuit according to any one of claims 1-5, characterized in that, The test data generation unit is used to: generate test data corresponding to each clock cycle; The calculation and summarization unit is used for: The system receives output data from the second target unit under test corresponding to each clock cycle for the test data corresponding to each clock cycle; wherein, the second target unit under test corresponding to each clock cycle is a first target unit under test capable of processing the test data of the corresponding clock cycle. The output data corresponding to each clock cycle is aggregated to obtain the aggregated data corresponding to each clock cycle. Data aggregation processing is performed on each bit of the aggregated data corresponding to multiple clock cycles to obtain target output data corresponding to at least one second target unit under test; wherein, the standard output data is determined based on the output data generated by the fault-free second target unit under test corresponding to each clock cycle.

8. The fault detection circuit according to any one of claims 1-5, characterized in that, The fault detection circuit also includes a selector; The selector is used to: in response to a first signal, open the path between the fault detection circuit and the circuit under test; or, in response to a second signal, close the path between the fault detection circuit and the circuit under test, and open the path between the preset memory and the circuit under test; wherein the circuit under test is used to write or read data to the preset memory.

9. A method for detecting circuit faults, characterized in that, Applied to a fault detection circuit, the fault detection circuit is used to detect faults in the circuit under test, and the method includes: The test data generation unit generates test data; wherein the test data is determined based on a preset seed value stored in the fault detection circuit; The data distribution unit sends the test data to at least one first target unit under test in the circuit under test; wherein each first target unit under test is used to process the test data and obtain output data; The calculation and summarization unit receives the output data of each of the first target tested units and processes the output data of each of the first target tested units based on a preset calculation to obtain target output data corresponding to at least one of the target tested units; wherein, each of the first target tested units is determined after dividing at least one tested unit in the tested circuit based on a preset grouping method, and the preset grouping method is determined based on the type of the tested circuit. Based on the standard output data corresponding to the test data and the target output data, the verification unit determines at least one fault detection result corresponding to the first target tested unit.

10. A fault detection system, characterized in that, The fault detection system includes a fault detection circuit as described in any one of claims 1-8, and a circuit under test; wherein the fault detection circuit is used to perform fault detection on the circuit under test to obtain a fault detection result.

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