Voltage stabilizing circuit

Abstract

The invention provides a voltage stabilizing circuit. The voltage stabilizing circuit comprises a circuit output end, an error amplifier, a conversion circuit, a current mirror, a pull-down current generating circuit and an auxiliary current generating circuit. The circuit output end is used for outputting the output voltage. The error amplifier generates a control voltage according to a reference voltage and a feedback voltage corresponding to an output voltage. The conversion circuit generates a control current according to the control voltage. The current mirror generates an output current and a sensing current according to the driving current. The current value of the sensing current is associated with the current value of the output current and the control voltage, and the ratio of the sensing current to the driving current is a first multiplying power. The pull-down current generating circuit generates an output current according to the control voltage. The auxiliary current generating circuit generates an auxiliary current according to the sensing current. The current value of the drive current is equal to the sum of the current value of the control current and the current value of the auxiliary current.

Description

Technical Field

[0001] This invention relates to a circuit, and more particularly to a voltage regulator circuit. Background Technology

[0002] A voltage regulator circuit can provide a stable output voltage based on the input voltage. The transient response of the voltage regulator circuit determines its performance. Therefore, how to provide a good transient response is one of the key research focuses for those skilled in the art. Summary of the Invention

[0003] This invention provides a voltage regulator circuit with good transient response.

[0004] According to one embodiment of the present invention, the voltage regulator circuit includes a circuit output terminal, an error amplifier, a conversion circuit, a current mirror, a pull-down current generating circuit, and an auxiliary current generating circuit. The circuit output terminal is used to output an output voltage. The error amplifier generates a control voltage based on a reference voltage and a feedback voltage corresponding to the output voltage. The conversion circuit is coupled to the output terminal of the error amplifier. The conversion circuit generates a control current based on the control voltage. The current mirror is coupled to the conversion circuit and the circuit output terminal. The current mirror generates an output current and a sense current based on a drive current. The value of the sense current is related to the value of the output current and the control voltage, and its ratio to the drive current is a first multiple. The pull-down current generating circuit is coupled between the error amplifier and the circuit output terminal. The pull-down current generating circuit generates the output current based on the control voltage. The auxiliary current generating circuit is coupled to the current mirror and the conversion circuit. The auxiliary current generating circuit generates an auxiliary current based on the sense current. The value of the drive current is equal to the sum of the value of the control current and the value of the auxiliary current.

[0005] Based on the above, the current mirror generates the output current and the sensing current based on the drive current. The auxiliary current is generated based on the sensing current. The pull-down current generation circuit generates the output current based on the control voltage. The auxiliary current generation circuit generates the auxiliary current based on the sensing current. It should be noted that the value of the drive current is equal to the sum of the values ​​of the control current and the auxiliary current. Therefore, the swing of the drive current value can be amplified. In this way, the voltage regulator circuit can have good transient response. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention;

[0007] Figure 2 This is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention;

[0008] Figure 3This is a loop gain type Bode plot shown according to an embodiment of the present invention;

[0009] Figure 4 This is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention.

[0010] Explanation of reference numerals in the attached figures

[0011] 100, 200, 300: Voltage Regulator Circuit

[0012] 110, 210: Conversion circuit

[0013] 120, 220, 320: Current mirror

[0014] 130, 230: Pull-down current generation circuit

[0015] 140, 240: Auxiliary current generating circuit

[0016] 150, 250: Compensation circuit

[0017] 160, 260: Compensation current generation circuit

[0018] 170, 270: Feedback circuit

[0019] 241: Auxiliary Current Circuit

[0020] 261: Current source

[0021] 262: Inverter

[0022] CC1, CF: Compensation capacitors

[0023] CL: Load capacitor

[0024] EA: Error Amplifier

[0025] I1: Control current

[0026] I2: Compensation current

[0027] IB: Auxiliary Current

[0028] ID: Drive Current

[0029] Idis: Discharge current

[0030] IM: Mapped Current

[0031] IOUT: Output current

[0032] IREF: Reference Current

[0033] ISEN: Sensing Current

[0034] KSE1: First Multiplier

[0035] KSE2: Second Multiplier

[0036] N1, NB1, NB2, P1, P2, P3: Transistors

[0037] ND1: First node

[0038] ND2: Second Node

[0039] NDF: Feedback Node

[0040] PP1, PP2, PF: Poles

[0041] RC1, RC2: Compensation resistors

[0042] RF1, RF2: Feedback resistors

[0043] rOUT: Equivalent impedance

[0044] SW: Switch

[0045] TC: Control Transistor

[0046] TC1, TC2: Compensation transistors

[0047] TOUT: Circuit output terminal

[0048] VFB: Feedback Voltage

[0049] VG: Control voltage

[0050] VH: Voltage source

[0051] VIN: Input voltage

[0052] VOUT: Output voltage

[0053] VREF: Reference Voltage

[0054] Z1, ZF1, ZF2: Zero point Detailed Implementation

[0055] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0056] Please refer to Figure 1 , Figure 1This is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention. In this embodiment, the voltage regulator circuit 100 includes a circuit output terminal TOUT, an error amplifier EA, a conversion circuit 110, a current mirror 120, a pull-down current generating circuit 130, and an auxiliary current generating circuit 140. The circuit output terminal TOUT is used to output the output voltage VOUT. The error amplifier EA generates a control voltage VG based on a reference voltage VREF and a feedback voltage VFB corresponding to the output voltage VOUT. For example, the voltage value of the feedback voltage VFB is proportional to the voltage value of the output voltage VOUT. The conversion circuit 110 is coupled to the output terminal of the error amplifier EA. The conversion circuit 110 generates a control current I1 based on the control voltage VG.

[0057] In this embodiment, the current mirror 120 is coupled to the conversion circuit 110 and the circuit output terminal TOUT. The current mirror 120 generates an output current IOUT and a sense current ISEN based on the drive current ID. The ratio of the sense current ISEN to the drive current ID is a first multiple. The sense current ISEN is related to the output current IOUT and the control voltage VG.

[0058] In this embodiment, the pull-down current generating circuit 130 is coupled between the error amplifier EA and the circuit output terminal TOUT. The pull-down current generating circuit 130 generates the output current IOUT based on the control voltage VG. The auxiliary current generating circuit 140 is coupled to the current mirror 120 and the conversion circuit 110. The auxiliary current generating circuit 140 generates the auxiliary current IB based on the sensed current ISEN. The current value of the drive current ID is equal to the sum of the current value of the control current I1 and the current value of the auxiliary current IB.

[0059] It is worth mentioning that the current mirror 120 generates the output current IOUT and the sensing current ISEN based on the drive current ID. The auxiliary current IB is generated based on the sensing current ISEN. The current value of the drive current ID is equal to the sum of the current values ​​of the control current I1 and the auxiliary current IB. Therefore, the swing of the drive current ID can be amplified. In this way, the voltage regulator circuit 100 can have good transient response.

[0060] For example, the inverting input of error amplifier EA receives the feedback voltage VFB. The non-inverting input of error amplifier EA receives the reference voltage VREF. When the load (not shown) increases, the output voltage VOUT at the circuit output TOUT decreases accordingly. The feedback voltage VFB decreases. Therefore, the control voltage VG increases. The control current I1 and the drive current ID increase. The current mirror 120 generates a sensing current ISEN based on the drive current ID. Therefore, the sensing current ISEN also increases. The auxiliary current IB also increases. Therefore, the drive current ID is further increased.

[0061] For example, when the load decreases, the output voltage VOUT at the circuit output terminal TOUT rises accordingly. The feedback voltage VFB rises. Therefore, the control voltage VG falls. The control current I1 and the drive current ID fall. The sensing current ISEN and the auxiliary current IB also fall. Therefore, the drive current ID falls further.

[0062] It should be noted that because variations in the drive current ID can be amplified, the range of variation in the control voltage VG can be reduced. This, in turn, reduces the design complexity of the error amplifier EA.

[0063] In this embodiment, the pull-down current generating circuit 130 pulls down the output current IOUT based on the control voltage VG. For example, when the load decreases, the output voltage VOUT rises accordingly. The feedback voltage VFB rises. Therefore, the control voltage VG decreases. The pull-down current generating circuit 130 quickly pulls down the output current IOUT based on the decrease in the control voltage VG. In this way, under light load or no load conditions, the pull-down current generating circuit 130 can quickly reduce the output current IOUT. In this embodiment, the pull-down current generating circuit 130 can use the discharge current Idis to reduce the output current IOUT.

[0064] In this embodiment, the voltage regulator circuit 100 further includes a compensation circuit 150, a compensation current generation circuit 160, and a feedback circuit 170. The feedback circuit 170 is coupled to the circuit output terminal TOUT and the error amplifier EA. The feedback circuit 170 provides a feedback voltage VFB based on the output voltage VOUT. The compensation circuit 150 is coupled to the circuit output terminal TOUT, the current mirror 120, and the error amplifier EA. The voltage regulator circuit 100 utilizes at least the compensation circuit 150 and the conversion circuit 110 to improve its phase margin. Therefore, the power supply rejection ratio (PSRR) of the voltage regulator circuit 100 can be improved.

[0065] The compensation current generating circuit 160 is coupled to the auxiliary current generating circuit 140. The compensation current generating circuit 160 generates a mapped current IM based on the sensed current ISEN. When the current value of the mapped current IM is greater than the reference current value of the reference current IREF, the compensation current generating circuit 160 outputs a compensation current I2 to further increase the current value of the drive current ID.

[0066] In some embodiments, the voltage regulator circuit 100 does not include the compensation circuit 150, the compensation current generation circuit 160, and the feedback circuit 170.

[0067] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention. In this embodiment, the voltage regulator circuit 200 includes a circuit output terminal TOUT, an error amplifier EA, a conversion circuit 210, a current mirror 220, a pull-down current generating circuit 230, an auxiliary current generating circuit 240, a compensation circuit 250, a compensation current generating circuit 260, and a feedback circuit 270.

[0068] In this embodiment, the conversion circuit 210 includes a control transistor TC. A first terminal of the control transistor TC is coupled to a first node ND1. A second terminal of the control transistor TC is coupled to a reference low voltage (e.g., ground). The control terminal of the control transistor TC is coupled to the output of the error amplifier EA. In this embodiment, the control transistor TC is implemented using an N-type transistor, but the invention is not limited thereto.

[0069] In this embodiment, the conversion circuit 210 further includes a compensation resistor RC1 and a compensation capacitor CC1. The compensation capacitor CC1 and the compensation resistor RC1 are connected in series between the output of the error amplifier EA and the reference low voltage.

[0070] In this embodiment, the current mirror 220 includes transistors P1 to P3. The first terminal of transistor P1 is coupled to the input voltage VIN. The second terminal of transistor P1 is coupled to the first node ND1 and the control terminal of transistor P1. The first terminal of transistor P2 is coupled to the input voltage VIN. The second terminal of transistor P2 is coupled to the circuit output terminal TOUT. The control terminal of transistor P2 is coupled to the control terminal of transistor P1. The first terminal of transistor P3 is coupled to the input voltage VIN. The control terminal of transistor P3 is coupled to the first node ND1. The second terminal of transistor P3 is coupled to the second node ND2.

[0071] In this embodiment, transistor P1 generates the drive current ID. Transistor P2 generates the output current IOUT. Transistors P1 to P3 are each implemented using P-type transistors, but the invention is not limited thereto. In this embodiment, transistors P1 to P3 are each implemented using P-type transistors with high voltage tolerance, but the invention is not limited thereto.

[0072] In this embodiment, the current mirror 220 further includes a sensing circuit 221. The sensing circuit 221 is coupled to the transistor P2. The sensing circuit 221 multiplies the current value of the drive current ID by a first multiplier KSE1 to generate a sensing current ISEN. In other words, the ratio of the current value of the sensing current ISEN to the drive current ID is the first multiplier KSE1. In this embodiment, the first multiplier KSE1 is a positive real number. For example, the sensing circuit 221 may be implemented by a current mirror circuit, but the present invention is not limited thereto.

[0073] In this embodiment, the pull-down current generating circuit 230 is coupled to the control terminal of the control transistor TC to receive the control voltage VG, and pulls down the output current IOUT according to the voltage value of the control voltage VG.

[0074] In this embodiment, the auxiliary current generating circuit 240 includes an auxiliary current circuit 241. The auxiliary current circuit 241 is coupled to the current mirror 220 and the conversion circuit 210. The auxiliary current circuit 241 adjusts the current value of the sensed current ISEN based on a second multiplier KSE2 to generate an auxiliary current IB. Furthermore, the current value of the auxiliary current IB is equal to "1 / KSE2" times the current value of the sensed current ISEN.

[0075] It should be noted that the current mirror 220 and the auxiliary current circuit 241 have a positive feedback mechanism. That is, without limiting the first multiplier KSE1 and the second multiplier KSE2, as the current value of the sensed current ISEN increases, the current value of the auxiliary current IB increases accordingly, and the current value of the drive current ID increases accordingly, thereby further increasing the current values ​​of the sensed current ISEN and the auxiliary current IB. Conversely, without limiting the first multiplier KSE1 and the second multiplier KSE2, the changes in the current values ​​of the sensed current ISEN and the auxiliary current IB are gradually amplified. Therefore, in this embodiment, the first multiplier KSE1 is less than the second multiplier KSE2. The changes in the current values ​​of the sensed current ISEN and the auxiliary current IB are converged and prevented from being continuously amplified.

[0076] In this embodiment, the auxiliary current circuit 241 includes transistors NB1 and NB2. The first terminal of transistor NB1 is coupled to the first node ND1. The second terminal of transistor NB1 is coupled to a reference low voltage. The first terminal of transistor NB2 receives the sensed current ISEN and is coupled to the control terminal of transistors NB1 and NB2. The second terminal of transistor NB2 is coupled to the reference low voltage. The auxiliary current circuit 241 receives the sensed current ISEN from the sensing circuit 221 and provides an auxiliary current IB to the first node ND1. In this embodiment, transistors NB1 and NB2 are implemented using N-type transistors, but the invention is not limited thereto.

[0077] In this embodiment, the feedback circuit 270 includes feedback resistors RF1 and RF2. Feedback resistor RF2 is coupled between the circuit output terminal TOUT and the feedback node NDF. Feedback resistor RF1 is coupled between the feedback node NDF and the reference low voltage. The feedback circuit 270 provides the feedback voltage VFB to the error amplifier EA via the feedback node NDF.

[0078] In this embodiment, the compensation circuit 250 includes a compensation resistor RC2 and a compensation capacitor CF. The compensation resistor RC2 is connected between the second node ND2 and the circuit output terminal TOUT. The compensation capacitor CF is coupled between the second node ND2 and the feedback node NDF.

[0079] In this embodiment, the compensation current generating circuit 260 includes a switch SW and a compensation transistor TC1. The first terminal of the switch SW is coupled to the current mirror 220 and the switching circuit 210 via a first node ND1. The first terminal of the compensation transistor TC1 is coupled to the second terminal of the switch SW. The second terminal of the compensation transistor TC1 is coupled to a reference low voltage. The control terminal of the compensation transistor TC1 is coupled to the output terminal of the error amplifier EA. The control terminal of the compensation transistor TC1 receives a control voltage VG. The compensation current generating circuit 260 generates a mapped current IM based on the sensed current ISEN. When the value of the mapped current IM is greater than the reference current value of the reference current IREF, the compensation current generating circuit 260 turns on the switch SW. When the value of the mapped current IM is less than the reference current value of the reference current IREF, the compensation current generating circuit 260 turns off the switch SW. When the value of the mapped current IM is equal to the reference current value of the reference current IREF, the switch SW remains in its current switching state.

[0080] Furthermore, the compensation current generating circuit 260 also includes a current source 261, a compensation transistor TC2, and an inverter 262. The current source 261 provides a reference current value for the reference current IREF based on the voltage source VH. The first terminal of the compensation transistor TC2 is coupled to the current source 261. The second terminal of the compensation transistor TC2 is coupled to a reference low voltage. The control terminal of the compensation transistor TC2 is coupled to the control terminals of transistors NB1 and NB2. The input terminal of the inverter 262 is coupled to the first terminal of the compensation transistor TC2. The output terminal of the inverter 262 is coupled to the control terminal of the switch SW. In this embodiment, the switch SW and the compensation transistors TC1 and TC2 are implemented using N-type transistors, but the invention is not limited thereto.

[0081] In this embodiment, the reference current value of the reference current IREF is, for example, 10mA. The compensation transistor TC2 generates a mapped current IM. When the mapped current IM is lower than the reference current IREF, the input of inverter 262 is at a high level. This causes the output of inverter 262 to be at a low level. Therefore, switch SW is turned off. When the mapped current IM is higher than the reference current IREF, the input of inverter 262 is at a low level. This causes the output of inverter 262 to be at a high level. Switch SW is turned on. Therefore, the compensation current generation circuit 160 outputs a compensation current I2. In other words, when the mapped current IM is higher than the reference current IREF, the drive current ID is approximately equal to the sum of the control current I1, the auxiliary current IB, and the compensation current I2.

[0082] Please refer to Figure 2 as well as Figure 3 , Figure 3This is a loop gain Bode plot according to an embodiment of the present invention. In this embodiment, the voltage regulator circuit 200 provides poles PP1, PP2, PF and zeros Z1, ZF1, ZF2. Pole PP2 is lower than pole PP1. Pole PP1 is lower than zero ZF1. Zero ZF1 is lower than pole PF. Pole PF is lower than zero Z1. Zero Z1 is lower than zero ZF2. Pole PF is a feedback pole. Zeros ZF1 and ZF2 are feedback zeros.

[0083] The pole PP1 can be determined by formula (1). In other words, the pole PP1 can be determined by the resistance value rC1 of the compensation resistor RC1, the equivalent impedance ro1 of the output terminal of the error amplifier EA, and the capacitance value cC of the compensation capacitor CC1.

[0084]

[0085] The pole PP2 can be determined by formula (2). In other words, the pole PP2 can be determined by the equivalent impedance rOUT of the circuit output terminal TOUT and the capacitance cL of the load capacitor CL.

[0086]

[0087] The pole PF can be determined by formula (3). In other words, the pole PF can be determined by dividing the resistance value rF1 of feedback resistor RF1 by the resistance value rF1 of feedback resistor RF2, the resistance value rF2 of feedback resistor RF2, and the capacitance value cF of compensation capacitor CF. Furthermore, the frequency of the pole PF can be determined by the parallel resistance value of feedback resistors RF1 and RF2 (i.e., rF1 / / rF2) and the capacitance value cF.

[0088]

[0089] The zero point Z1 can be determined by formula (4). In other words, the zero point Z1 can be determined by the resistance value rC1 of the compensation resistor RC1 and the capacitance value cC of the compensation capacitor CC1.

[0090]

[0091] The zero point ZF1 can be determined by formula (5). In other words, the zero point ZF1 can be determined by the resistance value rF2 of the feedback resistor RF2 and the capacitance value cF of the compensation capacitor CF.

[0092]

[0093] The zero point ZF2 can be determined by formula (6). In other words, the zero point ZF2 can be determined by the gain function KC, the resistance value rC2 of the compensation resistor RC2, and the capacitance value cL of the load capacitor CL.

[0094]

[0095] Generally, the mathematical relationship between the loop gain A of a typical voltage regulator circuit and the resistance values ​​rF1 and rF2 of feedback resistor RF1 and RF2 is shown in formula (7). From formula (7), it can be seen that the loop gain A is obtained by dividing the resistance value rF1 of feedback resistor RF1 by the sum of the resistance values ​​rF1 and rF2 of feedback resistor RF2. The loop gain A is directly proportional to the quotient.

[0096]

[0097] For typical design requirements, the frequency of the feedback zero (e.g., zero ZF1) must be sufficiently low to ensure the phase margin of the voltage regulator circuit 200. The frequency of the feedback pole (e.g., pole PF) must be sufficiently high. Therefore, based on equations (3) and (5), the resistance value rF2 of the feedback resistor RF2 is designed to be much larger than the resistance value rF1 of the feedback resistor RF1 (i.e., rF2 >> rF1). However, this design reduces the loop gain A of the voltage regulator circuit 200. Consequently, the power supply rejection ratio (PSRR) of the voltage regulator circuit 200 is reduced.

[0098] It should be noted that in this embodiment, a zero point ZF2 lower than zero point ZF1 is established. The compensation resistor RC2 and the feedback resistor RF2 are connected in series between the current mirror 220 and the feedback node NDF. Therefore, the resistance value rC2 of the compensation resistor RC2 can be increased. This allows the resistance value rF2 of the feedback resistor RF2 to be reduced. In this way, the voltage regulator circuit 200 has a sufficiently low zero point ZF2, a sufficiently high pole PF, and a good loop gain A.

[0099] Furthermore, based on formula (6), the resistance value rC2 of the compensation resistor RC2 is increased. This allows the capacitance value cC of the compensation capacitor CC1 to be reduced, thereby improving the PSRR of the voltage regulator circuit 200.

[0100] Please refer to Figure 4 , Figure 4This is a schematic diagram of a voltage regulator circuit according to an embodiment of the present invention. In this embodiment, the voltage regulator circuit 300 includes a circuit output terminal TOUT, an error amplifier EA, a conversion circuit 210, a current mirror 320, a pull-down current generating circuit 230, an auxiliary current generating circuit 240, a compensation circuit 250, a compensation current generating circuit 260, and a feedback circuit 270. Implementation details of the error amplifier EA, conversion circuit 210, pull-down current generating circuit 230, auxiliary current generating circuit 240, compensation circuit 250, compensation current generating circuit 260, and feedback circuit 270 are already provided. Figure 2 The embodiments are clearly illustrated and will not be repeated here.

[0101] In this embodiment, the current mirror 320 includes transistors P1-P3 and N1. The first terminal of transistor P1 is coupled to the input voltage VIN. The second terminal of transistor P1 is coupled to the control terminal of transistor P1. The first terminal of transistor N1 is coupled to the second terminal of transistor P1. The second terminal of transistor N1 is coupled to the first node ND1. The control terminal of transistor N1 receives a voltage source VH. The first terminal of transistor P2 is coupled to the input voltage VIN. The second terminal of transistor P2 is coupled to the circuit output terminal TOUT. The control terminal of transistor P2 is coupled to the control terminal of transistor P1. The first terminal of transistor P3 is coupled to the input voltage VIN. The control terminal of transistor P3 is coupled to the first node ND1. The second terminal of transistor P3 is coupled to the second node ND2. In this embodiment, transistors P1-P3 are each implemented using P-type transistors with high voltage withstand capability. Transistor N1 is implemented using N-type transistors with high voltage withstand capability. Transistor N1 is continuously turned on and used to provide high-voltage protection for the first node ND1.

[0102] In summary, the current mirror generates the output current and sense current based on the drive current. The auxiliary current is generated based on the sensed current. The pull-down current generation circuit generates the output current based on the control voltage. The auxiliary current generation circuit generates the auxiliary current based on the sensed current. It should be noted that the drive current is equal to the sum of the control current and the auxiliary current. Therefore, fluctuations in the drive current can be amplified. This allows the voltage regulator circuit to have good transient response. Furthermore, the resistance value of the compensation resistor in the compensation circuit and the capacitance value of the load capacitor connected to the circuit output can form a new zero point. The compensation resistor helps to give the voltage regulator circuit good loop gain and PSRR.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage regulator circuit, characterized in that, The voltage regulator circuit includes: The circuit output terminal is used to output the output voltage. An error amplifier is configured to generate a control voltage based on a reference voltage and a feedback voltage corresponding to the output voltage; A conversion circuit, coupled to the output of the error amplifier, is configured to generate a control current based on the control voltage; A current mirror, coupled to the conversion circuit and the circuit output, is configured to generate an output current and a sensing current based on the drive current, wherein the current value of the sensing current is related to the current value of the output current and the control voltage, and the ratio of the sensing current to the drive current is a first multiple. A pull-down current generating circuit, coupled between the error amplifier and the circuit output, is configured to generate the output current based on the control voltage; and An auxiliary current generating circuit, coupled to the current mirror and the conversion circuit, is configured to generate an auxiliary current based on the sensed current. The driving current is equal to the sum of the control current and the auxiliary current.

2. The voltage regulator circuit according to claim 1, characterized in that, The current mirror also includes: A transistor, wherein a first terminal of the transistor is coupled to an input voltage, a control terminal of the transistor is coupled to a first node, and a second terminal of the transistor is coupled to a second node.

3. The voltage regulator circuit according to claim 1, characterized in that, The auxiliary current generating circuit includes: An auxiliary current circuit, coupled to the current mirror and the conversion circuit, is configured to reduce the current value of the sensed current based on a second factor to generate the auxiliary current.

4. The voltage regulator circuit according to claim 3, characterized in that, The first multiplier is less than the second multiplier.

5. The voltage regulator circuit according to claim 3, characterized in that, The voltage regulator circuit also includes: A compensation current generating circuit, coupled to the auxiliary current circuit, is configured to generate a mapped current based on the sensed current, and outputs a compensation current to increase the value of the drive current when the value of the mapped current is greater than the reference current value.

6. The voltage regulator circuit according to claim 5, characterized in that, The compensation current generating circuit includes: A switch, the first end of which is coupled to the current mirror and the switching circuit via a first node; and A compensation transistor, wherein a first terminal of the compensation transistor is coupled to a second terminal of the switch, a second terminal of the compensation transistor is coupled to a reference low voltage, and a control terminal of the compensation transistor is coupled to the output terminal of the error amplifier.

7. The voltage regulator circuit according to claim 2, characterized in that, The voltage regulator circuit further includes a compensation circuit, which includes: A first compensation resistor is coupled between the second node and the circuit output terminal; and The first compensation capacitor is coupled between the second node and the feedback node.

8. The voltage regulator circuit according to claim 7, characterized in that, The load capacitor and the first compensation resistor constitute the zero point of the voltage regulator circuit.

9. The voltage regulator circuit according to claim 7, characterized in that, The conversion circuit includes: A control transistor, wherein a first terminal of the control transistor is coupled to the first node, a second terminal of the control transistor is coupled to a reference low voltage, and a control terminal of the control transistor is coupled to the output terminal of the error amplifier; Second compensation resistor; and The second compensation capacitor is connected in series with the first compensation resistor between the output terminal of the error amplifier and the reference low voltage. The capacitance of the second compensation capacitor is less than that of the first compensation capacitor.

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