Data processing method, computing device and computer program product

Abstract

Embodiments of the present specification provide a data processing method, the method being implemented based on a computing device comprising a processor, an IOMMU, and at least one platform device, the platform device comprising a direct memory access (DMA) controller, the DMA controller comprising a plurality of pre-configured process address identifiers. In the data processing process, due to the fact that a plurality of process address identifiers are configured in the DMA controller in advance, an IOMMU can find a virtual address page table shared with a CPU according to a target identifier, translation from a virtual address to a physical address is executed according to the page table, DMA operation is completed, and in the whole process, the operation efficiency is improved. According to the method, a set of shared CPU virtual addresses are used in the interaction process among the processor, the DMA controller and the IOMMU, a page table of the IOMMU does not need to be additionally constructed, data handling from a kernel mode to a user mode is also avoided, and therefore the data processing efficiency is improved.

Description

Technical Field

[0001] This specification relates to the field of computer application technology, specifically to shared virtual address technology in the field of computer application technology, and more specifically to a data processing method, computing device, and computer program product. Background Technology

[0002] DMA (Direct Memory Access) is a technology that allows hardware devices in a computing device (such as disk controllers, network cards, audio and video codecs, etc.) to directly read and write data with main memory without the continuous involvement of the processor. Its purpose is to free the processor from heavy data moving work.

[0003] However, in traditional DMA operations, user-mode programs mostly use virtual addresses to describe the location of data in memory, while devices typically require physical addresses to perform the actual DMA operation. Therefore, in traditional DMA operations, the virtual address needs to be translated into a physical address using the kernel's page table before the device can access the actual data. This process requires copying data between user mode and kernel mode, resulting in data copying overhead and reduced data processing efficiency. Summary of the Invention

[0004] This specification provides a data processing method, computing device, and computer program product to improve data processing efficiency.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions: In a first aspect, one embodiment of this specification provides a data processing method applied to a computing device, the computing device including a processor, an input / output memory management unit (IOMMU), and at least one platform device. The processor is used to run a target application and a driver for the platform device. The platform device includes a direct memory access (DMA) controller, the DMA controller including a plurality of pre-configured process address identifiers and at least one device identifier. The process address identifiers correspond to processes, and the device identifiers correspond to the platform device. The data processing method includes: The target application sends a data processing request carrying a virtual address to the driver of the target platform device. The data processing request is used to instruct the target platform device to configure the virtual address in the DMA controller of the target platform device. The DMA controller of the target platform device sends a DMA request carrying a target identifier and the virtual address to the IOMMU. The DMA request is used to instruct the IOMMU to perform a DMA operation on the target data corresponding to the virtual address according to the target identifier. The target identifier includes a target device identifier and a process address identifier describing the target process. The target process is the process that initiates the data processing request in the target application. The target device identifier is used to describe the target platform device.

[0006] Secondly, one embodiment of this specification provides a computing device, including: a processor, an IOMMU, and at least one platform device, the platform device including a direct memory access (DMA) controller, the DMA controller including a plurality of pre-configured process address identifiers and at least one device identifier, the process address identifiers corresponding to processes, and the device identifiers corresponding to the platform device, wherein the processor is configured to: run a target application and a driver for the platform device; The processor is further configured to: send a data processing request carrying a virtual address to the driver of the target platform device based on the running target application, the data processing request being used to instruct the target platform device to configure the virtual address in the DMA controller of the target platform device; The DMA controller of the target platform device sends a DMA request carrying a target identifier and the virtual address to the IOMMU. The DMA request is used to instruct the IOMMU to perform a DMA operation on the target data corresponding to the virtual address according to the target identifier. The target identifier includes a target device identifier and a process address identifier describing the target process. The target process is the process that initiates the data processing request in the target application. The target device identifier is used to describe the target platform device.

[0007] Thirdly, one embodiment of this specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the data processing method described above.

[0008] Fourthly, embodiments of this specification provide a computer program product or computer program, the computer program product including a computer program stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, it implements the steps of the data processing method described above. Optionally, the computer program may be stored in a computer-readable storage medium or in the cloud; the processor of the computer device reads the computer program from the readable storage medium or in the cloud.

[0009] As can be seen from the above technical solutions, the embodiments of this specification provide a method for platform devices to perform DMA operations based on shared virtual address technology. Specifically, the method is implemented based on a computing device including a processor, an IOMMU, and at least one platform device. The processor is used to run a target application and a driver for the platform device. The platform device includes a direct memory access DMA controller. The DMA controller includes a plurality of pre-configured process address identifiers and at least one device identifier. The device identifier corresponds to the platform device, and the process address identifier corresponds to a process. The platform device is identified by the device identifier, and the context and address space of different processes are identified by the process address identifier, laying the foundation for the processor and platform device to share virtual addresses.

[0010] During data processing, the target application directly sends a data processing request carrying a virtual address to the driver of the target platform device. This request instructs the target platform device to configure the virtual address in its DMA controller. The DMA controller then sends a DMA request carrying a target identifier and the virtual address to the IOMMU. The DMA request instructs the IOMMU to perform a DMA operation on the target data corresponding to the virtual address based on the target identifier. Thus, throughout the DMA operation, because the DMA controller is pre-configured with multiple process address identifiers and at least one device identifier (with process address identifiers corresponding to processes and device identifiers corresponding to platform devices), the context and address space of the corresponding process are identified using the process address identifier. The IOMMU finds the virtual address page table shared with the processor based on the target identifier and performs the translation from virtual address to physical address according to this page table, thereby completing the DMA operation. Throughout this process, a shared set of processor virtual addresses is used in the interaction between the processor, DMA controller, and IOMMU, eliminating the need to construct additional IOMMU page tables and avoiding data transfer from kernel mode to user mode, thereby improving data processing efficiency. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a computing device provided for the implementation of this specification.

[0013] Figure 2 This is a flowchart illustrating a data processing method provided for an embodiment of this specification.

[0014] Figure 3 This is a schematic diagram of a hardware architecture for implementing a data processing method, provided for the embodiments of this specification.

[0015] Figure 4 This is a signaling flowchart of a data processing method provided for an embodiment of this specification. Detailed Implementation

[0016] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0017] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0018] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0019] Overview To address the issue of low data processing efficiency caused by data copying between kernel mode and user mode in traditional DMA processes, Shared Virtual Address (SVA) technology was introduced. This technology aims to allow the processor's MMU (Memory Management Unit) and IOMMU (Import and Output Memory Management Unit) to share the same set of process page tables. This allows user-mode programs to directly hand over virtual addresses to the hardware for DMA execution, eliminating the cumbersome process of traditional DMA that involves "allocating a kernel buffer—mmapping (memory mapping) to user mode → the user-mode program copying data to that area → notifying the hardware device to execute DMA (the hardware device uses the IOMMU to map the IOVA (IO Virtual Address) of the kernel buffer)".

[0020] Currently, SVA technology has made some progress in PCIe (Peripheral Component Interconnect Express) controllers. Hardware devices cache the mapping between virtual addresses and physical addresses through the PCIe controller's Address Translation Service (ATS) and dynamically handle page faults through the Page Request Interface (PRI), ensuring cache consistency between the hardware device and the CPU. This functionality has brought significant performance improvements to the storage and graphics processing fields. Specifically, solid-state drives (SSDs) and graphics processing units (GPUs) that support the NVMe (Non-Volatile Memory Express) protocol can directly access user-space memory using the input / output virtual address mechanism. This direct access method avoids the cumbersome data transfer steps of traditional methods, greatly reducing data transfer latency, thereby significantly improving the data read / write speed of storage devices and the rendering efficiency of graphics processors, providing users with a smoother and more efficient user experience.

[0021] However, platform devices lack support for SVA technology. During data processing, these devices cannot leverage the advantages of SVA and still need to copy data between user space and kernel space, resulting in low data processing efficiency. This not only limits further performance improvements but also hinders their expansion into more high-end application scenarios.

[0022] To enable platform devices to support SVA technology and improve their efficiency in data processing, improvements were first made to the platform devices themselves. Multiple process address identifiers and at least one device identifier were pre-configured in the DMA controller of the platform device. The device identifier corresponds to the platform device. These process address identifiers can identify the process's context and address space, allowing the platform device and processor to share the same address semantics and translation context based on these process address identifiers. This prevents out-of-bounds access during DMA operations and ensures spatial isolation between different processes. This lays the foundation for the DMA controller to directly initiate DMA requests to the IOMMU using virtual addresses. The DMA controller can use the target identifier to identify the process that needs to initiate the DMA request and send the target identifier to the IOMMU. The IOMMU can then select the correct process page table based on the target identifier and perform address translation, ultimately implementing the DMA operation based on the memory controller.

[0023] Based on the aforementioned hardware architecture, a data processing method is proposed. During data processing, the target application directly sends a data processing request carrying a virtual address to the driver of the target platform device. This request instructs the target platform device to configure the virtual address in its DMA controller. The DMA controller then sends a DMA request carrying a target identifier and the virtual address to the IOMMU. The DMA request instructs the IOMMU to perform a DMA operation on the target data corresponding to the virtual address based on the target identifier. Thus, throughout the DMA operation, because the DMA controller is pre-configured with multiple process address identifiers and at least one device identifier (with process address identifiers corresponding to processes and device identifiers corresponding to platform devices), the context and address space of the corresponding process are identified using the process address identifier. The IOMMU finds the virtual address page table shared with the processor based on the target identifier and performs virtual address to physical address translation according to this page table, thereby completing the DMA operation. Throughout this process, the pre-configured device identifier and multiple process address identifiers enable the platform device to share virtual addresses with the processor, allowing the platform device to directly use virtual addresses from user space, avoiding data transfer from kernel space to user space, and thus improving data processing efficiency.

[0024] When there are multiple platform devices, in order for the IOMMU to distinguish between different platform devices, there can be multiple device identifiers, each corresponding to a different platform device. The target device identifier (Stream ID, SID) of the target identifier can be used to describe the target platform device. This device identifier can be used to identify the platform device. Specifically, in one embodiment, the device identifier can describe at least one of the platform device's device configuration, security policy, and global settings. The IOMMU can identify which platform device the request originates from based on the device identifier, thereby achieving device-based access control and meeting the DMA access requirements of multiple platform devices in the computing device.

[0025] Based on the above concept, this specification proposes a data processing method. Before introducing the data processing method, the terminology that may be used in this specification will be explained: In this specification, "platform device" can refer to a hardware device in a computing device based on the ARM architecture; or, more specifically, a hardware device in a computing device that communicates with the processor via the AXI (Advanced eXtensible Interface) protocol or the APB (Advanced Peripheral Bus) protocol; or, even more specifically, a platform device in a computing device that includes a DMA controller. Platform devices can encompass various on-chip peripherals and interface devices.

[0026] The IOMMU (Input-Output Memory Management Unit) is hardware used for address translation, memory protection, and isolation. The IOMMU supports PCIe passthrough and security enhancements (i.e., protection against DMA attacks). In this specification, the IOMMU is also used to support SVA (System Memory Management). The name of the IOMMU may vary depending on the architecture. For example, in one architecture, the IOMMU may also be called the SMMU (System Memory Management Unit), and in another, it may be called VT-d (Virtualization Technology for Directed I / O). This specification will not exhaustively list them all. Unlike the MMU (Memory Management Unit) in the processor, the IOMMU can be processor-independent hardware, providing memory management for external devices (such as on-chip peripherals) and handling DMA requests or I / O transactions initiated by these devices. The MMU, on the other hand, serves the processor itself, handling virtual address access needs during instruction execution.

[0027] IOPF (Input / Output Page Fault) is a key mechanism in device passthrough technology, used to handle page faults that occur when virtual machines or platform devices directly access physical memory. When a device requests access to a physical memory page that is not mapped to its I / O page table (IOPT) via DMA (Direct Memory Access), IOPF triggers an exception handling process, dynamically allocating or mapping the required memory page to ensure the continuity and correctness of device access.

[0028] The data processing method provided in the embodiments of this specification will now be described exemplarily with reference to the accompanying drawings.

[0029] Exemplary methods To be applied Figure 1 Taking a computing device 100 as an example, some embodiments of this specification exemplify the data processing method. The computing device 100 includes a processor 10, an input / output memory management unit (IOMMU) 30, and at least one platform device 20. The processor 10 is used to run a target application and a driver for the platform device 20. The platform device 20 includes a direct memory access (DMA) controller. The DMA controller includes a plurality of pre-configured process address identifiers and at least one device identifier. The process address identifiers correspond to processes, and the device identifiers correspond to the platform device. Figure 2As shown, the data processing method includes: S201: The target application sends a data processing request carrying a virtual address to the driver of the target platform device 20, the data processing request being used to instruct the target platform device 20 to configure the virtual address in the DMA controller of the target platform device 20; S202: The DMA controller of the target platform device 20 sends a DMA request carrying a target identifier and the virtual address to the IOMMU 30. The DMA request is used to instruct the IOMMU 30 to perform a DMA operation on the target data corresponding to the virtual address according to the target identifier. The target identifier includes a target device identifier and a process address identifier describing the target process. The target process is the process that initiates the data processing request in the target application. The target device identifier is used to describe the target platform device.

[0030] A process address space identifier (PASID, or SubstreamID, SSID) can be used to identify the context and address space of a process. In some implementations, the DMA controller can determine the process address space identifier corresponding to the process of the application that initiated the data processing request, and send the process address space identifier along with the virtual address to the IOMMU30, so that the IOMMU30 can perform the virtual address translation process in the address space corresponding to the process based on the process address space identifier, thereby completing the subsequent DMA operation.

[0031] The process address identifier configuration process in the DMA controller can be completed by the driver of platform device 20. Specifically, it can be completed during the initialization process of the driver of platform device 20. That is, after computing device 100 starts up, when the application loads the driver of platform device 20, the driver can complete the process of configuring the process address identifier of each process in platform device 20.

[0032] The target device identifier (Stream ID, SID) is used to describe the target platform device 20. This device identifier can be used to identify the platform device 20. Specifically, in one embodiment, the device identifier can also describe at least one of the following information: device configuration, security policy, and global settings of the platform device 20. The IOMMU 30 can identify which platform device 20 the request specifically originates from based on the device identifier, thereby achieving device-based access control and meeting the DMA access needs of multiple platform devices 20 in the computing device 100.

[0033] In one embodiment, to better implement the data processing method provided in this specification, the IOMMU30 can be adaptively configured to enable its SVA function and configure the bit width of the process address identifier. In a normal DMA process, the IOMMU30 terminates the DMA transaction and returns an error message upon encountering address translation failure. However, after configuring the SVA function support parameters of the platform device 20 in the IOMMU30, the IOMMU30 can pause the current DMA transaction and trigger IOPF when encountering address translation failure. Once the page fault problem is resolved through IOPF, the IOMMU30 will resume the DMA transaction, ensuring the DMA ultimately succeeds.

[0034] The DMA controller of platform device 20 may include multiple DMA channels, each of which is an independent, parallel-operating data transfer engine within the DMA controller. Each DMA control channel may have its own register set, state machine, and data path, thereby meeting the need for independently executing data transfer tasks. In some implementations, the process address identifier may be configured in the registers of the DMA channel; of course, in other implementations, the process address identifier may also be configured in the DMA controller in other ways, and this specification does not limit this.

[0035] In this embodiment, during data processing, the target application directly sends a data processing request carrying a virtual address to the driver of the target platform device 20. This request instructs the target platform device 20 to configure the virtual address in its DMA controller. The DMA controller then sends a DMA request carrying a target identifier and the virtual address to the IOMMU 30. The DMA request instructs the IOMMU 30 to perform a DMA operation on the target data corresponding to the virtual address based on the target identifier. Thus, throughout the DMA operation, because the DMA controller is pre-configured with multiple process address identifiers and at least one device identifier, with each process address identifier corresponding to a process and each device identifier corresponding to a platform device, the process address identifier identifies the context and address space of its corresponding process. This allows the IOMMU 30 to translate the virtual address within the address space of the process corresponding to the target identifier, thereby completing the DMA operation. Throughout this process, the pre-configured device identifier and multiple process address identifiers enable the platform device 20 to share virtual addresses with the processor 10, allowing the platform device 20 to directly use virtual addresses from user space, avoiding data transfer from kernel space to user space, and thus improving data processing efficiency.

[0036] In some implementations, the communication protocol between the DMA controller of platform device 20 and IOMMU30 may differ, which may cause the original DMA controller to not support the transmission of process address identifier. To solve this problem, the DMA controller and the IOMMU30 are connected through multiple signal lines, and the DMA controller communicates based on a first bus protocol, which lacks the field of the target identifier. The process by which the DMA controller of the target platform device 20 transmits the target identifier to the IOMMU 30 includes: The DMA controller of the target platform device 20 writes the target identifier into the target field and transmits it to the IOMMU 30 through the signal line corresponding to the target field, so as to instruct the IOMMU 30 to parse the target identifier from the target field, wherein the target field is an extended field in the first bus protocol.

[0037] In this embodiment, the DMA controller of platform device 20 communicates based on a first bus protocol. However, the first bus protocol lacks the target identifier field. Without adjusting the communication protocol of the DMA controller, this embodiment provides a feasible process for transmitting the target identifier between the DMA controller and IOMMU 30, which communicate based on the first bus protocol. Specifically, research has shown that the first bus protocol can include at least one extended field. These extended fields are fields used to transmit additional information unrelated to the protocol. The meaning of these extended fields can be defined by the designer, and the bit width can be configured according to requirements. Therefore, when the DMA controller and IOMMU 30 exchange information, the target identifier can be written into the target field, thereby achieving the goal of meeting the target identifier transmission requirements without changing the communication protocol of the DMA controller, which improves the applicability of the method.

[0038] In some implementations, the IOMMU30 can communicate based on a second bus protocol, in which a field for a target identifier can be defined.

[0039] Optionally, in one embodiment, the first bus protocol includes the Advanced Extensible Interface (AXI4) protocol, and the target field is a User field. The second bus protocol may include the AXI5 protocol. In this embodiment, using the User field of the first bus protocol as the field carrying the target identifier has the following advantages: When the DMA controller communicates with other AXI4 protocol slave devices besides IOMMU30, these slave devices can ignore the User field and operate normally without affecting the normal communication between the DMA controller and other AXI4 protocol slave devices. Furthermore, the bit width and semantics of the User field can be customized, which can meet the requirements of extending the User field to carry the target identifier in the embodiments of this specification. Moreover, the User field can be transmitted in parallel with the address / data without adding extra transmission cycles, which is beneficial for increasing transmission efficiency.

[0040] In one embodiment of this specification, a feasible method is provided for configuring platform device 20 to enable shared virtual address functionality. Specifically, the computing device 100 further stores a device tree, which is pre-configured with first support parameters. The data processing method further includes: In response to the startup operation, the processor 10 loads and parses the device tree to obtain the first support parameters; Based on the first support parameter, the platform device 20 is configured to enable the shared virtual address function.

[0041] A device tree is a data structure that describes hardware system components and their connections. It can describe various hardware devices in a tree structure. Device trees can separate hardware descriptions from kernel code. By modifying the device tree, the same kernel image can support different hardware configurations without needing to compile corresponding kernels for different hardware systems.

[0042] In this embodiment, the device tree can be modified to pre-configure the first support parameter, so that the processor 10 can obtain the first support parameter by parsing the device tree during the startup process, and then configure the platform device 20 to enable the corresponding shared virtual address function.

[0043] Specifically, in one embodiment, the first support parameter is used to establish the association between the platform device 20 and the IOMMU 30, specify the bit width of the process address identifier, and indicate support for DMA stall, wherein the DMA stall includes pausing the current DMA operation and triggering an I / O page fault event when an address translation failure is encountered.

[0044] In this embodiment, the first support parameter can establish an association between platform device 20 and IOMMU 30. For example, the SID of platform device 20 can be specified in IOMMU 30 to establish a mapping between IOMMU 30 and platform device 20. The first support parameter can also specify the bit width of the process address identifier, for example, it can be 20 bits. A 20-bit process address identifier can support 2... 20 =1,048,576 processes, which can meet the concurrent needs of a large number of processes in various applications. In addition, the first support parameter can also instruct the IOMMU30 to support DMA stall mode, so that when the IOMMU30 encounters a virtual address translation failure due to a page fault, it can pause the current DMA transaction, trigger IOPF, wait for page fault handling, and resume DMA transaction execution after the page fault handling is completed. By adding the first support parameter to the device tree, the following objectives can be achieved: 1. Inform the operating system of processor 10: Platform device 20 has shared virtual address functionality; please enable the corresponding software support; 2. Establish the hardware topology relationship between platform device 20 and IOMMU30, enabling them to work together; 3. Provide the necessary configuration information for the shared virtual address system (i.e., the relevant hardware implementing SVA functionality) in computing device 100, and activate advanced features such as IOPF. This achieves system-level support for SVA functionality.

[0045] In one implementation, at various hardware levels, to better support SVA functionality, the data processing method further includes: Load the driver for the platform device 20, register the character device of the platform device 20, enable the I / O page fault function and the shared virtual address function, wherein the character device is the unified device access interface of the user mode of the platform device 20; Load the driver for the IOMMU30, enable the I / O page fault function, and configure the bit width of the process address identifier.

[0046] In this embodiment, the drivers for platform device 20 and IOMMU 30 were also adjusted. By loading the driver for platform device 20, the character device of platform device 20 is registered, providing a unified device access interface for applications and meeting the needs of user-mode applications to access platform device 20, thus avoiding switching between user mode and kernel mode. Furthermore, the I / O page fault function and shared virtual address function of the character device are enabled by the driver for platform device 20. Simultaneously, by loading the driver for IOMMU 30, the I / O page fault function is enabled, and the bit width of the process address identifier is configured, laying the foundation for the cooperation between IOMMU 30 and platform device 20 to implement the SVA function.

[0047] To meet the requirement that user-mode applications directly issue virtual addresses to platform device 20 without switching kernel mode, one embodiment of this specification provides a feasible method for transmitting data processing requests to the driver of platform device 20. Specifically, the method for the target application to send a data processing request carrying a virtual address to the driver of target platform device 20 includes: The target application sends the virtual address to the character device of the target platform device 20; as mentioned above, the character device of the target platform device 20 is the user-mode unified device access interface of the DMA controller; The character device of the target platform device 20 sends a data processing request carrying the virtual address to the driver of the target platform device 20 according to the virtual address.

[0048] In this embodiment, the character device of the target platform device 20 and the driver of the target platform device 20 are used as a data transmission bridge between the target application and the platform device 20, which avoids the problem of switching between kernel mode and user mode for data transmission between the target application and the platform device 20, and improves data processing efficiency.

[0049] In one implementation, a feasible process for an IOMMU30 to perform a DMA operation is provided. Specifically, the IOMMU30 performs a DMA operation on the target data corresponding to the virtual address based on the target identifier, including: The IOMMU30 determines the process page table based on the target identifier, and performs address translation on the virtual address according to the determined process page table. If the address translation fails due to the physical page where the target data is located not being allocated (i.e., a page fault), a target interrupt is triggered, and DMA stall is executed, pausing the current DMA operation. The target interrupt is used to instruct the IOMMU30 driver to handle the target interrupt, call the page fault handling function, allocate a physical page for the virtual address, update the process page table, and return an interrupt handling completion notification to the IOMMU30 after the target interrupt is handled. In response to the interrupt handling completion notification, the IOMMU30 continues to execute the DMA operation, translates the virtual address according to the updated process page table to obtain the physical address corresponding to the virtual address, and sends a processing request carrying the physical address to the target controller. The processing request is used to instruct the target controller to perform corresponding operations on the target data, and returns response information to the target application after the execution is completed.

[0050] In this embodiment, after the DMA controller of platform device 20 transmits the virtual address and target identifier to IOMMU30, IOMMU30 implements address translation and data transfer operations under the SVA function based on the IOPF mechanism, achieving the goal of not requiring user mode and kernel mode switching throughout the DMA process, thus improving data processing efficiency.

[0051] In one specific embodiment, a feasible process is provided from preparation to implementation of the data processing method provided in this specification, and the hardware architecture for implementing the data processing method provided in this specification is as follows: Figure 3 As shown, the hardware architecture includes a CPU, platform bus, IOMMU30, platform device 20, and memory. Platform device 20 communicates based on the AXI4 protocol, while IOMMU30 communicates based on AXI5. Figure 3 In the hardware architecture shown, the IOMMU30 may include hardware such as a translation buffer unit and a translation control unit, and the platform device 20 may include hardware such as read control, write control, registers and SRAM (static random access memory). Figure 3 In the text, number 0 indicates the process of setting relevant registers in the DMA controller of the software platform device 20. These registers may include source address, destination address, length, SID and SSID registers, etc. Finally, the enable DMA register can be written to enable the DMA controller to start working. Figure 3 The feasible data flow process in the hardware architecture shown can include: by Figure 3 The sequence number indicated by the middle arrow represents the flow process as follows: The sequence 1->2->3->4->5->2->6->7->8->3->4->5, where "5->2->6" is the process of reading data into the local SRAM of the platform device 20, and "7->8->3->4->5" is the process of writing data to the destination address, can complete one data transfer operation.

[0052] Based on such Figure 3 The hardware architecture shown, and the process of preparing and implementing the data processing method provided in the embodiments of this specification, may include: Firstly, to enable the platform device 20 based on the AXI4 protocol to support the transmission of process address identifiers and device identifiers, the platform device 20 can be improved as follows: 1. Add a readable and writable channel register dma_cX_ssid to each DMA channel of the DMA controller of the platform device 20 for configuring process address identifiers; 2. The transmission output of the platform device 20 is a port based on the AXI4 protocol. Taking the process address identifier as an example, the user field can be widened and the process address identifier can be added to the user field. When the platform device 20 is connected to the IOMMU30, the IOMMU30 can parse the process address identifier from the user field.

[0053] In the data sent from the DMA controller of platform device 20 to IOMMU30, SID (device identifier, hereinafter referred to as SID) and SSID (process address identifier, hereinafter referred to as SSID) can come from the registers in the DMA controller. In the data fields exchanged between the DMA controller and IOMMU30, when the Substream field is 0, the Substream Valid field is invalid; when Substream is non-zero, it is valid.

[0054] The following table shows the source of each field signal and related explanations: The feasible improvement process for adding a channel register to the DMA controller of platform device 20 and transmitting information such as SSID through user fields is as follows: a. Create a register for configuring the SSID in the channel register file of the DMA controller of platform device 20: Specifically, the register SSID can be created in chal_reg_file.v (i.e., the channel register file of the DMA controller) in the design / rtl / dmac_test / rtl directory.

[0055] b. Set the offset address of the SSID storage location: For example, you can set the offset address of the SSID to: 12'h68; c. Reading and writing to the SSID register via the APB channel; d. Expand the user field of the DMA controller, and transmit information such as SSID, SID, and ATSt (Address Translation Status, used to indicate whether the virtual address has undergone PCIe ATS translation) to the IOMMU30 via AXI. In specific implementation, the user field of the DMA controller's AW channel can be expanded to 40 bits, and information such as SSID, SID, and ATSt can be transmitted through the AXI signal. When the DMA controller is connected to the IOMMU30, the IOMMU30 splits the user field to the AXI5 port.

[0056] Once the hardware preparation is complete, the software preparation can include: 1. Configure the platform device 20's support parameters for SVA features in the device tree (i.e., the first support parameter): Specifically, the fields IOMMU30s, pasid-num-bits, and dma-can-stall can be added to the device tree. These fields are used to establish the association between the platform device 20 and the IOMMU30, specify the bit width of the process address identifier, and indicate support for DMA stall, respectively.

[0057] The device tree after adding the above fields can be as follows: gdma@26080000 { indicates that the node name is gdma and its base address is: 0x26080000; `compatible = "vendor A, gdma";` is a compatibility identifier used to locate the corresponding driver. `reg =<0x00000000 0x26080000 0x00000000 0x00001000>;` defines the register's base address and memory size. clocks =<0x00008000 0x00008000>; is used to configure the clock and specify the clock source; interrupts =<0x00000000 0x00000011 0x00000004 0x00000000 0x000000120x00000004>; is used to configure interrupts; interrupt-names = "chan0", "chan1"; Interrupt names; iommus 30s =<&IOMMU30 0x000000ff>; This is used to establish the association between platform device 20 and IOMMU30; pasid-num-bits =; Specifies that the bit width of the process address identifier is 0x14 (i.e., 20 bits); dma-can-stall; Indicates that platform device 20 supports DMA stall; }; 2. Add the following process to the driver for the DMA controller of platform device 20. # Enable SVA when character device is opened, that is, enable the SVA feature when the character device of the DMA controller is opened, enabling the platform device 20 to share the virtual address space with the processor 10; IOMMU30_dev_enable_feature(dev, IOMMU30_DEV_FEAT_IOPF); enables the IOPF feature. IOMMU30_dev_enable_feature(dev, IOMMU30_DEV_FEAT_SVA); enables the SVA feature. # Bind process address space; struct IOMMU30_sva *handle = IOMMU30_sva_bind_device(dev, mm, NULL); / / Binds the IOMMU30 to the process's address space; pasid = IOMMU30_sva_get_pasid(handle); / / Get the SSID (i.e., PASID) from the bound handle; #set SID to SID reg; #set PASID to SSID reg; #Character device close unbind device SSID; IOMMU30_sva_unbind_device(handle); / / Unbind SSID when character device is turned off. #Unbind SVA and disable IOPF feature IOMMU30_dev_disable_feature(dev, IOMMU30_DEV_FEAT_IOPF); / / Disable IOPF; IOMMU30_dev_disable_feature(dev, IOMMU30_DEV_FEAT_SVA); / / Disable SVA.

[0058] After the hardware and software preparations are completed, the data processing methods provided in the embodiments of this manual can be implemented, such as... Figure 4 As shown, the hardware involved in this implementation process includes processor 10, IOMMU30, DMA controller, and memory controller. It also involves the application running on processor 10, the character device of the DMA controller, the driver for the DMA controller, and the driver for the IOMMU30. The process specifically includes: S1. Initialization process: During the initialization process of IOMMU30, processor 10 loads and runs the driver for IOMMU30, enables stall mode (stall_enabled), and sets the bit width of SSID (pasid-num-bits). During the initialization process of the DMA controller, the DMA controller driver is loaded, the character device is registered with the system (probe() registers the character device), and the IOPF and SVA features are enabled.

[0059] S2. Register Configuration: When an application opens (open()) the character device of the DMA controller, the character device creates a memory descriptor (mm_struct), binds platform device 20 to the process address space (IOMMU30_sva_bind_device), obtains the SSID (IOMMU30_sva_get_pasid), and sets the register (set ssid reg); The DMA controller driver completes the binding of the platform device 20 to the process address space (arm_smmu_sva_bind) and sets the registers in the DMA controller used to store the SID and SSID (set SID, SSID registers). The IOMMU30 driver updates the CD (Context Descriptor) corresponding to the SSID.

[0060] After the DMA controller completes the register settings, it returns a response result.

[0061] S3.DMA operation: When an application needs to perform a DMA operation, it obtains the virtual address of the data to be operated on using the malloc function (malloc src dst). These virtual addresses can include the source address (src) and destination address (dst) of the data. The application then transmits the virtual address and data length parameters to the character device of the DMA controller by calling the ioctl() function (ioctl() passes src, dst, and len parameters). The DMA controller's character device begins preparing the DMA transfer channel (dma_request_chan). During this process, there's no need to call functions like dma_map_single to map virtual addresses and lock memory, thus avoiding data copying or memory locking overhead. The DMA controller's character device requests the DMA controller's driver to initialize the DMA descriptor and directly sets the virtual address into the DMA controller's source and destination address registers (dmaengine_prep_dma_memcpy).

[0062] The DMA controller driver sends a DMA request carrying a virtual address (VA) to the DMA controller.

[0063] The DMA controller responds to the DMA request by passing parameters such as virtual address, SSID (VA+SSID), and SID to IOMMU30.

[0064] IOMMU30 translates virtual addresses based on parameters such as SSID and SID. If the address translation fails (Fault_TRANSLATION) due to an unallocated physical page (i.e., a page fault) where the target data is located, a stall is triggered, and a target interrupt (evt irq) is triggered and handled by the IOMMU30 driver.

[0065] When IOMMU30 responds to the target interrupt, it directly calls the page fault handling function of CPU memory management to allocate a physical page for the virtual address and update the process page table (the EVT interrupt handling function calls back IOMMU30_queue_iopf() and handle_mm_fault()). If the page fault has been resolved, it sends a page response (IOMMU30_page_response) to IOMMU30 and a recovery command (CMD_RESUME) to IOMMU30.

[0066] In response to the recovery command, IOMMU30 resumes the previously paused DMA transaction, continues address translation, and after obtaining the physical address (PA) corresponding to the virtual address, sends the physical address to the memory controller, which then performs the corresponding data processing based on the physical address.

[0067] After completing the data transfer, the memory controller reports an interrupt to the DMA controller driver. The DMA controller driver processes the interrupt information and updates the descriptor state.

[0068] The DMA controller's character device confirms completion through a user-mode query and returns a response message to the application. The application compares the data addresses to verify the correctness of the data processing. After verification, it closes the DMA controller's character device. The DMA controller's character device requests the DMA controller's driver to close the device. The DMA controller's driver unbinds the SVA and disables the IOPF feature.

[0069] Exemplary computing device 100 Another embodiment of this application also proposes a computing device 100, such as... Figure 1 As shown, the system includes: a processor 10, an IOMMU 30, and at least one platform device 20. The platform device 20 includes a direct memory access (DMA) controller. The DMA controller includes a pre-configured process address identifier and at least one device identifier. The process address identifier corresponds to a process, and the device identifier corresponds to the platform device. The processor 10 is configured to run the target application and the driver for the platform device 20. The processor 10 is further configured to send a data processing request carrying a virtual address to the driver of the target platform device 20 based on the running target application, the data processing request being used to instruct the target platform device 20 to configure the virtual address in the DMA controller of the target platform device 20; The DMA controller of the target platform device 20 is configured to send a DMA request carrying a target identifier and the virtual address to the IOMMU 30. The DMA request is used to instruct the IOMMU 30 to perform a DMA operation on the target data corresponding to the virtual address. The target identifier includes a target device identifier and a process address identifier describing the target process. The target process is the process in the target application that initiates the data processing request. The target device identifier is used to describe the target platform device.

[0070] Optionally, the DMA controller further includes multiple registers, each corresponding to a multiple DMA channel, and each register is used to configure the process address identifier.

[0071] Optionally, the platform device 20 includes at least one of a compression engine, a decompression engine, and a cryptographic engine.

[0072] The computing device 100 provided in the embodiments of this specification can implement the data processing method described in any of the above embodiments. During the data processing, the target application directly sends a data processing request carrying a virtual address to the driver of the target platform device 20. The request instructs the target platform device 20 to configure the virtual address in the DMA controller of the target platform device 20. The DMA controller sends a DMA request carrying a target identifier and the virtual address to the IOMMU 30. The DMA request is used to instruct the IOMMU 30 to perform a DMA operation on the target data corresponding to the virtual address according to the target identifier. Thus, during the entire DMA operation, since the DMA controller is pre-configured with multiple process address identifiers and at least one device identifier, and the process address identifier corresponds to the process and the device identifier corresponds to the platform device, the process address identifier is used to identify the context and address space of the corresponding process. This allows the IOMMU30 to translate the virtual address within the address space of the process corresponding to the target identifier, thereby completing the DMA operation. Throughout the process, the processor 10, the DMA controller, and the IOMMU30 use a shared set of processor virtual addresses during their interaction, without the need to build additional page tables for the IOMMU, and also avoids data transfer from kernel mode to user mode, thereby improving data processing efficiency.

[0073] For feasible limitations on each step of the data processing method, please refer to the relevant descriptions above; this manual will not repeat them here.

[0074] Exemplary computer program products and storage media In addition to the methods and devices described above, the data processing methods provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the data processing methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0075] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0076] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0077] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the data processing methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0078] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A data processing method, characterized in that, The method is applied to a computing device, which includes a processor, an input / output memory management unit (IOMMU), and at least one platform device. The processor is used to run a target application and a driver for the platform device. The platform device includes a direct memory access (DMA) controller, which includes a plurality of pre-configured process address identifiers and at least one device identifier. The process address identifiers correspond to processes, and the device identifiers correspond to the platform device. The data processing method includes: The target application sends a data processing request carrying a virtual address to the driver of the target platform device. The data processing request is used to instruct the target platform device to configure the virtual address in the DMA controller of the target platform device. The DMA controller of the target platform device sends a DMA request carrying a target identifier and the virtual address to the IOMMU. The DMA request is used to instruct the IOMMU to perform a DMA operation on the target data corresponding to the virtual address according to the target identifier. The target identifier includes a target device identifier and a process address identifier describing the target process. The target process is the process that initiates the data processing request in the target application. The target device identifier is used to describe the target platform device.

2. The method according to claim 1, characterized in that, The DMA controller communicates based on a first bus protocol, which lacks the field of the target identifier. The process by which the DMA controller of the target platform device transmits the target identifier to the IOMMU includes: The DMA controller of the target platform device writes the target identifier into the target field and transmits it to the IOMMU through the signal line corresponding to the target field, so as to instruct the IOMMU to parse the target identifier from the target field, wherein the target field is an extended field in the first bus protocol.

3. The method according to claim 2, characterized in that, The first bus protocol includes the Advanced Extensible Interface (AXI4) protocol, and the target field is a user field.

4. The method according to claim 1, characterized in that, The computing device also stores a device tree, which is pre-configured with a first support parameter. The data processing method further includes: In response to the startup operation, the processor loads and parses the device tree to obtain the first support parameters; Based on the first support parameter, configure the platform device to enable the shared virtual address function.

5. The method according to claim 4, characterized in that, The first support parameter is used to establish the association between the platform device and the IOMMU, specify the bit width of the process address identifier, and indicate support for DMA stall. The DMA stall includes pausing the current DMA operation and triggering an I / O page fault event when an address translation failure is encountered.

6. The method according to claim 1, characterized in that, Also includes: Load the driver for the platform device, register the character device for the platform device, enable I / O page fault function and shared virtual address function, wherein the character device is the unified device access interface for the user mode of the platform device; Load the IOMMU driver, enable I / O page fault functionality, and configure the bit width of the process address identifier.

7. The method according to claim 1, characterized in that, The target application sends a data processing request carrying a virtual address to the driver of the target platform device, including: The target application sends the virtual address to the character device of the target platform device; the character device of the target platform device is the user-mode unified device access interface of the DMA controller; The character device of the target platform device sends a data processing request carrying the virtual address to the driver of the target platform device based on the virtual address.

8. The method according to any one of claims 1 to 7, characterized in that, The IOMMU performs a DMA operation on the target data corresponding to the virtual address based on the target identifier, including: The IOMMU determines the process page table based on the target identifier, and performs address translation on the virtual address according to the determined process page table. If the address translation fails due to the physical page containing the target data not being allocated, a target interrupt is triggered, and DMA stall is executed, pausing the current DMA operation. The target interrupt is used to instruct the IOMMU driver to handle the target interrupt, call the page fault handling function, allocate a physical page for the virtual address, update the process page table, and return an interrupt handling completion notification to the IOMMU after the target interrupt is handled. In response to the interrupt handling completion notification, the IOMMU continues to execute the DMA operation, translates the virtual address according to the updated process page table to obtain the physical address corresponding to the virtual address, and sends a processing request carrying the physical address to the target controller. The processing request is used to instruct the target controller to perform corresponding operations on the target data, and returns response information to the target application after the execution is completed.

9. A computing device, characterized in that, include: The processor, IOMMU, and at least one platform device, the platform device including a direct memory access (DMA) controller, the DMA controller including a plurality of pre-configured process address identifiers and at least one device identifier, the process address identifiers corresponding to processes, and the device identifiers corresponding to the platform device, wherein the processor is configured to run a target application and a driver for the platform device; The processor is further configured to: send a data processing request carrying a virtual address to the driver of the target platform device based on the running target application, the data processing request being used to instruct the target platform device to configure the virtual address in the DMA controller of the target platform device; The DMA controller of the target platform device sends a DMA request carrying a target identifier and the virtual address to the IOMMU. The DMA request is used to instruct the IOMMU to perform a DMA operation on the target data corresponding to the virtual address according to the target identifier. The target identifier includes a target device identifier and a process address identifier describing the target process. The target process is the process that initiates the data processing request in the target application. The target device identifier is used to describe the target platform device.

10. The computing device according to claim 9, characterized in that, The DMA controller also includes multiple registers, each corresponding to a DMA channel, and each register is used to configure the process address identifier.

11. The computing device according to claim 9, characterized in that, The platform device includes at least one of a compression engine, a decompression engine, and a cryptographic engine.

12. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the data processing method as described in any one of claims 1 to 8.

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