Ultrasonic fingerprint readout circuit and ultrasonic fingerprint chip

Abstract

The present disclosure provides an ultrasonic fingerprint readout circuit and an ultrasonic fingerprint chip, and relates to the technical field of semiconductors. The ultrasonic fingerprint readout circuit comprises: a detection module configured to convert ultrasonic wave echoes into periodic echo voltages; a pixel integration module comprising a first switch assembly and a pixel integration operational amplifier; a scanning control module connected with the first switch assembly, configured to configure the pixel integration operational amplifier to periodically integrate the echo voltages in a first scanning period and a second scanning period, and correspondingly output continuous echo integration voltages; and a sampling module configured to sample the echo integration voltages multiple times in the first scanning period and the second scanning period respectively, to obtain multiple sampling voltages, and the multiple sampling voltages are configured to perform differential operation to offset the offset error of the pixel integration operational amplifier, to obtain a target signal. Through the technical scheme of the present disclosure, the fingerprint readout precision is improved while reducing the complexity of the circuit design.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an ultrasonic fingerprint reading circuit and an ultrasonic fingerprint chip. Background Technology

[0002] Due to its strong anti-interference capabilities, ultrasonic fingerprint chips have been widely used in various mobile terminals. The ultrasonic fingerprint chip mainly uses an ultrasonic fingerprint readout circuit to convert ultrasonic echoes into electrical signals and further output signals that characterize fingerprint features. The ultrasonic fingerprint readout circuit includes a pixel integration operational amplifier. Since the pixel integration operational amplifier inevitably has an offset voltage, and the offset voltage will produce a fixed error in each integration, and this error will accumulate with the increase of integration times, thus affecting the signal accuracy.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide an ultrasonic fingerprint reading circuit and an ultrasonic fingerprint chip, which at least to some extent overcomes the problem in the related art that the accuracy of ultrasonic fingerprint chips needs to be improved due to the continuous accumulation of offset errors of pixel integral operational amplifiers.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, an ultrasonic fingerprint reading circuit is provided, comprising: a detection module configured to capture ultrasonic echoes and convert the ultrasonic echoes into periodic echo voltages; a pixel integration module electrically connected to the detection module, including a first switching component and a pixel integration operational amplifier; a scan control module connected to the first switching component, configured to sequentially send a first set of switch control signals and a second set of switch control signals to the first switching component, wherein the first set of switch control signals controls the first switching component to perform an on / off action corresponding to a first scan period, and the second set of switch control signals controls the first switching component to perform an on / off action corresponding to a second scan period, the pixel integration operational amplifier being configured to periodically integrate the echo voltages during the first scan period and the second scan period, and correspondingly output a continuous echo integration voltage; and a sampling module configured to sample the echo integration voltages multiple times during the first scan period and the second scan period to obtain multiple sampled voltages, the multiple sampled voltages being configured to perform differential operations to cancel the offset error of the pixel integration operational amplifier to obtain a target signal, the target signal being used for ultrasonic fingerprint reading.

[0007] In one embodiment of this disclosure, the first scanning period and the second scanning period respectively include the isolation period of the detection module, the reset period of the pixel integration amplifier, the first sampling period, the integration period, and the second sampling period, wherein the echo integration voltage is sampled during the first sampling period and the second sampling period of the first scanning period, and during the first sampling period and the second sampling period of the second scanning period, respectively, to obtain the first sampling voltage, the second sampling voltage, the third sampling voltage, and the fourth sampling voltage.

[0008] In one embodiment of this disclosure, the integration directions during the first scan period and the second scan period are opposite.

[0009] In one embodiment of this disclosure, during the first scanning period, the pixel integrating operational amplifier integrates the trough-to-peak phase of the echo voltage in each echo cycle; during the second scanning period, the pixel integrating operational amplifier integrates the peak-to-trough phase of the echo voltage in each echo cycle.

[0010] In one embodiment of this disclosure, the sampling module performs differential operations, including: performing differential operations on the second sampling voltage and the first sampling voltage to obtain a first differential value; performing differential operations on the fourth sampling voltage and the third sampling voltage to obtain a second differential value; and performing offset error cancellation operations based on the first differential value and the second differential value to obtain a target signal.

[0011] In one embodiment of this disclosure, performing an offset error cancellation operation based on the first difference value and the second difference value includes: determining the target signal based on the difference between the second difference value and the first difference value.

[0012] In one embodiment of this disclosure, the system further includes: a chopper control module, comprising a chopper switch assembly connected to the pixel integral operational amplifier, and a chopper controller that sends a chopper control signal to the chopper switch assembly, wherein the chopper controller switches the level of the chopper control signal between the first scan period and the second scan period so that the polarity of the offset voltage of the pixel integral operational amplifier is opposite between the first scan period and the second scan period, and the switching frequency of the chopper control signal is consistent with the switching frequency of the scan period.

[0013] In one embodiment of this disclosure, the pixel integrating operational amplifier includes a first-stage amplification unit and a second-stage amplification unit. The chopper switch assembly includes: a first chopper switch disposed between the first switch assembly and the first-stage amplification unit, used to connect the first switch assembly to different input terminals of the first-stage amplification unit during the first scan period and the second scan period based on the chopper control signal; and a second chopper switch disposed between the first-stage amplification unit and the second-stage amplification unit, used to enable the first-stage amplification unit and the second-stage amplification unit to have different connection paths during the first scan period and the second scan period based on the chopper control signal.

[0014] In one embodiment of this disclosure, the first-stage amplification unit includes a first MOS transistor and a second MOS transistor connected to a common source, a third MOS transistor connected to a common drain of the first MOS transistor, and a fourth MOS transistor connected to a common gate of the third MOS transistor. The fourth MOS transistor is connected to the second MOS transistor via a common drain. The gate of the first MOS transistor serves as the first input terminal of the pixel integrating operational amplifier, the gate of the second MOS transistor serves as the second input terminal of the pixel integrating operational amplifier, the common drain connection point of the first MOS transistor and the third MOS transistor serves as the first differential signal point, the common drain connection point of the second MOS transistor and the fourth MOS transistor serves as the second differential signal point, and the common gate connection point of the third MOS transistor and the fourth MOS transistor serves as the bias point. The second-stage amplification unit includes a fifth MOS transistor and a sixth MOS transistor connected in series. The pixel integrating operational amplifier further includes an LC series circuit, one end of which serves as an intermediate output point, and the other end is connected to the connection point of the fifth MOS transistor and the sixth MOS transistor, with the connection point serving as the operational amplifier output terminal of the pixel integrating operational amplifier.

[0015] In one embodiment of this disclosure, the input terminal of the first chopper switch is connected to the first switching assembly and the first reference voltage access point, respectively, and the output terminal of the first chopper switch is connected to the first input terminal and the second input terminal of the pixel integration operational amplifier, respectively; the input terminal of the second chopper switch is connected to the first differential signal point and the second differential signal point, respectively, and the output terminal of the second chopper switch is connected to the bias point and the intermediate output point, respectively.

[0016] In one embodiment of this disclosure, the first scan period and the second scan period have the same integration direction.

[0017] In one embodiment of this disclosure, during the first scan period and the second scan period, the pixel integrating operational amplifier integrates the peak-to-trough phase of the echo voltage in each echo cycle.

[0018] In one embodiment of this disclosure, performing an offset error cancellation operation based on the first difference value and the second difference value includes: determining the target signal based on the sum of the second difference value and the first difference value.

[0019] In one embodiment of this disclosure, the sampling module includes: an operational amplifier with a third input terminal and a fourth input terminal; a first sampling capacitor and a second sampling capacitor, one end of the first sampling capacitor being connected to the third input terminal and one end of the second sampling capacitor being connected to the fourth input terminal; a sampling clock component and an amplification clock component, the sampling clock component including a first sampling clock switch and a second sampling clock switch, the amplification clock component including a first amplification clock switch and a second amplification clock switch, both the first sampling clock switch and the first amplification clock switch being connected to the other end of the first sampling capacitor, and both the second sampling clock switch and the second amplification clock switch being connected to the other end of the second sampling capacitor, wherein, during the second scanning period, if the sampling clock component is closed and the amplification clock component is open, the first sampling capacitor is connected to the fourth sampling voltage, the second sampling capacitor is connected to the third sampling voltage, the sampling clock component is open and the amplification clock component is closed, and the operational amplifier outputs the second differential value; if the sampling clock component is closed and the amplification clock component is open, the first sampling capacitor is connected to the third sampling voltage, the second sampling capacitor is connected to the fourth sampling voltage, the sampling clock component is open and the amplification clock component is closed, and the operational amplifier outputs the inverted second differential value.

[0020] In one embodiment of this disclosure, the first switch assembly includes: a first switch, one end of which is connected to a pixel plate in the detection module, and the other end of which is grounded; a second switch, one end of which is connected to the pixel plate, and the other end of which is connected to a second reference voltage; a third switch disposed between the pixel plate and the pixel integrating operational amplifier; and a fourth switch disposed in parallel with the pixel integrating operational amplifier. During the isolation period, the first switch closes; during the first sub-period of the reset period, the first switch opens; the fourth switch closes; during the second sub-period of the reset period, the second switch closes; during the first sampling period, the fourth switch opens; during the integration period, the second and third switches alternately open and close; during the second sampling period, the second switch closes and the third switch opens.

[0021] In one embodiment of this disclosure, it further includes: an analog-to-digital conversion module connected to the sampling module, used to convert the target signal into an echo digital signal, so as to read out the ultrasonic fingerprint based on the echo digital signal.

[0022] According to another aspect of this disclosure, an ultrasonic fingerprint chip is provided, comprising: the ultrasonic fingerprint reading circuit provided in the above embodiments.

[0023] The voltage conversion scheme provided in the embodiments of this disclosure converts ultrasonic echoes into periodic echo voltages through a detection module. Then, under the timing control of the scanning control module, the pixel integration module periodically integrates the echo voltages in two scanning periods, outputting a continuous echo integrated voltage. The sampling module samples multiple sets of voltages in each of the two scanning periods. Finally, differential operations are used to cancel the offset error of the pixel integration operational amplifier, resulting in a target signal that can distinguish fingerprint ridges and valleys. Since the circuit environment and operational amplifier state can be kept consistent in the first and second scanning periods, the error introduced by the offset voltage of the pixel integration operational amplifier in the two scans is the same. By performing differential operations on the sampling results of the two scans, the offset error can be canceled, thus eliminating the need for real-time reversal of the offset voltage polarity through high-frequency chopping. This also helps to reduce the stringent requirements on the bandwidth and response speed of the pixel integration operational amplifier, thereby improving fingerprint reading accuracy while reducing circuit design complexity.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 A schematic diagram of an ultrasonic fingerprint reading circuit in the related art is shown;

[0027] Figure 2 This diagram illustrates the timing of an ultrasonic fingerprint reading circuit operating according to an embodiment of the present disclosure.

[0028] Figure 3 A schematic block diagram of an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic diagram of an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure is shown;

[0030] Figure 5 Show Figure 4 A schematic diagram of the working timing of the ultrasonic fingerprint reading circuit;

[0031] Figure 6 A schematic diagram of another ultrasonic fingerprint reading circuit according to an embodiment of this disclosure is shown;

[0032] Figure 7A A signal schematic diagram of a chopper switch according to an embodiment of the present disclosure is shown;

[0033] Figure 7B A schematic diagram of the structure of a chopper switch according to an embodiment of the present disclosure is shown;

[0034] Figure 8 A schematic diagram of a pixel integral operational amplifier according to an embodiment of the present disclosure is shown;

[0035] Figure 9 A schematic diagram of a first chopper switch in an embodiment of this disclosure is shown;

[0036] Figure 10 A schematic diagram of a second chopper switch in an embodiment of this disclosure is shown;

[0037] Figure 11 Show Figure 6 A schematic diagram of the working timing of the ultrasonic fingerprint reading circuit;

[0038] Figure 12 A schematic circuit diagram of a sampling module according to an embodiment of this disclosure is shown. Detailed Implementation

[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0040] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0041] An ultrasonic fingerprint chip is a semiconductor chip that receives ultrasonic echoes through a detection module, converts them into electrical signals, and then processes these signals through a readout circuit to identify fingerprint ridge features, achieving high-precision biometric identification. In related technologies, an ultrasonic fingerprint chip typically contains many detection units, each integrating a piezoelectric sensing capacitor. ,like Figure 1 The ultrasonic fingerprint reading circuit shown may include a piezoelectric sensing capacitor 102, a pixel module 104, a programmable gain amplifier (PGA) 106, and an analog-to-digital converter (ADC) 108. The piezoelectric sensing capacitor 102 includes an upper electrode 1022, a lower electrode (i.e., the top metal electrode of the detection unit) 1024, and a piezoelectric layer 1026 between the upper and lower electrodes 1022 and 1024. When a finger is pressed against the surface of the ultrasonic fingerprint chip, a driving voltage applied to the upper electrode 1022 drives the piezoelectric layer 1026 to generate an ultrasonic wave emission signal. When the echo signal of the ultrasonic wave reaches the piezoelectric layer 1026, the voltage on the lower electrode 1024 changes and is detected by the reading circuit, i.e., the echo voltage is detected. By judging the echo voltage The amplitude is used to determine whether it is a valley or a ridge, thus completing the fingerprint recognition operation. Additionally... Parasitic capacitance in pixel module 104 It is the reset voltage of pixel module 104. It is the reference voltage of the pixel operational amplifier pxl_op. and The relationship can be: = =1 / 2 power supply voltage.

[0042] Figure 2 It shows Figure 1 The ultrasonic fingerprint reading circuit shown has one possible operating timing, such as... Figure 2 As shown, when the high-voltage coding circuit of the ultrasonic fingerprint chip ( Figure 1 When working (not shown), that is, during the t0 period, S1 is pulled high, which pulls PXL low. After the coding is completed, the t1 period begins, S1 is set low, S4 is pulled high, and pxl_op is reset. Then, the t2 period begins, S2 is pulled high, and PXL is also reset to Vref1. At this point, both pxl_op and PXL have completed their resets. Then S4 is pulled low, and the pxl_op reset ends.

[0043] At some point during time period t3, the PGA samples px_out for the first time to obtain vs1. Then, during time period t4, S2 is pulled low and S3 is pulled high. The PIXEL circuit integrates V1 for the first time, from the peak to the trough. After integration, S3 is pulled low and S2 is pulled high, PXL is reset. After the reset, S2 is pulled low and S3 is pulled high, and the PIXEL circuit integrates V1 for the second time, from the peak to the trough. This integration process is repeated multiple times (e.g., ...). Figure 2 As shown in the figure (integration 5 times), we can see that time period t4 is the integration time of the PIXEL circuit. After the 5 integrations are completed, time period t5 begins. S3 is pulled low and S2 is pulled high. At some point in time period t5, the PGA samples px_out for the second time to obtain vs2. The output of the PGA is gain. (vs2-vs1), where gain is the known gain of the PGA, can be determined by quantizing the output of the PGA using the ADC. This allows us to judge the fingerprint status above the detection unit.

[0044] based on Figure 1 and Figure 2 It can be seen that the inherent offset voltage Vos of the pixel operational amplifier pxl_op will be transmitted through the circuit's parasitic capacitance. The coupling with the feedback capacitor Cfb generates an error voltage of Vos×Cpar / Cfb at the output px_out after each integration. This error voltage accumulates continuously with the number of integrations. To solve the offset error problem, the offset polarity needs to be reversed in real time during each integration process. Since switching occurs with each integration, high-frequency chopping is required. Consequently, the circuit structure needs to be adapted to high-frequency scenarios, which increases the design complexity of the pixel operational amplifier.

[0045] Therefore, there is an urgent need for an ultrasonic fingerprint readout circuit that can suppress the offset voltage of the operational amplifier pxl_op without having an overly complex structure.

[0046] like Figure 3 As shown, an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure includes:

[0047] The detection module 302 is configured to capture ultrasonic echoes and convert the ultrasonic echoes into periodic echo voltages.

[0048] like Figure 4 As shown, in some embodiments, the detection module 302 includes pixel piezoelectric capacitors. Pixel piezoelectric capacitor It includes a pixel electrode plate 3022, a piezoelectric electrode plate 3024, and a piezoelectric layer 3026 disposed between the piezoelectric electrode plate and the pixel electrode plate.

[0049] Among them, the piezoelectric electrode plate refers to the electrode plate covering the piezoelectric layer.

[0050] In some embodiments, the piezoelectric layer may be a piezoelectric material layer such as PVDF (Polyvinylidene Fluoride) or PZT (Lead Zirconate Titanate).

[0051] In some embodiments, electrode plates are respectively provided on both sides of the piezoelectric layer to realize the transmission of ultrasonic waves and the reception and conduction of echo signals: one side is the first electrode plate, i.e., the piezoelectric electrode plate, which adopts a thin metal layer structure covering the entire surface of the piezoelectric layer, preferably made of silver (Ag). The electrode shape is not limited and can be set as a structure covering the entire surface of the piezoelectric layer or a discrete electrode structure; the other side is the second electrode plate, i.e., the pixel electrode plate, which adopts a metal electrode plate design and can be fabricated based on the top metal layer of the chip. Its electrode shape is also not limited, and can be a full-surface electrode matching the first electrode plate or a discrete electrode adapted to the fingerprint detection resolution. During operation, in the ultrasonic wave transmission stage, a driving voltage difference is formed between the first electrode plate and the second electrode plate to excite the piezoelectric layer. Specifically, various driving methods can be adopted: the first electrode plate can be connected to a high-voltage driving signal, and the second electrode plate can be grounded or connected to a low voltage inside the chip; or the second electrode plate can be connected to an inverted high-voltage driving signal, and the first electrode plate can be grounded or connected to a low voltage inside the chip. The method of applying the driving voltage is not limited. In the echo reception stage, the second electrode plate is connected to the subsequent readout circuit to conduct the echo induced voltage.

[0052] In some embodiments, the detection module 302 may also be a symmetrical structure consisting of a double piezoelectric layer combined with an intermediate electrode.

[0053] In some embodiments, after the ultrasonic signal emitted by the fingerprint recognition chip comes into contact with the fingerprint area, the reflection energy and penetration depth of the echo signal are significantly different due to the physical structure differences between the fingerprint ridges and valleys. Specifically, the fingerprint ridges are in direct contact with the chip surface, resulting in strong ultrasonic reflection energy, while the fingerprint valleys form an air gap with the chip surface, resulting in weak ultrasonic reflection energy. This energy difference drives the piezoelectric layer to generate mechanical vibration of a corresponding amplitude. The detection module uses the piezoelectric effect to convert the mechanical vibration into an echo voltage that corresponds one-to-one with the echo energy intensity.

[0054] The pixel integration module 304 is electrically connected to the detection module 302 and includes a first switching component and a pixel integration operational amplifier.

[0055] In some embodiments, the pixel integration module mainly includes a pixel integration operational amplifier and an integration capacitor connected in parallel with the pixel integration operational amplifier. By controlling the on / off state of the first switching component, a connection path between the echo voltage and the integration capacitor is established. When the connection path is opened based on the on / off operation of the first switching component, the periodic echo voltage output by the detection module is input to the input terminal of the pixel integration operational amplifier. The operational amplifier performs integration operation on the echo voltage based on the feedback capacitor, converting the periodic voltage signal into a continuously changing echo integrated voltage, thereby realizing the cumulative amplification of the signal.

[0056] The scanning control module 306 is connected to the first switching component and is used to send a first set of switching control signals and a second set of switching control signals to the first switching component in sequence. The first set of switching control signals is used to control the first switching component to perform the on / off action corresponding to the first scanning period, and the second set of switching control signals is used to control the first switching component to perform the on / off action corresponding to the second scanning period. The pixel integration operational amplifier is configured to periodically integrate the echo voltage during the first scanning period and the second scanning period, and output a continuous echo integrated voltage accordingly.

[0057] In some embodiments, the scanning control module adopts time-based control logic. First, it outputs a first set of switch control signals to control the first switch component to be turned on or off according to a preset timing sequence, so that the pixel integration module enters the first scanning period and completes the first round of periodic integration of the echo voltage. After the first scanning period ends, it outputs a second set of switch control signals to switch the on / off state of the first switch component, so that the pixel integration module enters the second scanning period and performs integration operation. Through the timing switching of the two sets of control signals, two independent and co-originating scanning integration processes are realized.

[0058] The sampling module 308 is used to sample the echo integral voltage multiple times during the first scanning period and the second scanning period respectively to obtain multiple sampled voltages. The multiple sampled voltages are configured to perform differential operations to cancel the offset error of the pixel integral operational amplifier to obtain the target signal, which is used for ultrasonic fingerprint reading.

[0059] In one embodiment of this disclosure, it further includes: an analog-to-digital conversion module 310, electrically connected to the sampling module 308, for converting the target signal into an echo digital signal, the echo digital signal of which can be further processed to obtain a fingerprint signal.

[0060] In some embodiments, the functionality of the module can be implemented using a programmable gain amplifier (PGA).

[0061] In some embodiments, the sampling module performs two sampling operations during the first scanning period, one after the pixel integrating operational amplifier is reset and the other after the integration operation is completed, to obtain two sets of reference sampling voltages and integrated sampling voltages. During the second scanning period, the same sampling operation is performed to obtain two more sets of sampling voltages. The sampling module transmits the collected voltage signals to the subsequent signal processing unit. By performing differential operations on the sampling results of the two scans, the operational amplifier offset error that exists in both scans is canceled out, and only the effective signal related to the ultrasonic echo energy is retained. Finally, the target signal that can characterize the fingerprint valley ridge features is output.

[0062] In this embodiment, the ultrasonic echo is converted into a periodic echo voltage by the detection module. Then, the pixel integration module, under the timing control of the scanning control module, periodically integrates the echo voltage in two scanning periods, outputting a continuous echo integrated voltage. The sampling module samples multiple sets of voltages in the two scanning periods. Finally, the offset error of the pixel integration operational amplifier is canceled by differential operation to obtain the target signal that can distinguish the fingerprint ridges. Since the circuit environment and operational amplifier state can be kept consistent in the first and second scanning periods, the error introduced by the offset voltage of the pixel integration operational amplifier in the two scans is the same. By performing differential operation on the sampling results of the two scans, the offset error can be canceled, so that the offset voltage polarity can be reversed in real time by high-frequency chopping. This also helps to reduce the stringent requirements on the bandwidth and response speed of the pixel integration operational amplifier. In this way, the fingerprint reading accuracy can be improved while reducing the complexity of circuit design, achieving a low-complexity, high-precision ultrasonic fingerprint reading effect.

[0063] like Figure 4 As shown in one embodiment of this disclosure, the first switching component includes:

[0064] The first switch S1 has one end connected to the pixel plate in the detection module and the other end grounded; the second switch S2 has one end connected to the pixel plate and the other end connected to the second reference voltage; the third switch S3 is located between the pixel plate and the pixel integrating operational amplifier; the fourth switch S4 is connected in parallel with the pixel integrating operational amplifier. During the isolation period, the first switch closes; during the first sub-period of the reset period, the first switch opens; the fourth switch closes; during the second sub-period of the reset period, the second switch closes; during the first sampling period, the fourth switch opens; during the integration period, the second and third switches alternately open and close; during the second sampling period, the second switch closes and the third switch opens.

[0065] like Figure 5As shown, in one embodiment of this disclosure, the first scanning period and the second scanning period respectively include the isolation period t0 of the detection module, the reset period (t1+t2) of the pixel integration amplifier, the first sampling period t3, the integration period t4, and the second sampling period t5. The echo integration voltage is sampled during the first and second sampling periods of the first scanning period and the first and second sampling periods of the second scanning period, respectively, to obtain the first sampling voltage VA, the second sampling voltage VB, the third sampling voltage VC, and the fourth sampling voltage VD.

[0066] In some embodiments, the first switching component is made to correspond to different switching states during the first scanning period based on the first set of switching control signals, thereby realizing different functions at different stages, including:

[0067] During the isolation period t0, S1 is turned on, and S2, S3 and S4 are turned off. Based on the first set of switch control signals, the connection between the disconnection detection module and the pixel integration module is executed to prevent external signal interference.

[0068] During the reset period (t1+t2), the input / output terminals of the pixel integration op-amp are pulled to the reference voltage to complete the op-amp reset. During the t1 period, S1 is open, S4 is closed, and S2 and S3 remain open. During the t2 period, S2 switches to closed.

[0069] During the first sampling period t3, S4 switches to disconnect. After the reset is completed, the sampling module collects the voltage at the px_out terminal to obtain the first sampling voltage VA.

[0070] During the integration period t4, S2 and S3 alternately open and close, and the pixel integration operational amplifier performs periodic integration of the echo voltage V1 from peak to trough. The px_out voltage changes gradually with the integration.

[0071] During the second sampling period t5, after integration is completed, S2 remains closed and S3 remains open. The sampling module acquires the px_out voltage to obtain the second sampling voltage VB.

[0072] During time period t6, the second S2 switches to disconnect, so time period t6 can be regarded as the period between the first scan period and the second scan period.

[0073] In some embodiments, the first switching component is made to correspond to different switching states during the second scanning period based on the second set of switching control signals. The switching control of the first switching component during the second scanning period is the same as that during the first scanning period, and different functions are implemented at different stages, including:

[0074] Repeat the isolation period t0 and the reset period (t1+t2) operation, and collect the third sampling voltage VC in the first sampling period t3.

[0075] Integration period t4: The pixel integrating operational amplifier performs periodic integration of the echo voltage V1 from trough to peak, which is opposite to the integration direction of the first scanning period.

[0076] The second sampling period t5: The integrated px_out voltage is collected to obtain the fourth sampling voltage VD.

[0077] Finally, the PGA performs a differential operation (VB-VA) - (VD-VC) on VA, VB, VC, and VD to output the target signal.

[0078] In one embodiment of this disclosure, the integration directions during the first and second scanning periods are opposite.

[0079] In this embodiment, by using the logic of two-scan reverse integration and four-sampling differential, each operation is decomposed into a specific time period, namely t0-t6. Combined with the timing control of the first switching component, the detection, reset, sampling and integration are decoupled, preventing signal crosstalk between different stages. The calculation result of (VB-VA)-(VD-VC)=VB-VD not only filters the reset noise, namely VA and VC, but also retains the amplitude difference of the echo voltage. Thus, the offset error of the pixel integration amplifier can be offset by using the reverse characteristic of the integration direction and the differential operation, without relying on high-frequency chopping to solve the offset problem.

[0080] In one embodiment of this disclosure, during a first scanning period, the pixel integrating operational amplifier integrates the trough-to-peak phase of the echo voltage in each echo cycle; during a second scanning period, the pixel integrating operational amplifier integrates the peak-to-trough phase of the echo voltage in each echo cycle.

[0081] In this embodiment, since the echo voltage is a periodic fluctuating signal, the voltage rise segment from the trough to the peak in each cycle and the voltage fall segment from the peak to the trough. By integrating over multiple cycles, the integration results of the two scans can show the same amplitude but opposite polarity. Combined with subsequent differential operations, errors can be canceled out, and the effective signals can be superimposed and enhanced. This not only increases the amplitude of the target signal and enhances the distinguishability of fingerprint ridge and valley features, but also achieves the cancellation of misalignment errors through differential operations.

[0082] In one embodiment of this disclosure, the sampling module performs differential operations to cancel the offset error of the pixel integral operational amplifier, including:

[0083] Perform a differential operation on the second sampling voltage VB and the first sampling voltage VA to obtain the first differential value; perform a differential operation on the fourth sampling voltage VD and the third sampling voltage VC to obtain the second differential value; perform an offset error cancellation operation based on the first and second differential values ​​to obtain the target signal.

[0084] In this embodiment, the first sampling voltage VA and the third sampling voltage VC can be understood as the reference voltage including the operational amplifier offset error after the operational amplifier is reset, and the second sampling voltage VB and the fourth sampling voltage VD can be understood as the signal voltage including the effective signal and offset error after integration. The voltage after integration and the voltage after reset within the same scan are first differentially divided to separate the effective signal and offset error of a single scan. By splitting the differential, the common-mode noise in the reset stage is first filtered out, and the effective signal and offset error of a single scan are integrated into a single differential value, which makes the subsequent offset cancellation operation simpler and more feasible.

[0085] In one embodiment of this disclosure, performing an offset error cancellation operation based on a first difference value and a second difference value includes: determining a target signal based on the difference between the second difference value and the first difference value.

[0086] In some embodiments, PXL is scanned twice. The first scan integrates from peak to trough, and the second scan integrates from trough to peak. A total of four samples are taken during the scan, resulting in four sampled voltages. One sample is taken after the pxl_op pixel integration op-amp resets during the first scan period (denoted as VA). Another sample is taken after integration in the first scan (denoted as VB). Another sample is taken after the pxl_op resets during the second scan period (denoted as VC). Finally, another sample is taken after integration in the second scan (denoted as VD). The difference between the two scans is calculated on the PGA: (VB - VA) - (VD - VC). Ignoring noise in VA and VC, we know that (VB - VA) - (VD - VC) = VB - VD. Let Ap be the peak-to-peak value of the echo voltage, Vos be the op-amp offset voltage, and 5 integrations be performed. Since VA and VC are both sampled voltages after the pxl_op pixel integration op-amp resets, their values ​​are the same. Therefore, we can obtain:

[0087] (1)

[0088] (2)

[0089] (3)

[0090] in, For pixel piezoelectric capacitors, This is a parasitic capacitance.

[0091] In other words, the first difference (VB-VA) = effective signal S + offset error E, and the second difference (VD-VC) = -effective signal S + offset error E. After subtracting the two, the offset error E will be canceled out, the signal strength will double, and the effect of the offset will disappear. Therefore, by implementing the operation (VB-VA)-(VD-VC) on the PGA and designing the PGA as an offset storage structure, the offset error introduced by pxl_op and the offset error of the PGA itself can be eliminated.

[0092] In this embodiment, the processing of two inverse integrations combined with four samplings and PGA differential operations, because the inverse integration direction causes the effective signal to exhibit opposite polarity, the operation of determining the target signal based on the difference between the second and first differential values ​​can completely cancel the offset error of the pixel integration amplifier, while doubling the amplitude of the target signal. The error cancellation process can be implemented based on mathematical operation logic and basic circuit structure, without the need for additional hardware such as chopper switches and calibration modules.

[0093] In one embodiment of this disclosure, it further includes: a chopper control module (not shown in the figures), comprising a chopper switch assembly connected to a pixel integration operational amplifier, and a chopper controller that sends a chopper control signal to the chopper switch assembly, wherein the chopper control signal is... Figure 6 The CHOP signal shown in the figure is used to switch the level of the chopper control signal between the first scan period and the second scan period so that the polarity of the offset voltage of the pixel integration operational amplifier is opposite between the first scan period and the second scan period, and the switching frequency of the chopper control signal is consistent with the switching frequency of the scan period.

[0094] like Figure 7A As shown, in a chopper switch according to an embodiment of this disclosure, the CHOP signal passes through two stages of inverters to generate complementary control signals CHOPB and CHOPA, as follows: Figure 7B As shown, if CHOP=1, then CHOPA=1, CHOPB=0), IN1 is connected to OUT1 through the switch controlled by CHOPB, and IN2 is connected to OUT2 through the switch controlled by CHOPA. If CHOP=0, then CHOPA=0, CHOPB=1, IN1 is connected to OUT2 through the switch controlled by CHOPA, and IN2 is connected to OUT1 through the switch controlled by CHOPB, thus allowing the input and output to be interchanged.

[0095] In some embodiments, by setting a chopper switch and a chopper controller, the chopper chop signal is switched once between two scans. For example, the chop signal is switched from 0 to 1. This enables the op-amp offset to be Vos in the first scan and -Vos in the second scan. The two offsets have opposite polarities and the same magnitude, eliminating the need for frequent switching during integration. Combined with the four samplings in the working timing, error cancellation is achieved through the summation operation of (VB-VA)+(VD-VC). Only one chopper switch needs to be completed between two scans, eliminating the need for real-time calibration using high-frequency chopper. Furthermore, the chopper operation is completed during the op-amp reset phase, giving the pixel integration op-amp sufficient time to re-stabilize after the switch.

[0096] In one embodiment of this disclosure, the pixel integration operational amplifier includes a first-stage amplification unit and a second-stage amplification unit. The chopper switch assembly includes: a first chopper switch disposed between the first switch assembly and the first-stage amplification unit, used to connect the first switch assembly to different input terminals of the first-stage amplification unit during a first scan period and a second scan period based on a chopper control signal; and a second chopper switch disposed between the first-stage amplification unit and the second-stage amplification unit, used to enable the first-stage amplification unit and the second-stage amplification unit to have different connection paths during the first scan period and the second scan period based on the chopper control signal.

[0097] In some embodiments, by setting a first chopper switch and a second chopper switch in the signal input link of the pixel integrating operational amplifier and the interstage transmission link of the two-stage amplification unit, respectively, the two chopper switches operate synchronously based on the same chopper control signal. During the first and second scan periods, the input connection relationship and interstage transmission path of the signal are switched synchronously. This ensures that the offset voltage of the pixel integrating operational amplifier exhibits opposite polarities in the two scan periods through the switching of the input terminal of the first chopper switch, providing a basis for subsequent differential operations to cancel offset errors. Furthermore, the interstage path switching of the second chopper switch matches the signal polarity switching action of the first chopper switch, ensuring that the output signal of the first-stage amplification unit can be effectively transmitted to the second-stage amplification unit according to the design logic of the amplification link.

[0098] In this embodiment, the first chopper switch is used to switch the polarity of the signal input to the first-stage amplification unit, and the second chopper switch synchronously matches the output polarity of the first-stage amplification unit to ensure that the signal transmission logic of the two amplification units is consistent. Ultimately, the polarity of the operational amplifier offset voltage is reversed in the two scans, so that the chopper controller does not need to be driven by a high-frequency clock, nor does it need to optimize the high-frequency performance of the operational amplifier, thereby helping to reduce the complexity of the circuit.

[0099] like Figure 8As shown, in one embodiment of this disclosure, the first-stage amplification unit includes a first MOSFET M1 and a second MOSFET M2 connected to the common source, a third MOSFET M3 connected to the common drain of the first MOSFET M1, and a fourth MOSFET M4 connected to the common gate of the third MOSFET M3. The fourth MOSFET and the second MOSFET are connected to the common drain. The gate of the first MOSFET serves as the first input terminal VIN1 of the pixel integrating operational amplifier, the gate of the second MOSFET serves as the second input terminal VIP1 of the pixel integrating operational amplifier, the common drain connection point of the first MOSFET and the third MOSFET serves as the first differential signal point Vop, the common drain connection point of the second MOSFET and the fourth MOSFET serves as the second differential signal point Von, and the common gate connection point of the third MOSFET and the fourth MOSFET serves as the bias point VBP. The second-stage amplification unit includes a fifth MOSFET M5 and a sixth MOSFET M6 connected in series. The pixel integrating operational amplifier also includes an LC series circuit, one end of which serves as the intermediate output point Vout1, and the other end is connected to the connection point of the fifth MOSFET and the sixth MOSFET, and the connection point serves as the operational amplifier output terminal Vout of the pixel integrating operational amplifier.

[0100] like Figure 9 As shown, in one embodiment of this disclosure, a first chopper switch is provided, the input terminals of which are respectively connected to a first switching assembly and a first reference voltage access point as VIN and VIP, and the output terminals of the first chopper switch are respectively connected to the first input terminal VIN1 and the second input terminal VIP1 of the pixel integration operational amplifier.

[0101] like Figure 10 As shown, the input terminals of the second chopper switch are connected to the first differential signal point Vop and the second differential signal point Von, respectively, and the output terminals of the second chopper switch are connected to the bias point VBP and the intermediate output point Vout1, respectively.

[0102] In one embodiment of this disclosure, the first switching assembly includes: a first switch S1, a second switch S2, a third switch S3 disposed between the pixel electrode and the pixel integration operational amplifier, and a fourth switch S4 disposed in parallel with the pixel integration operational amplifier.

[0103] In some embodiments, the input terminal of the first chopper switch is connected to the series connection point of the third switch S3 and the fourth switch S4, and the other end is connected to the first reference voltage access point (connected to Vref2). The output terminal is connected to the two input terminals of the first stage amplification unit, namely VIN1 and VIP1. The input terminal of the second chopper switch is connected to the two differential signal points Vop and Von of the first stage amplification unit, and the output terminal is connected to the bias point VBP and the intermediate output point Vout1. The second chopper switch switches synchronously with the first chopper switch to reverse the polarity of the differential signal output by the first stage amplification unit, so as to ensure that the signal transmission logic of the two stages amplification units matches the input polarity.

[0104] In some embodiments, when chop=0, the echo voltage signal transmitted by the third switch S3 is directly connected to the first input terminal VIN1 of the pixel integrating operational amplifier, the second input terminal VIP1 is connected to the reference voltage Vref2, the differential signal point Vop of the first stage amplification unit is connected to the bias point VBPVBP, and Von is connected to the intermediate output point Vout1. The pixel integrating operational amplifier integrates the echo voltage from the peak to the trough, and the offset voltage is +Vos. The integration result is directly transmitted through the two-stage amplification unit to output the echo integrated voltage, thus completing the signal accumulation of the first scanning period.

[0105] In some embodiments, when chop=1, the echo voltage signal is connected to the second input terminal VIP1 of the operational amplifier, and the first input terminal VIN1 is connected to Vref2. The polarity of the input signal is reversed. The Vop of the first-stage amplification unit is connected to the intermediate output point Vout1, and the Von is connected to the bias point VBPVBP. The reverse logic of the matching input signal is used. The pixel integrating operational amplifier integrates the echo voltage from the peak to the trough. The offset voltage becomes -Vos. The integrated signal is cross-transmitted through the two-stage amplification unit and outputs the inverse echo integrated voltage corresponding to the rising segment, completing the signal accumulation of the second scan.

[0106] In this embodiment, a first chopper switch is placed between the first switching assembly and the first-stage amplification unit, and a second chopper switch is placed between the first-stage amplification unit and the second-stage amplification unit. Through the synchronous operation of the two switches, the polarity reversal of the input signal and the polarity matching of the amplification link can be achieved. That is, when the chopper state switches, the first chopper switch reverses the polarity of the signal input to the first-stage amplification unit to ensure that the operational amplifier offset voltage exhibits ±Vos reverse characteristics in the two scans. The second chopper switch synchronously cross-switches the transmission path of the differential signal to prevent signal distortion.

[0107] The first-stage amplification unit uses a common-source and common-gate MOS transistor combination structure. The second-stage amplification unit is equipped with an LC series circuit. The common-source and common-gate structure can improve the gain and bandwidth of the amplification unit, ensuring that the inverted signal can still be stably amplified. The LC series circuit can optimize the frequency response of the signal, thus adapting to the signal amplification requirements after chopping.

[0108] Connecting the first chopper switch to the series connection point of the third switch S3 and the fourth switch S4 ensures the capture of the echo voltage transmitted by the pixel plate. Combined with the on / off control of the third switch S3 and the fourth switch S4, the timing matching of signal sampling and integration is achieved. The dual chopper switch only needs to switch once between two scans, without high-frequency operation, which means that the complex drive circuit and noise suppression design required for high-frequency chopping are not needed, thus helping to reduce the overall complexity of the circuit.

[0109] In one embodiment of this disclosure, the first scan period and the second scan period have the same integration direction.

[0110] In this embodiment, the offset voltage polarity is reversed by synchronous switching of dual chopper switches, eliminating the need to adjust the signal polarity by changing the integration direction. The same integration direction ensures that the integration timing and switching control logic of the two scans are consistent, which helps to simplify the timing control and signal processing logic of the circuit, prevents the complexity of timing calibration caused by the difference in integration direction, reduces the design workload of the circuit control module, and ensures that the effective signal of the echo voltage maintains a consistent accumulation pattern in the two scans. The offset voltage polarity is changed by switching the chopper switch, and the offset error can be canceled by subsequent differential operation.

[0111] In one embodiment of this disclosure, during a first scan period and a second scan period, the pixel integrating operational amplifier integrates the peak-to-trough phase of the echo voltage in each echo cycle.

[0112] In this embodiment, the peak-to-trough phase of the echo voltage is the interval with the largest voltage change amplitude and the most concentrated energy. Furthermore, both scans focus on the same half-cycle integration, eliminating the need for additional control circuitry to switch the integration direction. The same integration timing logic can be directly reused, reducing the design difficulty of switching control and signal sampling.

[0113] In one embodiment of this disclosure, performing an offset error cancellation operation based on a first difference value and a second difference value includes: determining a target signal based on the sum of the second difference value and the first difference value.

[0114] In some embodiments, when chop=0, the offset voltage of pxl_op is Vos, and when chop=1, the offset voltage of pxl_op is -Vos. This is equivalent to a chopping operation for the op-amp, except that the chopping operation is performed between two scans at a low frequency, and the op-amp has enough time to regain stability after the chopping switch is switched.

[0115] Perform two scans on the PIXEL, and Figure 4The ultrasonic fingerprint reading circuit in this model differs from others in its operation. Due to the use of two chopper switches, both scans involve integrating from the peak to the trough of the waveform. The PGA also samples the PIXEL output four times. In the first scan, after pxl_op resets, a sample is taken once (VA). After integration in the first scan, another sample is taken (VB). In the second scan, after pxl_op resets, a sample is taken once (VC). After integration in the second scan, another sample is taken (VD). The results of the two scans are added on the PGA, resulting in (VB - VA) + (VD - VC). Since the offset of pxl_op has opposite polarities but the same magnitude when chop is 0 and 1, we can obtain:

[0116] (1)

[0117] (2)

[0118] (4)

[0119] The above operations can also eliminate the error introduced by the offset of pxl_op and double the target semaphore.

[0120] like Figure 11 As shown, in some embodiments, during the first scan phase, CHOP=1, the offset voltage of pxl_op is Vos, and the first switching component is made to correspond to different switching states during the first scan period based on the first set of switching control signals, thereby realizing different functions in different phases, including:

[0121] During the isolation period t0, S1 is turned on, and S2, S3 and S4 are turned off. Based on the first set of switch control signals, the connection between the disconnection detection module and the pixel integration module is executed to prevent external signal interference.

[0122] During the reset period (t1+t2), the input / output terminals of the pixel integration op-amp are pulled to the reference voltage to complete the op-amp reset. During the t1 period, S1 is open, S4 is closed, and S2 and S3 remain open. During the t2 period, S2 switches to closed.

[0123] During the first sampling period t3, S4 switches to disconnect. After the reset is completed, the sampling module collects the voltage at the px_out terminal to obtain the first sampling voltage VA.

[0124] During the integration period t4, S2 and S3 alternately open and close, and the pixel integration operational amplifier performs periodic integration of the echo voltage V1 from peak to trough. The px_out voltage changes gradually with the integration.

[0125] During the second sampling period t5, after integration is completed, S2 remains closed and S3 remains open. The sampling module acquires the px_out voltage to obtain the second sampling voltage VB.

[0126] During time period t6, the second S2 switches to disconnect, so time period t6 can be regarded as the period between the first scan period and the second scan period.

[0127] Starting from the first sampling, each time s2 and s3 are turned on, the op-amp integrates the voltage from the peak to the trough of V1, causing px_out to accumulate and rise until it finally reaches the integration peak VB of the first scan.

[0128] In some embodiments, after the CHOP signal switches to a low level, the operational amplifier offset voltage is reversed, and the first switching component is made to correspond to different switching states during the second scanning period based on the second set of switch control signals. The switching control of the first switching component during the second scanning period is the same as that during the first scanning period, and different functions are implemented in different stages, including:

[0129] Repeat the isolation period t0 and the reset period (t1+t2) operation, and collect the third sampling voltage VC in the first sampling period t3.

[0130] Integration period t4: The pixel integrating operational amplifier performs periodic integration of the echo voltage V1 from trough to peak, which is opposite to the integration direction of the first scanning period.

[0131] The second sampling period t5: The integrated px_out voltage is collected. Starting from the reset voltage VC, px_out continues to rise in a stepwise manner: the op-amp repeatedly integrates the falling segment voltage of V1, and px_out continues the accumulation trend, eventually rising to VD, which is the fourth sampling voltage VD.

[0132] Finally, the PGA performs a differential operation (VB-VA) + (VD-VC) on VA, VB, VC, and VD to output the target signal.

[0133] In some embodiments, the first switching component is made to correspond to different switching states during the second scanning period based on the second set of switching control signals. The switching control of the first switching component during the second scanning period is the same as that during the first scanning period, and different functions are implemented at different stages, including:

[0134] Repeat the isolation period t0 and the reset period (t1+t2) operation, and collect the third sampling voltage VC in the first sampling period t3.

[0135] Integration period t4: The pixel integrating operational amplifier performs periodic integration of the echo voltage V1 from trough to peak, which is opposite to the integration direction of the first scanning period.

[0136] The second sampling period t5: The integrated px_out voltage is collected to obtain the fourth sampling voltage VD.

[0137] Finally, the PGA performs a differential operation (VB-VA) - (VD-VC) on VA, VB, VC, and VD to output the target signal.

[0138] like Figure 12 As shown, in one embodiment of this disclosure, the sampling module includes: an operational amplifier pga_op, including a third input terminal and a fourth input terminal; a first sampling capacitor Cs1 and a second sampling capacitor Cs2, one end of the first sampling capacitor Cs1 being connected to the third input terminal and one end of the second sampling capacitor Cs2 being connected to the fourth input terminal; a sampling clock component and an amplification clock component, the sampling clock component including a first sampling clock switch clks1 and a second sampling clock switch clks2, and the amplification clock component including a first amplification clock switch clka1 and a second amplification clock switch clka2, both the first sampling clock switch clks1 and the first amplification clock switch clka1 being connected to the other end of the first sampling capacitor Cs1. The second sampling clock switch clks2 and the second amplification clock switch clka2 are both connected to the other end of the second sampling capacitor Cs2. During the second scan period, if the sampling clock component is closed and the amplification clock component is open, the first sampling capacitor Cs1 is connected to the fourth sampling voltage, the second sampling capacitor Cs2 is connected to the third sampling voltage, the sampling clock component is open, the amplification clock component is closed, and the operational amplifier pga_op outputs the second differential value. If the sampling clock component is closed and the amplification clock component is open, the first sampling capacitor Cs1 is connected to the third sampling voltage, the second sampling capacitor Cs2 is connected to the fourth sampling voltage, the sampling clock component is open, the amplification clock component is closed, and the operational amplifier pga_op outputs the inverted second differential value.

[0139] In some embodiments, the sampling module may be a PGA with an offset storage structure.

[0140] In some embodiments, during the sampling phase, the first sampling clock switch clks and the second sampling clock switch clks2 remain closed, while the first amplification clock switch clka1 and the second amplification clock switch clka2 remain open.

[0141] During the first scan, clks1 and clks2 of the sampling clock component are closed, and the amplification clock component is open. The other end of the first sampling capacitor Cs1 is connected to the first sampling voltage (the positive terminal of the differential input of the first scan), and the other end of the second sampling capacitor Cs2 is connected to the second sampling voltage (the negative terminal of the differential input of the first scan). Cs1 and Cs2 synchronously acquire the differential input signal of the first scan, and at the same time, the offset voltage of the operational amplifier pga_op is stored in the feedback capacitor Cf1.

[0142] During the second scan, the sampling clock component remains closed, while the amplification clock component remains open. The other end of the first sampling capacitor Cs1 is switched to the fourth sampling voltage, and the other end of the second sampling capacitor Cs2 is switched to the third sampling voltage (the two are the differential input pair for the second scan), thus completing the sampling of the differential signal for the second scan. At the same time, Cf2 stores the operational amplifier offset of the current stage.

[0143] In some embodiments, after entering the amplification phase, the sampling clock component is disconnected, the amplification clock component is closed, and the circuit switches to signal amplification and level calibration mode. At this time, the other end of the first sampling capacitor Cs1 and the second sampling capacitor Cs2 switches from receiving the input signal to receiving the target voltage of the amplification phase, and may further include the following operating scenario:

[0144] The first sampling capacitor Cs1 is connected to the fourth sampling voltage through the closed first amplification clock switch clka1, and the second sampling capacitor Cs2 is connected to the third sampling voltage through the closed second amplification clock switch clka2. At this time, the voltage difference across the sampling capacitors is the fourth sampling voltage minus the third sampling voltage. The operational amplifier pga_op amplifies this voltage difference and outputs the second differential value through the feedback link of the sampling capacitor Cs and the feedback capacitor Cf (the gain is determined by Cf / Cs).

[0145] The first sampling capacitor Cs1 is connected to the third sampling voltage, and the second sampling capacitor Cs2 is connected to the fourth sampling voltage. The voltage difference across the sampling capacitors is reversed to become the third and fourth sampling voltages. The operational amplifier pga_op outputs the amplified inverted second differential value.

[0146] Simultaneously, during the amplification process, the sampling capacitor is also connected to the output voltage vdacp (corresponding to a part of the fourth sampling voltage) and vdacn (corresponding to a part of the third sampling voltage) of the differential DAC. The DC component of the DAC voltage is used to cancel the DC offset in the input signal, and the output level of the operational amplifier pga_op is adjusted to the middle region of the ADC range.

[0147] An ultrasonic fingerprint chip according to an embodiment of the present disclosure includes: the ultrasonic fingerprint reading circuit described in any of the above embodiments.

[0148] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0149] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0150] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0151] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An ultrasonic fingerprint reading circuit, characterized in that, include: The detection module is configured to capture ultrasonic echoes and convert the ultrasonic echoes into periodic echo voltages; The pixel integration module, electrically connected to the detection module, includes a first switching component and a pixel integration operational amplifier; A scanning control module, electrically connected to the first switching component, is used to sequentially send a first set of switching control signals and a second set of switching control signals to the first switching component. The first set of switching control signals is used to control the first switching component to perform on / off actions corresponding to a first scanning period. The second set of switching control signals is used to control the first switching component to perform on / off actions corresponding to a second scanning period. The pixel integration operational amplifier is configured to periodically integrate the echo voltage during the first scanning period and the second scanning period, and output a continuous echo integrated voltage accordingly. The sampling module is used to sample the echo integral voltage multiple times during the first scanning period and the second scanning period to obtain multiple sampled voltages. The multiple sampled voltages are configured to perform differential operations to cancel the offset error of the pixel integral operational amplifier to obtain a target signal. The target signal is used for ultrasonic fingerprint reading.

2. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, The first scanning period and the second scanning period respectively include the isolation period of the detection module, the reset period of the pixel integration amplifier, the first sampling period, the integration period and the second sampling period, wherein the echo integration voltage is sampled during the first sampling period and the second sampling period of the first scanning period, and during the first sampling period and the second sampling period of the second scanning period, respectively, to obtain the first sampling voltage, the second sampling voltage, the third sampling voltage and the fourth sampling voltage.

3. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, The integration directions during the first and second scan periods are opposite.

4. The ultrasonic fingerprint reading circuit according to claim 3, characterized in that, During the first scanning period, the pixel integrating operational amplifier integrates the trough-to-peak phase of the echo voltage in each echo cycle; During the second scanning period, the pixel integrating operational amplifier integrates the peak-to-trough phase of the echo voltage in each echo cycle.

5. The ultrasonic fingerprint reading circuit according to claim 2, characterized in that, The sampling module performs differential operations, including: Perform a difference operation on the second sampled voltage and the first sampled voltage to obtain the first difference value; Perform a differential operation on the fourth sampling voltage and the third sampling voltage to obtain a second differential value; Based on the first difference value and the second difference value, an offset error cancellation operation is performed to obtain the target signal.

6. The ultrasonic fingerprint reading circuit according to claim 5, characterized in that, Perform offset error cancellation operation based on the first difference value and the second difference value, including: The target signal is determined based on the difference between the second difference value and the first difference value.

7. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, Also includes: The chopper control module includes a chopper switch assembly connected to the pixel integration operational amplifier, and a chopper controller that sends a chopper control signal to the chopper switch assembly. The chopper controller switches the level of the chopper control signal between the first scan period and the second scan period so that the polarity of the offset voltage of the pixel integration operational amplifier is opposite between the first scan period and the second scan period. The switching frequency of the chopper control signal is consistent with the switching frequency of the scan period.

8. The ultrasonic fingerprint reading circuit according to claim 7, characterized in that, The pixel integrating operational amplifier includes a first-stage amplification unit and a second-stage amplification unit, and the chopper switch assembly includes: A first chopper switch is disposed between the first switch assembly and the first stage amplification unit, and is used to connect the first switch assembly to a different input terminal from the first stage amplification unit during the first scanning period and the second scanning period based on the chopper control signal. A second chopper switch is disposed between the first-stage amplification unit and the second-stage amplification unit, and is used to enable the first-stage amplification unit and the second-stage amplification unit to have different connection paths during the first scanning period and the second scanning period based on the chopper control signal.

9. The ultrasonic fingerprint reading circuit according to claim 8, characterized in that, The first-stage amplification unit includes a first MOS transistor and a second MOS transistor connected to a common source, a third MOS transistor connected to a common drain of the first MOS transistor, and a fourth MOS transistor connected to a common gate of the third MOS transistor. The fourth MOS transistor is connected to the second MOS transistor via a common drain. The gate of the first MOS transistor serves as the first input terminal of the pixel integrating operational amplifier, the gate of the second MOS transistor serves as the second input terminal of the pixel integrating operational amplifier, the common drain connection point of the first MOS transistor and the third MOS transistor serves as the first differential signal point, the common drain connection point of the second MOS transistor and the fourth MOS transistor serves as the second differential signal point, and the common gate connection point of the third MOS transistor and the fourth MOS transistor serves as the bias point. The second-stage amplification unit includes a fifth MOSFET and a sixth MOSFET connected in series; The pixel integrating operational amplifier also includes an LC series circuit, one end of which serves as an intermediate output point, and the other end is connected to the connection point of the fifth MOS transistor and the sixth MOS transistor, with the connection point serving as the operational amplifier output terminal of the pixel integrating operational amplifier.

10. The ultrasonic fingerprint reading circuit according to claim 9, characterized in that, The input terminals of the first chopper switch are respectively connected to the first switch assembly and the first reference voltage access point, and the output terminals of the first chopper switch are respectively connected to the first input terminal and the second input terminal of the pixel integration operational amplifier. The input terminals of the second chopper switch are respectively connected to the first differential signal point and the second differential signal point, and the output terminals of the second chopper switch are respectively connected to the bias point and the intermediate output point.

11. The ultrasonic fingerprint reading circuit according to claim 7, characterized in that, The first scan period and the second scan period have the same integration direction.

12. The ultrasonic fingerprint reading circuit according to claim 11, characterized in that, During the first and second scanning periods, the pixel integrating operational amplifier integrates the peak-to-trough phase of the echo voltage in each echo cycle.

13. The ultrasonic fingerprint reading circuit according to claim 5, characterized in that, Perform offset error cancellation operation based on the first difference value and the second difference value, including: The target signal is determined based on the sum of the second difference value and the first difference value.

14. The ultrasonic fingerprint reading circuit according to claim 5, characterized in that, The sampling module includes: An operational amplifier, including a third input terminal and a fourth input terminal; A first sampling capacitor and a second sampling capacitor, one end of the first sampling capacitor is connected to the third input terminal, and one end of the second sampling capacitor is connected to the fourth input terminal; The system includes a sampling clock component and an amplification clock component. The sampling clock component includes a first sampling clock switch and a second sampling clock switch. The amplification clock component includes a first amplification clock switch and a second amplification clock switch. Both the first sampling clock switch and the first amplification clock switch are connected to the other end of the first sampling capacitor. Both the second sampling clock switch and the second amplification clock switch are connected to the other end of the second sampling capacitor. During the second scanning period, if the sampling clock component is closed and the amplification clock component is open, the first sampling capacitor is connected to the fourth sampling voltage, the second sampling capacitor is connected to the third sampling voltage, the sampling clock component is open, the amplification clock component is closed, and the operational amplifier outputs the second differential value. If the sampling clock component is closed and the amplification clock component is open, the first sampling capacitor is connected to the third sampling voltage, the second sampling capacitor is connected to the fourth sampling voltage, the sampling clock component is open, the amplification clock component is closed, and the operational amplifier outputs the inverted second differential value.

15. The ultrasonic fingerprint reading circuit according to claim 2, characterized in that, The first switching component includes: A first switch, one end of which is connected to the pixel plate in the detection module, and the other end of which is grounded; A second switch, one end of which is connected to the pixel electrode plate, and the other end of which is connected to a second reference voltage; A third switch is disposed between the pixel electrode and the pixel integration amplifier; The fourth switch is connected in parallel with the pixel integration operational amplifier. During the isolation period, the first switch is closed. During the first sub-period of the reset period, the first switch is opened and the fourth switch is closed. During the second sub-period of the reset period, the second switch is closed. During the first sampling period, the fourth switch is opened and the integration period is entered. During the second sampling period, the second switch is closed and the third switch is opened and closed alternately.

16. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, Also includes: An analog-to-digital conversion module, connected to the sampling module, is used to convert the target signal into an echo digital signal so as to read out the ultrasonic fingerprint based on the echo digital signal.

17. An ultrasonic fingerprint chip, characterized in that, include: The ultrasonic fingerprint reading circuit as described in any one of claims 1 to 16.

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