Gate driver and electronic device

Abstract

The invention discloses a gate driver and an electronic device. The gate driver includes a plurality of stages. Each of the plurality of stages includes: an input circuit configured to provide an input signal to a control node in response to a first clock signal; a first inverting control circuit configured to control a voltage of an inverting control node in response to a voltage of the control node; and a gate output circuit configured to output a gate signal in response to the voltage of the control node and the voltage of the inverting control node.

Description

Technical Field

[0001] Embodiments of the present invention relate to gate drivers and display devices including gate drivers. More specifically, the present invention relates to gate drivers for reducing power consumption and dead zones, and display devices including gate drivers. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, and pixels. The display panel driver includes a gate driver for providing gate signals to the gate lines, a data driver for providing data voltages to the data lines, and a drive controller for controlling the gate driver and the data driver. Summary of the Invention

[0003] A gate driver comprises multiple stages, and each stage has various configurations. For example, the configuration can be a transistor, a signal line, and a voltage line. As the configuration increases, the power consumption of the gate driver may increase, and the dead time may become larger.

[0004] Embodiments of the present invention provide gate drivers for simplifying construction to reduce power consumption and dead time.

[0005] Embodiments of the present invention provide a display device including a gate driver.

[0006] In an embodiment of the gate driver according to the present invention, the gate driver includes multiple stages. Each of the multiple stages includes: an input circuit configured to provide an input signal to a control node in response to a first clock signal; a first inverting control circuit configured to control the voltage of the inverting control node in response to the voltage of the control node; and a gate output circuit configured to output a gate signal in response to the voltage of the control node and the voltage of the inverting control node.

[0007] In an embodiment, the input circuit may include a first transistor including a gate electrode for receiving a first clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; the first inverting control circuit includes a second transistor including a gate electrode connected to the control node, a first electrode, and a second electrode connected to the inverting control node; and the gate output circuit includes: a fourth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving a first gate voltage having a relatively high first level, and a second electrode connected to a gate output node from which a gate signal is output; and a fifth transistor including a gate electrode connected to the control node, a first electrode for receiving a second clock signal, and a second electrode connected to the gate output node.

[0008] In an embodiment, each of the plurality of stages may further include a second inverting control circuit configured to control the voltage of an inverting control node in response to a first clock signal, and the second inverting control circuit includes a third transistor including a gate electrode for receiving the first clock signal, a first electrode, and a second electrode connected to the inverting control node.

[0009] In an embodiment, the first to fifth transistors may be p-type metal-oxide-semiconductor (“PMOS”) transistors.

[0010] In an embodiment, the gate output circuit may further include a first capacitor, which includes a first electrode receiving a first gate voltage and a second electrode connected to an inverting control node.

[0011] In an embodiment, the gate output circuit may further include a second capacitor, which includes a first electrode connected to the gate output node and a second electrode connected to the control node.

[0012] In one embodiment, the first electrode of the second transistor can receive a first clock signal, and the first electrode of the third transistor can also receive a first clock signal.

[0013] In an embodiment, the control node may include a first control node and a second control node. Each of the plurality of levels may further include a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node. The node partitioning circuit may include a sixth transistor, which includes a gate electrode for receiving a first clock signal, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0014] In one embodiment, the first electrode of the second transistor may receive a first clock signal, and the first electrode of the third transistor may receive a second gate voltage having a second level lower than the first gate voltage.

[0015] In an embodiment, the control node may include a first control node and a second control node. Each of the plurality of levels may further include a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node. The node partitioning circuit may include a sixth transistor, which includes a gate electrode receiving a second gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0016] In an embodiment, the first electrode of the third transistor can receive a first clock signal, and the first inverting control circuit can further include a seventh transistor, which includes a gate electrode that receives a second clock signal, a first electrode that receives a first gate voltage, and a second electrode connected to the first electrode of the second transistor.

[0017] In an embodiment, the control node may include a first control node and a second control node. Each of the plurality of levels may further include a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node. The node partitioning circuit may include a sixth transistor, which includes a gate electrode for receiving a first clock signal, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0018] In an embodiment, the first electrode of the third transistor may receive a second gate voltage having a second level lower than the first gate voltage, and the first inverting control circuit may further include a seventh transistor, which includes a gate electrode for receiving a second clock signal, a first electrode for receiving the first gate voltage, and a second electrode connected to the first electrode of the second transistor.

[0019] In an embodiment, the control node may include a first control node and a second control node. Each of the plurality of levels may further include a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node. The node partitioning circuit may include a sixth transistor, which includes a gate electrode receiving a second gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

[0020] In an embodiment of the gate driver conceived according to the present invention, the gate driver includes multiple stages. Each of the multiple stages includes: a first transistor including a gate electrode receiving a first clock signal, a first electrode receiving an input signal, and a second electrode connected to a control node; a second transistor including a gate electrode connected to the control node, a first electrode, and a second electrode connected to an inverting control node; a fourth transistor including a gate electrode connected to the inverting control node, a first electrode receiving a first gate voltage having a relatively high first level, and a second electrode connected to a gate output node from which a gate signal is output; and a fifth transistor including a gate electrode connected to the control node, a first electrode receiving a second clock signal, and a second electrode connected to a gate output node.

[0021] In an embodiment, each of the plurality of stages may further include a third transistor, the third transistor including a gate electrode for receiving a first clock signal, a first electrode, and a second electrode connected to an inverting control node.

[0022] In an embodiment, each of the plurality of stages may further include a first capacitor, the first capacitor including a first electrode receiving a first gate voltage and a second electrode connected to an inverting control node.

[0023] In an embodiment of a display device according to the present invention, the display device includes: a display panel including pixels; a data driver configured to provide a data voltage to the pixels; a gate driver configured to provide a gate signal to the pixels; and a drive controller configured to control the data driver and the gate driver. The gate driver includes multiple stages, each of the multiple stages including: an input circuit configured to provide an input signal to a control node in response to a first clock signal; a first inverting control circuit configured to control the voltage of an inverting control node in response to the voltage of the control node; and a gate output circuit configured to output a gate signal in response to the voltage of the control node and the voltage of the inverting control node.

[0024] In an embodiment, the input circuit may include a first transistor, which includes a gate electrode for receiving a first clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node. The first inverting control circuit may include a second transistor, which includes a gate electrode connected to the control node, a first electrode, and a second electrode connected to the inverting control node. The gate output circuit may include: a fourth transistor, which includes a gate electrode connected to the inverting control node, a first electrode for receiving a first gate voltage having a relatively high first level, and a second electrode connected to a gate output node from which it outputs a gate signal; and a fifth transistor, which includes a gate electrode connected to the control node, a first electrode for receiving a second clock signal, and a second electrode connected to the gate output node.

[0025] In an embodiment, each of the plurality of stages may further include a second inverting control circuit configured to control the voltage of an inverting control node in response to a first clock signal, and the second inverting control circuit may include a third transistor including a gate electrode receiving the first clock signal, a first electrode, and a second electrode connected to the inverting control node.

[0026] Depending on the gate driver and the display device, the gate driver can have a smaller structure (e.g., transistors, signal lines, and voltage lines). Accordingly, the power consumption and dead time of the gate driver can be reduced. Attached Figure Description

[0027] The above and other features of the embodiments of the present invention will become more apparent from the detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1This is a block diagram illustrating an embodiment of a display device based on the concept of the present invention;

[0029] Figure 2 It is shown Figure 1 Block diagram of the gate driver;

[0030] Figure 3 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0031] Figure 4 It is shown Figure 3 Timing diagram of the input signal, first clock signal, second clock signal, voltage of control node, voltage of inverting control node and gate signal;

[0032] Figure 5 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation during the first duration;

[0033] Figure 6 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation during the second duration;

[0034] Figure 7 It is shown Figure 3 The level at Figure 4 The circuit diagram of the operation during the third duration;

[0035] Figure 8 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0036] Figure 9 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0037] Figure 10 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0038] Figure 11 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0039] Figure 12 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0040] Figure 13 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0041] Figure 14 It is shown Figure 2 Circuit diagram of an embodiment of the level;

[0042] Figure 15 It is a block diagram showing an electronic device; and

[0043] Figure 16 It is shown that Figure 15 The diagram shows an embodiment of an electronic device implemented as a smartphone. Detailed Implementation

[0044] The inventive concept will be described in more detail below with reference to the accompanying drawings.

[0045] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element.

[0046] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings of this document.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless expressly indicated otherwise, the singular forms “a” and “the” are intended to include the plural forms, including “at least one”. “Or” means “and / or”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms “comprising” or “including” are used in this specification, they indicate the presence of stated features, areas, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, an element described as being “down” to the other elements will be oriented “up” to the other elements. Thus, depending on the specific orientation of the drawing, the exemplary term “down” can cover both “down” and “up” orientations. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented “above” the other elements. Thus, the exemplary terms “below” or “under” can cover both “up” and “down” orientations.

[0049] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, a term such as “approximately” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] Figure 1 This is a block diagram illustrating an embodiment of a display device 10 according to the present invention.

[0052] refer to Figure 1 The display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0053] The display panel 100 may include a display area for displaying images and a peripheral area disposed adjacent to the display area.

[0054] The display panel 100 may include a grid line GL, a data line DL, and a pixel PX electrically connected to each of the grid line GL and the data line DL. The grid line GL may extend in a first direction, and the data line DL may extend in a second direction intersecting the first direction.

[0055] The drive controller 200 can receive input image data IMG and input control signal CONT from an external device (not shown). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0056] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0057] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0058] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0059] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0060] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0061] The gate driver 300 can generate gate signals for driving the gate lines GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can sequentially output the gate signals to the gate lines GL, row by row.

[0062] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF based on the third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0063] In an embodiment, for example, the gamma reference voltage generator 400 may be located within the drive controller 200 or the data driver 500.

[0064] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and convert the data signal DATA into a data voltage of analog type. The data driver 500 can output the data voltage to the data line DL.

[0065] Figure 2 It is shown Figure 1 Block diagram of the gate driver 300.

[0066] refer to Figure 2 The gate driver 300 may include multiple stages STG1, STG2, STG3, STG4, ... etc. Stages STG1, STG2, STG3, STG4, ... can receive the gate start signal FLM, the first clock signal CLK1, and the second clock signal CLK2. Stages STG1, STG2, STG3, STG4, ... etc. can sequentially output gate signals GS1, GS2, GS3, GS4, ... etc.

[0067] The first stage STG1 can receive the gate start signal FLM as an input signal, and subsequent stages STG2, STG3, STG4, ... can receive gate signals GS1, GS2, GS3, GS4, ... as input signals.

[0068] In an embodiment, for example, the first-stage STG1 may receive the gate start signal FLM as an input signal in response to the first clock signal CLK1. The first-stage STG1 may output the second clock signal CLK2 as the first gate signal GS1.

[0069] In one embodiment, for example, the second-stage STG2 can receive the first gate signal GS1 as an input signal in response to the second clock signal CLK2. The second-stage STG2 can output the first clock signal CLK1 as the second gate signal GS2.

[0070] In an embodiment, for example, the third-stage STG3 can receive the second gate signal GS2 as an input signal in response to the first clock signal CLK1. The third-stage STG3 can output the second clock signal CLK2 as the third gate signal GS3.

[0071] In an embodiment, for example, the fourth-stage STG4 can receive the third gate signal GS3 as an input signal in response to the second clock signal CLK2. The fourth-stage STG4 can output the first clock signal CLK1 as the fourth gate signal GS4.

[0072] Figure 3 It is shown Figure 2 The circuit diagram of an embodiment of the level. Figure 4 It is shown Figure 3 The timing diagram includes the input signal IN, the first clock signal CLK1, the second clock signal CLK2, the voltage of the control node NQ, the voltage of the inverting control node NQB, and the gate signal GS. Figure 5 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation in the first duration DU1. Figure 6 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation during the second duration DU2. Figure 7 It is shown Figure 3 The level at Figure 4 The circuit diagram for the operation in the third duration DU3.

[0073] refer to Figure 3 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0074] The input circuit can provide the input signal IN to the control node NQ in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. The first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltage of the control node NQ, and the first inverting control circuit may include a second transistor T2. The second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of the control node NQ and the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The first transistor T1 to the fifth transistor T5 may be PMOS transistors.

[0075] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to a control node NQ.

[0076] The second transistor T2 may include a gate electrode connected to the control node NQ, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the second transistor T2 may receive a first clock signal CLK1.

[0077] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive the first clock signal CLK1.

[0078] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage (also referred to as the first gate voltage) VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0079] The fifth transistor T5 may include a gate electrode connected to the control node NQ, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0080] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0081] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control node NQ.

[0082] refer to Figure 4 and Figure 5 During the first duration DU1, the input signal IN may have a relatively low level L, the first clock signal CLK1 may have a relatively low level (also referred to as the second level) L, for example, a logic low level, and the second clock signal CLK2 may have a relatively high level (also referred to as the first level) H, for example, a logic high level.

[0083] The first transistor T1 can be turned on in response to a first clock signal CLK1 having a relatively low level L, so as to provide an input signal IN having a relatively low level L to the control node NQ. Therefore, the voltage of the control node NQ can have a relatively low level L.

[0084] The second transistor T2 can be turned on in response to the voltage of the control node NQ having a relatively low level L, so as to provide the first clock signal CLK1, also having a relatively low level L, to the inverting control node NQB. Therefore, the voltage of the inverting control node NQB can have a relatively low level L.

[0085] The third transistor T3 can be turned on in response to a first clock signal CLK1 having a relatively low level L, so as to provide the first clock signal CLK1 having a relatively low level L to the inverting control node NQB. Therefore, the voltage of the inverting control node NQB can have a relatively low level L.

[0086] The fourth transistor T4 can be turned on in response to the voltage of the inverting control node NQB, which has a relatively low level L, to provide a relatively high gate voltage VGH to the gate output node NGS. Therefore, the gate signal GS can have a relatively high level H.

[0087] The fifth transistor T5 can be turned on in response to the voltage of the control node NQ, which has a relatively low level L, and provides the second clock signal CLK2, which has a relatively high level H, to the gate output node NGS. Therefore, the gate signal GS can have a relatively high level H.

[0088] refer to Figure 4 and Figure 6 During the second duration DU2, the input signal IN can have a relatively high level H, the first clock signal CLK1 can have a relatively high level H, and the second clock signal CLK2 can have a relatively low level L.

[0089] The first transistor T1 can be turned off in response to the first clock signal CLK1, which has a relatively high level H. The third transistor T3 can also be turned off in response to the first clock signal CLK1, which has a relatively high level H. Therefore, the voltage of the control node NQ can be maintained at a relatively low level L.

[0090] The second transistor T2 can be turned on in response to the voltage of the control node NQ, which has a relatively low level L, to provide the first clock signal CLK1, which has a relatively high level H, to the inverting control node NQB. Therefore, the voltage of the inverting control node NQB can have a relatively high level H.

[0091] The fourth transistor T4 can be turned off in response to the voltage of the inverting control node NQB, which has a relatively high level H.

[0092] The fifth transistor T5 can be turned on in response to the voltage of the control node NQ with a relatively low level L, so as to provide the second clock signal CLK2 with a relatively low level L to the gate output node NGS.

[0093] In this configuration, the gate signal GS can have a relatively high level H during the first duration DU1 and a relatively low level L during the second duration DU2. Since the second capacitor C2 maintains the voltage difference between the two electrodes, when the gate signal GS decreases from the relatively high level H to the relatively low level L, the voltage of the control node NQ can decrease by the voltage change of the gate signal GS. Therefore, the voltage of the control node NQ can decrease from the relatively low level L to a second relatively low level L2. Here, the second relatively low level L2 can be lower than the relatively low level L.

[0094] refer to Figure 4 and Figure 7 During the third duration DU3, the input signal IN can have a relatively high level H, the first clock signal CLK1 can have a relatively low level L, and the second clock signal CLK2 can have a relatively high level H.

[0095] The first transistor T1 can be turned on in response to a first clock signal CLK1 with a relatively low level L, and can provide an input signal IN with a relatively high level H to the control node NQ. Therefore, the voltage of the control node NQ can have a relatively high level H.

[0096] The second transistor T2 can be turned off in response to the voltage of the control node NQ, which has a relatively high level H.

[0097] The third transistor T3 can be turned on in response to a first clock signal CLK1 having a relatively low level L, and provides the first clock signal CLK1 having a relatively low level L to the inverting control node NQB. Therefore, the voltage of the inverting control node NQB can have a relatively low level L.

[0098] The fourth transistor T4 can be turned on in response to the voltage of the inverting control node NQB, which has a relatively low level L, and provides a relatively high gate voltage VGH to the gate output node NGS. Therefore, the gate signal GS can have a relatively high level H.

[0099] The fifth transistor T5 can be turned off in response to the voltage of the control node NQ, which has a relatively high level H.

[0100] Therefore, the gate driver 300 may include five transistors, two capacitors, two clock signals, and a gate voltage. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0101] exist Figures 3 to 7 In the middle, it is described Figure 2 An example of a higher level. In Figures 8 to 14 In the middle, description Figure 2 Other embodiments of the class. Figures 8 to 14 The circuit diagram is constructed similarly to Figure 3 The circuit diagrams are similar, and Figures 8 to 14 Circuit diagram operation and Figure 3 The operation is similar to that of the circuit diagram. Therefore, it is omitted. Figures 8 to 14 A description of the operation of the circuit diagram.

[0102] Figure 8 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0103] refer to Figure 8 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0104] The input circuit can provide the input signal IN to control nodes NQ1 and NQ2 in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. The first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltages of control nodes NQ1 and NQ2, and the first inverting control circuit may include a second transistor T2. The second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of control nodes NQ1 and NQ2 and the voltage of the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Each stage may further include a node partitioning circuit. Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2. A node partitioning circuit may be located between the first control node NQ1 and the second control node NQ2 to partition the first control node NQ1 and the second control node NQ2. The node partitioning circuit may include a sixth transistor T6. The first transistor T1 to the sixth transistor T6 may be PMOS transistors.

[0105] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to control nodes NQ1 and NQ2.

[0106] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode connected to the control nodes NQ1 and NQ2, and connected to the inverting control node NQB. In an embodiment, the first electrode of the second transistor T2 may receive a first clock signal CLK1.

[0107] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive the first clock signal CLK1.

[0108] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0109] The fifth transistor T5 may include a gate electrode connected to control nodes NQ1 and NQ2, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0110] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0111] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control nodes NQ1 and NQ2.

[0112] Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2.

[0113] The sixth transistor T6 may include a gate electrode for receiving the first clock signal CLK1, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2.

[0114] Figure 9 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0115] refer to Figure 9 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0116] The input circuit can provide the input signal IN to the control node NQ in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. The first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltage of the control node NQ, and the first inverting control circuit may include a second transistor T2. The second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of the control node NQ and the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The first transistor T1 to the fifth transistor T5 may be PMOS transistors.

[0117] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to a control node NQ.

[0118] The second transistor T2 may include a gate electrode connected to the control node NQ, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the second transistor T2 may receive a first clock signal CLK1.

[0119] The third transistor T3 may include a gate electrode that receives the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive a relatively low gate voltage (also referred to as the second gate voltage) VGL.

[0120] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0121] The fifth transistor T5 may include a gate electrode connected to the control node NQ, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0122] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0123] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control node NQ.

[0124] Therefore, the gate driver 300 may include five transistors, two capacitors, two clock signals, and two gate voltages. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0125] Figure 10 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0126] refer to Figure 10 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0127] The input circuit can provide the input signal IN to control nodes NQ1 and NQ2 in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. The first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltages of control nodes NQ1 and NQ2, and the first inverting control circuit may include a second transistor T2. The second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of control nodes NQ1 and NQ2 and the voltage of the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Each stage may further include a node partitioning circuit. Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2. A node partitioning circuit may be located between the first control node NQ1 and the second control node NQ2 to partition the first control node NQ1 and the second control node NQ2. The node partitioning circuit may include a sixth transistor T6. The first transistor T1 to the sixth transistor T6 may be PMOS transistors.

[0128] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to control nodes NQ1 and NQ2.

[0129] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode connected to the control nodes NQ1 and NQ2, and connected to the inverting control node NQB. In an embodiment, the first electrode of the second transistor T2 may receive a first clock signal CLK1.

[0130] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive a relatively low gate voltage VGL.

[0131] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0132] The fifth transistor T5 may include a gate electrode connected to control nodes NQ1 and NQ2, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0133] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0134] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control nodes NQ1 and NQ2. The control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2.

[0135] The sixth transistor T6 may include a gate electrode that receives a relatively low gate voltage VGL, a first electrode connected to a first control node NQ1, and a second electrode connected to a second control node NQ2.

[0136] Therefore, the gate driver 300 may include six transistors, two capacitors, two clock signals, and two gate voltages. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0137] Figure 11 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0138] refer to Figure 11 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0139] The input circuit can provide the input signal IN to the control node NQ in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. The first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltage of the control node NQ, and the first inverting control circuit may include a second transistor T2 and a seventh transistor T7. The second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of the control node NQ and the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The first transistors T1 to T5 and the seventh transistor T7 may be PMOS transistors.

[0140] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to a control node NQ.

[0141] The second transistor T2 may include a gate electrode connected to the control node NQ, a first electrode, and a second electrode connected to the inverting control node NQB.

[0142] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive the first clock signal CLK1.

[0143] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0144] The fifth transistor T5 may include a gate electrode connected to the control node NQ, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0145] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0146] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control node NQ.

[0147] The seventh transistor T7 may include a gate electrode that receives the second clock signal CLK2, a first electrode that receives a relatively high gate voltage VGH, and a second electrode that is connected to the first electrode of the second transistor T2.

[0148] Therefore, the gate driver 300 may include six transistors, two capacitors, two clock signals, and a gate voltage. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0149] Figure 12 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0150] refer to Figure 12 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0151] The input circuit can provide the input signal IN to control nodes NQ1 and NQ2 in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. A first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltages of control nodes NQ1 and NQ2, and the first inverting control circuit may include a second transistor T2 and a seventh transistor T7. A second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of control nodes NQ1 and NQ2 and the voltage of the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Each stage may further include a node partitioning circuit. Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2, and a node partitioning circuit may be disposed between the first control node NQ1 and the second control node NQ2 to partition the first control node NQ1 and the second control node NQ2, and the node partitioning circuit may include a sixth transistor T6. The first transistor T1 to the seventh transistor T7 may be PMOS transistors.

[0152] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to control nodes NQ1 and NQ2.

[0153] The second transistor T2 may include a gate electrode connected to control nodes NQ1 and NQ2, a first electrode, and a second electrode connected to the inverting control node NQB.

[0154] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive the first clock signal CLK1.

[0155] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0156] The fifth transistor T5 may include a gate electrode connected to control nodes NQ1 and NQ2, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0157] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0158] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control nodes NQ1 and NQ2.

[0159] The seventh transistor T7 may include a gate electrode that receives the second clock signal CLK2, a first electrode that receives a relatively high gate voltage VGH, and a second electrode that is connected to the first electrode of the second transistor T2.

[0160] Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2.

[0161] The sixth transistor T6 may include a gate electrode for receiving the first clock signal CLK1, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2.

[0162] Therefore, the gate driver 300 may include seven transistors, two capacitors, two clock signals, and a gate voltage. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0163] Figure 13 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0164] refer to Figure 13 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0165] The input circuit can provide the input signal IN to the control node NQ in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. The first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltage of the control node NQ, and the first inverting control circuit may include a second transistor T2 and a seventh transistor T7. The second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of the control node NQ and the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. The first transistors T1 to T5 and the seventh transistor T7 may be PMOS transistors.

[0166] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to a control node NQ.

[0167] The second transistor T2 may include a gate electrode connected to the control node NQ, a first electrode, and a second electrode connected to the inverting control node NQB.

[0168] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive a relatively low gate voltage VGL.

[0169] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0170] The fifth transistor T5 may include a gate electrode connected to the control node NQ, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0171] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0172] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control node NQ.

[0173] The seventh transistor T7 may include a gate electrode that receives the second clock signal CLK2, a first electrode that receives a relatively high gate voltage VGH, and a second electrode that is connected to the first electrode of the second transistor T2.

[0174] Therefore, the gate driver 300 may include six transistors, two capacitors, two clock signals, and two gate voltages. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0175] Figure 14 It is shown Figure 2 The circuit diagram of an embodiment of the level.

[0176] refer to Figure 14 The gate driver 300 in the embodiments of the present invention may include multiple stages. Each stage may include an input circuit, a first inverting control circuit, a second inverting control circuit, and a gate output circuit.

[0177] The input circuit can provide the input signal IN to control nodes NQ1 and NQ2 in response to the first clock signal CLK1, and the input circuit may include a first transistor T1. A first inverting control circuit can control the voltage of the inverting control node NQB in response to the voltages of control nodes NQ1 and NQ2, and the first inverting control circuit may include a second transistor T2 and a seventh transistor T7. A second inverting control circuit can control the voltage of the inverting control node NQB in response to the first clock signal CLK1, and the second inverting control circuit may include a third transistor T3. The gate output circuit can output the gate signal GS in response to the voltages of control nodes NQ1 and NQ2 and the voltage of the inverting control node NQB, and the gate output circuit may include a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Each stage may further include a node partitioning circuit. Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2. A node partitioning circuit may be disposed between the first control node NQ1 and the second control node NQ2 to partition the first control node NQ1 and the second control node NQ2. The node partitioning circuit may include a sixth transistor T6. The first transistor T1 to the seventh transistor T7 may be PMOS transistors.

[0178] The first transistor T1 may include a gate electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal IN, and a second electrode connected to control nodes NQ1 and NQ2.

[0179] The second transistor T2 may include a gate electrode connected to control nodes NQ1 and NQ2, a first electrode, and a second electrode connected to the inverting control node NQB.

[0180] The third transistor T3 may include a gate electrode for receiving the first clock signal CLK1, a first electrode, and a second electrode connected to the inverting control node NQB. In an embodiment, the first electrode of the third transistor T3 may receive a relatively low gate voltage VGL.

[0181] The fourth transistor T4 may include a gate electrode connected to the inverting control node NQB, a first electrode receiving a relatively high gate voltage VGH, and a second electrode connected to the gate output node NGS from which it outputs the gate signal GS.

[0182] The fifth transistor T5 may include a gate electrode connected to control nodes NQ1 and NQ2, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS.

[0183] The first capacitor C1 may include a first electrode that receives a relatively high gate voltage VGH and a second electrode that is connected to the inverting control node NQB.

[0184] The second capacitor C2 may include a first electrode connected to the gate output node NGS and a second electrode connected to the control nodes NQ1 and NQ2.

[0185] The seventh transistor T7 may include a gate electrode that receives the second clock signal CLK2, a first electrode that receives a relatively high gate voltage VGH, and a second electrode that is connected to the first electrode of the second transistor T2.

[0186] Control nodes NQ1 and NQ2 may include a first control node NQ1 and a second control node NQ2.

[0187] The sixth transistor T6 may include a gate electrode that receives a relatively low gate voltage VGL, a first electrode connected to a first control node NQ1, and a second electrode connected to a second control node NQ2.

[0188] Therefore, the gate driver 300 may include seven transistors, two capacitors, two clock signals, and two gate voltages. Accordingly, the construction can be simplified, and the power consumption and dead time of the gate driver 300 can be reduced.

[0189] Figure 15 This is a block diagram showing the electronic device 1000. Figure 16 It is shown that Figure 15 The diagram shows an embodiment of the electronic device 1000 implemented as a smartphone.

[0190] refer to Figure 15 and Figure 16 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be… Figure 1The display device 10. Additionally, the electronic device 1000 may further include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, or other electronic devices.

[0191] In an embodiment, such as Figure 16 As described herein, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited thereto. In embodiments, for example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet personal computer (“PC”), car navigation system, computer monitor, laptop computer, or head-mounted display (“HMD”) device, etc.

[0192] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, a central processing unit (“CPU”), or an application processor (“AP”), etc. Processor 1010 can be connected to other components via address buses, control buses, or data buses, etc. In addition, processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0193] The memory device 1020 can store data for the operation of the electronic device 1000. In embodiments, for example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device.

[0194] Storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or an optical disc read-only memory (“CD-ROM”) device, etc.

[0195] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, or touchscreen, or output devices such as a printer or speaker. In some embodiments, I / O device 1040 may include display device 1060.

[0196] Power supply 1050 can provide power for the operation of electronic device 1000.

[0197] The display device 1060 can be connected to other components via a bus or other communication link.

[0198] The inventive concept can be applied to any display device and any electronic device, including touch panels. In embodiments, for example, the inventive concept can be applied to mobile phones, smartphones, tablet computers, digital televisions (“TV”), three-dimensional (“3D”) televisions, personal computers (“PC”), home appliances, laptop computers, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0199] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. Although some embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the clauses "mean plus function" are intended to cover structures described herein that perform the detailed functions, covering not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting it to the disclosed illustrative embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the claims. The inventive concept is defined by the claims, and equivalents of the claims should be included therein.

Claims

1. A gate driver comprising multiple stages, each of the multiple stages comprising: The input circuit is configured to provide an input signal to the control node in response to a first clock signal; The first inverting control circuit is configured to control the voltage of the inverting control node in response to the voltage of the control node; as well as The gate output circuit is configured to output a gate signal in response to the voltage of the control node and the voltage of the inverting control node.

2. The gate driver according to claim 1, wherein, The input circuit includes a first transistor, which includes a gate electrode for receiving the first clock signal, a first electrode for receiving the input signal, and a second electrode connected to the control node. The first inverting control circuit includes a second transistor, the second transistor including a gate electrode connected to the control node, a first electrode, and a second electrode connected to the inverting control node, and The gate output circuit includes: The fourth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving a first gate voltage having a relatively high first level, and a second electrode connected to a gate output node from which the gate signal is output; and The fifth transistor includes a gate electrode connected to the control node, a first electrode for receiving a second clock signal, and a second electrode connected to the gate output node.

3. The gate driver according to claim 2, wherein, Each of the plurality of stages further includes a second inverting control circuit configured to control the voltage of the inverting control node in response to the first clock signal, and The second inverting control circuit includes a third transistor, which includes a gate electrode for receiving the first clock signal, a first electrode, and a second electrode connected to the inverting control node.

4. The gate driver according to claim 3, wherein, The first to the fifth transistors are p-type metal-oxide-semiconductor transistors.

5. The gate driver according to claim 3, wherein, The gate output circuit further includes a first capacitor, the first capacitor including a first electrode receiving the first gate voltage and a second electrode connected to the inverting control node.

6. The gate driver according to claim 3, wherein, The gate output circuit further includes a second capacitor, the second capacitor including a first electrode connected to the gate output node and a second electrode connected to the control node.

7. The gate driver according to claim 3, wherein, The first electrode of the second transistor receives the first clock signal, and the first electrode of the third transistor also receives the first clock signal.

8. The gate driver according to claim 7, wherein, The control nodes include a first control node and a second control node. Each of the plurality of levels further includes a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node, and The node partitioning circuit includes a sixth transistor, which includes a gate electrode for receiving the first clock signal, a first electrode connected to the first control node, and a second electrode connected to the second control node.

9. The gate driver according to claim 3, wherein, The first electrode of the second transistor receives the first clock signal, and the first electrode of the third transistor receives a second gate voltage having a second level lower than the first level of the first gate voltage.

10. The gate driver according to claim 9, wherein, The control nodes include a first control node and a second control node. Each of the plurality of levels further includes a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node, and The node partitioning circuit includes a sixth transistor, which includes a gate electrode for receiving the second gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

11. The gate driver according to claim 3, wherein, The first electrode of the third transistor receives the first clock signal, and The first inverting control circuit further includes a seventh transistor, the seventh transistor including a gate electrode for receiving the second clock signal, a first electrode for receiving the first gate voltage, and a second electrode connected to the first electrode of the second transistor.

12. The gate driver according to claim 11, wherein, The control nodes include a first control node and a second control node. Each of the plurality of levels further includes a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node, and The node partitioning circuit includes a sixth transistor, which includes a gate electrode for receiving the first clock signal, a first electrode connected to the first control node, and a second electrode connected to the second control node.

13. The gate driver according to claim 3, wherein, The first electrode of the third transistor receives a second gate voltage having a second level lower than the first level of the first gate voltage, and The first inverting control circuit further includes a seventh transistor, the seventh transistor including a gate electrode for receiving the second clock signal, a first electrode for receiving the first gate voltage, and a second electrode connected to the first electrode of the second transistor.

14. The gate driver according to claim 13, wherein, The control nodes include a first control node and a second control node. Each of the plurality of levels further includes a node partitioning circuit disposed between the first control node and the second control node and configured to partition the first control node and the second control node, and The node partitioning circuit includes a sixth transistor, which includes a gate electrode for receiving the second gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.

15. A gate driver comprising multiple stages, each of the multiple stages comprising: The first transistor includes a gate electrode for receiving a first clock signal, a first electrode for receiving an input signal, and a second electrode connected to a control node; The second transistor includes a gate electrode connected to the control node, a first electrode, and a second electrode connected to the inverting control node; The fourth transistor includes a gate electrode connected to the inverting control node, a first electrode receiving a first gate voltage having a relatively high first level, and a second electrode connected to a gate output node from which it outputs a gate signal; as well as The fifth transistor includes a gate electrode connected to the control node, a first electrode for receiving a second clock signal, and a second electrode connected to the gate output node.

16. The gate driver according to claim 15, wherein, Each of the plurality of stages further includes a third transistor, the third transistor including a gate electrode for receiving the first clock signal, a first electrode, and a second electrode connected to the inverting control node.

17. The gate driver according to claim 15, wherein, Each of the plurality of stages further includes a first capacitor, the first capacitor including a first electrode receiving the first gate voltage and a second electrode connected to the inverting control node.

18. An electronic device comprising: The display device includes: Display panel, including pixels; A data driver is configured to provide a data voltage to the pixel; The gate driver according to any one of claims 1-17 is configured to provide a gate signal to the pixel; and A drive controller is configured to control the data driver and the gate driver.

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