Display panel and display device

Abstract

The invention provides a display panel and a display device. The gate drive circuit of the display panel comprises a plurality of gate drive parts, a signal generation part of each gate drive part comprises a level transmission module and a level transmission signal line, and each level transmission signal line comprises a first level transmission section, a second level transmission section and a third level transmission section which are continuous; according to the invention, the first stage transmission section electrically connected with the (n-x) th stage signal generation part, the second stage transmission section electrically connected with the output end of the nth stage transmission module, and the third stage transmission section electrically connected with the (n + y) th stage signal generation part are continuous stage transmission signal lines; the level transmission signal output by the nth level can be simultaneously transmitted to the first level transmission section and the third level transmission section through the second level transmission section, the arrangement of connecting via holes is reduced, the situation that a level transmission signal line for uploading and a level transmission signal line for downloading are independent transmission lines is avoided, the space occupied by the level transmission signal lines is reduced, and the transmission efficiency is improved. The width of the gate drive circuit is reduced, and the narrow frame design of the display panel is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] To achieve a narrow bezel design, current display panels use gate drive circuits instead of gate drive chips to drive pixel circuits. Gate drive circuits include thin-film transistors and signal traces, with the signal traces connected to the thin-film transistors via connecting lines. However, current gate drive circuits still occupy a relatively large space. Summary of the Invention

[0003] This application provides a display panel and a display device to solve the technical problem that the gate driving circuit of existing display panels occupies a large space.

[0004] This application provides a display panel including a gate driving circuit, the gate driving circuit including N cascaded gate driving sections; wherein, the nth stage gate driving section includes: Output section; A signal generation unit is electrically connected to the output unit at the first control node, and the signal generation unit includes a transmission module. A series of transmission signal lines, including a continuous first-stage transmission segment, a second-stage transmission segment, and a third-stage transmission segment; Wherein, the end of the first-level transmission segment furthest from the second-level transmission segment is electrically connected to the signal generation unit of the nx-th level, the second-level transmission segment is electrically connected to the output terminal of the transmission module of the n-th level, and the end of the third-level transmission segment furthest from the second-level transmission segment is electrically connected to the signal generation unit of the n+y-th level. n, x, y, and N are all positive integers, and n is less than or equal to N and greater than x.

[0005] Meanwhile, embodiments of this application provide a display device, which includes the display panel as described above.

[0006] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0009] Figure 1 This is a first structural diagram of the display panel of this application.

[0010] Figure 2 This is a first circuit diagram of the gate driving section in the display panel of this application.

[0011] Figure 3 This is a second circuit diagram of the gate driving section in the display panel of this application.

[0012] Figure 4 This is a diagram of the film structure in the display panel of this application.

[0013] Figure 5 for Figure 2 The circuit diagram shown is a film layer stack diagram.

[0014] Figure 6 for Figure 3 The circuit diagram shown is a first part of a film layer stacking diagram.

[0015] Figure 7 for Figure 3 The second part of the circuit diagram shown is a film stack diagram.

[0016] Figure 8 for Figure 3 The circuit diagram shown is a third part of the film stack diagram.

[0017] Figure 9 for Figure 3 The fourth part of the circuit diagram shown is a film stack diagram. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0019] Please see Figures 1 to 9 This application proposes a display panel 100, which includes a gate driving circuit 300, the gate driving circuit 300 including N cascaded gate driving sections 300A.

[0020] In this embodiment, the gate driving section 300A of the nth stage includes a transmission signal line ST, an output section 300a and a signal generation section 300b. The signal generation section 300b and the output section 300a are electrically connected to the first control node Q. The signal generation section 300b includes a transmission module 50.

[0021] In this embodiment, the cascade signal line ST includes a continuous first-stage transmission segment STa, a second-stage transmission segment STb, and a third-stage transmission segment STc. The end of the first-stage transmission segment STa away from the second-stage transmission segment STb is electrically connected to the signal generation unit 300b of the nx-th stage. The second-stage transmission segment STb is electrically connected to the output terminal of the cascade module 50 of the n-th stage. The end of the third-stage transmission segment STc away from the second-stage transmission segment STb is electrically connected to the signal generation unit 300b of the n+y-th stage. n, x, y, and N are all positive integers, and n is less than or equal to N and greater than x.

[0022] It should be noted that the current gate drive circuit 300 includes an up-level transmission line ST and a down-level transmission line. The up-level transmission line is used to transmit the transmission signal of this stage to the gate drive circuit 300 of an upper stage, such as the gate drive circuit 300 of the n+y stage. The down-level transmission line is used to transmit the transmission signal of this stage to the gate drive circuit 300 of an lower stage, such as the gate drive circuit 300 of the nx stage. The up-level transmission line and the down-level transmission line are usually two independent transmission lines. Therefore, the transmission signal of this stage needs to be electrically connected to the up-level transmission line and the down-level transmission line through two sets of connecting vias to transmit the transmission signal of this stage downward and upward. Due to the setting of connecting vias and the setting of two independent transmission lines, the current gate drive circuit occupies a large space, which is contrary to the current narrow bezel design.

[0023] This application achieves a narrow bezel design for the display panel 100 by making the first stage transmission segment STa, which is electrically connected to the signal generation unit 300b of the nx stage, the second stage transmission segment STb, which is electrically connected to the output terminal of the stage transmission module 50 of the nth stage, and the third stage transmission segment STc, which is electrically connected to the signal generation unit 300b of the n+y stage, continuous stage transmission signal lines ST. The stage transmission signal output from the nth stage can be simultaneously transmitted to the first stage transmission segment STa and the third stage transmission segment STc through the second stage transmission segment STb. This reduces the number of connection vias and avoids the stage transmission signal lines ST used for uplink and downlink being independent transmission lines. This reduces the space occupied by the stage transmission signal lines ST and the width of the gate drive circuit 300.

[0024] In this embodiment, the output unit 300a includes a pull-up module 20, and the signal generation unit 300b includes a pull-up control module 10, a pull-down module 30, and a pull-down sustaining module 40. The pull-up module 20, the pull-down module 30, and the pull-up control module 10 are all electrically connected to the first control node Q, and the pull-down sustaining module 40 is electrically connected to the first control node Q and the output terminal of the pull-up module 20.

[0025] In this embodiment, the end of the first-level transmission segment STa that is away from the second-level transmission segment STb is electrically connected to the control terminal of the nx-th level pull-up control module 10, and the end of the third-level transmission segment STc that is away from the second-level transmission segment STb is electrically connected to the control terminal of the n+y-th level pull-down module 30.

[0026] For example, in Figure 2 In the structure, the end of the first-level transmission segment STa of the nth level that is far away from the second-level transmission segment STb is electrically connected to the control terminal of the pull-up control module 10 of the n-4th level, and the end of the third-level transmission segment STc of the nth level that is far away from the second-level transmission segment STb is electrically connected to the control terminal of the pull-down module 30 of the n+6th level.

[0027] For example, in Figure 3 In the structure, the end of the first-level transmission segment STa of the nth level that is far away from the second-level transmission segment STb is electrically connected to the control terminal of the pull-up control module 10 of the n-6th level, and the end of the third-level transmission segment STc of the nth level that is far away from the second-level transmission segment STb is electrically connected to the control terminal of the pull-down module 30 of the n+8th level.

[0028] The technical solution of this application will now be described in conjunction with specific embodiments.

[0029] Please see Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA has multiple rows of sub-pixels PL. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0030] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0031] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be mTnC, and this application does not impose specific limitations.

[0032] Please see Figure 1A gate driving circuit 300 can be disposed in the non-display area NA, and the gate driving circuit 300 can be disposed on both sides or one side of the display area AA; the gate driving circuit 300 can include N cascaded gate driving units 300A, and the multiple gate driving units 300A can be arranged along the first direction X, and the structure of the gate driving unit 300A can be various.

[0033] Please see Figure 2 The gate drive section 300A of the nth stage may include a pull-up control module 10, a first capacitor C1, a second capacitor C2, a pull-up module 20, a pull-down module 30, a pull-down sustaining module 40, and a stage transmission module 50. The pull-up control module 10 and the pull-up module 20 are connected to the first control node Q(n), the pull-down module 30 is electrically connected to the first control node Q(n) and the first low potential line VSSQ, and the pull-down sustaining module 40 is electrically connected to the first control node Q(n) and the second low potential line VSSG.

[0034] In this embodiment, the pull-up control module 10 is used to pull the first control node Q(n) high to a first high potential and to charge the first capacitor C1 and the second capacitor C2; the first capacitor C1 and the second capacitor C2 are used to maintain the potential of the first control node Q(n); the pull-up module 20 is used to output a first gate drive signal to the gate signal terminal G(n) of the nth stage and to output a second gate drive signal to the gate signal terminal G(n+1) of the (n+1)th stage; the pull-down module 30 is used to pull the potential of the first control node Q(n) low to a first low potential; the pull-down maintenance module 40 is used to pull the potential of the gate signal terminal G(n) of the nth stage low to a second low potential and to pull the potential of the gate signal terminal G(n+1) of the (n+1)th stage low to a second low potential.

[0035] Please see Figure 2 The pull-up control module 10 is connected to the stage transmission signal terminal ST(n-4) of the (n-4)th stage, the first control node Q(n), the first high potential line VGH, and the pull-down sustaining module 40. The stage transmission signal terminal ST(n-4) of the (n-4)th stage is used to output the first stage transmission signal. The pull-up control module 10 includes a pull-up control transistor T11A. The gate of the pull-up control transistor T11A is connected to the stage transmission signal terminal ST(n-4) of the (n-4)th stage, the source of the pull-up control transistor T11A is connected to the first high potential line VGH, and the drain of the pull-up control transistor T11A is connected to the first control node Q(n) and the pull-down sustaining module 40.

[0036] Please see Figure 2The pull-up module 20 includes a first pull-up unit 210 and a second pull-up unit 220. The first pull-up unit 210 is connected to the first control node Q(n), the clock signal line CK(n) of the nth stage, and the gate signal terminal G(n) of the nth stage. The second pull-up unit 220 is connected to the first control node Q(n), the clock signal line CK(n+1) of the (n+1)th stage, and the gate signal terminal G(n+1) of the (n+1)th stage. The clock signal line CK(n) of the nth stage is used to provide a first clock signal, and the clock signal line CK(n+1) of the (n+1)th stage is used to provide a second clock signal.

[0037] Please see Figure 2 The first pull-up unit 210 includes a first pull-up transistor T21A, the gate of the first pull-up transistor T21A is connected to the first control node Q(n), the source of the first pull-up transistor T21A is connected to the clock signal line CK(n) of the nth stage, and the drain of the first pull-up transistor T21A is connected to the gate signal terminal G(n) of the nth stage.

[0038] In this embodiment, the second pull-up unit 220 includes a second pull-up transistor T23A. The gate of the second pull-up transistor T23A is connected to the first control node Q(n), the source of the second pull-up transistor T23A is connected to the clock signal line CK(n+1) of the (n+1)th stage, and the drain of the second pull-up transistor T23A is connected to the gate signal terminal G(n+1) of the (n+1)th stage.

[0039] Please see Figure 2 The stage transmission module 50 includes a stage transmission transistor T22A; the gate of the stage transmission transistor T22A is connected to the first control node Q(n), the source of the stage transmission transistor T22A is connected to the first clock signal line, and the drain of the stage transmission transistor T22A is connected to the stage transmission signal terminal ST(n) of the nth stage.

[0040] Please see Figure 2 The pull-down module 30 includes a pull-down transistor T41A. The gate of the pull-down transistor T41A is connected to the stage transmission signal terminal ST(n+6) of the (n+6)th stage. The source of the pull-down transistor T41A is connected to the first control node Q(n). The drain of the pull-down transistor T41A is connected to the first low potential line VSSQ. The stage transmission signal terminal ST(n+6) of the (n+6)th stage is used to provide the second stage transmission signal.

[0041] Please see Figure 2 The pull-down sustaining module 40 includes an inverter 410 and a voltage regulation unit 420. The voltage regulation unit 420 and the inverter 410 are connected to the second control node P(n). The inverter 410 is used to control the potential of the second control node P(n).

[0042] In this embodiment, the voltage regulation unit 420 includes a first regulation transistor T32A, a second regulation transistor T33A, a third regulation transistor T42A, a fourth regulation transistor T43A, and a fifth regulation transistor T72A.

[0043] The gate of the first regulating transistor T32A is connected to the second control node P(n), the source of the first regulating transistor T32A is connected to the gate signal terminal G(n) of the nth stage, and the drain of the first regulating transistor T32A is connected to the second low potential line VSSG; the gate of the second regulating transistor T33A is connected to the second control node P(n), the source of the second regulating transistor T33A is connected to the gate signal terminal G(n+1) of the (n+1)th stage, and the drain of the second regulating transistor T33A is connected to the first low potential line VSSQ; the gate of the third regulating transistor T42A is connected to the second control node P(n). The source of the third regulating transistor T42A is connected to the first control node Q(n), and the drain of the third regulating transistor T42A is connected to the first low potential line VSSQ; the gates of the fourth regulating transistor T43A and the fifth regulating transistor T72A are connected to the second control node P(n), the source of the fourth regulating transistor T43A is connected to the first control node Q(n), the drains of the fourth regulating transistor T43A and the source of the fifth regulating transistor T72A are connected to the stage transmission signal terminal ST(n) of the nth stage, and the drain of the fifth regulating transistor T72A is connected to the first low potential line VSSQ.

[0044] Please see Figure 2The inverter 410 includes a first inverter transistor T51A, a second inverter transistor T52A, a third inverter transistor T53A, a fourth inverter transistor T54A, a sixth inverter transistor T56A, and a fifth inverter transistor T55A. The gate of the first inverter transistor T51A is connected to the clock signal line CK(n+6) of the (n+6)th stage. The sources of the first inverter transistor T51A and the third inverter transistor T53A are connected to the second high-potential line VDD. The drain of the first inverter transistor T51A and the gate of the third inverter transistor T53A are connected to the third control node S(n), and the drain of the third inverter transistor T53A is connected to the second control node P(n). The gate of the second inverter transistor T52A and the gate of the fourth inverter transistor T55A are connected to the clock signal line CK(n+6) of the (n+6)th stage. The gate of transistor 4A is connected to the first control node Q(n), the source of the second inverting transistor T52A is connected to the third control node S(n), the source of the fourth inverting transistor T54A and the source of the sixth inverting transistor T56A are connected to the second control node P(n), and the drain of the second inverting transistor T52A, the drain of the fourth inverting transistor T54A and the drain of the sixth inverting transistor T56A are connected to the first low potential line VSSQ; the gate of the fifth inverting transistor T55A and the gate of the sixth inverting transistor T56A are connected to the clock signal line CK(n+2) of the (n+2)th stage, the source of the fifth inverting transistor T55A is connected to the third control node S(n), and the drain of the fifth inverting transistor T55A is connected to the first low potential line VSSQ.

[0045] In this embodiment, the clock signal line CK(n+6) of the (n+6)th stage is used to output the third clock signal, and the clock signal line CK(n+2) of the (n+2)th stage is used to output the fourth clock signal. The third clock signal and the fourth clock signal are mutually coupled signals.

[0046] Please see Figure 2 The inverter 410 also includes a first reset transistor T44A and a second reset transistor T45A. The gate of the second reset transistor T45A is connected to the reset signal line Rest, the source of the second reset transistor T45A is connected to the second high potential line VDD, and the drain of the second reset transistor T45A is connected to the second control node P(n). The gate of the first reset transistor T44A is connected to the reset signal line Rest, the source of the first reset transistor T44A is connected to the first low potential line VSSQ, and the drain of the first reset transistor T44A is connected to the first control node Q(n).

[0047] Please see Figure 2One plate of the first capacitor C1 is connected to the first control node Q(n) and the pull-up module 20, and the other plate of the first capacitor C1 is connected to the gate signal terminal G(n) of the nth stage; one plate of the second capacitor C2 is connected to the first control node Q(n) and the pull-up module 20, and the other plate of the second capacitor C2 is connected to the gate signal terminal G(n+1) of the (n+1)th stage.

[0048] Please see Figure 3 The gate drive section 300A of the nth stage may include a pull-up control module 10, a bootstrap capacitor Cst, a pull-up module 20, a pull-down module 30, a pull-down sustaining module 40, and a stage transmission module 50. The pull-up control module 10 and the pull-up module 20 are connected to the first control node Q(n), the pull-down module 30 is electrically connected to the first control node Q(n) and the first low potential line VSSQ, and the pull-down sustaining module 40 is electrically connected to the first control node Q(n) and the second low potential line VSSG.

[0049] In this embodiment, the pull-up control module 10 is used to pull the first control node Q(n) high to a first high potential and charge the bootstrap capacitor Cst; the bootstrap capacitor Cst is used to maintain the potential of the first control node Q(n); the pull-up module 20 is used to output a first gate drive signal to the gate signal terminal G(n) of the nth stage and a second gate drive signal to the gate signal terminal G(n+1) of the (n+1)th stage; the pull-down module 30 is used to pull the potential of the first control node Q(n) low to a first low potential; and the pull-down maintenance module 40 is used to pull the potential of the gate signal terminal G(n) of the nth stage low to a second low potential.

[0050] Please see Figure 3 The nth stage pull-up control module 10 is connected to the stage transmission signal terminal ST(n-6) of the n-6th stage, the first control node Q(n), the first high potential line VGH, and the pull-down sustaining module 40. The stage transmission signal terminal ST(n-6) of the n-6th stage is used to output the first stage transmission signal. The pull-up control module 10 includes a pull-up control transistor T11B. The gate of the pull-up control transistor T11B is connected to the stage transmission signal terminal ST(n-6) of the n-6th stage, the source of the pull-up control transistor T11B is connected to the first high potential line VGH, and the drain of the pull-up control transistor T11B is connected to the first control node Q(n) and the pull-down sustaining module 40.

[0051] Please see Figure 3 The nth stage pull-up module 20 includes a first pull-up transistor T21B, the gate of the first pull-up transistor T21B is connected to the first control node Q(n), the source of the first pull-up transistor T21B is connected to the clock signal line CK(n) of the nth stage, and the drain of the first pull-up transistor T21B is connected to the gate signal terminal G(n) of the nth stage.

[0052] Please see Figure 3 The nth stage transmission module 50 includes a transmission transistor T22B; the gate of the transmission transistor T22B is connected to the first control node Q(n), the source of the transmission transistor T22B is connected to the first clock signal line, and the drain of the transmission transistor T22B is connected to the nth stage transmission signal terminal ST(n).

[0053] Please see Figure 3 The nth stage pull-down module 30 includes a pull-down transistor T41B. The gate of the pull-down transistor T41B is connected to the stage transmission signal terminal ST(n+8) of the (n+8)th stage. The source of the pull-down transistor T41B is connected to the first control node Q(n). The drain of the pull-down transistor T41B is connected to the first low potential line VSSQ. The stage transmission signal terminal ST(n+8) of the (n+8)th stage is used to provide the second stage transmission signal.

[0054] Please see Figure 3 The nth-level pull-down sustaining module 40 includes an inverter 410 and a voltage regulation unit 420. The voltage regulation unit 420 and the inverter 410 are connected to the second control node P(n). The inverter 410 is used to control the potential of the second control node P(n).

[0055] In this embodiment, the voltage regulation unit 420 includes a first regulation transistor T32B, a second regulation transistor T33B, a third regulation transistor T42B, a fourth regulation transistor T43B, a fifth regulation transistor T72B, and a sixth regulation transistor T73B.

[0056] In the voltage regulation unit 420 of the nth stage, the gate of the first regulating transistor T32B is connected to the second control node P(n) of the nth stage, the source of the first regulating transistor T32B is connected to the gate signal terminal G(n) of the nth stage, and the drain of the first regulating transistor T32B is connected to the second low potential line VSSG; the gate of the third regulating transistor T42B is connected to the second control node P(n) of the nth stage, the source of the third regulating transistor T42B is connected to the first control node Q(n), and the drain of the third regulating transistor T42B is connected to the first low potential line VSSQ; the gate of the fifth regulating transistor T72B is connected to the second control node P(n) of the nth stage, the source of the fifth regulating transistor T72B is connected to the stage transmission signal terminal ST(n) of the nth stage, and the drain of the fifth regulating transistor T72B is connected to the second low potential line VSSG.

[0057] In the voltage regulation unit 420 of the nth stage, the gate of the second regulating transistor T33B is connected to the second control node P(n+1) of the (n+1)th stage, the source of the second regulating transistor T33B is connected to the gate signal terminal G(n) of the nth stage, and the drain of the second regulating transistor T33B is connected to the second low potential line VSSG; the gate of the fourth regulating transistor T43B is connected to the second control node P(n+1) of the (n+1)th stage, the source of the fourth regulating transistor T43B is connected to the first control node Q(n), and the drain of the fourth regulating transistor T43B is connected to the first low potential line VSSQ; the gate of the sixth regulating transistor T73B is connected to the second control node P(n+1) of the (n+1)th stage, the source of the sixth regulating transistor T73B is connected to the stage transmission signal terminal ST(n) of the nth stage, and the drain of the sixth regulating transistor T73B is connected to the second low potential line VSSG.

[0058] In this embodiment, the voltage regulation unit 420 of the nth stage and the voltage regulation unit 420 of the (n+1)th stage have the same or similar structures, except that the gates of the second regulation transistor T33C, the fourth regulation transistor T43C and the sixth regulation transistor T73C are all connected to the second control node P(n) of the nth stage.

[0059] Please see Figure 3 The nth stage inverter 410 includes a first inverter transistor T51B, a second inverter transistor T52B, a third inverter transistor T53B, a fourth inverter transistor T54B, a sixth inverter transistor T56B, and a fifth inverter transistor T55B.

[0060] In the nth stage inverter 410, the gate of the first inverter transistor T51B is connected to the first inverting signal line LC1, the source of the first inverter transistor T51B and the source of the third inverter transistor T53B are connected to the first inverting signal line LC1, the drain of the first inverter transistor T51B and the gate of the third inverter transistor T53B are connected to the third control node S, and the drain of the third inverter transistor T53B is connected to the second control node P(n).

[0061] In the nth stage inverter 410, the gates of the second inverter transistor T52B and the fourth inverter transistor T54B are connected to the first control node Q(n), the source of the second inverter transistor T52B is connected to the third control node S(n), the source of the fourth inverter transistor T54B and the source of the sixth inverter transistor T56B are connected to the second control node P(n), and the drains of the second inverter transistor T52B, the fourth inverter transistor T54B, and the sixth inverter transistor T56B are connected to the first low potential line VSSQ.

[0062] In the nth stage inverter 410, the gate of the fifth inverter transistor T55B is connected to the first control node Q(n+1) of the (n+1)th stage, the gate of the sixth inverter transistor T56B is connected to the first control node Q(n-2) of the (n-2)th stage, the source of the fifth inverter transistor T55B is connected to the third control node S(n), and the drain of the fifth inverter transistor T55B is connected to the first low potential line VSSQ.

[0063] The inverter 410 of the (n+1)th stage is the same as or similar to the inverter 410 of the nth stage, except that: the gate of the first inverter transistor T51C, the source of the first inverter transistor T51C, and the source of the third inverter transistor T53C are connected to the second inverting signal line LC2; the gate of the fifth inverter transistor T55C is connected to the first control node Q(n) of the nth stage; and the gate of the sixth inverter transistor T56C is connected to the first control node Q(n-1) of the (n-1)th stage.

[0064] In this embodiment, the phases of the inverted signals output by the first inverted signal line LC1 and the second inverted signal line LC2 are opposite.

[0065] Please see Figure 3 The inverter 410 also includes a first reset transistor T44B, the gate of which is connected to the reset signal line Rest, the source of which is connected to the first low potential line VSSQ, and the drain of which is connected to the first control node Q(n).

[0066] Please see Figure 3 One plate of the bootstrap capacitor Cst of the nth stage is connected to the first control node Q(n) and the pull-up module 20, and the other plate of the bootstrap capacitor Cst is connected to the gate signal terminal G(n) of the nth stage.

[0067] It should be noted that, in order to distinguish the transistors in the gate driving section 300A of the nth stage and the gate driving section 300A of the (n+1)th stage, the transistors in the gate driving section 300A of the nth stage are identified by the letter "B" and the transistors in the gate driving section 300A of the (n+1)th stage are identified by the letter "C".

[0068] It should be noted that some transistors in this application adopt a single-gate design and some adopt a dual-gate design. For transistors with a single-gate design, the gate is its only gate. For transistors with a dual-gate design, the gate refers to the bottom gate and the top gate.

[0069] It should be noted that in this application, the source is one of the input and output terminals of the transistor, and the drain is the other of the input and output terminals of the transistor. The source and drain in this application can be interchanged.

[0070] The following is about Figure 2 and Figure 3 The structure of the film layer of the display panel 100 of this application is described.

[0071] Please see Figure 4 The display area AA and the non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. The film structure in the non-display area NA is described below.

[0072] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0073] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0074] Please see Figure 4 The array driving layer 120 may include multiple thin-film transistors (TFTs). These TFTs may be etch-block type, back-channel etch type, or classified according to the position of the gate and active layer as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 4 The thin-film transistor in the text does not represent Figure 2 and Figure 3 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of this application.

[0075] Please see Figure 4 The array driving layer 120 may include a gate layer 113 disposed on the substrate 110, an inter-insulating layer 114 disposed on the gate layer 113, an active layer 115 disposed on the inter-insulating layer 114, a source-drain layer 116 disposed on the active layer 115, a passivation layer 117 disposed on the source-drain layer 116, and a pixel electrode layer 118 disposed on the passivation layer 117.

[0076] In this embodiment, the materials of the gate layer 113 and the source / drain layer 116 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals; for example, the material of the gate layer 113 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0077] In this embodiment, the materials of the inter-insulating layer 114 and the passivation layer 117 can both be composed of compounds consisting of nitrogen, silicon and oxygen elements. For example, they can be single-layer silicon oxide, silicon oxide film, or stacked structures such as silicon oxide, silicon nitride, and aluminum oxide.

[0078] In this embodiment, the active layer 115 can be made of silicon semiconductor, such as polycrystalline silicon or low-temperature polycrystalline silicon; or, the active layer 115 can be made of oxide semiconductor, such as indium gallium zinc oxide semiconductor or other metal oxide semiconductor.

[0079] In this embodiment, the material of the pixel electrode layer 118 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, etc.

[0080] The following section, based on a specific film stacking diagram, discusses... Figure 2 The structure is described.

[0081] Please see Figure 5 The output section 300a and the signal generation section 300b are both arranged along the first direction X, and the transmission signal line ST extends along the second direction Y. The first direction X and the second direction Y intersect, and the output section 300a and the display area AA are arranged adjacent to each other, while the signal generation section 300b is arranged away from the display area AA, so that the gate drive signal generated by the output section 300a can be directly transmitted to the display area AA.

[0082] Please see Figure 5 The pull-up module 20 includes a first pull-up unit 210 and a second pull-up unit 220. The first pull-up unit 210 is used to output the gate drive signal G(n) of the nth stage, and the second pull-up unit 220 is used to output the gate drive signal G(n+1) of the (n+1)th stage. The first pull-up unit 210 and the second pull-up unit 220 are arranged along the second direction Y.

[0083] Please see Figure 5The first pull-up unit 210 and the second pull-up unit 220 are both electrically connected to the signal generation unit 300b. That is, the signal generation unit 300b of the nth stage is shared by the first pull-up unit 210 and the second pull-up unit 220. This means that only one stage of the signal generation unit 300b is needed to output two gate drive signals.

[0084] Please see Figure 5 The first pull-up transistor T21A and the second pull-up transistor T23A may include multiple interconnected pull-up transistor units, that is, the first pull-up transistor T21A and the second pull-up transistor T23A may be composed of multiple pull-up transistor units connected in series.

[0085] Please see Figure 5 The first capacitor C1 and the first pull-up transistor T21A are arranged adjacent to each other, and part of the first capacitor C1 is located between the display area AA and the first pull-up transistor T21A, part of the first capacitor C1 is located on both sides of the first pull-up transistor T21A in the second direction Y, and part of the first capacitor C1 is located between two adjacent pull-up crystal units.

[0086] Please see Figure 5 The second capacitor C2 and the second pull-up transistor T23A are arranged adjacent to each other, and part of the second capacitor C2 is located between the display area AA and the second pull-up transistor T23A, part of the second capacitor C2 is located on both sides of the second pull-up transistor T23A in the second direction Y, part of the second capacitor C2 is located between two adjacent pull-up crystal units, and part of the second capacitor C2 is located on the side of the plurality of pull-up crystal units near the signal generation unit 300b.

[0087] Please see Figure 5 The gate layer 113 includes the gate of the first pull-up transistor T21A, the gate of the second pull-up transistor T23A, the first plate C1a of the first capacitor C1, and the first plate C2a of the second capacitor C2, which are connected to each other. The gates of the first pull-up transistor T21A and the second pull-up transistor T23A are spaced apart along the second direction Y, and both the gate of the first pull-up transistor T21A and the gate of the second pull-up transistor T23A include two pull-up gate units spaced apart along the second direction Y.

[0088] Please see Figure 5The source-drain layer 116 includes the source and drain of the first pull-up transistor T21A, the source and drain of the second pull-up transistor T23A, the second plate C1b of the first capacitor C1, and the second plate C2b of the second capacitor C2. The source and drain of the first pull-up transistor T21A overlap with the gate of the first pull-up transistor T21A, and the source and drain of the second pull-up transistor T23A overlap with the gate of the second pull-up transistor T23A. The second plate C1b of the first capacitor C1 overlaps with the first plate C1a of the first capacitor C1, and the second plate C2b of the second capacitor C2 overlaps with the first plate C2a of the second capacitor C2.

[0089] Please see Figure 5 The source-drain layer 116 also includes a first clock signal line CK(n) and a second clock signal line CK(n+1). The first clock signal line CK(n) is used to transmit a clock signal to the first pull-up transistor T21A of the nth stage, and the second clock signal line CK(n+1) is used to transmit a clock signal to the second pull-up transistor T23A of the nth stage. The first clock signal line CK(n) and the second clock signal line CK(n+1) are located on both sides of the gate driving section 300A of the nth stage in the second direction Y. The first clock signal line CK(n) extends between the two gate units of the first pull-up transistor T21A and is connected to the source T21A of the first pull-up transistor T21A. The second clock signal line CK(n+1) extends between the two gate units of the second pull-up transistor T23A and is connected to the source T23A of the second pull-up transistor T23A.

[0090] It should be noted that each stage of the gate drive section 300A is provided with a first clock signal line CK(n) and a second clock signal line CK(n+1). For ease of description, it can be... Figure 2 and Figure 5 In this context, n is replaced with 2k-1, where k is a positive integer. For example, the first clock signal line CK1 of the first stage is used to transmit the clock signal to the first pull-up transistor T21A of the first stage, and the second clock signal line CK2 of the first stage is used to transmit the clock signal to the second pull-up transistor T23A of the first stage. Similarly, the first clock signal line CK3 of the second stage is used to transmit the clock signal to the first pull-up transistor T21A of the second stage, and the second clock signal line CK4 of the second stage is used to transmit the clock signal to the second pull-up transistor T23A of the second stage. Likewise, the first clock signal line CK(2k-1) of the kth stage is used to transmit the clock signal to the first pull-up transistor T21A of the kth stage, and the second clock signal line CK(2k) of the kth stage is used to transmit the clock signal to the second pull-up transistor T23A of the kth stage.

[0091] In this embodiment, to avoid setting up additional transmission lines for transmitting cascade signals, the cascade signal line ST of this application is located in the area where the signal generation unit 300b is located, so that the cascade signal line ST is directly electrically connected to the corresponding module in the signal generation unit 300b.

[0092] Please see Figure 5 The pull-down sustaining module 40 includes an inverter 410 and a voltage regulation unit 420 arranged along the first direction X. The transmission module 50 and the pull-up control module 10 are arranged along the first direction X. The transmission module 50 and the voltage regulation unit 420 are arranged along the second direction Y. The pull-up control module 10, the pull-down module 30 and the inverter 410 are arranged along the second direction Y.

[0093] In this embodiment, the cascade signal line ST is located between the inverter 410 and the voltage regulation unit 420, and the cascade signal line ST is located between the cascade module 50 and the pull-up control module 10.

[0094] Please see Figure 5 In the voltage regulation unit 420, the second regulation transistor T33A, the first regulation transistor T32A, and the fifth regulation transistor T72A are arranged along the second direction Y, and the fourth regulation transistor T43A and the third regulation transistor T42A are arranged along the second direction Y. The fourth regulation transistor T43A and the third regulation transistor T42A are both arranged along the first direction X with the second regulation transistor T33A.

[0095] Please see Figure 5 The gate layer 113 includes the gate of the second regulating transistor T33A, the gate of the first regulating transistor T32A, the gate of the fifth regulating transistor T72A, the gate of the fourth regulating transistor T43A, and the gate of the third regulating transistor T42A. The gates of the second regulating transistor T33A, the first regulating transistor T32A, the fourth regulating transistor T43A, and the third regulating transistor T42A are all connected to the gate of the second regulating transistor T33A.

[0096] Please see Figure 5 The gate driving section 300A of the nth stage also includes a first combined electrode CT1, a second combined electrode CT2, a third combined electrode CT3, a fourth combined electrode CT4, a fifth combined electrode CT5, and a sixth combined electrode CT6. Each of the above combined electrodes includes a first conductive block located in the gate layer 113, a second conductive block located in the source-drain layer 116, and a third conductive block located in the pixel electrode layer 118. The third conductive block serves as a connecting electrode to electrically connect the first conductive block in the gate layer 113 and the second conductive block in the source-drain layer. That is, the first conductive block and the second conductive block are not directly connected, and the third conductive block is required as a connecting electrode.

[0097] Please see Figure 5 The gates of the third regulating transistor T42A and the fifth regulating transistor T72A are electrically connected through the first combined electrode CT1. The first combined electrode CT1 and the fifth regulating transistor T72A are arranged along the first direction X, and the third regulating transistor T42A and the first combined electrode CT1 are arranged along the second direction Y.

[0098] Please see Figure 5 The source-drain layer 116 includes the source and drain of the second regulating transistor T33A, the source and drain of the first regulating transistor T32A, the source and drain of the fifth regulating transistor T72A, the source and drain of the fourth regulating transistor T43A, and the source and drain of the third regulating transistor T42A. The source and drain of the above transistors have overlapping portions with the gate of the corresponding transistor.

[0099] Please see Figure 5 The gate layer 113 also includes a second low potential line VSSG extending along the second direction Y, the second low potential line VSSG being located between the output section 300a and the display area AA.

[0100] Please see Figure 5 The source-drain layer 116 also includes a first conductive segment ET1, a second conductive segment ET2, a third conductive segment ET3, a fourth conductive segment ET4, and a fifth conductive segment ET5. The first conductive segment ET1 extends along the first direction X. A portion of the first conductive segment ET1 is located between the first pull-up transistor T21A and the second pull-up transistor T23A. The drain of the second regulating transistor T33A and the drain of the first regulating transistor T32A are both connected to one end of the first conductive segment ET1. The other end of the first conductive segment ET1 is electrically connected to the second low potential line VSSG.

[0101] The second conductive segment ET2 extends along the second direction Y. Part of the second conductive segment ET2 is located between the second regulating transistor T33A and the fourth regulating transistor T43A, and between the second regulating transistor T33A and the third regulating transistor T42A. One end of the second conductive segment ET2 is connected to the source of the fifth regulating transistor T72A, and the other end of the second conductive segment ET2 is connected to the drain of the stage transistor T22A.

[0102] The third conductive segment ET3 extends along the second direction Y. The third conductive segment ET3 is located between the first regulating transistor T32A and the first combined electrode CT1. One end of the third conductive segment ET3 is connected to the drain of the third regulating transistor T42A, and the other end of the third conductive segment ET3 is connected to the drain of the fifth regulating transistor T72A.

[0103] The fourth conductive segment ET4 includes a horizontal segment ET40 and a first vertical segment ET41, a second vertical segment ET42, and a third vertical segment ET43 connected to the horizontal segment ET40. The horizontal segment ET40 spans multiple transmission signal lines ST. The first vertical segment ET41 is located on the side of the multiple transmission signal lines ST closest to the display area AA. The second vertical segment ET42 and the third vertical segment ET43 are both located on the side of the multiple transmission signal lines ST furthest from the display area AA. The end of the horizontal segment ET40 closest to the display area AA is connected to the source of the fourth regulating transistor T43A and the source of the third regulating transistor T42A.

[0104] The end of the first vertical segment ET41 away from the horizontal segment ET40 is connected to the gate of the stage transistor T22A, and the first vertical segment ET41 and the stage transistor T22A are directly connected to the second combined electrode CT2. The gates of the first vertical segment ET41 and the stage transistor T22A are electrically connected through the second combined electrode CT2.

[0105] The end of the second vertical segment ET42 away from the horizontal segment ET40 is connected to the drain of the pull-up control transistor T11A and the source of the pull-down transistor T41A. The end of the third vertical segment ET43 away from the horizontal segment ET40 is electrically connected to the gate of the fourth inverting transistor T54A and the gate of the second inverting transistor T52A. A third combined electrode CT3 is provided between the third vertical segment ET43 and the fourth inverting transistor T54A. The gates of the third vertical segment ET43 and the fourth inverting transistor T54A are electrically connected through the third combined electrode CT3.

[0106] The fifth conductive segment ET5 extends along the first direction X and is adjacent to the second clock signal line CK(n+1). One end of the fifth conductive segment ET5 is connected to the first low potential line VSSQ, and the other end of the fifth conductive segment ET5 is connected to the drain of the fifth regulating transistor T72A and the first combined electrode CT1.

[0107] Please see Figure 5 The gate layer 113 includes the gate of the stage transistor T22A, and the source-drain layer 116 includes the source T22A and the drain T22A of the stage transistor T22A. The source and drain of the stage transistor T22A both overlap with the gate of the stage transistor T22A. The gate of the stage transistor T22A is connected to the gate cell of the first pull-up transistor T21A on the side away from the second pull-up transistor T23A.

[0108] Please see Figure 5The gate layer 113 includes the gate of the pull-up control transistor T11A, and the source-drain layer 116 includes the source T11A and the drain T11A of the pull-up control transistor T11A. The source and drain of the pull-up control transistor T11A overlap with the gate of the pull-up control transistor T11A. The gate of the pull-up control transistor T11A is connected to the stage transmission signal line ST of the (n-4)th stage.

[0109] Please see Figure 5 The gate layer 113 includes the gate of the pull-down transistor T41A, and the source-drain layer 116 includes the source T41A and the drain T41A of the pull-down transistor T41A. The source and drain of the pull-down transistor T41A both overlap with the gate of the pull-down transistor T41A. The gate of the pull-down transistor T41A is connected to the stage transmission signal line ST of the (n+6)th stage. The gate of the pull-down transistor T41A and the gate of the pull-up control transistor T11A are spaced apart along the second direction Y, and the drain of the pull-down transistor T41A and the drain of the pull-up control transistor T11A are arranged opposite to each other along the second direction Y.

[0110] Please see Figure 5 In inverter 410, the fourth inverter transistor T54A, the second inverter transistor T52A, and the fifth inverter transistor T55A are arranged along the first direction X. The second inverter transistor T52A and the sixth inverter transistor T56A are arranged at intervals along the second direction Y. The first inverter transistor T51A, the third inverter transistor T53A, and the second reset transistor T45A are arranged at intervals along the second direction Y. The first reset transistor T44A and the second reset transistor T45A are arranged adjacent to each other along the first direction X. The first reset transistor T44A and the pull-down transistor T41A are arranged adjacent to each other and at intervals along the second direction Y.

[0111] Please see Figure 5 The gate layer 113 includes the gate of the fourth inverting transistor T54A, the gate of the second inverting transistor T52A, the gate of the fifth inverting transistor T55A, the gate of the sixth inverting transistor T56A, the gate of the first inverting transistor T51A, the gate of the third inverting transistor T53A, the gate of the second reset transistor T45A, and the gate of the first reset transistor T44A. The gate of the fourth inverting transistor T54A and the gate of the second inverting transistor T52A are directly connected. The gate of the second inverting transistor T52A and the gate of the fifth inverting transistor T55A are spaced apart. The gate of the fifth inverting transistor T55A and the gate of the sixth inverting transistor T56A are connected through an electrical connection segment. The gate of the second reset transistor T45A and the gate of the first reset transistor T44A are connected.

[0112] Please see Figure 5The gate layer 113 also includes a reset signal line Reset located in the region of the gate driving section 300A of the nth stage. The reset signal line Reset is located on the side of the signal generation section 300b away from the output section 300a. The reset signal line Reset is electrically connected to the pull-down sustaining module 40. For example, the reset signal line Reset and the gate of the second reset transistor T45A are directly connected. Since the gate of the second reset transistor T45A and the gate of the first reset transistor T44A are connected, the gate of the second reset transistor T45A and the gate of the first reset transistor T44A both receive the reset signal transmitted by the reset signal line Reset.

[0113] Please see Figure 5 The source-drain layer 116 includes the source and drain of the fourth inverting transistor T54A, the source and drain of the second inverting transistor T52A, the source and drain of the fifth inverting transistor T55A, the source and drain of the sixth inverting transistor T56A, the source and drain of the first inverting transistor T51A, the source and drain of the third inverting transistor T53A, the source and drain of the second reset transistor T45A, and the source and drain of the first reset transistor T44A. The source and drain of the above transistors all have overlapping portions with the gate of the corresponding transistor.

[0114] Please see Figure 5 The source-drain layer 116 includes a sixth conductive segment ET6, a seventh conductive segment ET7, an eighth conductive segment ET8, a ninth conductive segment ET9, a tenth conductive segment ET10, an eleventh conductive segment ET11, a twelfth conductive segment ET12, a thirteenth conductive segment ET13, and a fourteenth conductive segment ET14. The eighth conductive segment ET8, the ninth conductive segment ET9, the tenth conductive segment ET10, the eleventh conductive segment ET11, and the twelfth conductive segment ET12 are arranged at intervals along the second direction Y.

[0115] Please see Figure 5 The source of the second inverting transistor T52A and the source of the fifth inverting transistor T55A are both connected to one end of the sixth conductive segment ET6. The gate of the third inverting transistor T53A and the drain of the first inverting transistor T51A are connected to the other end of the sixth conductive segment ET6. A fourth combined electrode CT4 is provided between the third inverting transistor T53A and the first inverting transistor T51A. The fourth combined electrode CT4 is simultaneously connected to the gate of the third inverting transistor T53A, the drain of the first inverting transistor T51A, and the end of the sixth conductive segment ET6 away from the fifth inverting transistor T55A.

[0116] One end of the seventh conductive segment ET7 is connected to the drain of the sixth inverting transistor T56A, and the other end of the seventh conductive segment ET7 is electrically connected to the drain of the first reset transistor T44A; the eighth conductive segment ET8 is used to transmit the clock signal of the (n+2)th stage, and the eighth conductive segment ET8 is connected to the gate of the fifth inverting transistor T55A; the ninth conductive segment ET9 is used to transmit the clock signal of the (n+6)th stage, and the ninth conductive segment ET9 is connected to the gate of the first inverting transistor T51A; the tenth conductive segment ET10 is used to transmit a high level. The source, the tenth conductive segment ET10, is simultaneously connected to the source of the first inverting transistor T51A, the source of the third inverting transistor T53A, and the source of the second reset transistor T45A; one end of the eleventh conductive segment ET11 is connected to the first low potential line VSSQ, and the other end of the eleventh conductive segment ET11 is simultaneously connected to the seventh conductive segment ET7 and the drain of the pull-down transistor T41A; the twelfth conductive segment ET12 is used to transmit a high-level source, and the twelfth conductive segment ET12 is connected to the source of the pull-up control transistor T11A.

[0117] Please see Figure 5 A fifth combined electrode CT5 is provided between the reset signal line Reset and the fifth inverting transistor T55A, and a sixth combined electrode CT6 is provided between the reset signal line Reset and the sixth conductive segment ET6. The eighth conductive segment ET8 and the gate of the fifth inverting transistor T55A are electrically connected through the fifth combined electrode CT5, and the ninth conductive segment ET9 and the gate of the first inverting transistor T51A are electrically connected through the sixth combined electrode CT6.

[0118] Please see Figure 5 The thirteenth conductive segment ET13 and the fourteenth conductive segment ET14 are connected. The fourteenth conductive segment ET14 spans multiple transmission signal lines ST, and one end of the fourteenth conductive segment ET14 is connected to the first combined electrode CT1. The other end of the fourteenth conductive segment ET14 is connected to the thirteenth conductive segment ET13 and the source of the sixth inverting transistor T56A. The end of the thirteenth conductive segment ET13 away from the fourteenth conductive segment ET14 is simultaneously connected to the drain of the second reset transistor T45A and the drain of the third inverting transistor T53A.

[0119] Please see Figure 5 The nth stage gate driving section 300A also includes a first transfer electrode TE1 and a first connection electrode LE1. The first transfer electrode TE1 and the first connection electrode LE1 both overlap with the second stage transmission segment STb in the thickness direction of the display panel 100.

[0120] For example, please see Figure 5Multiple transmission signal lines ST include the transmission signal line ST of level n+6, the transmission signal line ST of level n+4, the transmission signal line ST of level n+2, the transmission signal line ST of level n, the transmission signal line ST of level n-2, and the transmission signal line ST of level n-4.

[0121] In this embodiment, the first transfer electrode TE1, the first connection electrode LE1, and the stage transmission signal line ST are disposed on different layers. For example, the first transfer electrode TE1 is located in the pixel electrode layer 118, the first connection electrode LE1 is located in the source-drain layer 116, and the stage transmission signal line ST is located in the gate layer 113. This means that the second stage transmission segment STb, the first transfer electrode TE1, and the first connection electrode LE1 constitute a combined electrode to transmit the stage transmission signal line ST output from the drain of the stage transmission transistor T22A to the second stage transmission segment STb through the first transfer electrode TE1. The second stage transmission segment STb transmits to the gate driving section 300A of a certain stage through the first stage transmission segment STa, and transmits to the gate driving section 300A of a certain stage through the third stage transmission segment STc.

[0122] Please see Figure 5 One end of the first connecting electrode LE1 is electrically connected to the output end of the transmission module 50. One end of the first transfer electrode TE1 passes through the first via HL1 and is electrically connected to the other end of the first transfer electrode TE1. The other end of the first transfer electrode TE1 passes through the second via HL2 and is electrically connected to the second transmission segment STb.

[0123] For example, the first connecting electrode LE1 of this application can be concave, the second stage transmission segment STb and the first transfer electrode TE1 can be elongated, the first transfer electrode TE1 can be electrically connected to the first connecting electrode LE1 through two first vias HL1, the two first vias HL1 correspond to the first connecting electrode LE1 in a convex structure, the first transfer electrode TE1 can be electrically connected to the second stage transmission segment STb through two second vias HL2, that is, in the second direction Y, the two first vias HL1 and the two second vias HL2 are arranged alternately.

[0124] Similarly, in the first combined electrode CT1, the second combined electrode CT2, the third combined electrode CT3, the fourth combined electrode CT4, the fifth combined electrode CT5, and the sixth combined electrode CT6, there exists the first via HL1 and the second via HL2. That is, the first via HL1 is used to electrically connect the conductive structure located in the pixel electrode layer 118 and the conductive structure located in the source-drain layer 116, and the second via HL2 is used to electrically connect the conductive structure located in the pixel electrode layer 118 and the conductive structure located in the gate layer 113.

[0125] In this embodiment, the width of the second-level transmission segment STb is greater than the width of the first-level transmission segment STa and the third-level transmission segment STc on the side closest to the second-level transmission segment STb; that is, since vias need to be provided on the second-level transmission segment STb, and in order to make the first transfer electrode TE1 and the second-level transmission segment STb electrically connected, this application can increase the width of the second-level transmission segment STb in this area.

[0126] Similarly, the ends of the first-level transmission segment STa and the third-level transmission segment STc that are far from the second-level transmission segment STb need to transmit the corresponding transmission signals to the corresponding level's pull-up control module 10 or pull-down module 30. Therefore, the width of the ends of the first-level transmission segment STa and the third-level transmission segment STc that are far from the second-level transmission segment STb also needs to be increased.

[0127] Please see Figure 5 The gate driving section 300A of the nth stage also includes a second transfer electrode TE2 and a third transfer electrode TE3. The second transfer electrode TE2 and the third transfer electrode TE3 are located on both sides of the multiple stage transmission signal lines ST. The second transfer electrode TE2 is located on the side of the multiple stage transmission signal lines ST closer to the output section 300a, and the third transfer electrode TE3 is located on the side of the multiple stage transmission signal lines ST away from the output section 300a.

[0128] Please see Figure 5 The gate drive section 300A of the nth stage also includes a second connection electrode LE2, which overlaps at least partially with one of the multiple stage transmission signal lines ST. One end of the second connection electrode LE2 is electrically connected to the second transfer electrode TE2, and the other end of the second connection electrode LE2 is electrically connected to the third transfer electrode TE3.

[0129] In this embodiment, the third segment STc of the first-level signal line ST closest to the output section 300a among the multiple tiered signal lines ST is electrically connected to the second transfer electrode TE2, the control terminal of the pull-down module 30 is electrically connected to the third transfer electrode TE3, and the first segment STa of the first-level signal line ST closest to the output section 300a among the multiple tiered signal lines ST is electrically connected to the control terminal of the pull-up control module 10.

[0130] exist Figure 5In the structure, the second transfer electrode TE2 and the third transfer electrode TE3 are located in the pixel electrode layer 118, and the second connection electrode LE2 is located in the source-drain layer 116. The second transfer electrode TE2, one end of the second connection electrode LE2 and the end of the first stage transmission segment STa of the stage transmission signal line ST of the (n+6)th stage constitute a combined electrode. The other end of the third transfer electrode TE3, the second connection electrode LE2 and the conductive block connected to the gate of the pull-down transistor T41A constitute a combined electrode. That is, the present application transmits the stage transmission signal of the stage transmission signal line ST of the (n+6)th stage to the gate of the pull-down transistor T41A of the nth stage through the second transfer electrode TE2, the third transfer electrode TE3 and the second connection electrode LE2.

[0131] It should be noted that, since the first pull-up transistor T21A and the second pull-up transistor T23A are used to output gate drive signals to the display area AA, the output load of the first pull-up transistor T21A and the second pull-up transistor T23A is relatively large. That is, the area of ​​the first pull-up transistor T21A and the second pull-up transistor T23A in this application is the largest in the gate drive section 300A, and the areas of the first pull-up transistor T21A and the second pull-up transistor T23A can be the same. Secondly, the pull-up control transistor T11A is used to adjust the potential of the first control node Q. Therefore, the area of ​​the pull-up control transistor T11A is smaller than the area of ​​the first pull-up transistor T21A or the second pull-up transistor T23A, but it is larger than the area of ​​other transistors.

[0132] The following section, based on a specific film stacking diagram, discusses... Figure 3 The structure is described.

[0133] Please see Figures 6 to 9 , Figure 6 The diagram shows gate driving units 300A of the nth and n+1th stages. Gate driving units 300A of two adjacent stages are arranged along the second direction Y, and output units 300a and signal generation units 300b are both arranged along the first direction X. The stage transmission signal line ST extends along the second direction Y. Output units 300a and display areas AA are arranged adjacent to each other, and signal generation units 300b are arranged away from display areas AA, so that the gate driving signal generated by output units 300a can be directly transmitted to display areas AA.

[0134] Please see Figure 6 The pull-up transistor T21B may include multiple interconnected pull-up crystal units, that is, the first pull-up transistor T21B may be composed of multiple pull-up transistor T21B units connected in series.

[0135] Please see Figure 6The bootstrap capacitor Cst and the pull-up transistor T21B are arranged adjacent to each other, and part of the bootstrap capacitor Cst is located between the display area AA and the pull-up transistor T21B, while part of the bootstrap capacitor Cst is located between two adjacent pull-up transistor units.

[0136] Please see Figure 6 The gate layer 113 includes the gate of the pull-up transistor T21B and the first plate of the bootstrap capacitor Cst, which are connected to each other. The source-drain layer 116 includes the source and drain of the pull-up transistor T21B and the second plate of the bootstrap capacitor Cst. The source and drain of the pull-up transistor T21B both overlap with the gate of the pull-up transistor T21B. The second plate of the bootstrap capacitor Cst overlaps with the first plate of the bootstrap capacitor Cst.

[0137] Please see Figure 6 The source-drain layer 116 also includes a first clock signal line CK(n) and a second clock signal line CK(n+1). The first clock signal line CK(n) is used to transmit a clock signal to the pull-up transistor T21B of the nth stage, and the second clock signal line CK(n+1) is used to transmit a clock signal to the pull-up transistor T21B of the nth stage. The first clock signal line CK(n) is located on one side of the gate driving section 300A of the nth stage in the second direction Y, and the second clock signal line CK(n+1) is located on the other side of the gate driving section 300A of the (n+1)th stage in the second direction Y. Both the first clock signal line CK(n) and the second clock signal line CK(n+1) extend along the first direction X.

[0138] In this embodiment, to avoid setting up additional transmission lines for transmitting cascade signals, the cascade signal line ST of this application is located in the area where the signal generation unit 300b is located, so that the cascade signal line ST is directly electrically connected to the corresponding module in the signal generation unit 300b.

[0139] Please see Figures 6 to 9 The pull-down sustaining module 40 includes an inverter 410 and a voltage regulation unit 420 arranged along the first direction X. The pull-up module 20, voltage regulation unit 420, stage transmission module 50, pull-up control module 10, pull-down module 30, and inverter 410 are arranged sequentially along the first direction X, and the stage transmission signal line ST is located between the stage transmission module 50 and the pull-up control module 10.

[0140] Please see Figure 7In the voltage regulation unit 420, the second regulation transistor T33B and the first regulation transistor T32B are arranged along the second direction Y, the fifth regulation transistor T72B and the sixth regulation transistor T73B are arranged along the second direction Y, the fourth regulation transistor T43B and the third regulation transistor T42B are arranged along the second direction Y, the second regulation transistor T33B, the sixth regulation transistor T73B and the fourth regulation transistor T43B are arranged along the first direction X, and the first regulation transistor T32B, the fifth regulation transistor T72B and the third regulation transistor T42B are arranged along the first direction X.

[0141] Please see Figure 7 The fifth regulating transistor T72B of the nth stage is located between the first regulating transistor T32C and the fifth regulating transistor T72C of the (n+1)th stage. The sixth regulating transistor T73B of the nth stage is located between the second regulating transistor T33C and the sixth regulating transistor T73C of the (n+1)th stage. The third regulating transistor T42B of the nth stage is located on the side of the third regulating transistor T42C of the (n+1)th stage away from the output section 300a. The fourth regulating transistor T43B of the nth stage is located on the side of the fourth regulating transistor T43C of the (n+1)th stage away from the output section 300a. The sixth regulating transistor T73C and the fourth regulating transistor T43C of the (n+1)th stage are arranged adjacent to each other in the first direction X. The fifth regulating transistor T72C and the third regulating transistor T42C of the (n+1)th stage are arranged adjacent to each other in the first direction X.

[0142] Please see Figure 7The gate layer 113 includes the gate of the second regulating transistor T33B, the gate of the first regulating transistor T32B, the gate of the fifth regulating transistor T72B, the gate of the sixth regulating transistor T73B, the gate of the fourth regulating transistor T43B, and the gate of the third regulating transistor T42B. The gates of the second regulating transistor T33B, the sixth regulating transistor T73B, and the fourth regulating transistor T43B of the nth stage are connected. The gates of the first regulating transistor T32B, the fifth regulating transistor T72B, and the third regulating transistor T42B of the nth stage are also connected. The gate of the second regulating transistor T42B of the (n+1)th stage is connected. The gate of transistor T33C, the gate of the sixth regulating transistor T73C of the (n+1)th stage, and the gate of the fourth regulating transistor T43C of the (n+1)th stage are connected. The gate of the first regulating transistor T32C of the (n+1)th stage, the gate of the fifth regulating transistor T72C of the (n+1)th stage, and the gate of the third regulating transistor T42C of the (n+1)th stage are connected. The gate of the second regulating transistor T33C of the (n+1)th stage and the gate of the first regulating transistor T32B of the nth stage are arranged adjacent to each other along the second direction Y and are connected. The gate of the first regulating transistor T32C of the (n+1)th stage and the gate of the second regulating transistor T33B of the nth stage are arranged spaced apart along the second direction Y and are connected.

[0143] Please see Figures 6 to 9 The nth stage gate drive unit 300A also includes a seventh combined electrode CT7, an eighth combined electrode CT8, a ninth combined electrode CT9, a tenth combined electrode CT10, an eleventh combined electrode CT11, a twelfth combined electrode CT12, a thirteenth combined electrode CT13, and a fourteenth combined electrode CT14. The seventh combined electrode CT7 overlaps with the second low-potential line VSSG. The eighth combined electrode CT8 is located between the voltage adjustment unit 420 and the stage transmission module 50. The ninth combined electrode CT9 is located between the stage transmission module 50 and multiple stage transmission signal lines ST. The tenth combined electrode CT7... Electrode CT10 is located between inverter 410 and pull-down module 30. Eleventh combination electrode CT11, twelfth combination electrode CT12, and thirteenth combination electrode CT13 are arranged sequentially at intervals along the first direction X. Eleventh combination electrode CT11 and twelfth combination electrode CT12 are located between third inverting transistor T53B and first inverting transistor T51B. Thirteenth combination electrode CT13 is located between first inverting transistor T51B and second inverting transistor T52B. Fourteenth combination electrode CT14 is located on the side of inverter 410 away from output section 300a.

[0144] In this embodiment, the above-mentioned combined electrodes each include a first conductive block located in the gate layer 113, a second conductive block located in the source-drain layer 116, and a third conductive block located in the pixel electrode layer 118. The third conductive block serves as a connecting electrode to electrically connect the first conductive block in the gate layer 113 and the second conductive block in the source-drain layer. That is, the first conductive block and the second conductive block are not directly connected, and the third conductive block is required as a connecting electrode.

[0145] Please see Figure 7 The source-drain layer 116 includes the source and drain of the second regulating transistor T33B, the source and drain of the first regulating transistor T32B, the source and drain of the fifth regulating transistor T72B, the source and drain of the sixth regulating transistor T73B, the source and drain of the fourth regulating transistor T43B, and the source and drain of the third regulating transistor T42B. The source and drain of the above transistors all have overlapping portions with the gate of the corresponding transistor.

[0146] Please see Figure 6 The gate layer 113 also includes a second low potential line VSSG extending along the second direction Y, the second low potential line VSSG being located between the output section 300a and the display area AA.

[0147] Please see Figures 6 to 9 The source-drain layer 116 also includes the fifteenth conductive segment ET15, the sixteenth conductive segment ET16, the seventeenth conductive segment ET17, the eighteenth conductive segment ET18, and the nineteenth conductive segment ET19.

[0148] Please see Figures 6 to 9 The fifteenth conductive segment ET15 extends along the first direction X. Part of the fifteenth conductive segment ET15 is located between two adjacent pull-up transistors T21B. The drain of the second regulating transistor T33B and the drain of the first regulating transistor T32B are both connected to one end of the fifteenth conductive segment ET15. The other end of the fifteenth conductive segment ET15 is electrically connected to the second low potential line VSSG.

[0149] Please see Figures 6 to 9 One end of the sixteenth conductive segment ET16 is connected to the source of the fifth regulating transistor T72B and the source of the sixth regulating transistor T73B, and the other end of the sixteenth conductive segment ET16 is connected to the drain of the stage transistor T22B.

[0150] Please see Figures 6 to 9The seventeenth conductive segment ET17 is used to transmit the potential of the first control node Q. One end of the seventeenth conductive segment ET17 is connected to the source of the third regulating transistor T42B and the source of the fourth regulating transistor T43B. The seventeenth conductive segment ET17 is connected to the gate of the stage transistor T22B through the ninth combined electrode CT9. The seventeenth conductive segment ET17 is connected to the gate of the fourth inverting transistor T54B through the tenth combined electrode CT10. The seventeenth conductive segment ET17 is connected to the gate of the second inverting transistor T52B through the eleventh combined electrode CT11. The seventeenth conductive segment ET17 is connected to the gate of the second inverting transistor T52B and the gate of the fifth inverting transistor T55B of the next stage through the eleventh combined electrode CT11. The seventeenth conductive segment ET17 is connected to the source of the first reset transistor T44B through the fourteenth combined electrode CT14.

[0151] Please see Figures 6 to 9 The eighteenth conductive segment ET18 is used to transmit the potential of the second control node, and one end of the eighteenth conductive segment ET18 is connected to one end of the seventh combined electrode CT7, and the other end of the eighth combined electrode CT8 is connected to the gate of the third regulating transistor T42B. Please see Figures 6 to 9 One end of the nineteenth conductive segment ET19 is connected to the first low potential line VSSQ, and the other end of the nineteenth conductive segment ET19 is connected to the drain of the fifth regulating transistor T72B, the drain of the sixth regulating transistor T73B, the drain of the fourth regulating transistor T43B, and the drain of the third regulating transistor T42B of the nth and n+1th stages.

[0152] Please see Figure 7 The gate layer 113 includes the gate of the stage transistor T22B, and the source-drain layer 116 includes the source and drain of the stage transistor T22B. The source and drain of the stage transistor T22B both have overlapping portions with the gate of the stage transistor T22B. The gate of the stage transistor T22B is located on the side of the seventh combined electrode CT7 away from the output section 300a.

[0153] Please see Figure 8 The gate layer 113 includes the gate of the pull-up control transistor T11B, and the source-drain layer 116 includes the source and drain of the pull-up control transistor T11B. The source and drain of the pull-up control transistor T11B overlap with the gate of the pull-up control transistor T11B. The gate of the nth stage pull-up control transistor T11B is connected to the stage transmission signal line ST of the (n-6)th stage.

[0154] Please see Figures 8 to 9The gate layer 113 includes the gate of the pull-down transistor T41B, and the source-drain layer 116 includes the source and drain of the pull-down transistor T41B. The source and drain of the pull-down transistor T41B overlap with the gate of the pull-down transistor T41B. The gate of the nth stage pull-down transistor T41B is connected to the stage transmission signal line ST of the (n+8)th stage. The gate of the pull-down transistor T41B and the gate of the pull-up control transistor T11B are spaced apart along the first direction X.

[0155] Please see Figures 8 to 9 The source-drain layer 116 also includes a twentieth conductive segment ET20 and a twelfth conductive segment ET21. One end of the twentieth conductive segment ET20 is connected to the source of the pull-up control transistor T11B, the other end of the twentieth conductive segment ET20 is connected to a high-level source, one end of the twentieth conductive segment ET20 is connected to the drain of the pull-down transistor T41B, and the other end of the twentieth conductive segment ET20 is connected to the first low-potential line VSSQ.

[0156] Please see Figure 9 In inverter 410, the fourth inverter transistor T54B, the sixth inverter transistor T56B, and the third inverter transistor T53B are arranged alternately along the first direction X, and the second inverter transistor T52B and the fifth inverter transistor T55B are arranged alternately along the first direction X.

[0157] Please see Figure 9 The gate layer 113 includes the gate of the fourth inverting transistor T54B, the gate of the second inverting transistor T52B, the gate of the fifth inverting transistor T55B, the gate of the sixth inverting transistor T56B, the gate of the first inverting transistor T51B, the gate of the third inverting transistor T53B, and the gate of the first reset transistor T44B. The gate of the sixth inverting transistor T56B of the nth stage is connected to the first control node Q of the (n-2)th stage.

[0158] Please see Figure 9 The gate layer 113 also includes a reset signal line Reset located in the region of the gate driving section 300A of the nth stage. The reset signal line Reset is located on the side of the signal generation section 300b away from the output section 300a. The reset signal line Reset and the first reset transistor T44B have an overlapping portion, and part of the reset signal line Reset is multiplexed as the gate of the first reset transistor T44B.

[0159] Please see Figure 9The source-drain layer 116 includes the source and drain of the fourth inverting transistor T54B, the source and drain of the second inverting transistor T52B, the source and drain of the fifth inverting transistor T55B, the source and drain of the sixth inverting transistor T56B, the source and drain of the first inverting transistor T51B, the source and drain of the third inverting transistor T53B, and the source and drain of the first reset transistor T44B. The source and drain of the above transistors all have overlapping portions with the gate of the corresponding transistor.

[0160] Please see Figure 9 The source-drain layer 116 also includes a 22nd conductive segment ET22 and a 23rd conductive segment ET23. One end of the 22nd conductive segment ET22 is connected to the source of the third inverting transistor T53B of the nth stage, the source of the first inverting transistor T51B, and the gate of the first inverting transistor T51B through the 13th combined electrode CT13. The other end of the 22nd conductive segment ET22 is connected to the first inverting signal line LC1. One end of the 23rd conductive segment ET23 is connected to the source of the third inverting transistor T53C of the (n+1)th stage, the source of the first inverting transistor T51C, and the gate of the first inverting transistor T51C through the 13th combined electrode CT13. The other end of the 23rd conductive segment ET23 is connected to the second inverting signal line LC2.

[0161] Please see Figure 9 One end of the twelfth combined electrode CT12 is connected to the gate of the third inverting transistor T53B, and the other end of the twelfth combined electrode CT12 is connected to the drain of the first inverting transistor T51B, the source of the second inverting transistor T52B, and the source of the fifth inverting transistor T55B.

[0162] Please see Figure 8 The nth stage gate driving section 300A also includes a first transfer electrode TE1 and a first connection electrode LE1. The first transfer electrode TE1 and the first connection electrode LE1 both overlap with the second stage transmission segment STb in the thickness direction of the display panel 100.

[0163] For example, please see Figure 8Multiple transmission signal lines ST include the transmission signal line ST of level n+9, level n+8, level n+7, level n+6, level n+5, level n+4, level n+3, level n+2, level n+1, level n, level n, level n-1, level n-2, level n-3, level n-4, level n-5, and level n-6.

[0164] In this embodiment, the first-level transmission segment STa is located on the side of the first transfer electrode TE1 close to the pull-up module 20, and the third-level transmission segment STc is located on the side of the first transfer electrode TE1 away from the pull-up module 20; that is, the first-level transmission segment STa in the multiple transmission signal lines ST is located between the multiple second-level transmission segments STb and the multiple pull-up control modules 10, and the third-level transmission segment STc in the multiple transmission signal lines ST is located between the multiple second-level transmission segments STb and the multiple transmission modules 50.

[0165] In this embodiment, the first transfer electrode TE1, the first connection electrode LE1, and the stage transmission signal line ST are disposed on different layers. For example, the first transfer electrode TE1 is located on the pixel electrode layer 118, the first connection electrode LE1 is located on the source-drain layer 116, and the stage transmission signal line ST is located on the gate layer 113. This means that the second stage transmission segment STb, the first transfer electrode TE1, and the first connection electrode LE1 constitute a combined electrode to transmit the stage transmission signal line ST output from the drain of the stage transmission transistor T22B to the second stage transmission segment STb through the first transfer electrode TE1. The second stage transmission segment STb transmits to the gate driving section 300A of a certain stage through the first stage transmission segment STa, and transmits to the gate driving section 300A of a certain stage through the third stage transmission segment STc.

[0166] Please see Figure 8 One end of the first connecting electrode LE1 is electrically connected to the output end of the transmission module 50. One end of the first transfer electrode TE1 passes through the first via HL1 and is electrically connected to the other end of the first transfer electrode TE1. The other end of the first transfer electrode TE1 passes through the second via HL2 and is electrically connected to the second transmission segment STb. For example, the first connecting electrode LE1 of this application can be concave, the second stage transmission segment STb and the first transfer electrode TE1 can be elongated, the first transfer electrode TE1 can be electrically connected to the first connecting electrode LE1 through two first vias HL1, the two first vias HL1 correspond to the first connecting electrode LE1 in a convex structure, the first transfer electrode TE1 can be electrically connected to the second stage transmission segment STb through two second vias HL2, that is, in the second direction Y, the two first vias HL1 and the two first vias HL1 are arranged alternately.

[0167] Similarly, the seventh combined electrode CT7, the eighth combined electrode CT8, the ninth combined electrode CT9, the tenth combined electrode CT10, the eleventh combined electrode CT11, the twelfth combined electrode CT12, the thirteenth combined electrode CT13, and the fourteenth combined electrode CT14 all contain the aforementioned first via HL1 and second via HL2. That is, the first via HL1 is used to electrically connect the conductive structure located in the pixel electrode layer 118 and the conductive structure located in the source drain layer 116, and the second via HL2 is used to electrically connect the conductive structure located in the pixel electrode layer 118 and the conductive structure located in the gate layer 113.

[0168] In this embodiment, the width of the second-level transmission segment STb is greater than the width of the first-level transmission segment STa and the third-level transmission segment STc on the side closest to the second-level transmission segment STb; that is, since vias need to be provided on the second-level transmission segment STb, and in order to make the first transfer electrode TE1 and the second-level transmission segment STb electrically connected, this application can increase the width of the second-level transmission segment STb in this area.

[0169] Similarly, the ends of the first-level transmission segment STa and the third-level transmission segment STc that are far from the second-level transmission segment STb need to transmit the corresponding transmission signals to the corresponding level's pull-up control module 10 or pull-down module 30. Therefore, the width of the ends of the first-level transmission segment STa and the third-level transmission segment STc that are far from the second-level transmission segment STb also needs to be increased.

[0170] In this embodiment, all the combined electrode groups of this application extend along the first direction X.

[0171] Please see Figure 8 The gate driving section 300A of the nth stage also includes a fourth transfer electrode TE4 and a fifth transfer electrode TE5. The fourth transfer electrode TE4 and the fifth transfer electrode TE5 are located on both sides of the multiple stage transmission signal lines ST. The fourth transfer electrode TE4 is located on the side of the multiple stage transmission signal lines ST closer to the output section 300a, and the fifth transfer electrode TE5 is located on the side of the multiple stage transmission signal lines ST away from the output section 300a.

[0172] Please see Figure 8The gate drive section 300A of the nth stage also includes a third connection electrode LE3, which overlaps at least partially with one of the multiple stage transmission signal lines ST. One end of the third connection electrode LE3 is electrically connected to the second transfer electrode TE2, and the other end of the first connection electrode LE1 is electrically connected to the third transfer electrode TE3.

[0173] In this embodiment, the first stage segment STa of the first stage signal line ST closest to the output section 300a among the multiple stage signal lines ST is electrically connected to the fourth transfer electrode TE4, the control terminal of the pull-up control module 10 is electrically connected to the fifth transfer electrode TE5, and the third stage segment STc of the first stage signal line ST furthest from the output section 300a among the multiple stage signal lines ST is electrically connected to the control terminal of the pull-down module 30.

[0174] In this embodiment, multiple third-stage transmission segments STc are disposed between the fourth transfer electrode TE4 and the first transfer electrode TE1, and multiple first-stage transmission segments STa are disposed between the fifth transfer electrode TE5 and the first transfer electrode TE1. exist Figure 8 In the structure, the fourth transition electrode TE4 and the fifth transition electrode TE5 are located in the pixel electrode layer 118, and the third connecting electrode LE3 is located in the source-drain layer 116. One end of the fourth transition electrode TE4, one end of the third connecting electrode LE3, and the end of the first stage transmission segment STa of the stage transmission signal line ST of the n-6th stage constitute a combined electrode. The other end of the fifth transition electrode TE5, the third connecting electrode LE3, and the conductive block connected to the gate of the pull-up control transistor T11B constitute a combined electrode. That is, the present application transmits the stage transmission signal of the stage transmission signal line ST of the n-6th stage to the gate of the pull-up control transistor T11B of the nth stage through the fourth transition electrode TE4, the fifth transition electrode TE5, and the third connecting electrode LE3.

[0175] In the two embodiments described above, this application makes each transmission signal line ST include a continuous first transmission segment STa, a second transmission segment STb, and a third transmission segment STc. The first transmission segment STa is electrically connected to the signal generation unit 300b of the nx-th stage, the second transmission segment STb is electrically connected to the output terminal of the transmission module 50 of the n-th stage, and the third transmission segment STc is electrically connected to the third transmission segment STc of the signal generation unit 300b of the n+y-th stage. The transmission signal output from the n-th stage can be simultaneously transmitted to the first transmission segment STa and the third transmission segment STc through the second transmission segment STb. This reduces the number of connection vias and avoids the transmission signal lines ST used for uplink and downlink being independent transmission lines. This reduces the space occupied by the transmission signal lines ST and the width of the gate drive circuit 300, thus achieving a narrow bezel design for the display panel 100.

[0176] It should be noted that in the above two embodiments, since the pull-up transistor T21B is used to output the gate drive signal to the display area AA, the output load of the pull-up transistor T21B is relatively large, that is, the area of ​​the pull-up transistor T21B in this application is the largest in the gate drive section 300A; secondly, the pull-up control transistor T11B is used to adjust the potential of the first control node Q, so the area of ​​the pull-up control transistor T11B is smaller than that of the pull-up transistor T21B, but both are larger than the areas of other transistors.

[0177] It should be noted that in actual products Figures 6 to 9 The structure in the image is a continuous stacked film structure, which is separated in this application for ease of description.

[0178] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0179] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0180] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0181] In the above embodiments, the structures shown in the accompanying drawings are only schematic diagrams, and the specific structure of the display panel of this application is based on the description in the specification.

[0182] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0183] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The system includes a gate driving circuit, which comprises N cascaded gate driving sections; wherein the nth stage gate driving section includes: Output section; A signal generation unit is electrically connected to the output unit at the first control node, and the signal generation unit includes a transmission module. A series of transmission signal lines, including a continuous first-stage transmission segment, a second-stage transmission segment, and a third-stage transmission segment; Wherein, the end of the first-level transmission segment furthest from the second-level transmission segment is electrically connected to the signal generation unit of the nx-th level, the second-level transmission segment is electrically connected to the output terminal of the transmission module of the n-th level, and the end of the third-level transmission segment furthest from the second-level transmission segment is electrically connected to the signal generation unit of the n+y-th level. n, x, y, and N are all positive integers, and n is less than or equal to N and greater than x.

2. The display panel as described in claim 1, characterized in that, The output unit includes a pull-up module, and the signal generation unit includes a pull-up control module, a pull-down module, and a pull-down sustaining module. The pull-up module, the pull-down module, and the pull-up control module are all electrically connected to the first control node, and the pull-down sustaining module is electrically connected to the output terminals of the first control node and the pull-up module. Specifically, the end of the first-level transmission segment furthest from the second-level transmission segment is electrically connected to the control terminal of the pull-up control module of the nx-th level, and the end of the third-level transmission segment furthest from the second-level transmission segment is electrically connected to the control terminal of the pull-down module of the n+y-th level.

3. The display panel as described in claim 2, characterized in that, The gate driving section of the nth stage further includes a first transfer electrode and a first connection electrode, wherein the first transfer electrode and the first connection electrode overlap with the second stage segment in the thickness direction of the display panel. Wherein, one end of the first connecting electrode is electrically connected to the output end of the transmission module, one end of the first adapter electrode passes through the first via and is electrically connected to the other end of the first adapter electrode, and the other end of the first adapter electrode passes through the second via and is electrically connected to the second transmission segment.

4. The display panel as described in claim 3, characterized in that, The first adapter electrode, the first connecting electrode, and the transmission signal line are arranged in different layers.

5. The display panel as described in claim 3, characterized in that, The width of the second-level transmission segment is greater than the width of the first-level transmission segment and the third-level transmission segment on the side closest to the second-level transmission segment.

6. The display panel as described in any one of claims 3 to 5, characterized in that, The output section and the signal generation section are arranged along a first direction, and the transmission signal line extends along a second direction, wherein the first direction and the second direction intersect. The transmission signal line is located within the area where the signal generation unit is located.

7. The display panel as described in claim 6, characterized in that, The pull-up module includes a first pull-up unit and a second pull-up unit. The first pull-up unit is used to output the gate drive signal of the nth stage, and the second pull-up unit is used to output the gate drive signal of the (n+1)th stage. The first pull-up unit and the second pull-up unit are arranged along the second direction. Both the first pull-up unit and the second pull-up unit are electrically connected to the signal generation unit.

8. The display panel as described in claim 7, characterized in that, The pull-down sustaining module includes an inverter and a voltage regulation unit arranged along the first direction, the cascade module and the pull-up control module are arranged along the first direction, the cascade module and the voltage regulation unit are arranged along the second direction, and the pull-up control module, the pull-down module and the inverter are arranged along the second direction. The cascade signal line is located between the inverter and the voltage regulation unit, and the cascade signal line is located between the cascade module and the pull-up control module.

9. The display panel as described in claim 8, characterized in that, The gate driving circuit includes multiple stage transmission signal lines, and the gate driving section of the nth stage further includes: The second and third transfer electrodes are located on both sides of the plurality of stage transmission signal lines. The second transfer electrode is located on the side of the plurality of stage transmission signal lines closer to the output section, and the third transfer electrode is located on the side of the plurality of stage transmission signal lines away from the output section. The second connecting electrode overlaps at least partially with one of the plurality of transmission signal lines, one end of the second connecting electrode is electrically connected to the second adapter electrode, and the other end of the second connecting electrode is electrically connected to the third adapter electrode. Among them, the third stage segment of the multi-stage transmission signal line near the output section is electrically connected to the second adapter electrode, the control terminal of the pull-down module is electrically connected to the third adapter electrode, and the first stage segment of the multi-stage transmission signal line near the output section is electrically connected to the control terminal of the pull-up control module.

10. The display panel as claimed in claim 6, characterized in that, The pull-down sustaining module includes an inverter and a voltage regulation unit arranged along the first direction, and the pull-up module, the voltage regulation unit, the cascade module, the pull-up control module, the pull-down module, and the inverter are arranged sequentially along the first direction; The cascading signal line is located between the cascading module and the pull-up control module.

11. The display panel as claimed in claim 10, characterized in that, The first stage transmission segment is located on the side of the first adapter electrode closer to the pull-up module, and the third stage transmission segment is located on the side of the first adapter electrode farther away from the pull-up module.

12. The display panel as claimed in claim 11, characterized in that, The gate driving circuit includes multiple stage transmission signal lines, and the gate driving section of the nth stage further includes: The fourth and fifth adapter electrodes are located on both sides of the plurality of stage transmission signal lines. The fourth adapter electrode is located on the side of the plurality of stage transmission signal lines closer to the output section, and the fifth adapter electrode is located on the side of the plurality of stage transmission signal lines farther from the output section. The third connecting electrode overlaps at least partially with one of the plurality of transmission signal lines, one end of the third connecting electrode is electrically connected to the fourth adapter electrode, and the other end of the third connecting electrode is electrically connected to the fifth adapter electrode. Among them, the first stage segment of the stage transmission signal line closest to the output section is electrically connected to the fourth adapter electrode, the control terminal of the pull-up control module is electrically connected to the fifth adapter electrode, and the third stage segment of the stage transmission signal line furthest from the output section is electrically connected to the control terminal of the pull-down module.

13. The display panel as claimed in claim 12, characterized in that, Multiple third-stage transmission segments are disposed between the fourth transfer electrode and the first transfer electrode, and multiple first-stage transmission segments are disposed between the fifth transfer electrode and the first transfer electrode.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

Images