Pixel circuit of electroluminescent display

Abstract

A pixel circuit of an electroluminescent display includes: a level shift transistor coupled between a corresponding light emitting element and a level shift terminal for limiting an operating voltage drop between a voltage of the level shift terminal and a first potential not to exceed a clamping level according to an enable light emitting signal; a bias transistor configured to operate according to a bias signal to provide a luminance current; the display transistor and the bias transistor are connected in series between the level shift end and the first potential, and the display transistor is used for operating according to the display signal to modulate the luminance current into display current to be provided for the corresponding light-emitting element; wherein the light-emitting element is coupled between the level shift transistor and a second potential, and the first potential is different from the second potential.

Description

Technical Field

[0001] This invention relates to a pixel circuit of an electroluminescent display, and more particularly to a pixel circuit of an electroluminescent display in which a level shift transistor limits the operating voltage drop between the voltage at the level shift terminal and a first potential to not exceed the clamping level. Background Technology

[0002] Figure 1 This image shows a prior art pixel 140 diagram from US patent application US20080048949A1. Figure 1 As shown, pixel 140 includes an organic light-emitting diode (OLED) and a pixel circuit 142. In the case of a pixel 140 in the nth column and mth row, the pixel circuit 142 of the nth column and mth pixel 140 is connected to the mth data line Dm, the nth scan line Sn, and the nth emission control line En, and controls the corresponding organic light-emitting diode (OLED).

[0003] The anode electrode of the organic light-emitting diode (OLED) is connected to the pixel circuit 142, while its cathode electrode is connected to the negative drive voltage ELVSS. The OLED produces light with a preset brightness corresponding to the current supplied to it from the pixel circuit 142.

[0004] When a corresponding scan signal is supplied to scan line Sn, pixel circuit 142 controls the amount of current supplied to the organic light-emitting diode (OLED) based on the corresponding data signal supplied to data line Dm. More specifically, a predetermined current is supplied to the OLED from a driving transistor included in pixel circuit 142, and a predetermined voltage is applied to the corresponding OLED. In this case, pixel circuit 142 controls the amount of current flowing to the OLED based on the predetermined voltage applied to the OLED.

[0005] like Figure 1 As shown, the pixel circuit 142 includes a first transistor M1, a second transistor M2, and a third transistor M3, as well as a storage capacitor Cst. The gate of the first transistor M1 is connected to the nth scan line Sn, and the first electrode of the first transistor M1 is connected to the data line Dm. The second electrode of the first transistor M1, i.e., the driving transistor, is connected to the gate of the second transistor M2. When the corresponding scan signal is provided to the scan line Sn, the first transistor M1 transmits the corresponding data signal supplied to the data line Dm to the gate of the second transistor M2.

[0006] The first electrode of the second transistor M2 is connected to the positive driving voltage ELVDD. The second electrode of the second transistor M2 is connected to the first electrode of the third transistor M3. The second transistor M2 controls the current flowing from the positive driving voltage ELVDD to the negative driving voltage ELVSS and through the organic light-emitting diode (OLED) according to the gate voltage applied to the second transistor M2. Here, the positive driving voltage ELVDD is, for example, an internal supply voltage supplying a positive power source, and the negative driving voltage ELVSS is, for example, a ground potential.

[0007] The first electrode of the third transistor M3 is connected to the second electrode of the second transistor M2, and the second electrode of the third transistor M3 is connected to the organic light-emitting diode (OLED). The gate of the third transistor M3 is connected to the emission control line En. When an emission control signal is provided to the emission control line En, for example, when the emission control line is in a high-level state, the third transistor M3 is turned off; otherwise, for example, when the emission control line is in a low-level state, the third transistor M3 is turned on.

[0008] One end of the storage capacitor Cst is connected to the gate of the second transistor M2, while the other end is connected to the second electrode of the third transistor M3, which is the anode electrode of the organic light-emitting diode (OLED). When the first transistor M1 is turned on, the storage capacitor Cst is charged by a voltage corresponding to the data signal. Furthermore, the storage capacitor Cst transfers a voltage change corresponding to the voltage difference across the anode electrode of the OLED to the gate of the second transistor M2.

[0009] Figure 1 In the prior art shown, during the phase where the scan signal Sn is high and the transmit control signal Dm is low, the first transistor M1 is turned off, while the third transistor M3 is turned on. During this phase, the second transistor M2 transfers the current corresponding to the voltage applied to the first node N1 to the organic light-emitting diode (OLED). In this case, the voltage of the second node N2 changes according to the following formula:

[0010]

[0011] Here, V_OLED represents the voltage applied to the organic light-emitting diode (OLED), corresponding to the current flowing through the OLED. Therefore, the V_OLED voltage corresponds to the amount of current flowing through the OLED.

[0012] Therefore, the voltage at the first node N1 is in a floating state and will change according to the voltage change at the second node N2 caused by the storage capacitor Cst. Figure 1In the prior art shown, since the voltage change of the second node N2 is based on the threshold voltage change of the second transistor M2, i.e., based on the current flowing to the organic light-emitting diode (OLED), the threshold voltage of the second transistor M2 is compensated according to the voltage change of the second node N2. Therefore, in Figure 1 In the prior art shown, the second transistor M2 then delivers a current corresponding to the voltage applied to the first node N1 to the organic light-emitting diode OLED, causing the organic light-emitting diode OLED to produce light of a predetermined brightness corresponding to the current supplied.

[0013] Figure 1 In the existing technology shown, the voltage across an organic light-emitting diode (OLED) is typically above 3 volts (V) in current applications, such as microLEDs or OLEDs. Therefore, the first transistor M1, the second transistor M2, and the third transistor M3 must all be selected as components with a voltage rating of 3V or higher. Compared to transistors with a typical voltage rating of 1.2V, transistors with a voltage rating of 3V or higher have a larger component area. Therefore, in order to control different LEDs such as microLEDs or OLEDs, the first transistor M1, the second transistor M2, and the third transistor M3 in the pixel circuit must all be selected as components with a voltage rating of 3V or higher. Compared to transistors with lower voltage ratings, this pixel circuit requires a larger area. In the evolution of circuit technology, miniaturization has always been considered an important improvement, which is common knowledge in the field.

[0014] In view of this, the present invention addresses the shortcomings of the prior art by proposing a pixel circuit for an electroluminescent display that can use transistors with lower voltage ratings to reduce the pixel circuit area. Summary of the Invention

[0015] From one perspective, the present invention provides a pixel circuit for an electroluminescent display, comprising: a quasi-shift transistor coupled between a corresponding light-emitting element and a quasi-shift terminal, for limiting an operating voltage drop between the voltage of the quasi-shift terminal and a first potential to not exceed a clamping level according to an enable light-emitting signal; a bias transistor operated according to a bias signal to provide a luminance current; and a display transistor connected in series with the bias transistor between the quasi-shift terminal and the first potential, for operating according to a display signal to modulate the luminance current into a display current and provide it to the corresponding light-emitting element; wherein the light-emitting element is coupled between the quasi-shift transistor and a second potential, and the first potential is different from the second potential.

[0016] In a preferred embodiment, the level shift transistor, the display transistor, and the bias transistor are coupled to a common cathode structure, and the level shift transistor, the display transistor, and the bias transistor are all P-type metal-oxide-semiconductor (PMOS) devices.

[0017] In a preferred embodiment, the level shift transistor, the display transistor, and the bias transistor are coupled to a common anode structure, and the level shift transistor, the display transistor, and the bias transistor are all N-type metal-oxide-semiconductor (NMOS) devices.

[0018] In a preferred embodiment, both the display transistor and the bias transistor have a withstand voltage exceeding the clamping level, so that both the display transistor and the bias transistor can be guaranteed to operate within the clamping level.

[0019] In a preferred embodiment, the display signal includes a pulse width modulation (PWM) signal with a duty cycle, which is used to switch the corresponding display transistor to generate the display current, thereby determining the grayscale of the corresponding light-emitting element.

[0020] In a preferred embodiment, the display transistor is connected in series between the bias transistor and the level shift transistor.

[0021] In a preferred embodiment, the bias transistor is connected in series between the display transistor and the level shift transistor.

[0022] In a preferred embodiment, the bias transistor and the display transistor share the same transistor.

[0023] In a preferred embodiment, the voltage withstand capability of the level shift transistor exceeds a series voltage difference between the first potential and the second potential, and the series voltage difference exceeds the voltage withstand capability of the bias transistor and the display transistor.

[0024] In a preferred embodiment, the pixel circuit of the electroluminescent display further includes a gate capacitor for charging / discharging the gate capacitor with a luminance current during a refresh period to maintain the level of the bias signal, and for coupling with the bias transistor during a display period to provide the luminance current by maintaining the voltage difference between a transconductance control terminal of the bias transistor and the first potential.

[0025] In a preferred embodiment, the pixel circuit of the electroluminescent display further includes: a refresh switch for operating according to a refresh signal to provide the luminance current during the refresh period; and an auxiliary switch for electrically connecting a resistor output terminal of the bias transistor to a resistor control terminal during the refresh period, configured as a diode connection, and connected in parallel with the gate capacitor between the first potential and a current input / output terminal to charge / discharge the capacitor to maintain the level of the bias signal.

[0026] In a preferred embodiment, the auxiliary switch is turned off after the update period ends, and the update period and the display period do not overlap, wherein during the display period, the pixel circuit supplies the display current to the corresponding light-emitting element.

[0027] In a preferred embodiment, the bias transistor includes a transducer transistor and a transconductance transistor, and the transducer transistor and the transconductance transistor do not share the same transistor; wherein the auxiliary switch, during the segment update period, electrically connects the transducer output terminal of the transducer transistor to the transducer control terminal, configured as a diode connection, for use in parallel with the gate capacitor between the first potential and the current input / output terminal, and charges / discharges the capacitor to maintain the level of the bias signal; wherein the auxiliary switch is turned off during the segment display period, and the gate capacitor is coupled between the first potential and the transconductance control terminal of the transconductance transistor to provide the brightness current according to the voltage difference between the transconductance control terminal and the first potential.

[0028] In a preferred embodiment, the segment update period and the segment display period may optionally have an overlapping period or not overlap with each other.

[0029] In a preferred embodiment, the transconducting transistor, the auxiliary switch, and the transconducting transistor form a current mirror circuit, and during the update period, the luminance current is mirrored and converted into the luminance current.

[0030] The advantage of this invention is that the circuit of this invention can use transistors with low withstand voltage relative to the series voltage difference between the first potential and the second potential in the pixel circuit of an electroluminescent display, thereby relatively reducing the pixel circuit area.

[0031] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0032] Figure 1 This diagram illustrates a prior art pixel 140.

[0033] Figure 2This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0037] Figure 6 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0039] Figure 8 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0040] Figure 9 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0041] Figure 10 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0042] Figure 11 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0043] Figure 12 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention.

[0044] Explanation of symbols in the diagram

[0045] 10, 20, 22: Pixel circuits of electroluminescent displays

[0046] 11: Level displacement control circuit

[0047] 13: Memory and Control Logic Circuits

[0048] 140: pixels

[0049] 142: Pixel Circuit

[0050] 221: Level Shift Transistor

[0051] 222: Bias transistor

[0052] 223: Display transistor

[0053] 224: Update Switch

[0054] 225: Auxiliary switch

[0055] 23: Drive circuit

[0056] 232: Current-to-Digital Converter

[0057] BIAS: Bias signal

[0058] C: Capacitor

[0059] Cst: Storage capacitor

[0060] DIS: Display Signal

[0061] Dm: Data cable

[0062] ELVDD: Positive drive voltage

[0063] ELVSS: Negative Drive Voltage

[0064] EM: Enable emission signal

[0065] En: Launch Control Line

[0066] Frame1: During the frame

[0067] GND: Grounding potential

[0068] Idis: Displays current

[0069] Igrs: Luminance Current

[0070] Igrs1: First luminance current

[0071] Igrs2: Second luminance current

[0072] LS: Level displacement end

[0073] LV1: First potential

[0074] LV2: Second potential

[0075] M1: First transistor

[0076] M2: Second transistor

[0077] M3: Third transistor

[0078] MP1, MN1: Level shift transistors

[0079] MP2, MN2, MN21, MN22, MN23: Display transistors

[0080] MP3, MN3: Bias transistors

[0081] N1: First node

[0082] N2: Second node

[0083] Ncr: Resistor control terminal

[0084] Nio: Resistor output terminal

[0085] RFSH: Update signal

[0086] Sn: Scan line

[0087] uLED: Light-emitting element

[0088] Vls: Voltage at the level shift terminal

[0089] Vod: Operating voltage drop

[0090] Vrm: Holding voltage Detailed Implementation

[0091] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in this invention are illustrative and are primarily intended to illustrate the coupling relationships between circuits and the relationships between signal waveforms; the circuits, signal waveforms, and frequencies are not drawn to scale.

[0092] Figure 2 This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention. Figure 2 As shown, the pixel circuit 10 of the electroluminescent display includes a level shift transistor MP1, a display transistor MP2, and a bias transistor MP3. Figure 2As shown, level shift transistor MP1 is coupled between the corresponding light-emitting element uLED and the level shift terminal LS. It is used to limit the operating voltage drop Vod between the voltage Vls of the level shift terminal LS and the first potential LV1 to not exceed the clamping level, based on the enable light-emitting signal EM generated by the level shift control circuit 11. Bias transistor MP3 operates according to the bias signal BIAS to provide the luminance current Igrs. Display transistor MP2 and bias transistor MP3 are connected in series between the level shift terminal LS and the first potential LV1. They operate according to the display signal DIS to modulate the luminance current Igrs into a display current Idis, providing the display current Idis to the corresponding light-emitting element uLED. The light-emitting element uLED is coupled between level shift transistor MP1 and the second potential LV2, and the first potential LV1 and the second potential LV2 are different, meaning that the series voltage difference between the first potential LV1 and the second potential LV2 is non-zero. The light-emitting element uLED is, for example, but not limited to, a light-emitting diode, a micro-light-emitting diode, or an organic light-emitting diode.

[0093] In this embodiment, the level shift transistor MP1, the display transistor MP2, and the bias transistor MP3 are coupled in a common cathode structure, and all of the level shift transistor MP1, the display transistor MP2, and the bias transistor MP3 are P-type metal oxide semiconductor (PMOS) devices.

[0094] In this embodiment, the voltage ratings of both the display transistor MP2 and the bias transistor MP3 exceed the clamping level. That is, the level shift transistor MP1 uses a transistor with a relatively high voltage rating, and it is used to limit the operating voltage drop Vod between the voltage Vls at the level shift terminal LS and the first potential LV1 to not exceed the clamping level. Thus, as long as the voltage rating of the level shift transistor MP1 exceeds the voltage difference between the first potential LV1 and the second potential LV2, and both the display transistor MP2 and the bias transistor MP3 use transistors with voltage ratings exceeding the clamping level, the configuration according to this invention will prevent damage during normal operation. In other words, both the display transistor MP2 and the bias transistor MP3 can use transistors with relatively low voltage ratings, i.e., less than the voltage difference between the first potential LV1 and the second potential LV2, to reduce the pixel circuit area. From another perspective, according to the configuration of the present invention, during operation, the cross voltages (e.g., source-drain voltage, gate-drain voltage) of the display transistor MP2 and the bias transistor MP3 are both limited below the clamping level. When the clamping level is selected to be sufficiently low, the display transistor MP2 and the bias transistor MP3 can be transistors with relatively low withstand voltage, thereby reducing the pixel circuit area.

[0095] For example, the first potential LV1 is, for instance, the positive power supply voltage VDD, which is, for example, 1.2V, and the second potential LV2 is, for instance, the negative drive voltage ELVSS, which is, for instance, between -3V and -8V. The level shift transistor MP1, based on the enable signal EM, limits the operating voltage drop Vod between the level shift terminal LS and the first potential LV1 to, for example, no more than 1.2V, meaning the clamping level is, for example, 1.2V. Therefore, as long as both the display transistor MP2 and the bias transistor MP3 are transistors with a withstand voltage exceeding 1.2V (a 1.2V withstand transistor has a smaller component area compared to an 8V withstand transistor), they will not be damaged under normal operation. On the other hand, taking a negative drive voltage ELVSS of -6.4V as an example, the level shift transistor MP1 must be selected as a transistor with a withstand voltage of more than 7.6V. However, the display transistor MP2 and the bias transistor MP3 connected in series between the first potential LV1 and the second potential LV2 can be selected as having a withstand voltage of more than 1.2V. It is only necessary for the withstand voltage of the level shift transistor MP1 to exceed the series voltage difference of 7.6V. Since the pixel circuit uses some transistors with lower withstand voltage (smaller area), it is not necessary to use all transistors with higher withstand voltage (larger area). The pixel circuit area is relatively reduced, and a relatively high resolution can be obtained per unit area of ​​the display panel.

[0096] In this embodiment, the level displacement control circuit 11 generates an enable light emission signal EM during the enable period of the corresponding light-emitting element uLED, to turn on the level displacement transistor MP1, and limits the operating voltage drop Vod between the voltage Vls at the level displacement terminal LS and the first potential LV1 to not exceed the clamping level. The enable period can be set by the user or determined according to signals generated by other circuits.

[0097] In this embodiment, the memory and control logic circuit 13 generates a display signal DIS, which includes a pulse width modulation (PWM) signal with a duty cycle. The PWM signal is used to switch the corresponding display transistor MP2, thereby generating a display current Idis, which in turn determines the grayscale of the corresponding light-emitting element uLED. The memory and control logic circuit 13 generates the display signal DIS, for example, based on a preset temporary or long-term memory setting, in conjunction with the output of the PWM signal generation circuit. For example, the luminance current Igrs is, for instance, the current that makes the light-emitting element uLED have the highest luminance (brightest). This current is modulated by the display signal DIS, which includes the PWM signal, and the grayscale of the light-emitting element uLED can be adjusted according to the user's needs.

[0098] In this embodiment, the display transistor MP2 is connected in series between the bias transistor MP3 and the level shift transistor MP1.

[0099] In this embodiment, the bias transistor MP3 and the display transistor MP2 do not share the same transistor, but are different transistors.

[0100] It should be noted that the bias transistor MP3 operates according to the bias signal BIAS to provide the luminance current Igrs. This luminance current Igrs needs to have a fixed and stable level when the corresponding light-emitting element uLED emits light, so that the corresponding light-emitting element uLED has a fixed and stable luminance when emitting light; and the grayscale of the corresponding light-emitting element uLED is determined by the duty cycle of the pulse width modulation signal of the display signal DIS. Therefore, in one embodiment, for example, when the corresponding light-emitting element uLED emits light, the gate-source voltage of the bias transistor MP3 is maintained at a fixed and stable level to provide a fixed and stable luminance current Igrs.

[0101] Figure 3 This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention. Figure 3 The pixel circuit 10 of the electroluminescent display shown is... Figure 2 Similarly, it is also a common cathode structure. Figure 3 Example 10 shown and Figure 2 The difference in the illustrated embodiment is that, in Figure 3 In the pixel circuit 10 of the electroluminescent display shown, the bias transistor MP3 is connected in series between the display transistor MP2 and the level shift transistor MP1.

[0102] Figure 4 This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention. Figure 4 As shown, the pixel circuit 20 of the electroluminescent display includes a level shift transistor MN1, a display transistor MN2, and a bias transistor MN3. For example... Figure 4 As shown, level shift transistor MN1 is coupled between the corresponding light-emitting element uLED and the level shift terminal LS. It is used to limit the operating voltage drop Vod between the voltage Vls of the level shift terminal LS and the first potential LV1 to not exceed the clamping level, based on the enable light-emitting signal EM generated by the level shift control circuit 11. Bias transistor MN3 operates according to the bias signal BIAS to provide the luminance current Igrs. Display transistor MN2 and bias transistor MN3 are connected in series between the level shift terminal LS and the first potential LV1. They operate according to the display signal DIS to modulate the luminance current Igrs into a display current Idis, providing the display current Idis to the corresponding light-emitting element uLED. The light-emitting element uLED is coupled between level shift transistor MN1 and the second potential LV2, and the first potential LV1 and the second potential LV2 are different, meaning that the series voltage difference between the first potential LV1 and the second potential LV2 is non-zero.

[0103] In this embodiment, the level shift transistor MN1, the display transistor MN2, and the bias transistor MN3 are coupled in a common anode structure, and all three are N-type metal oxide semiconductor (NMOS) devices.

[0104] In this embodiment, the voltage ratings of both the display transistor MN2 and the bias transistor MN3 exceed the clamping level. That is, the level shift transistor MN1 uses a transistor with a relatively high voltage rating, and the level shift transistor MP1 is used to limit the operating voltage drop Vod between the voltage Vls at the level shift terminal LS and the first potential LV1 to not exceed the clamping level. Thus, as long as the voltage rating of the level shift transistor MN1 exceeds the voltage difference between the first potential LV1 and the second potential LV2, and both the display transistor MN2 and the bias transistor MN3 use transistors with voltage ratings exceeding the clamping level, the configuration according to the present invention will prevent damage under normal operation. In other words, both the display transistor MN2 and the bias transistor MN3 can use transistors with relatively low voltage ratings, i.e., less than the voltage difference between the first potential LV1 and the second potential LV2, to reduce the pixel circuit area.

[0105] For example, the first potential LV1 is, for example, ground potential GND, which is, for example, 0V, and the second potential LV2 is, for example, the positive drive voltage ELVDD, which is, for example, between 3V and 8V. The level shift transistor MN1, based on the enable signal EM, limits the operating voltage drop Vod between the level shift terminal LS and the first potential LV1 to, for example, no more than 1.2V, meaning the clamping level is, for example, 1.2V. Therefore, as long as both the display transistor MN2 and the bias transistor MN3 are transistors with a withstand voltage exceeding 1.2V (a 1.2V withstand transistor has a smaller component area compared to an 8V withstand transistor), they will not be damaged under normal operation. On the other hand, taking a positive drive voltage ELVDD of 7.6V as an example, the level shift transistor MN1 must be selected as a transistor with a withstand voltage exceeding 7.6V. However, the display transistor MN2 and the bias transistor MN3 connected in series between the first potential LV1 and the second potential LV2 can be selected as having a withstand voltage exceeding 1.2V. It is only necessary for the withstand voltage of the level shift transistor MN1 to exceed the series voltage difference of 7.6V. Since the pixel circuit uses some transistors with lower withstand voltage (smaller component area), it is not necessary to use all transistors with higher withstand voltage (larger component area). The pixel circuit area is relatively reduced, and a relatively high resolution can be obtained per unit area of ​​the display panel.

[0106] In this embodiment, the display transistor MN2 is connected in series between the bias transistor MN3 and the level shift transistor MN1.

[0107] In this embodiment, the bias transistor MN3 and the display transistor MN2 do not share the same transistor, but are different transistors.

[0108] Figure 5 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. Figure 5 The pixel circuit 20 of the electroluminescent display shown is... Figure 4 Similarly, it is also a common anode structure. Figure 5 Example 20 shown Figure 4 The difference in the illustrated embodiment is that, in Figure 5 In the pixel circuit 20 of the electroluminescent display shown, the bias transistor MN3 is connected in series between the display transistor MN2 and the level shift transistor MN1.

[0109] Figure 6 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. Figure 6 The pixel circuit 10 of the electroluminescent display shown is... Figure 2 Similarly, it is also a common cathode structure. Figure 6 The illustrated embodiments and Figure 2 The difference in the illustrated embodiment is that, in Figure 6 In the pixel circuit 10 of the electroluminescent display shown, the bias transistor MP3 and the display transistor MP2 share the same transistor. It should be noted that in this embodiment, when the bias transistor MP3 and the display transistor MP2 share the same transistor, the display signal DIS, in addition to providing a pulse width modulation signal to control the grayscale of the light-emitting element uLED, also maintains the luminance current Igrs (in this embodiment, the luminance current Igrs is the same as the display current Idis) at a fixed and stable level when the display signal DIS enables the light-emitting element uLED to emit light (in this embodiment, it is a low level because the bias transistor MP3 is a PMOS element, and it is turned on at a low level to enable the light-emitting element uLED to emit light). This ensures that the corresponding light-emitting element uLED has a fixed and stable luminance when it emits light.

[0110] Figure 7 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. Figure 7 The pixel circuit 20 of the electroluminescent display shown is... Figure 4 Similarly, it is also a common cathode structure. Figure 7 The illustrated embodiments and Figure 4 The difference in the illustrated embodiment is that, in Figure 7In the pixel circuit 20 of the electroluminescent display shown, the bias transistor MN3 and the display transistor MN2 share the same transistor. It should be noted that in this embodiment, when the bias transistor MN3 and the display transistor MN2 share the same transistor, the display signal DIS, in addition to providing a pulse width modulation signal to control the grayscale of the light-emitting element uLED, also maintains the luminance current Igrs (in this embodiment, the luminance current Igrs is the same as the display current Idis) at a fixed and stable level when the display signal DIS enables the light-emitting element uLED to emit light (a high level in this embodiment, because the bias transistor MN3 is an NMOS device, and a high level enables the light-emitting element uLED to emit light). This ensures that the corresponding light-emitting element uLED has a fixed and stable luminance when it emits light.

[0111] Figure 8 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. This embodiment is intended to illustrate a case where the pixel circuits of multiple electroluminescent displays are connected in parallel. Figure 8 As shown, in the pixel circuit of the parallel-connected electroluminescent display, multiple bias transistors MP3 can operate according to the same bias signal BIAS, and multiple level shift transistors MP1 can operate according to the same enable emission signal EM. Multiple display transistors MP21, MP22, MP23, etc., can operate according to their respective display signals DIS1, DIS2, DIS3, etc., to determine the grayscale of their respective light-emitting elements uLED. In this embodiment, the level shift transistors MP1, display transistors MP2, and bias transistors MP3 in the pixel circuit of the multiple electroluminescent displays are, for example, PMOS elements.

[0112] Figure 9 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. This embodiment is intended to illustrate a case where the pixel circuits of multiple electroluminescent displays are connected in parallel. Figure 9 As shown, in the pixel circuit of the parallel-connected electroluminescent display, multiple bias transistors MN3 can operate according to the same bias signal BIAS, and multiple level shift transistors MN1 can operate according to the same enable emission signal EM. Multiple display transistors MN2A, MN2B, MN2C, etc., can operate according to their respective display signals DIS1, DIS2, DIS3, etc., to determine the grayscale of their respective light-emitting elements uLED. In this embodiment, the level shift transistors MN1, display transistors MN2, and bias transistors MN3 in the pixel circuit of the multiple electroluminescent displays are, for example, NMOS elements.

[0113] Figure 10This is a schematic diagram of the pixel circuit of an electroluminescent display according to an embodiment of the present invention. This embodiment shows a schematic diagram of the pixel circuit 22 of an electroluminescent display operable in non-overlap mode according to the present invention. Figure 10 As shown, the pixel circuit 22 of the electroluminescent display includes a level shift transistor 221, a bias transistor 222, a display transistor 223, a refresh switch 224, an auxiliary switch 225, and a capacitor C. In this embodiment, the level shift transistor 221 is coupled between the corresponding light-emitting element uLED and the level shift terminal LS, and is used to limit the operating voltage drop Vod between the voltage Vls of the level shift terminal LS and the first potential LV1 to not exceed the clamping level according to the enable light-emitting signal EM. The bias transistor 222 is used to operate according to the bias signal Vrm to provide the luminance current Igrs. The display transistor 223 and the bias transistor 222 are connected in series between the level shift terminal LS and the first potential LV1, and are used to operate according to the display signal DIS to modulate the luminance current Igrs into a display current Idis, which is then provided to the corresponding light-emitting element uLED. The light-emitting element uLED is coupled between the level shift transistor 221 and the second potential LV2, and the first potential LV1 and the second potential are different from LV2.

[0114] During the update, update switch 224 and auxiliary switch 225 operate according to the update signal RFSH, turning on during the update period and electrically connecting the transresistor output terminal Nio of bias transistor 222 to the transresistor control terminal Ncr, thereby configuring bias transistor 222 (or the transresistor transistor therein, detailed later) as diode-connected. This diode-connected bias transistor 222 (or the transresistor transistor therein) and capacitor C are connected in parallel between the first potential LV1 and the current digital-to-analog converter (DAC) 232 of the corresponding drive circuit 23, thereby charging / discharging capacitor C to maintain the bias signal Vrm during the update period. The configuration of the transistor as diode-connected and the gate capacitance of the MOS capacitor are well known to those skilled in the art and will not be elaborated upon here.

[0115] Continue reading Figure 10 The update switch 224 operates according to the update signal RFSH. In this embodiment, the update switch 224 and the auxiliary switch 225 operate synchronously to conduct during the update period to charge / discharge the capacitor C; the update switch 224 and the auxiliary switch 225 are turned off after the update period ends to prevent leakage of the capacitor C.

[0116] In one embodiment, the bias transistor 222 includes a transresistor transistor and a transconductor transistor. Figure 10The pixel circuit 22 shown is suitable for operation in a non-overlapping mode, meaning the update period and the display period do not overlap. Therefore, the transducer and transconductance transistors of the bias transistor 222 can share the same transistor. During the update period, this transistor acts as the transducer of the bias transistor 222; while during the display period, it acts as the transconductance transistor of the bias transistor 222. In one embodiment, the update signal RFSH is a periodic signal with a fixed period, which, during the update period, alternately charges the capacitors C in the plurality of pixel circuits 22 in the light-emitting element array. In one embodiment, the period of the update signal RFSH is related to the leakage rate of the capacitor C. It should be noted that the non-overlapping update period and display period refer to the same pixel circuit 22; that is, while one pixel circuit 22 is operating during the display period, another pixel circuit 22 can operate during the update period.

[0117] Figure 11 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. Figure 11 The pixel circuit 22 of the electroluminescent display shown is... Figure 10 The pixel circuit 22 of the electroluminescent display shown is one specific embodiment. For example... Figure 11 As shown, in the pixel circuit 22 of the electroluminescent display, the level shift transistor 221, bias transistor 222, display transistor 223, update switch 224, and auxiliary switch 225 are, for example but not limited to, PMOS elements, and the capacitor C includes the gate capacitance of a MOS capacitor. In this embodiment, the transducer and transconductance transistors of the bias transistor 222 are the same transistor. The display transistor 223 operates according to the display signal DIS. In this embodiment, the display transistor 223, bias transistor 222, capacitor C, auxiliary switch 225, and update switch 224 are all P-type metal-oxide-semiconductor (MOS) elements. According to the present invention, the display transistor 223, bias transistor 222, capacitor C, auxiliary switch 225, and update switch 224 can also be NMOS elements, only requiring adjustment and coupling of each element and circuit in the overall circuit. In this embodiment, the drain of the bias transistor 222 serves as the transducer output terminal Nio, and the gate serves as the transducer control terminal Ncr.

[0118] Please continue reading. Figure 11During the update, the update signal RFSH turns on the auxiliary switch 225 and the update switch 224, causing the first luminance current Igrs1 to flow through the reluctance transistor and gate capacitor of the bias transistor 222 connected in parallel between the first potential VDD and the current-to-digital converter 232. In other words, the sum of the current flowing through the reluctance transistor and the current flowing through the capacitor C (gate capacitor) equals the first luminance current Igrs1. Since the reluctance transistor of the bias transistor 222 is configured as a diode, and the shunt current Igrs1 flows through the reluctance transistor of the bias transistor 222, it can be determined that the reluctance transistor operates in the saturation region in the steady state. The gate-source voltage of the transresistor gradually increases until the corresponding current flowing through it equals the first brightness current Igrs1, at which point the increase stops. When the gate-source voltage of the transresistor stops increasing, the voltage across the gate capacitance also stops increasing. By appropriately arranging the electrical characteristics of the transresistor, the voltage at the transresistor control terminal Ncr is maintained at a fixed bias signal Vrm. After the update period ends, the update signal RFSH turns off the auxiliary switch 225 and the update switch 224 to prevent leakage of the gate capacitance and maintain the bias signal Vrm.

[0119] On the other hand, during the display period, since the gate capacitance is coupled between the gate and source of the transconductance transistor of the bias transistor 222, the gate-source voltage of the transconductance transistor is determined by the voltage across the gate capacitance. Therefore, the transconductance transistor generates a second luminance current Igrs2 according to the bias signal Vrm, and the second luminance current Igrs2 is positively correlated with the first luminance current Igrs1 (in one embodiment, they are equal because the transresistance transistor and the transconductance transistor are the same transistor). The pulse width modulation signal is used as the display signal DIS to switch the display transistor 223 to modulate the second luminance current Igrs2 as the display current Idis, thereby determining the grayscale of the light-emitting element uLED. This update period and the display period do not overlap with each other. During the display period, the pixel circuit 22 of the electroluminescent display supplies the display current Idis to the corresponding at least one light-emitting element uLED.

[0120] Figure 12 This is a schematic diagram of the pixel circuit of an electroluminescent display according to another embodiment of the present invention. Figure 12 The pixel circuit 22 of the electroluminescent display shown is a more specific embodiment of an electroluminescent display pixel circuit 22 operable in overlap mode. For example... Figure 12 As shown, the pixel circuit 22 of the electroluminescent display includes a level shift transistor 221, a bias transistor 222 (including a transducer transistor 2221 and a transconductance transistor 2222), a display transistor 223, a refresh switch 224, an auxiliary switch 225, and a capacitor C.

[0121] Please continue reading. Figure 12 During the update, the update signal RFSH turns on the auxiliary switch 225 and the update switch 224, causing the first luminance current Igrs1 to flow through the transducer transistor 2221 and the capacitor C (gate capacitance) connected in parallel between the first potential VDD and the current-to-digital converter 232. In other words, the sum of the current flowing through the transducer transistor 2221 and the current flowing through the gate capacitor equals the first luminance current Igrs1. Since the transducer transistor 2221 is configured as a diode, and the first luminance current Igrs1 is shunt through the transducer transistor 2221, it can be determined that the transducer transistor 2221 operates in the saturation region in steady state. The gate-source voltage of the transducer transistor 2221 gradually increases until the current flowing through it equals the first brightness current Igrs1, at which point the increase stops. When the gate-source voltage of the transducer transistor 2221 stops increasing, the voltage across the gate capacitance also stops increasing. By appropriately arranging the electrical characteristics of the transducer transistor 2221, the voltage at the transducer control terminal Ncr is maintained at the bias signal Vrm. After the update period ends, the update signal RFSH turns off the auxiliary switch 225 and the update switch 224 to prevent leakage of the gate capacitance and maintain a fixed and stable bias signal Vrm during the update period.

[0122] On the other hand, during the display period, since the gate capacitance (capacitor C) is coupled between the gate and source of the transconducting transistor 2222, the gate-source voltage of the transconducting transistor 2222 is determined by the voltage across the gate capacitance. Therefore, the transconducting transistor 2222 generates a second luminance current Igrs2 according to the bias signal Vrm, and the second luminance current Igrs2 is positively correlated with the first luminance current Igrs1 (in one embodiment, they are equal, and the transresistor transistor 2221 and the transconducting transistor 2222 can be two transistors with the same electrical characteristics). The pulse width modulation signal is used as the display signal DIS to switch the display transistor 221, modulating the second luminance current Igrs2 into a display current Idis to determine the grayscale of the light-emitting element uLED. Since the transresistor transistor 2221 and the transconducting transistor 2222 are two different transistors, this update period and this display period can overlap with each other. During this display period, the pixel circuit 22 of the electroluminescent display supplies the display current Idis to the corresponding at least one light-emitting element uLED.

[0123] In this embodiment, the transducer transistor 2221, the auxiliary switch 225, and the transconducting transistor 2222 form a current mirror circuit, which mirrors the first luminance current Igrs1 into a second luminance current Igrs2 during the update period. The second luminance current Igrs2 generated by the transconducting transistor 2222 is maintained at a fixed level relative to the first luminance current Igrs1. This embodiment is operable in an overlap mode, meaning that the update period and the display period are not limited to not overlapping each other; that is, the update period and the display period can overlap each other, that is, the update period and the display period can optionally have an overlapping period. In one embodiment, the update period and the display period have an overlapping period; while in another embodiment, the update period and the display period do not overlap each other. Since the transconducting transistor 2222 can generate and maintain a second luminance current Igrs2 relative to the first luminance current Igrs1 during both the overlapping and non-overlapping display periods, therefore... Figure 12 In the illustrated embodiment, the update period and the display period may overlap. In one embodiment, the update signal RFSH is a periodic signal with a fixed period, the period of which depends on the pairing of the current digital-to-analog converter 232 with the pixel circuit 22 of the electroluminescent display. The pairing refers to whether the current digital-to-analog converter 232 drives a single-column or multi-column architecture.

[0124] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. Various equivalent variations can be conceived by those skilled in the art within the same spirit of the invention. In the embodiments, other steps that do not affect the main function can be inserted between two steps directly connected in the illustrations, as long as they do not affect the achievement of the purpose of the invention. All of these can be deduced by analogy from the teachings of the present invention; therefore, the scope of the invention should cover the above and all other equivalent variations. The foregoing embodiments are not limited to individual application and can also be combined, for example, but not limited to using two embodiments together, or substituting some steps of one embodiment for some steps of another embodiment.

Claims

1. A pixel circuit for an electroluminescent display, comprising: A quasi-shift transistor is coupled between a corresponding light-emitting element and a quasi-shift terminal to limit an operating voltage drop between the voltage of the quasi-shift terminal and a first potential to not exceed a clamping level, according to an enable light-emitting signal. A bias transistor, used to operate according to a bias signal to provide a brightness current; and A display transistor, connected in series with the bias transistor between the level shift terminal and the first potential, is used to operate according to a display signal to modulate the luminance current into a display current and provide it to the corresponding light-emitting element. in, The light-emitting element is coupled between the level shift transistor and a second potential, and the first potential is different from the second potential.

2. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The level shift transistor, the display transistor, and the bias transistor are coupled to a common cathode structure, and all three are P-type metal-oxide-semiconductor (PMOS) devices.

3. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The level shift transistor, the display transistor, and the bias transistor are coupled to a common anode structure, and all three are N-type metal-oxide-semiconductor (NMOS) devices.

4. The pixel circuit of the electroluminescent display as described in claim 1, wherein, Both the display transistor and the bias transistor have a voltage rating exceeding the clamping level.

5. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The display signal includes a pulse width modulation (PWM) signal with a duty cycle. The PWM signal is used to switch the corresponding display transistor to generate the display current, thereby determining the grayscale of the corresponding light-emitting element.

6. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The display transistor is connected in series between the bias transistor and the level shift transistor.

7. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The bias transistor is connected in series between the display transistor and the level shift transistor.

8. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The bias transistor and the display transistor share the same transistor.

9. The pixel circuit of the electroluminescent display as described in claim 1, wherein, The voltage withstand capability of the level shift transistor exceeds a series voltage difference between the first potential and the second potential, and the series voltage difference exceeds the voltage withstand capability of the bias transistor and the voltage withstand capability of the display transistor.

10. The pixel circuit of the electroluminescent display as claimed in claim 1, wherein, It also includes a gate capacitor for charging / discharging the gate capacitor with a luminance current during a refresh period to maintain the level of the bias signal, and is coupled to the bias transistor during a display period to provide the luminance current by maintaining the voltage difference between a transconductance control terminal of the bias transistor and the first potential.

11. The pixel circuit of the electroluminescent display as claimed in claim 10, wherein, Also includes: A refresh switch, operable in response to a refresh signal, to provide the luminance current during the refresh period; and An auxiliary switch is used to electrically connect a resistor output terminal of the bias transistor to a resistor control terminal during the update period, configured as a diode connection, and connected in parallel with the gate capacitor between the first potential and a current input / output terminal, to charge / discharge the capacitor to maintain the level of the bias signal.

12. The pixel circuit of the electroluminescent display as claimed in claim 11, wherein, The auxiliary switch is turned off after the update period ends, and the update period and the display period do not overlap. During the display period, the pixel circuit supplies the display current to the corresponding light-emitting element.

13. The pixel circuit of the electroluminescent display as described in claim 12, wherein, The bias transistor includes a resistive transistor and a transconducting transistor, and the resistive transistor and the transconducting transistor do not share the same transistor. During the update period, the auxiliary switch electrically connects the output terminal of the transducer transistor to the control terminal of the transducer transistor, and configures it as a diode connection, so as to connect it in parallel with the gate capacitor between the first potential and the current input / output terminal, and charges / discharges the gate capacitor to maintain the level of the bias signal. The auxiliary switch is turned off during the display segment, and the gate capacitor is coupled between the first potential and the transduction control terminal of the transduction transistor to provide the brightness current based on the voltage difference between the transduction control terminal of the transduction transistor and the first potential.

14. The pixel circuit of the electroluminescent display as described in claim 13, wherein, The update period of this segment and the display period of this segment may optionally overlap or not overlap.

15. The pixel circuit of the electroluminescent display as described in claim 13, wherein, The transconducting transistor, the auxiliary switch, and the transconducting transistor together form a current mirror circuit, which, during the update period, mirrors the luminance current into the luminance current.

Images