Memory, control method of memory, memory chip and electronic equipment

Abstract

The embodiment of the invention belongs to the technical field of storage, and particularly relates to a storage, a control method of the storage, a storage chip and electronic equipment. The memory comprises a memory controller and a memory chip. The storage controller is used for determining whether the failure rate of first data read from the storage chip is larger than a failure rate threshold value or not, when the failure rate is larger than the failure rate threshold value, a shielding circuit in the storage chip is controlled to shield a storage unit corresponding to second data in the storage chip, and the second data are data which are not read wrongly in the first data. An operation circuit of the storage chip is controlled to reread the storage unit corresponding to the first data to obtain third data, and the third data comprises data obtained after the unshielded storage unit is reread. And obtaining reread data according to the second data and the third data. By adopting the method and the device, the storage unit without errors can be prevented from being repeatedly read, and the probability of reading interference of the storage unit can be reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a method for controlling the memory, a memory chip, and an electronic device. Background Technology

[0002] Threshold voltage drift refers to the phenomenon that the threshold voltage of a memory cell gradually increases over time, and it is an important factor affecting the accuracy of data storage in memory chips.

[0003] In related technologies, to address the impact of threshold voltage drift on memory cells, memory chips can be configured with multiple read voltage levels for each cell. When reading multiple memory cells corresponding to a specific address, the memory chip can initially perform read operations using a lower read voltage. If it's determined that a large number of memory cells have failed reads, a higher read voltage can be used to perform read operations again. Thus, if the high failure rate of multiple memory cells is due to an increase in the cell's threshold voltage, synchronously increasing the read voltage can effectively solve this problem, thereby improving the accuracy of reading memory cells.

[0004] When performing read operations on multiple memory cells using a higher read voltage, memory cells that have not encountered errors will also be read again. Such frequent read operations on memory cells may cause read interference problems. Summary of the Invention

[0005] This application provides a memory, a memory control method, a memory chip, and an electronic device, which can prevent error-free memory cells from being repeatedly read, reduce the probability of read interference in memory cells, improve the lifespan of memory cells, and reduce the power consumption of the memory. The corresponding technical solutions include:

[0006] In a first aspect, a memory is provided, comprising a memory controller and a memory chip. The memory controller is configured to: determine whether the failure rate of first data read from the memory chip is greater than a failure rate threshold; if the failure rate is greater than the failure rate threshold, control a shielding circuit in the memory chip to shield the memory cell corresponding to second data, wherein the second data is the data in the first data that was not read incorrectly; control the operating circuit of the memory chip to reread the memory cell corresponding to the first data to obtain third data, wherein the third data includes data obtained after rereading the unshielded memory cell; and obtain reread data based on the second data and the third data.

[0007] In the memory shown in this application, after performing a read operation on multiple memory cells, if the failure rate of the first data obtained is high, a higher read voltage can be used to read the multiple memory cells again. During the rereading process, the memory can control the shielding circuit of the memory chip to shield the memory cells corresponding to the second data that was not read incorrectly, that is, to shield the subsequent operating voltage applied to these memory cells. In this way, when the operating circuit applies a read voltage to multiple memory cells again, the read voltage will only act on the memory cells that may have read errors. This reduces the number of times some memory cells are read, thereby reducing the probability of read interference in the memory cells, and improving the lifespan of the memory cells and reducing the power consumption of the memory chip.

[0008] In one possible implementation, the second data is the data in the first data that indicates the corresponding memory cell is in a low-impedance state. The memory controller is further configured to determine whether the first data is still cached in the memory chip after it has been read, and if it is determined that the first data is still cached in the memory chip, send a reread mask command to the operating circuitry of the memory chip. The operating circuitry of the memory chip, in response to the reread mask command, controls the masking circuit to mask the memory cell corresponding to the second data, and while the memory cell corresponding to the second data is masked, rereads the memory cell corresponding to the first data.

[0009] Threshold voltage drift primarily causes an increase in the threshold voltage of the memory cell, leading to a memory cell in a low-resistance state being mistakenly identified as a memory cell in a high-resistance state, resulting in data read errors. In other words, the data that may cause read errors mainly indicates that the memory cell is in a high-resistance state; therefore, the second data indicating that the corresponding memory cell is in a low-resistance state can be considered as data that was read without error. Thus, in the memory shown in this application, the shielding circuit in the memory chip can shield the memory cell according to the indication of the second data. Therefore, before shielding, the memory controller can determine whether the memory chip still caches the first data. If the memory chip caches the first data, the memory controller can directly send a reread shielding command to the operation circuit of the memory chip, instructing the shielding circuit to shield the memory cell according to the second data included in the first data. This improves the efficiency of the shielding circuit in shielding the memory cell.

[0010] In one possible implementation, the shielding circuit includes multiple inverting circuits. The inputs of these inverting circuits are connected to multiple first latches in the memory chip, and the outputs of these circuits are connected to the enable terminals of multiple memory cells corresponding to the first data. The multiple first latches are used to buffer the first data. The operating circuit of the memory chip is used to enable the multiple inverting circuits, causing the inverting circuit connected to the second latch to output a shielding signal to its connected enable terminal. The second latch is one of the multiple first latches that buffers the second data.

[0011] In the memory shown in this application, the inverting circuit can convert the high-level output of the second latch into a low-level output and apply it to the enable terminal corresponding to the memory cell, thereby shielding the memory cell. For latches that cache other data, the low-level output can be converted into a high-level output by the inverting circuit and applied to the enable terminal corresponding to the memory cell, without shielding the memory cell. Thus, the inverting circuit does not need to distinguish the second data separately; it can shield the memory cell corresponding to the second data based on the indication of the second data, thereby improving the efficiency of the shielding circuit in shielding the memory cell.

[0012] In one possible implementation, the storage controller is further configured to, upon determining that the first data is not in the storage chip cache, invert the first data, send the inverted data to a shielding circuit, and send a reread command to the operation circuit. The storage chip's shielding circuit is configured to shield the storage cell corresponding to the second data according to the inverted data. The storage chip's operation circuit, in response to the reread command, rereads the storage cell corresponding to the first data while the storage cell corresponding to the second data is shielded.

[0013] In the memory shown in this application, if the memory controller determines that the first data is no longer cached in the memory chip, the memory controller can invert the first data and send the inverted data to the shielding circuit to instruct the shielding circuit to shield the memory cell corresponding to the second data. This allows the shielding circuit to shield the memory cell even when the first data is not cached in the memory chip.

[0014] In one feasible implementation, the shielding circuit includes a register, with multiple output terminals connected to the enable terminals of multiple memory cells corresponding to the first data. The register of the shielding circuit stores the inverted data sent by the memory chip, causing the output terminal in the register corresponding to the fourth data to output a shielding signal to the connected enable terminal. The fourth data is data obtained by inverting the second data, which is included in the inverted data. In this way, the register in the shielding circuit can directly shield the memory cells by storing the inverted data sent by the memory controller, thus improving the efficiency of the shielding circuit in shielding the memory cells.

[0015] In one possible implementation, the memory controller is used to store the inverted data into a register via the data mask (DM) port of the memory chip or the input logic circuitry included in the operating circuitry.

[0016] In one possible implementation, the operating circuit includes an address decoding circuit, a sensing circuit, and an input / output gating circuit. The enable terminal of the memory cell includes an enable terminal in the address decoding circuit corresponding to the memory cell, an enable terminal in the sensing circuit corresponding to the memory cell, or an enable terminal in the input / output gating circuit corresponding to the memory cell.

[0017] In one possible implementation, the storage controller is used to replace all data in the third data except for the fourth data with the second data to obtain reread data, wherein the fourth data is the data obtained by rereading the unmasked storage cells included in the third data.

[0018] In the memory shown in this application, if the first data is not cached in the memory chip, the memory chip may store data corresponding to memory cells at other addresses. Therefore, after a reread, the data cached by the memory chip contains data from other addresses (i.e., the fourth data) and the reread data corresponding to the unmasked memory cells. Thus, by replacing the fourth data with the second data corresponding to the previously unread but erroneously accessed memory cell, the reread data can be obtained, which is the data that was not read incorrectly plus the data after rereading the potentially erroneously accessed data.

[0019] Secondly, a method for controlling a memory is provided, the memory including a memory controller and a memory chip, the method comprising:

[0020] The storage controller determines whether the failure rate of the first data read from the storage chip is greater than a failure rate threshold. If the failure rate is greater than the threshold, it controls the shielding circuit in the storage chip to shield the storage cell corresponding to the second data, where the second data is the data in the first data that was not read incorrectly. The storage controller then controls the storage chip to reread the storage cell corresponding to the first data to obtain the third data, which is the data obtained after rereading the unshielded storage cell. The reread data is obtained based on the second and third data.

[0021] In one possible implementation, the second data is the data in the first data that indicates the corresponding memory cell is in a low-resistance state, and the method further includes: the memory controller determining whether the first data is still cached in the memory chip after it has been read.

[0022] The storage controller controls the storage chip to reread the storage cell corresponding to the first data, including: when the storage controller determines that the first data is still in the storage chip cache, it sends a reread mask command to the storage chip's operating circuit. The storage chip's operating circuit responds to the reread mask command by controlling the masking circuit to mask the storage cell corresponding to the second data, and while the storage cell corresponding to the second data is masked, it rereads the storage cell corresponding to the first data.

[0023] In one possible implementation, the shielding circuit includes multiple inverting circuits. The inputs of these inverting circuits are connected to multiple first latches in the memory chip, and the outputs of these inverting circuits are connected to the enable terminals of multiple memory cells corresponding to the first data. The multiple first latches are used to buffer the first data. Controlling the shielding circuit to shield the memory cell corresponding to the second data includes: the memory chip's operating circuit enabling the multiple inverting circuits, causing the inverting circuit connected to the second latch to output a shielding signal to its connected enable terminal. The second latch is one of the multiple first latches that buffers the second data.

[0024] In one feasible approach, the shielding circuit in the memory chip shields the memory cell corresponding to the second data, including: if the memory controller determines that the first data is not in the memory chip cache, it inverts the first data, sends the inverted data to the shielding circuit, and sends a reread command to the operation circuit. The shielding circuit of the memory chip shields the memory cell corresponding to the second data according to the inverted data. Responding to the reread command, the operation circuit of the memory chip rereads the memory cell corresponding to the first data while the memory cell corresponding to the second data is shielded.

[0025] In one possible implementation, the shielding circuit includes a register, with multiple output terminals of the register connected to the enable terminals of multiple memory cells corresponding to the first data. The shielding circuit of the memory chip shields the memory cells corresponding to the second data according to the inverted data, including: the register of the shielding circuit stores the inverted data sent by the memory chip, so that the output terminal corresponding to the fourth data outputs a shielding signal to the connected enable terminal; the fourth data is the data obtained by inverting the second data, which is included in the inverted data.

[0026] In one feasible approach, sending the inverted data to the masking circuit includes: the storage controller storing the inverted data into a register via the Data Mask port of the storage chip or the input logic circuit included in the operation circuit.

[0027] In one possible implementation, the operating circuit includes an address decoding circuit, a sensing circuit, or an input / output gating circuit, and the enable terminal of the memory cell is the enable terminal connected to the memory cell in the address decoding circuit, the enable terminal connected to the memory cell in the sensing circuit, or the enable terminal connected to the memory cell in the input / output gating circuit.

[0028] In one feasible approach, obtaining reread data based on the second data and the third data includes: replacing all data in the third data except for the fourth data with the second data to obtain the reread data, wherein the fourth data is the data obtained after rereading the unmasked storage unit included in the third data.

[0029] Thirdly, a memory chip is provided, which is connected to a memory controller. The memory chip includes an operation circuit and a shielding circuit. The operation circuit reads first data and sends the first data to the memory controller. The shielding circuit shields the memory cell corresponding to second data in the memory chip when the memory controller determines that the failure rate of the first data is greater than a failure rate threshold. The second data is the data in the first data that was not read incorrectly. The operation circuit rereads the memory cell corresponding to the first data to obtain third data, which is the data obtained after rereading the unshielded memory cell. The operation circuit sends the third data to the memory controller so that the memory controller receives the reread data determined by the second and third data.

[0030] In one possible implementation, the second data is the data in the first data that indicates the corresponding memory cell is in a low-impedance state. The operating circuit of the memory chip is used to receive a reread masking command, control the masking circuit to mask the memory cell corresponding to the second data, and, while the memory cell corresponding to the second data is being masked, reread the memory cell corresponding to the first data. The reread masking command is sent by the memory controller after determining that the failure rate of the first data is greater than a failure rate threshold and that the first data is still in the memory chip cache after being read.

[0031] In one possible implementation, the shielding circuit includes multiple inverting circuits. The inputs of these inverting circuits are connected to multiple first latches in the memory chip, and the outputs of these circuits are connected to the enable terminals of multiple memory cells corresponding to the first data. The multiple first latches are used to buffer the first data. The operating circuit of the memory chip is used to enable the multiple inverting circuits, causing the inverting circuit connected to the second latch to output a shielding signal to its connected enable terminal. The second latch is one of the multiple first latches that buffers the second data.

[0032] In one possible implementation, the shielding circuit of the memory chip is used to receive inverted data of the first data, and to shield the memory cell corresponding to the second data according to the inverted data. The inverted data is sent by the memory controller after determining that the failure rate of the first data is greater than a failure rate threshold and that the first data is not cached by the memory chip after being read. The operating circuit of the memory chip is used to receive a reread instruction and, while the memory cell corresponding to the second data is shielded, to reread the memory cell corresponding to the first data. The reread instruction is sent by the memory controller after determining that the failure rate of the first data is greater than a failure rate threshold and that the first data is not cached by the memory chip after being read.

[0033] In one possible implementation, the shielding circuit includes a register, with multiple output terminals connected to the enable terminals of multiple memory cells corresponding to the first data. The register of the shielding circuit is used to store the inverted data sent by the memory chip, so that the output terminal corresponding to the fourth data outputs a shielding signal to the connected enable terminal. The fourth data is the data obtained by inverting the second data, which is included in the inverted data.

[0034] In one possible implementation, the register of the shielding circuit receives inverted data sent by the memory controller via the Data Mask port of the memory chip or the input logic circuitry included in the operating circuitry.

[0035] In one possible implementation, the operating circuit includes an address decoding circuit, a sensing circuit, and an input / output gating circuit. The enable terminal of the memory cell includes an enable terminal in the address decoding circuit corresponding to the memory cell, an enable terminal in the sensing circuit corresponding to the memory cell, or an enable terminal in the input / output gating circuit corresponding to the memory cell.

[0036] In one possible implementation, the operating circuitry of the memory chip is used to send third data to the memory controller, so that the memory controller replaces all data in the third data except for the fourth data with the second data to obtain reread data, wherein the fourth data is the data obtained after rereading the unmasked memory cells included in the third data.

[0037] Fourthly, an electronic device is provided, comprising a processor and a memory as described in the first aspect above, wherein the processor is configured to send read / write instructions to the memory to enable the memory to perform read / write operations. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0039] Figure 2This is a schematic diagram of a memory provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of a threshold voltage distribution provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0042] Figure 5 This is a flowchart of a control method for a memory chip provided in an embodiment of this application;

[0043] Figure 6 This is a flowchart of a control method for a memory chip provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of an instruction structure provided in an embodiment of this application;

[0046] Figure 9 This is a schematic diagram of a method for applying a shielding signal according to an embodiment of this application;

[0047] Figure 10 This is a connection diagram of an inverter provided in an embodiment of this application;

[0048] Figure 11 This is a waveform diagram of executing a read retry instruction provided in an embodiment of this application;

[0049] Figure 12 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0050] Figure 13 This is a schematic diagram of a register connection provided in an embodiment of this application;

[0051] Figure 14 This is a waveform diagram of executing a read retry instruction provided in an embodiment of this application;

[0052] Figure 15 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0053] Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0055] The following explains some terms used in the embodiments of this application:

[0056] Resistive memory: It uses changes in resistance to store or retrieve data. For example, a resistive memory can store "0" in a high resistance state and "1" in a low resistance state.

[0057] Phase Change Memory (PCM): A novel non-volatile semiconductor memory based on chalcogenide compounds, belonging to the resistive memory category. It utilizes the difference in resistance between the crystalline and amorphous states of the phase change material that makes up the PCM to store "0" and "1". Specifically, when the phase change material is in an amorphous state, it is in a high-resistance state, defined as the RESET(0) state; when the phase change material is in a crystalline state, it is in a low-resistance state, defined as the SET(1) state.

[0058] Ovonic Threshold Switch (OTS): A novel bidirectional gating device based on chalcogenide compounds. When an electrical pulse of arbitrary direction (either positive or negative) below the corresponding threshold voltage is applied to the OTS, the response current is small, exhibiting a high-resistance non-conducting state. When an electrical pulse of arbitrary direction (either positive or negative) above the corresponding threshold voltage is applied to the OTS, the response current is large, exhibiting a low-resistance conducting state.

[0059] 1S1R memory cell: A memory cell consisting of an OTS and a PCM. In one implementation, when the PCM in the 1S1R memory cell is in the RESET(0) state, the 1S1R memory cell stores "0", and at this time, the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in the SET(1) state, the 1S1R memory cell stores "1", and at this time, the 1S1R memory cell has a lower threshold voltage Vths. Wherein, Vthr is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET(0) state, and Vths is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET(1) state.

[0060] Based on the above characteristics, it can be seen that when the 1S1R memory cell stores "0", the 1S1R device cell has a small response current under a specific read voltage Vread (greater than Vths, less than Vthr); when the 1S1R memory cell stores "1", the 1S1R device cell has a larger response current under the specific read voltage Vread. Therefore, data stored in the 1S1R memory cell can be read by applying the read voltage Vread.

[0061] Erasure operation: This is achieved by applying a high-amplitude, narrow-width electrical pulse to the 1S1R memory cell. The amplitude of this electrical pulse is higher than the threshold voltage of the OTS. Under the action of this electrical pulse, the temperature of the PCM in the 1S1R memory cell is rapidly raised above the melting temperature and then quenched. Since the microscopic atoms do not have enough time to crystallize, they remain in a high-resistivity amorphous state, thus achieving the storage of "0".

[0062] Write operation: This is achieved by applying an electrical pulse with a relatively low amplitude but a relatively long duration to the 1S1R memory cell. The amplitude of this electrical pulse is higher than the threshold voltage of the OTS. Under the action of this electrical pulse, the temperature of the PCM in the 1S1R memory cell is raised to above the crystallization temperature but below the melting temperature. The PCM can be transformed into a low-resistance state through a thermal crystallization process, thus achieving the storage of "1".

[0063] Read operation: By applying a fixed read voltage Vread across the 1S1R memory cell, the data stored in the 1S1R memory cell can be read according to the response current of the 1S1R memory cell.

[0064] Word line: The signal line required to select a 1S1R memory cell in a memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.

[0065] Bit lines: Signal lines used to select a specific column in a memory array. Working together with word lines, they enable the selection of a 1S1R memory cell. By applying appropriate electrical pulses to the word lines and bit lines, write, erase, or read operations can be performed on the selected 1S1R memory cell.

[0066] OTS threshold voltage drift: The characteristic of OTS threshold voltage to change due to the influence of voltage applied to OTS and ambient temperature during the time from the last time it was turned on to the current time it was turned on is called OTS threshold voltage drift.

[0067] Read disturbance: When a memory cell is frequently read, its storage state may change due to factors such as fluctuations in its own current. For example, if a memory cell in a low-resistance state is frequently read, its corresponding threshold voltage may rise due to read disturbance, exceeding the read voltage. In this case, when the memory cell is read again using the read voltage, it may be mistakenly identified as a high-resistance memory cell.

[0068] Figure 1 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application. Figure 1 As shown, the memory chip 100 includes an operation circuit 110 and multiple memory arrays 120. These memory arrays 120 can generally be laid flat on the same plane or stacked in three-dimensional space. Each memory array 120 includes memory cells arranged in rows and columns. When performing read and write operations on the memory cells of the memory chip 100, memory cells with the same address can be selected within each memory array 120 to perform read and write operations on the selected memory cells.

[0069] In the storage array 120, storage cells located in the same row are connected to the same word line (WL), and storage cells located in the same column are connected to the same bit line (BL). Each storage cell can consist of a storage device and a gating device. The storage device can be a resistive storage device, such as a phase-change memory (PCM), ferroelectric memory, magnetic random access memory (MRAM), or resistive random access memory (RRAM). The gating device can be a bidirectional threshold switch. When the storage device is a PCM, the storage cell can be called a 1S1R storage cell, and the storage chip can be called a phase-change memory chip.

[0070] Figure 2 This is a schematic diagram of a memory provided in an embodiment of this application. For example... Figure 2 As shown, the memory 200 includes a memory controller 210 and one or more such as Figure 1 The storage chip 100 is shown. The storage controller 210 is a hardware device used to control the storage chip 100 to perform read and write operations. The storage controller 210 can send operation requests corresponding to read, write, or erase operations to the storage chip 100, so that the operation circuit 110 in the storage chip 100 selects the storage cell through word lines and bit lines, and applies read voltage, write voltage, or erase voltage to the selected storage cell, thereby realizing the execution of the read, write, or erase operation.

[0071] To address read errors in the storage cells, the storage controller 200 also incorporates an error correction algorithm. This algorithm verifies and corrects the read results from the storage chip, thereby avoiding or reducing erroneous data reads. In the memory provided in this embodiment, the storage controller 200 can also execute the control method provided in this embodiment, which improves the stability of data stored in the storage cells of the storage chip.

[0072] Figure 3 This is a schematic diagram of a threshold voltage distribution provided in an embodiment of this application. Figure 3 In the diagram, the horizontal axis (Vt) represents the threshold voltage, and the vertical axis (count) represents the number of memory cells. Figure 3 In the image, the solid curves represent the threshold voltage distribution curves of the memory cell threshold voltage without drift, derived from... Figure 3 It can be seen that the threshold voltage 'a' of a memory cell storing a "1" is less than the threshold voltage 'b' of a memory cell storing a "0". Therefore, by applying a voltage Vread1 greater than threshold voltage 'a' but less than threshold voltage 'b' to the memory cell, it is possible to distinguish whether the memory cell stores a "1" or a "0". Figure 3 In the diagram, the dashed curves represent the threshold voltage distribution curves after the threshold voltage of the memory cell has drifted. Figure 3 It can be seen that after the threshold voltage of the memory cell drifts, the threshold voltage of some memory cells storing "1" may be greater than Vread1. For these memory cells, if a read operation is performed by applying Vread1, these memory cells storing "1" will be misread as "0". This results in a high failure rate of the read data obtained from the read operation.

[0073] In some embodiments, to address the threshold voltage drift problem in memory cells, the memory chip can be configured with multiple read voltage levels. After the memory chip performs a read operation on multiple memory cells at a certain address using a lower read voltage, if the memory controller determines that the read data triggers an uncorrected error (UCE), it can send a reread instruction for the same address to the memory chip, causing the memory chip to re-perform the read operation on the multiple memory cells at that address using a higher read voltage. Figure 3 As shown, if a read operation is performed using Vread1 and triggers UCE, the read operation can be re-executed using Vread2. This synchronously increases the read voltage, which can cope with the drift of the memory cell threshold voltage and thus improve the accuracy of data reading by the memory chip.

[0074] Setting multiple read voltages in a memory chip can mitigate the decrease in read accuracy caused by threshold voltage drift in memory cells. However, each time a higher read voltage is used to perform a read operation on a memory cell at a certain address, read operations need to be performed on all memory cells corresponding to that address. This means that even memory cells that were not read incorrectly require a higher read voltage to be reread. Such frequent and continuous reading of all memory cells increases the probability of read interference, thus affecting the stability of the stored data. Furthermore, increasing the number of read operations also shortens the lifespan of memory cells and increases the power consumption of the memory chip.

[0075] Figure 4 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application, such as... Figure 4 As shown, the control logic circuit in the memory chip provided in this application includes an operation circuit and a shielding circuit. The operation circuit can apply a read voltage to memory cells in multiple memory arrays to perform read operations on the memory cells. The shielding circuit can selectively shield the read voltage applied by the operation circuit to the memory cells, enabling the operation circuit to select only a subset of memory cells to perform read operations during the process of performing read operations on multiple memory cells.

[0076] Figure 5 This is a flowchart of a memory control method provided in an embodiment of this application, which can be implemented using methods provided in the embodiments of this application, such as... Figure 2 The memory shown can be used for execution, and the memory may include a memory controller and other components such as memory controllers. Figure 4 The memory chip shown is shown in the image. Figure 5 The method includes:

[0077] Step 501: The storage controller reads the first data from the storage chip.

[0078] In implementation, the storage controller can send read commands to the operating circuit of the storage chip. These read commands may carry a first address corresponding to the cell to be stored. The operating circuit of the storage chip can then perform read operations on multiple storage cells corresponding to the first address, thereby obtaining the first data stored in those cells. After reading the first data, the operating circuit of the storage chip can send it back to the storage controller.

[0079] Step 502: The storage controller determines whether the failure rate of the first data read is greater than the failure rate threshold.

[0080] Step 503: When the storage controller determines that the failure rate is less than or equal to the failure rate threshold, it corrects the first data to obtain the corrected first data.

[0081] The storage controller is equipped with an error checking and correction (ECC) algorithm. The ECC algorithm can verify the first data, determine the number of storage cells that have read errors among the multiple storage cells, and thus obtain the failure rate corresponding to the first data.

[0082] Since the error correction capability of the ECC algorithm is limited, in implementation, the storage controller can set a failure rate threshold according to the error correction capability of the ECC algorithm. If the failure rate corresponding to the obtained first data is greater than the failure rate threshold, the ECC algorithm can normally correct the error of the first data and determine the first data after error correction as the final read result.

[0083] If the failure rate corresponding to the first data is less than or equal to the failure rate threshold, it means that the amount of data with errors in the first data is large and has exceeded the error correction capability of the ECC algorithm. In this case, it is necessary to further trigger a read retry, that is, to reread multiple memory cells at the same address using a higher read voltage, as detailed in step 504.

[0084] Step 504: When the memory controller determines that the failure rate is greater than the failure rate threshold, it controls the shielding circuit in the memory chip to shield the memory cell corresponding to the second data in the memory chip, and controls the operation circuit of the memory chip to reread the memory cell corresponding to the first data to obtain the third data. Here, the second data is the data in the first data that was not read incorrectly.

[0085] In one example, the second data that failed to read could be the data in the first data indicating that the corresponding memory cell was in a low-resistance state. Figure 3 It can be seen that after the threshold voltage drift occurs, the memory cells that cause read errors are mainly those in a low-resistivity state, whose threshold voltage increases and are therefore misread as being in a high-resistivity state. Conversely, for memory cells that were originally in a high-resistivity state, even after the threshold voltage drift, their corresponding threshold voltage remains higher than the read voltage, and they will still be read as being in a high-resistivity state. In other words, due to the threshold voltage shift, the memory cells that cause read errors are mainly those in a low-resistivity state that are misread as being in a high-resistivity state. Therefore, the memory cells that cause read errors are primarily those in a high-resistivity state indicated by the first data, while those in a low-resistivity state indicated by the first data are those that do not cause read errors. The data in the first data indicating that the memory cell is in a low-resistivity state can be called the second data. For example, the data indicating that the corresponding memory cell is in a low-resistivity state can be "1", and the data indicating that the corresponding memory cell is in a high-resistivity state can be "0".

[0086] In this way, when the memory controller determines that the failure rate of the first data is greater than the failure rate threshold, it can first control the shielding circuit to shield the memory cell corresponding to the second data included in the first data. Then, while the memory cell corresponding to the second data is being shielded, the operating circuit can control the operating circuit to reread multiple memory cells at the first address using a higher read voltage. This avoids rereading the memory cell corresponding to the second data. After the operating circuit of the memory chip rereads and obtains the third data, it can send the third data to the memory controller.

[0087] Step 505: The storage controller obtains the reread data based on the second data and the third data.

[0088] The third data obtained from the reread can include data obtained after rereading the unmasked memory cells corresponding to the first address. The data corresponding to the masked memory cells corresponding to the first address is the data that was read without errors, which is the second data. In one example, the storage controller can merge the second data and the data obtained from rereading the unmasked memory cells in the third data to obtain the reread data after rereading multiple memory cells corresponding to the first address.

[0089] In this embodiment, to reduce the number of read operations on memory cells by the memory chip, when rereading multiple memory cells at the same address, the shielding circuit in the memory chip can shield the memory cell corresponding to the second data that was not read incorrectly. This prevents the operating circuit from rereading the memory cell that was not read incorrectly during the rereading process of these multiple memory cells. This reduces the number of read operations on some memory cells in the memory chip, thereby reducing the probability of read interference in the memory cells, improving the lifespan of the memory cells, and reducing the power consumption of the memory chip.

[0090] The following is combined Figures 6 to 15 The memory control method provided in the embodiments of this application will be described in detail below:

[0091] Figure 6 This is a flowchart of a memory control method provided in an embodiment of this application, wherein the memory may include a memory controller and, for example, a memory controller. Figure 4 The memory chip shown is shown in the image. Figure 6 The method includes:

[0092] Step 601: The storage controller sends a read instruction corresponding to the first address to the operation circuit of the storage chip.

[0093] The memory chip can be connected to a memory controller, which can be connected to the host processor. When the host processor needs to read data stored in the memory chip, it can send a read command to the memory chip through the memory controller. This read command can carry the first address corresponding to the data to be read.

[0094] Step 602: The operation circuit of the memory chip performs a read operation on multiple memory cells corresponding to the first address according to the read instruction to obtain the first data.

[0095] Figure 7 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application, such as... Figure 7 As shown, the operating circuit may further include control logic circuitry and drive circuitry. Figure 7 (Not directly shown in the text) Address decoding circuit (row decoder, column decoder), sensing circuit and input / output gating circuit, etc.

[0096] In one example, the memory controller can send read commands to the control logic circuit via a bus. Upon receiving the read command, the control logic circuit can send the first address carried in the read command to the address decoding circuit and send a drive command corresponding to the first read voltage to the drive circuit. The first read voltage can be the lowest read voltage among multiple read voltage settings of the memory chip. After receiving the first address, the address decoding circuit can decode the first address and select the memory cell corresponding to the first address in each memory array. The drive circuit can apply the first read voltage to the selected memory cells. During the application of the first read voltage to each memory cell, the sensing circuit can determine the data stored in each memory cell by determining the current magnitude corresponding to each memory cell, thus obtaining the first data. For example, after applying the first read voltage to a memory cell, if the current flowing through the memory cell is small, it can be determined that the memory cell is in a high-resistance state, i.e., storing "0"; if the current flowing through the memory cell is large, it can be determined that the memory cell is in a low-resistance state, i.e., storing "1".

[0097] Step 603: The operating circuit of the memory chip transmits the first data it has read to the memory controller.

[0098] The memory chip includes latches for caching data read from memory cells in each memory array. The first data determined by the sensing circuit can be stored in multiple latches corresponding to multiple memory cells at a first address. Then, the input / output gating circuit included in the operation circuit can send the first data stored in the multiple latches to the memory controller.

[0099] Step 604: The storage controller determines whether the failure rate corresponding to the first data is greater than the failure rate threshold.

[0100] Step 605: When the storage controller determines that the failure rate is less than or equal to the failure rate threshold, it corrects the first data to obtain the corrected first data.

[0101] The processing of steps 604 to 605 is the same as that of steps 502 to 503 above, and will not be repeated here.

[0102] Step 606: When the storage controller determines that the failure rate is greater than the failure rate threshold, it determines whether the first data is still cached in the storage chip after the first data is read.

[0103] After determining that the failure rate is greater than the failure rate threshold, the memory controller needs to reread multiple memory cells at the first address using a higher read voltage. Furthermore, a shielding circuit needs to shield memory cells that were not read correctly based on the second data within the first data. Therefore, the memory controller can first determine whether the first data is still cached in the memory chip's latch. If the first data is still cached in the memory chip's latch, the memory controller can instruct the shielding circuit to shield the memory cells based on the first data cached in the latch. If the first data is not cached in the memory chip's latch, the memory controller can send data (such as the first data, or inverted data) to the shielding circuit to instruct it to shield the memory cells, thus enabling the shielding circuit to shield the memory cells.

[0104] Methods for a storage controller to determine whether the first data is still cached in the storage chip may include:

[0105] The storage controller can record each received read instruction and determine whether any other read instructions have been received after step 601. If no other read instructions have been received, it means that the storage controller has not performed a read operation on the storage chip after step 601, and the first data is still cached in the storage chip's latch, thus confirming that the first data is still cached in the storage chip. If other read instructions have been received, it means that the storage controller may have controlled the storage chip to perform a read operation again after step 601, thus updating the first data cached in the storage chip's latch, and confirming that the first data is no longer cached in the storage chip.

[0106] Furthermore, if the memory controller determines that it has received other read instructions, it can compare whether the address requested for reading in the other read instructions is the same as the first address. If they are different, it means that the first data cached in the memory chip's latch has been updated by data at other addresses, thus confirming that the first data is not cached in the memory chip. If they are the same, it means that the memory chip has performed a read operation on the memory cell at the first address again. However, in this case, the memory chip's latch will still cache the first data, thus confirming that the first data is still cached in the memory chip.

[0107] Furthermore, in a memory chip, multiple memory arrays are divided into different banks, and each bank can use its own set of latches to store read data corresponding to multiple memory arrays within that bank. Therefore, the memory controller can also compare the bank addresses in other read instructions with the bank addresses included in the first address to determine whether the first data is still cached in the memory chip. For example, if the bank address in another read instruction is different from the bank address in the first address, it indicates that the memory chip is performing a read operation on memory cells in other banks. In this case, the data corresponding to the memory cells in other banks will not refresh the latches storing the first data, meaning the first data is still cached in the memory chip. If the bank address in another read instruction is the same as the bank address in the first address, it indicates that the memory chip is performing a read operation on other memory cells in the same bank as the memory cell at the first address. In this case, the read data will refresh the latches storing the first data, meaning the first data is not cached in the memory chip.

[0108] Step 607: When the storage controller determines that the first data is still cached in the storage chip, it sends a reread mask command to the operation circuit of the storage chip.

[0109] Step 608: The operation circuit of the memory chip responds to the reread masking command by sending a masking command to the masking circuit so that the masking circuit masks the memory cell corresponding to the second data, and rereads the memory cell corresponding to the first data while the memory cell corresponding to the second data is masked.

[0110] Figure 8 This is a schematic diagram of a re-read masking instruction provided in an embodiment of this application. The re-read masking instruction can also be called a data mask read retry instruction, such as... Figure 8 As shown, the data mask read retry instruction includes the ADDR field and the UOP field. The ADDR field includes the same first address as the read operation that triggers UCE, and the UOP field includes voltage information (such as amplitude, pulse width, etc.) corresponding to the higher-level read voltage.

[0111] In one example, the UOP field of the data mask read retry instruction may also include an identifier indicating that the operation circuit enables the masking circuit. Therefore, upon receiving the data mask read retry instruction, the control logic circuit of the operation circuit can, on the one hand, control the drive circuit, address decoding circuit, etc., to reread the memory cell at the first address; on the other hand, it can send a masking instruction to the masking circuit to mask the memory cell corresponding to the second data. The masking instruction sent by the operation circuit to the masking circuit can be an enable signal that enables the masking circuit.

[0112] In steps 607 to 610, to ensure that the storage unit corresponding to the first data is reread while the storage unit corresponding to the second data is masked, the control logic circuit in the operation circuit can be configured to first send a masking command to the masking circuit, and then control other circuits to reread the storage unit at the first address. The corresponding time interval can be preset by a technician and is not limited in this embodiment. Alternatively, to ensure that the storage unit corresponding to the first data is reread while the storage unit corresponding to the second data is masked, the storage controller can split the reread masking command into a masking command and a reread command, and send them to the operation circuit sequentially. The time interval between sending the masking command and the reread command can also be preset by a technician and is not limited in this embodiment.

[0113] Step 609: The shielding circuit of the memory chip responds to the shielding command and shields the memory cell corresponding to the second data.

[0114] After receiving a shielding command, the shielding circuit can apply a shielding signal to the enable terminal corresponding to the storage cell storing the second data according to the indication of the second data in the first data stored in the latch in the storage chip, so as to shield the storage cell that has not been read and has an error.

[0115] The enable terminal corresponding to the storage unit can be the enable terminal of the address decoding circuit, sensing circuit, or input / output gating circuit of the operation circuit used to enable the storage unit.

[0116] In one example, the shielding signal can be a low-level signal. When a high level is applied to the enable terminal of the corresponding memory cell in the address decoding circuit, the bit line connected to the memory cell can be turned on, and the driving circuit can then apply a read voltage to the memory cell through the word line. If the enable terminal of the corresponding memory cell in the address decoding circuit is additionally applied a low level by the shielding circuit, then when a high level is applied to the enable terminal again, the current corresponding to the applied high level will be introduced into the shielding circuit that applied the low level, thereby pulling the high level low. In this case, the bit line connected to the memory cell cannot be turned on. Even if the driving circuit applies a read voltage to the word line connected to the memory cell, the read voltage cannot be successfully applied to the corresponding memory cell because the bit line connected to the memory cell cannot be turned on. Only when the enable terminal of the corresponding memory cell in the sensing circuit or input / output gate circuit is applied a high level can the memory cell form a loop with the sensing circuit or input / output gate circuit, and the memory cell can be turned on after a read voltage is applied to the memory cell. If the enable terminal of the corresponding memory cell in the sensing circuit or input / output gating circuit is additionally applied a low level by a shielded circuit, then when a high level is applied to that enable terminal, the current corresponding to the applied high level will be introduced into the shielded circuit that applied the low level, thereby pulling the high level low. In this case, the memory cell cannot be in a normal loop, and the read voltage cannot turn on the memory cell, meaning a read operation cannot be performed on the memory cell.

[0117] In one example, the inverting circuit can be an inverter. For example... Figure 7 As shown, the memory chip includes multiple memory arrays. The operating circuitry within the memory chip may include control logic circuitry, a read drive circuit corresponding to each memory array, input data circuitry, address decoding circuitry (row decoder, column decoder), and sensing circuitry. The memory chip also includes latches for storing read data and shielding circuitry, wherein the shielding circuitry includes an inverter corresponding to each memory array.

[0118] In this system, multiple latches correspond one-to-one with multiple memory cells being read, and each latch can store the read data corresponding to one memory cell. A latch outputs a low level when storing a "0" and a high level when storing a "1". The shielding circuit includes multiple inverters, each connected to one latch and one enable terminal. The latches and enable terminals connected to the same inverter correspond to the same memory cell. Thus, an inverter can convert the high level output of the corresponding latch to a low level and apply the low level to the corresponding enable terminal.

[0119] Figure 9 This is a schematic diagram illustrating a method for applying a shielding signal according to an embodiment of this application. Figure 9As shown, after performing read operations on multiple memory cells corresponding to the first address, the obtained first data can be stored in multiple latches. The latch storing "0" outputs a low level (...). Figure 9 (represented by "L" in Chinese), the latch storing "1" outputs a high level. Figure 9 (Represented by "H" in Chinese). The output of each latch can be connected to the input of an inverter in the shielding circuit, allowing the inverter to invert the bits of the first data stored in the latch. Thus, the inverter connected to a memory cell indicated by the second data in the first data being in a low-impedance state will output a low level, and this low level will be applied to the enable terminal corresponding to the same memory cell, thereby enabling the shielding circuit to apply a read voltage to that memory cell. Conversely, the inverter connected to memory cells indicated by other data in the first data being in a high-impedance state will output a high level, which will also be applied to the enable terminal corresponding to the memory cell. However, since the high level does not shield the high level at the enable terminal, it does not affect the application of a read voltage to the high-impedance memory cell during a reread.

[0120] Figure 10 This is a connection diagram of an inverter provided in an embodiment of this application. Figure 10 The diagram shows only the connection between an inverter in the shielded circuit and a memory array. (See attached diagram.) Figure 10 As shown, the input of the inverter can be connected to the output of the latch, and the output of the inverter can be connected to the enable terminal of the column decoder, the enable terminal of the sensing circuit, or the enable terminal of the input / output gating circuit in the corresponding operation circuit of the memory array. In one example, applying a low level to the enable terminal of the column decoder through the inverter prevents the column decoder from applying a read voltage to the memory cell through the bit line corresponding to the memory cell. Alternatively, applying a low level to the sensing circuit through the inverter prevents the sensing circuit from applying a read voltage to the word line connected to the memory cell. Or, applying a low level to the enable terminal of the input / output gating circuit through the inverter prevents the memory cell in the memory array from forming a loop with the input / output gating circuit through the bit line. Thus, even if a read voltage is applied to the memory cell through the bit line, the read voltage cannot turn on the memory cell, thereby preventing the memory cell from performing a read operation again.

[0121] Figure 11 This is a waveform diagram of executing a data mask read retry instruction according to an embodiment of this application. Figure 11In this context, CA represents the bus signal, DM_n represents the mask signal, DQ represents the data signal, and DQS is the clock signal corresponding to the data signal. Since the bit-by-bit inversion of the first data is performed internally by the memory chip, after receiving the data mask read retry instruction on the CA bus, the memory chip only needs to wait for the mask circuit to perform bit-by-bit inversion and apply the mask signal (for a duration of T) to the enable terminal in the operation circuit. RL-mask After that, you can perform a read operation to get the updated data.

[0122] Step 610: The operation circuit of the memory chip sends the third data obtained from the reread to the memory controller.

[0123] Since the latches of the memory chip also store the first data, the latches corresponding to the masked memory cells also cache the data before it was reread, which is the second data. For the latches corresponding to the unmasked memory cells, the data in these latches will be refreshed by the reread data. The resulting third data can include the second data that was not reread and has no errors, as well as the data after it was reread. Therefore, the operating circuit can send the third data from multiple latches to the memory controller, so that the memory controller can obtain the data after rereading the memory cell corresponding to the first data.

[0124] Step 611: If the storage controller determines that the first data is not in the storage chip cache, it inverts the first data, sends the inverted data to the shielding circuit, and sends a reread instruction to the operation circuit.

[0125] If the memory controller determines that the first data is not cached in the memory chip, it means that the latch in the memory chip does not cache the first data, and therefore the memory chip cannot perform a bit-by-bit inversion of the first data. Therefore, the memory controller can perform a bit-by-bit inversion of the first data and then send the inverted data to the shielding circuit, so that the shielding circuit can shield the memory cell based on the inverted data. Alternatively, a reread command can be sent to the operation circuit to instruct that the memory cell corresponding to the first data be reread while the memory cell corresponding to the second data is being shielded.

[0126] In steps 611 to 613, to ensure that the storage unit corresponding to the first data is reread while the storage unit corresponding to the second data is being shielded, the storage controller can first send inverted data to the shielding circuit, and then send a reread command to the operation circuit. The time interval can be preset by a technician, and is not limited in this embodiment.

[0127] Step 612: The shielding circuit of the memory chip shields the memory cell corresponding to the second data according to the inverted data.

[0128] The shielding circuit of the memory chip may include a register, which is used to store the inverted data after being inverted, and can shield the memory cell corresponding to the second data according to the output of the inverted data corresponding to the register.

[0129] Figure 12 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application. Figure 12 As shown, the memory chip includes multiple memory arrays, and the operating circuitry within the memory chip may further include control logic circuitry and drive circuitry. Figure 12 (Not directly shown), address decoding circuits (row decoder, column decoder), sensing circuits, and input / output gating circuits, etc. The memory chip also includes latches for storing read data and shielding circuits. The shielding circuits include registers for storing inverted data.

[0130] The register includes multiple first output terminals, each corresponding one-to-one with a data bit of the inverted data and one-to-one with the enable terminals of multiple memory cells at the first address. Each first output terminal is connected to the enable terminal corresponding to the memory cell. A first output terminal with a corresponding data bit of "0" in the register outputs a low level to the corresponding enable terminal. In one example, the data with a corresponding data bit of "0" in the register is the data obtained by inverting the second data in the first data by the memory controller. Thus, by storing the inverted data through the latch of the shielding circuit, the memory cell corresponding to the second data can be shielded. Furthermore, for a first output terminal with a corresponding data bit of "1" in the register, this first output terminal outputs a high level to the enable terminal corresponding to the memory cell in a high-impedance state indicated by the first data. However, since the high level does not shield the high level of the enable terminal, it does not affect the application of the read voltage to the high-impedance memory cell during rereading.

[0131] like Figure 12 As shown, the memory chip has a data mask (DM) port. The inputs of the register can be connected to the DM port. The memory controller can store inverted data into the register via the DM port. In another example, the memory controller can store inverted data into the register via the input logic circuitry included in the memory chip. Alternatively, the inputs of the register can be connected to a multiplexer (MUX), and the outputs of the DM port and the input logic circuitry can be connected to the MUX, allowing selection of the port from which inverted data is input into the register via the MUX.

[0132] Figure 13 This is a schematic diagram of a register connection provided in an embodiment of this application. Figure 13 The diagram only shows the connection between the first output terminal of the register in the shielded circuit and a memory array. (See diagram for example.) Figure 13 As shown, the first input of the register can be connected to the output of the latch. The first input of the register can also be connected to the enable terminal of the column decoder, the enable terminal of the sensing circuit, or the enable terminal of the input / output gating circuit in the corresponding operation circuit of the memory array. In one example, applying a low level to the enable terminal of the column decoder through the first input of the register prevents the column decoder from applying a read voltage to the memory cell through the bit line corresponding to the memory cell. Alternatively, applying a low level to the sensing circuit through the first input of the register prevents the sensing circuit from applying a read voltage to the word line connecting the memory cell. Or, applying a low level to the enable terminal of the input / output gating circuit through the first input of the register prevents the memory cell in the memory array from forming a loop with the input / output gating circuit through the bit line. Thus, even if a read voltage is applied to the memory cell through the bit line, the read voltage cannot turn on the memory cell, thereby preventing the memory cell from performing a read operation.

[0133] Figure 14 This is a waveform diagram of executing a read retry instruction provided in an embodiment of this application. Figure 14 In this context, CA represents the bus signal, DM_n represents the mask signal, DQ represents the data signal, and DQS is the clock signal corresponding to the data signal. Since the bit-inverting process of the first data is performed by the memory controller externally connected to the memory chip, after the memory controller triggers a read retry instruction on the CA bus, it first needs to invert the first data bit-by-bit, and then send the bit-inverted data to the memory chip (for a duration of T). WL-mask Then, the shielding circuit in the memory chip applies a shielding signal to the enable terminal (duration T). RL-mask Then you can perform a read operation to get the updated data.

[0134] Step 613: The operation circuit of the memory chip responds to the reread instruction and rereads the memory cell corresponding to the first data while the memory cell corresponding to the second data is masked.

[0135] Upon receiving a reread instruction, the operating circuitry of the memory chip can reread the memory cell corresponding to the first data while the memory cell corresponding to the second data is masked. Because the memory cell corresponding to the second data is masked, this reread will only reread the memory cells that are not masked, i.e., the memory cells that may have been read incorrectly.

[0136] Step 614: The operating circuit of the memory chip sends the third data obtained from the rereading to the memory controller.

[0137] Step 615: The storage controller replaces all data in the third data except for the fourth data with the second data to obtain reread data. The fourth data is the data obtained after rereading the unmasked storage cells included in the third data.

[0138] In steps 611 to 615, the first data stored in the multiple latches of the memory chip has been updated by other data. Therefore, after rereading the unmasked memory cell, the latch corresponding to the unmasked memory cell can be updated with the reread data, while the latch corresponding to the masked memory cell still caches other data. Thus, the obtained third data includes both the data reread from the unmasked memory cell and other data.

[0139] Since the other data included in the third data has the same data bits as the second data included in the first data, and the second data is all 0, the other data in the third data can be replaced with the second data by performing logical operations on the first data (or the reverse data) and the third data, thereby obtaining the reread data after rereading multiple memory cells corresponding to the first address.

[0140] The above Figure 7 A schematic diagram of an inverter in a shielded circuit performing internal inversion and shielding is shown above. Figure 12 This diagram illustrates a shielding circuit that performs shielding based on externally inverted data stored in a register. In practice, the shielding circuit may include... Figure 8 inverter and Figure 12 The register shown is shown. When the shielding circuit receives a shielding command from the operating circuit, it can internally invert the inverter to shield the memory cell. When the shielding circuit receives inverted data from the memory controller, it can internally invert the inverter to shield the memory cell. Figure 15 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application. Figure 15 As shown, the memory chip includes multiple memory arrays, and the operating circuitry within the memory chip may include control logic circuitry and drive circuitry. Figure 15 (Not directly shown), address decoding circuitry (row decoder, column decoder), sensing circuitry, and input / output gating circuitry, etc. The memory chip also includes latches and shielding circuitry. The shielding circuitry includes an inverter and a register for storing inverted data. The relationships between the register and inverter and the memory cell, the inverted data, and the enable terminal of the memory cell, respectively, are as described above. Figure 10 and Figure 13The same applies here, and will not be repeated. In one example, the outputs of the register and inverter are connected to their corresponding enable terminals via a multiplexer (MUX). In implementation, the MUX can be controlled by control logic circuitry to select different ways to shield the memory cells from the shielding circuitry.

[0141] In the memory and corresponding operation method provided in this application embodiment, when the operation circuit performs a read retry on the first memory cell corresponding to the first address, the shielding circuit can apply a shielding signal to the enable terminal corresponding to the first memory cell that did not have a read error. In this way, when the operation circuit applies a read voltage to multiple memory cells again, the read voltage will only be applied to the memory cells that may have read errors. This reduces the number of times some memory cells are read, thereby reducing the probability of read interference in the memory cells, improving the lifespan of the memory cells, and reducing the power consumption of the memory chip.

[0142] Based on the same inventive concept, this application also provides a memory chip, which can be the aforementioned... Figure 4 The memory chip shown includes an operation circuit, a shielding circuit, and multiple memory arrays. The operation circuit and shielding circuit within the memory chip, under the instruction of an external memory controller, can implement the memory control method described in the above embodiment. This reduces the number of read operations performed by some memory cells, lowers the probability of read interference in memory cells, increases the lifespan of memory cells, and reduces the power consumption of the memory chip.

[0143] Based on the same inventive concept, this application also provides an electronic device. Figure 16 This is a schematic diagram of the structure of an electronic device also provided in the embodiments of this application, such as... Figure 16 As shown, the electronic device includes a processor and, as Figure 2 The memory shown is used by a processor to send read instructions to the memory to perform read operations. During the read operation, if a UCE (Uninterrupted Read Entry) is triggered, the memory chip can perform read operations only on memory cells that may malfunction during the read retry process. This reduces the number of read operations performed on some memory cells, lowers the probability of read interference, increases the lifespan of memory cells, and reduces the power consumption of the memory chip.

[0144] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. In this application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0145] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory includes a memory controller and a memory chip; The storage controller is used for: Determine whether the failure rate of the first data read from the memory chip is greater than the failure rate threshold. When the failure rate is greater than the failure rate threshold, control the shielding circuit in the memory chip to shield the memory cell corresponding to the second data in the memory chip. The second data is the data in the first data that was not read incorrectly. The operating circuit of the memory chip controls the memory cell corresponding to the first data to reread the memory cell to obtain the third data, wherein the third data includes the data obtained after rereading the unmasked memory cell; The reread data is obtained based on the second data and the third data.

2. The memory according to claim 1, characterized in that, The second data is the data in the first data that indicates the corresponding memory cell is in a low-resistance state; The storage controller is further configured to determine whether the first data is still cached in the storage chip after the first data is read; and if it is determined that the first data is still cached in the storage chip, send a reread mask instruction to the operation circuit of the storage chip. The operating circuit of the memory chip is used to control the shielding circuit to shield the memory cell corresponding to the second data in response to the reread shielding command, and to reread the memory cell corresponding to the first data while the memory cell corresponding to the second data is shielded.

3. The memory according to claim 2, characterized in that, The shielding circuit includes multiple inverting circuits. The input terminals of the multiple inverting circuits are respectively connected to multiple first latches in the memory chip, and the output terminals of the inverting circuits are respectively connected to the enable terminals of multiple memory cells corresponding to the first data. The multiple first latches are used to cache the first data. The operating circuit of the memory chip is used to enable the plurality of inverting circuits so that the inverting circuit connected to the second latch outputs a shielding signal to the connected enable terminal, wherein the second latch is the latch among the plurality of first latches that caches the second data.

4. The memory according to claim 2, characterized in that, The storage controller is further configured to: invert the first data when it is determined that the first data is not in the storage chip cache, send the inverted data to the shielding circuit, and send a reread instruction to the operation circuit; The shielding circuit of the memory chip is used to shield the memory cell corresponding to the second data according to the inverted data; The operating circuit of the memory chip is used to, in response to the reread instruction, reread the memory cell corresponding to the first data while the memory cell corresponding to the second data is masked.

5. The memory according to claim 4, characterized in that, The shielding circuit includes a register, and the multiple output terminals of the register are respectively connected to the enable terminals of multiple storage units corresponding to the first data. The register of the shielding circuit is used to store the inverted data sent by the memory chip, so that the output terminal corresponding to the fourth data in the register outputs a shielding signal to the connected enable terminal. The fourth data is the data obtained by inverting the second data, which is included in the inverted data.

6. The memory according to claim 4 or 5, characterized in that, The storage controller is used to store the inverted data into the register via the Data Mask port of the storage chip or the input logic circuit included in the operation circuit.

7. The memory according to claim 3 or 5, characterized in that, The operating circuit includes an address decoding circuit, a sensing circuit, and an input / output gating circuit. The enable terminal of the storage unit includes the enable terminal corresponding to the storage unit in the address decoding circuit, the enable terminal corresponding to the storage unit in the sensing circuit, or the enable terminal corresponding to the storage unit in the input / output gating circuit.

8. The memory according to any one of claims 4 to 6, characterized in that, The storage controller is used for: The reread data is obtained by replacing all data in the third data except the fourth data with the second data, wherein the fourth data is the data obtained by rereading the unmasked storage unit included in the third data.

9. A method for controlling a memory, characterized in that, The memory includes a memory controller and a memory chip, and the method includes: The storage controller determines whether the failure rate of the first data read from the storage chip is greater than the failure rate threshold. When the failure rate is greater than the failure rate threshold, it controls the shielding circuit in the storage chip to shield the storage cell corresponding to the second data in the storage chip. The second data is the data in the first data that was not read incorrectly. The storage controller controls the storage chip to reread the storage cell corresponding to the first data to obtain the third data, wherein the third data is the data obtained after rereading the unmasked storage cell; The reread data is obtained based on the second data and the third data.

10. The method according to claim 9, characterized in that, The second data is the data in the first data that indicates the corresponding memory cell is in a low-resistance state, and the method further includes: The storage controller determines whether the first data is still cached in the storage chip after it has been read. The storage controller controls the storage chip to reread the storage cell corresponding to the first data, including: If the storage controller determines that the first data is still in the storage chip cache, it sends a reread mask instruction to the operation circuit of the storage chip. The operating circuit of the memory chip responds to the reread masking command, controls the masking circuit to mask the memory cell corresponding to the second data, and rereads the memory cell corresponding to the first data while the memory cell corresponding to the second data is masked.

11. The method according to claim 10, characterized in that, The shielding circuit includes multiple inverting circuits. The input terminals of the multiple inverting circuits are respectively connected to multiple first latches in the memory chip, and the output terminals of the inverting circuits are respectively connected to the enable terminals of multiple memory cells corresponding to the first data. The multiple first latches are used to cache the first data. The control of the shielding circuit to shield the storage unit corresponding to the second data includes: The operation circuit of the memory chip enables the plurality of inverting circuits so that the inverting circuit connected to the second latch outputs a shielding signal to the connected enable terminal. The second latch is the latch among the plurality of first latches that caches the second data.

12. The method according to claim 10, characterized in that, The control of the shielding circuit in the memory chip to shield the memory cell corresponding to the second data in the memory chip includes: If the storage controller determines that the first data is not in the storage chip cache, it inverts the first data, sends the inverted data to the shielding circuit, and sends a reread instruction to the operation circuit. The shielding circuit of the memory chip shields the memory cell corresponding to the second data according to the inverted data; The operating circuit of the memory chip responds to the reread instruction and rereads the memory cell corresponding to the first data while the memory cell corresponding to the second data is masked.

13. The method according to claim 12, characterized in that, The shielding circuit includes a register, and the multiple output terminals of the register are respectively connected to the enable terminals of multiple storage units corresponding to the first data. The shielding circuit of the memory chip shields the memory cell corresponding to the second data according to the inverted data, including: The register of the shielding circuit stores the inverted data sent by the memory chip, so that the output terminal corresponding to the fourth data outputs a shielding signal to the connected enable terminal. The fourth data is the data obtained by inverting the second data, which is included in the inverted data.

14. The method according to claim 12 or 13, characterized in that, Sending the inverted data to the shielding circuit includes: The storage controller stores the inverted data into the register via the Data Mask port of the storage chip or the input logic circuit included in the operation circuit.

15. The method according to claim 11 or 13, characterized in that, The operating circuit includes an address decoding circuit, a sensing circuit, or an input / output gating circuit. The enable terminal of the storage unit is the enable terminal connected to the storage unit in the address decoding circuit, the enable terminal connected to the storage unit in the sensing circuit, or the enable terminal connected to the storage unit in the input / output gating circuit.

16. The method according to any one of claims 12 to 14, characterized in that, The process of obtaining reread data based on the second data and the third data includes: The reread data is obtained by replacing all data in the third data except the fourth data with the second data, wherein the fourth data is the data obtained by rereading the unmasked storage unit included in the third data.

17. A memory chip, characterized in that, The memory chip is connected to the memory controller, and the memory chip includes an operating circuit and a shielding circuit. The operating circuit is used to read first data and send the first data to the storage controller; The shielding circuit is used to shield the storage cell corresponding to the second data in the storage chip when the storage controller determines that the failure rate of the first data is greater than the failure rate threshold, wherein the second data is the data in the first data that was not read incorrectly; The operating circuit is used to reread the storage unit corresponding to the first data to obtain the third data, wherein the third data is the data obtained after rereading the unmasked storage unit; The operating circuit is used to send the third data to the storage controller so that the storage controller obtains the reread data determined by the second data and the third data.

18. The memory chip according to claim 17, characterized in that, The second data is the data in the first data that indicates the corresponding memory cell is in a low-resistance state; The operating circuit of the memory chip is used to receive a reread masking instruction, control the masking circuit to mask the memory cell corresponding to the second data, and reread the memory cell corresponding to the first data during the process of the second data being masked. The reread masking instruction is sent when the memory controller determines that the failure rate of the first data is greater than the failure rate threshold and determines that the first data is still in the memory chip cache after it has been read.

19. The memory chip according to claim 18, characterized in that, The shielding circuit includes multiple inverting circuits. The input terminals of the multiple inverting circuits are respectively connected to multiple first latches in the memory chip, and the output terminals of the inverting circuits are respectively connected to the enable terminals of multiple memory cells corresponding to the first data. The multiple first latches are used to cache the first data. The operating circuit of the memory chip is used to enable the plurality of inverting circuits so that the inverting circuit connected to the second latch outputs a shielding signal to the connected enable terminal, wherein the second latch is a latch that caches the second data among the plurality of first latches.

20. The memory chip according to claim 18, characterized in that, The shielding circuit of the memory chip is used to receive the inverted data of the first data, and to shield the memory cell corresponding to the second data according to the inverted data. The inverted data is sent when the memory controller determines that the failure rate of the first data is greater than the failure rate threshold and that the first data is not cached by the memory chip after it is read. The operating circuit of the memory chip is used to receive a reread instruction and reread the memory cell corresponding to the first data while the memory cell corresponding to the second data is blocked. The reread instruction is sent when the memory controller determines that the failure rate of the first data is greater than the failure rate threshold and that the first data is not cached by the memory chip after it is read.

21. The memory chip according to claim 20, characterized in that, The shielding circuit includes a register, and the multiple output terminals of the register are respectively connected to the enable terminals of multiple storage units corresponding to the first data. The register of the shielding circuit is used to store the inverted data sent by the memory chip, so that the output terminal corresponding to the fourth data outputs a shielding signal to the connected enable terminal. The fourth data is the data obtained by inverting the second data included in the inverted data.

22. The memory chip according to claim 20 or 21, characterized in that, The register of the shielding circuit receives the inverted data sent by the storage controller through the Data Mask port of the storage chip or the input logic circuit included in the operation circuit.

23. The memory chip according to claim 19 or 21, characterized in that, The operating circuit includes an address decoding circuit, a sensing circuit, and an input / output gating circuit. The enable terminal of the storage unit includes the enable terminal corresponding to the storage unit in the address decoding circuit, the enable terminal corresponding to the storage unit in the sensing circuit, or the enable terminal corresponding to the storage unit in the input / output gating circuit.

24. The memory chip according to any one of claims 20 to 22, characterized in that, The operating circuit of the memory chip is used to send the third data to the memory controller, so that the memory controller replaces the other data in the third data except for the fourth data with the second data to obtain the reread data, wherein the fourth data is the data obtained after rereading the unmasked memory cell included in the third data.

25. An electronic device, characterized in that, The electronic device includes a processor and a memory as described in any one of claims 1 to 8; The processor is used to send read and write instructions to the memory so that the memory can perform read and write operations.

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