Sense amplifier circuit, memory device including same, and sensing method of memory device

Abstract

A sense amplifier circuit, a memory device including the sense amplifier circuit, and a sensing method of the memory device. The sense amplifier circuit may include: a first bit line; a bit line transistor electrically connected between the first bit line and the first node; a first control transistor electrically connected between the first node and the second node; a first inverter including an input terminal electrically connected to the second node; a second inverter electrically connected to the output node; and a pre-charge circuit electrically connected to the second node and configured to transfer a first voltage to the second node during a first time period and to transfer a second voltage greater than the first voltage to the second node during a second time period.

Description

Technical Field

[0001] This disclosure relates to a sense amplifier circuit, a memory device including the sense amplifier circuit, and a sensing method for the memory device. Background Technology

[0002] During read or refresh operations of a memory device, a sense amplifier senses data in a memory cell by detecting the voltage difference between the bit line and its complementary bit line. As memory devices become more integrated, cell sizes shrink and bit line loads increase, making it potentially difficult to maintain a sufficient voltage difference margin. Without maintaining this margin, data sensing of the memory cell may fail. Summary of the Invention

[0003] An example embodiment provides a sense amplifier circuit for amplifying a small voltage difference between a bit line and a complementary bit line, a memory device including the sense amplifier circuit, and a sensing method for the memory device.

[0004] An example embodiment provides a low-power sense amplifier circuit, a memory device including the sense amplifier circuit, and a sensing method for the memory device.

[0005] According to some embodiments of this disclosure, a sense amplifier circuit may include: a first bit line; a bit line transistor electrically connected between the first bit line and a first node; a first control transistor electrically connected between the first node and a second node; a first inverter including an input terminal electrically connected to the second node; a second inverter electrically connected to an output node; and a precharge circuit electrically connected to the second node and configured to transfer a first voltage to the second node during a first time period and to transfer a second voltage greater than the first voltage to the second node during a second time period.

[0006] According to some embodiments of this disclosure, a sense amplifier circuit may include: a memory cell; a bit line electrically connected to the memory cell; a first node; a second node; a bit line transistor electrically connected between the bit line and the first node; a first control transistor electrically connected between the first node and the second node; a first inverter including an input terminal electrically connected to the second node; a second inverter including an output terminal electrically connected to an output node; and a first precharge transistor electrically connected between the second node and the output node, wherein the sense amplifier circuit is configured to: during a first time period, when the first control transistor is turned on, transfer a first voltage to the bit line, the first node, and the second node, and after the first time period, transfer a second voltage to the bit line, the first node, and the second node. During the time period, when the first precharge transistor is turned off, a second voltage greater than the first voltage is transferred to the second node. During the third time period after the second time period, a charge sharing operation is performed between the capacitive component of the bit line and the memory cell, wherein the bit line transistor is configured to be turned off during the third time period. During the fourth time period after the third time period, charge is transferred from the bit line to the second node, wherein the bit line transistor is configured to be turned on during the fourth time period. During the fifth time period after the fourth time period, a first voltage line and a second voltage line electrically connected to each of the first inverter and the second inverter are configured to be turned on. During the sixth time period after the fifth time period, the first control transistor is configured to be turned on, and the first precharge transistor is configured to be turned on.

[0007] According to some embodiments of this disclosure, a sensing method for a memory device may include: pre-charging a bit line and a first node electrically connected to the bit line with a first voltage; storing offset information of a transistor electrically connected between the first node and a second node; pre-charging the second node with a second voltage greater than the first voltage and sharing the charge between the memory cell and the bit line; transferring the charge from the bit line to the second node; and sensing data of the memory cell based on the voltage at the second node. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a memory device according to some embodiments.

[0009] Figure 2 This is a diagram illustrating a memory cell array and a sense amplifier in a memory device according to some embodiments.

[0010] Figure 3 This is a circuit diagram illustrating the connection of a memory cell and a readout amplifier circuit in a memory device according to some embodiments.

[0011] Figure 4 This illustrates some embodiments. Figure 1 A three-dimensional view of the memory device.

[0012] Figure 5 This illustrates some embodiments. Figure 1 The circuit diagram of the memory cell array.

[0013] Figure 6 This is a circuit diagram illustrating a readout amplifier circuit according to some embodiments.

[0014] Figure 7 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some embodiments.

[0015] Figure 8 This is a circuit diagram illustrating a sense amplifier circuit that performs a precharge operation according to some embodiments.

[0016] Figure 9 This is a circuit diagram illustrating a sense amplifier circuit that performs offset compensation operation according to some embodiments.

[0017] Figure 10 This is a circuit diagram illustrating a sense amplifier circuit that performs charge-sharing operation according to some embodiments.

[0018] Figure 11 This is a circuit diagram illustrating a sense amplifier circuit that performs charge transfer operations according to some embodiments.

[0019] Figure 12 It is a graph showing the offset variation, charge sharing period variation, and charge transfer period variation of the readout amplifier circuit according to some embodiments.

[0020] Figure 13 This is a circuit diagram illustrating a sense amplifier circuit that performs sensing operations according to some embodiments.

[0021] Figure 14 This is a circuit diagram illustrating a readout amplifier circuit that performs a recovery operation according to some embodiments.

[0022] Figure 15 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some embodiments.

[0023] Figure 16 It is a graph showing the magnitude of the current generated in a readout amplifier circuit according to some embodiments.

[0024] Figure 17 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some other embodiments.

[0025] Figure 18 This is a circuit diagram illustrating a third precharge transistor that is turned off during offset compensation operation according to some other embodiments.

[0026] Figure 19 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some other embodiments.

[0027] Figure 20 This is a block diagram illustrating a computer device according to some embodiments. Detailed Implementation

[0028] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0029] Furthermore, in order to clearly explain this disclosure in the accompanying drawings, parts that are not relevant to the explanation may be omitted, and similar parts are given similar reference numerals throughout the specification.

[0030] Furthermore, unless explicitly expressed as “a” or “singular,” expressions written in the singular can be interpreted as either singular or plural. Terms including ordinal numbers (such as first, second, etc.) can be used to describe various components, but these components are not limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element.

[0031] As used herein, the terms “comprising,” “including,” “having,” and any other variations thereof indicate the presence of the stated features, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items.

[0032] In the following sections, exemplary embodiments of the present disclosure will be described in more detail. These embodiments are intended to illustrate the present disclosure only, and the scope of the present disclosure is not limited by these embodiments.

[0033] Figure 1 This is a block diagram illustrating a memory device according to some embodiments.

[0034] refer to Figure 1The memory device 100 may include a memory cell array 110, control logic circuitry 120, address buffer 130, sense amplifier 140, row decoder 150, column decoder 160, input / output (I / O) gating circuitry 170, and data I / O buffer 180. In some embodiments, the memory device 100 may be a dynamic random access memory (DRAM), but is not limited thereto.

[0035] The memory cell array 110 may include multiple rows, multiple columns, and multiple memory cells MC arranged at the intersections of the multiple rows and multiple columns. The multiple rows may be defined by multiple word lines WL, and the multiple columns may be defined by multiple bit lines BL.

[0036] Control logic circuitry 120 controls the operation of memory device 100. For example, control logic circuitry 120 can generate control signals that cause memory device 100 to perform read, write, or refresh operations. In some embodiments, control logic circuitry 120 can generate control signals by decoding a command CMD received from a memory controller (not shown). In some embodiments, control logic circuitry 120 can send control signals to sense amplifier 140, row decoder 150, and column decoder 160.

[0037] Address buffer 130 can receive address ADDR provided from memory controller. Address ADDR may include row address RA indicating a row of memory cell array 110 and column address CA indicating a column of memory cell array 110. Row address RA may be provided to row decoder 150 and column address CA may be provided to column decoder 160.

[0038] The row decoder 150 can select the row to be activated from among multiple rows of the memory cell array 110 based on the row address RA. To do this, the row decoder 150 can apply a drive voltage to the word line WL corresponding to the row to be activated.

[0039] Column decoder 160 can select the column to be activated among multiple columns of memory cell array 110 based on column address CA. For this purpose, column decoder 160 can activate a sense amplifier 140 corresponding to column address CA via input / output (I / O) gating circuitry 170. The sense amplifier 140 can be connected to bit line BL of memory cell array 110. The sense amplifier 140 can sense the voltage of bit line BL and output the sensed voltage. In some embodiments, input / output (I / O) gating circuitry 170 gates input / output data and may include a data latch for storing data read from memory cell array 110 and a write driver for writing data to memory cell array 110. Data read from memory cell array 110 can be sensed by sense amplifier 140 and can be stored in input / output (I / O) gating circuitry 170 (e.g., a data latch).

[0040] In some embodiments, data read from the memory cell array 110 (e.g., data stored in a data latch) may be provided to the memory controller via the data I / O buffer 180. Data to be written to the memory cell array 110 is provided from the memory controller to the data I / O buffer 180, and the data provided to the data I / O buffer 180 can be provided to the input / output (I / O) gating circuit 170.

[0041] Figure 2 This is a diagram illustrating a memory cell array and a sense amplifier in a memory device according to some embodiments.

[0042] refer to Figure 2 The memory cell array 200 may include multiple memory cell blocks (CB11, CB12, CB13, ..., CB1n) and multiple sense amplifier blocks (SA10, SA11, SA12, SA13, ..., SA1n-1, SA1n), where n is a positive integer. Each sense amplifier block SA1i corresponds to two adjacent memory cell blocks (CB1i, CB1i+1) among the multiple memory cell blocks (CB11 to CB1n), and can be connected to these two adjacent memory cell blocks (CB1i, CB1i+1), where i is an integer from 1 to n-1.

[0043] Each memory cell block CB1i may include multiple bit lines BL extending in a predetermined direction (e.g., in the column direction). Multiple memory cells may be connected to each bit line BL. The memory cell block CB1i may also include multiple word lines extending in different directions (e.g., in the row direction). Multiple memory cells connected to each bit line BL may be individually connected to multiple word lines. In some embodiments, such as... Figure 2As shown, some of the memory cell blocks CB11 to CB1n may include complementary bit lines BLB as bit lines. In this case, the memory cell blocks in which bit lines BL are formed and the memory cell blocks in which complementary bit lines BLB are formed are arranged alternately, and bit lines BL and complementary bit lines BLB can form complementary bit line pairs.

[0044] A sense amplifier block SA1i can be connected to some bit lines BL of a memory cell block CB1i and some complementary bit lines BLB of another memory cell block CB1i+1. In some embodiments, the sense amplifier block SA1i can be connected to the odd bit lines BL of memory cell block CB1i and the odd complementary bit lines BLB of memory cell block CB1i+1. In this case, the even bit lines BL of memory cell block CB1i can be connected to another sense amplifier block SA1i-1, and the even complementary bit lines BLB of memory cell block CB1i+1 can be connected to another sense amplifier block SA1i+1. In some other embodiments, the sense amplifier block SA1i can be connected to the even bit lines BL of memory cell block CB1i and the even complementary bit lines BLB of memory cell block CB1i+1.

[0045] In some embodiments, the sense amplifier block SA10 at one end can be connected to the bit line BL of a memory cell CB11, and the sense amplifier block SA1n at the other end can be connected to the complementary bit line BLB of a memory cell CB1n.

[0046] The sense amplifier block SA1i may include multiple sense amplifiers S / A. Each sense amplifier S / A may correspond to some bit lines BL of memory cell block CB1i and to some complementary bit lines BLB of another memory cell block CB1i+1. Each sense amplifier S / A may be connected to a corresponding bit line BL in some bit lines (e.g., odd bit lines) BL of memory cell block CB1i and a corresponding complementary bit line BLB in some complementary bit lines (e.g., odd complementary bit lines) BLB of another memory cell block CB1i+1.

[0047] Figure 3 This is a circuit diagram illustrating the connection of a memory cell and a readout amplifier circuit in a memory device according to some embodiments.

[0048] like Figure 3 As shown, in the cell array block CB1i, bit lines (BL0, BL2) can be connected to the sense amplifiers (S / Ai,0, S / Ai,1) of the sense amplifier block SA1i, respectively, and bit lines (BL1, BL3) can be connected to the sense amplifiers (S / Ai-1,0, S / Ai-1,1) of the sense amplifier block SA1i-1, respectively. Figure 3For ease of description, a word line WL and a memory cell MC connected to the word line WL are shown. Additionally, in... Figure 3 Although each memory cell MC is shown as including a transistor and a capacitor, the structure of the memory cell MC is not limited to this.

[0049] Figure 4 This illustrates some embodiments. Figure 1 A three-dimensional view of the memory device.

[0050] refer to Figures 1 to 4 Memory device ( Figure 1 The 100 in the document may include a unit wafer, a peripheral wafer, and bonding pads 430 for electrically connecting the unit wafer and the peripheral wafer. As used herein, the peripheral wafer may also be referred to as the outer edge wafer.

[0051] A cell die may include multiple memory cell regions 411 to 416. Among the multiple memory cell regions 411 to 416, some memory cell regions 411, 413, and 415 may include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple bit lines BL. Among the multiple memory cell regions 411 to 416, in addition to some memory cell regions 411, 413, and 415, the remaining memory cell regions 412, 414, and 416 may include multiple word lines WL, multiple complementary bit lines BLB, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple complementary bit lines BLB. The cell die may be arranged to overlap with peripheral wafers along a third axis D3 direction. As used herein, "element A overlaps with element B in direction X" (or similar language) means that there exists at least one straight line extending in direction X and intersecting both element A and element B.

[0052] The peripheral chip may include multiple peripheral regions 431 to 436. Each of the multiple peripheral regions 431 to 436 may include a sub-word line driver region SWD arranged along the second axis D2 and bit line sense amplifier regions BLSA1 and BLSA2 arranged along the first axis D1. The multiple sub-word line drivers may be placed in the sub-word line driver region SWD. The multiple sub-word line drivers can activate a specific word line among multiple word lines. The multiple bit line sense amplifiers may be arranged in the bit line sense amplifier regions BLSA1 and BLSA2. The multiple bit line sense amplifiers can determine the state of memory cells connected to multiple bit lines BL or multiple complementary bit lines BLB.

[0053] Bit line sense amplifier regions BLSA1 and BLSA2 can be electrically connected to some of the memory cell regions 411 to 416 via bonding pad 430. In this case, bit line sense amplifier regions BLSA1 and BLSA2 can be connected to bit line BL and complementary bit line BLB included in the memory cell regions 411 to 416.

[0054] For example, the bit line sense amplifier regions BLSA1 and BLSA2 of the first peripheral region 433 can be electrically connected to the bit line BL of the third memory cell region 413 and the complementary bit line BLB of the fourth memory cell region 414, which are adjacent to each other in the direction of the third axis D3.

[0055] Figure 5 This illustrates some embodiments. Figure 1 The circuit diagram of the memory cell array.

[0056] refer to Figure 5 The memory cell array 500 may include a plurality of memory cells MC1 to MC16 stacked along the third axis D3. The plurality of memory cells MC1 to MC16 may be connected to a plurality of bit lines BL11, BL12, BL21, and BL22 arranged along the third axis D3. For example, the first memory cell MC1 to the fourth memory cell MC4 may be connected to the first bit line BL11, and the fifth memory cell MC5 to the eighth memory cell MC8 may be connected to the second bit line BL21. Additionally, the ninth memory cell MC9 to the twelfth memory cell MC12 may be connected to the third bit line BL12, and the thirteenth memory cell MC13 to the sixteenth memory cell MC16 may be connected to the fourth bit line BL22.

[0057] The first bit line BL11 and the third bit line BL12 can be connected to the first strip STRAP1, which is arranged along the first axis D1. Furthermore, the second bit line BL21 and the fourth bit line BL22 can be connected to the second strip STRAP2, which is also arranged along the first axis D1. The number of bit lines connected to the first strip STRAP1 and the second strip STRAP2, and the number of memory cells connected to multiple bit lines, are merely examples and are not limited to this. Figure 5 The number shown.

[0058] Multiple word lines WL11, WL12, WL13, WL14, WL21, WL22, WL23 and WL24 are arranged along the second axis D2 direction, and voltages can be applied to the gates of transistors TR1 to TR16 included in multiple memory cells MC1 to MC16.

[0059] Word lines WL11, WL12, WL13, and WL14 can be connected to transistors TR1 to TR4 connected to the first word line BL11 and transistors TR5 to TR8 connected to the second word line BL21. For example, the first word line WL11 can be connected to the gate of the first transistor TR1 and the gate of the fifth transistor TR5, and the second word line WL12 can be connected to the gate of the second transistor TR2 and the gate of the sixth transistor TR6. Furthermore, the third word line WL13 can be connected to the gate of the third transistor TR3 and the gate of the seventh transistor TR7, and the fourth word line WL14 can be connected to the gate of the fourth transistor TR4 and the gate of the eighth transistor TR8. Similarly, word lines WL21, WL22, WL23, and WL24 can be connected to transistors TR9 to TR12 connected to the third word line BL12 and transistors TR13 to TR16 connected to the fourth word line BL22.

[0060] Each of the plurality of memory cells MC1 to MC16 includes capacitors CS1 to CS16 which can be connected to transistors TR1 to TR16 included in each of the plurality of memory cells MC1 to MC16 in the direction of a first axis D1, the direction of the first axis D1 being orthogonal to the direction of a third axis D3 along which the plurality of memory cells MC1 to MC16 are stacked. For example, first capacitors CS1 to fourth capacitors CS4 can be connected to first transistors TR1 to fourth transistors TR4 respectively along the direction of the first axis D1, and fifth capacitors CS5 to eighth capacitors CS8 can be connected to fifth transistors TR5 to eighth transistors TR8 respectively along the direction of the first axis D1. In addition, ninth capacitors CS9 to twelfth capacitors CS12 can be connected to ninth transistors TR9 to twelfth transistors TR12 respectively along the direction of the first axis D1, and thirteenth capacitors CS13 to sixteenth capacitors CS16 can be connected to thirteenth transistors TR13 to sixteenth transistors TR16 respectively along the direction of the first axis D1.

[0061] When the first capacitor CS1 to the sixteenth capacitor CS16 are connected to the first transistor TR1 to the sixteenth transistor TR16 along the first axis D1, the chip space efficiency of the memory cell array 500 can be improved. As the chip space efficiency is improved, the number of memory cells MC1 to MC16 that can be integrated per unit area increases, which can increase the overall memory capacity.

[0062] Figure 6 This is a circuit diagram showing a readout amplifier circuit 600 according to some embodiments.

[0063] refer to Figure 6The readout amplifier circuit 600 may include a first circuit 610 and a second circuit 620. The first circuit 610 may be connected to a plurality of memory cells MC via a bit line BL and a complementary bit line BLB. Each of the plurality of memory cells MC may include a transistor TR and a capacitor CS.

[0064] The second circuit 620 can be electrically connected to the local input / output line LIO. The voltage of the output node OUT of the second circuit 620 can be transmitted to the local input / output line LIO through the local transistor MN1. The column select line CSL is connected to the gate of the local transistor MN1, and the operation of the local transistor MN1 can be determined based on the potential of the column select line CSL. For example, the local transistor MN1 can be turned on when the column select line CSL is at a logic high level, and the local transistor MN1 can be turned off when the column select line CSL is at a logic low level. Although the local transistor MN1 is shown as an N-type transistor, this disclosure is not limited thereto, and in some embodiments, it can be a P-type transistor.

[0065] The first circuit 610 may include a first control transistor MN2, a second control transistor MN3, a third control transistor MP1, a bit line transistor MN4, and a complementary bit line transistor MN5.

[0066] The source of the first control transistor MN2 can be connected to the first node N1, the drain of the first control transistor MN2 can be connected to the second node N2, and a control signal PTG can be applied to the gate of the first control transistor MN2. The control signal PTG can be the bias voltage Vb of the first control transistor MN2 or a supply voltage Va having a voltage level higher than (i.e., greater than) the bias voltage Vb. The supply voltage Va can be VDD. The bias voltage Vb can be provided by a second control transistor MN3 that is turned on based on an active level control signal PC. The supply voltage Va can be provided by a third control transistor MP1 that is turned on based on an active level control signal PR. The bias voltage Vb and the supply voltage Va can be generated from a separate voltage generator (not shown).

[0067] The gate of the first control transistor MN2 can selectively receive a bias voltage Vb and a power supply voltage Va. When the second control transistor MN3 is turned on and the third control transistor MP1 is turned off, the gate of the first control transistor MN2 can receive the bias voltage Vb. Furthermore, when the second control transistor MN3 is turned off and the third control transistor MP1 is turned on, the gate of the first control transistor MN2 can receive the power supply voltage Va.

[0068] Bit line transistor MN4 and complementary bit line transistor MN5 can be electrically connected to the first node N1. Specifically, the drain of bit line transistor MN4 can be connected to the first node N1, and the drain of complementary bit line transistor MN5 can be connected to the first node N1. Bit line BL and complementary bit line BLB can receive the charge accumulated in the first node N1 through bit line transistor MN4 and complementary bit line transistor MN5. The capacitive component CBL of bit line BL can be connected in parallel with memory cell MC relative to bit line node BL1.

[0069] The second circuit 620 may include a first inverter 621, a second inverter 622, and a pre-charge circuit 623.

[0070] Inverter (or first inverter) 621 is connected between high-voltage line LA and low-voltage line LAB, and can provide the power supply voltage VINTA of high-voltage line LA or the power supply voltage VSS of low-voltage line LAB to the third node N3 according to the voltage of the second node N2. Inverter (or second inverter) 622 is connected between high-voltage line LA and low-voltage line LAB, and can provide the power supply voltage VINTA of high-voltage line LA or the power supply voltage VSS of low-voltage line LAB to the output node OUT according to the voltage of the fourth node N4. In some embodiments, inverters 621 and 622 may be CMOS (complementary MOS) inverters. In this case, inverter 621 may include transistor MP2 located between high-voltage line LA and the third node N3 and transistor MN6 located between the third node N3 and the low-voltage line LAB, and inverter 622 may include transistor MP3 located between high-voltage line LA and the output node OUT and transistor MN7 located between the output node OUT and the low-voltage line LAB. The gates of transistors MP2 and MN6 may be connected to the second node N2, which serves as the first input inverter terminal. The first inverter 621 includes a first input inverter terminal. In other words, the first inverter 621 may include an input terminal connected to the second node N2. The gates of transistors MP3 and MN7 may be connected to the fourth node N4, which serves as the second input inverter terminal. The second inverter 622 includes a second input inverter terminal. In other words, the second inverter 622 may include an input terminal connected to the fourth node N4. The second inverter 622 may be connected to the output node OUT. For example, the second inverter 622 may include an input terminal connected to the output node OUT.

[0071] The pre-charge circuit 623 can pre-charge the second node N2 to the first voltage VSS by transmitting the first voltage VSS to the second node N2 for a first time period in response to the control signal PE, or it can pre-charge the second node N2 to the second voltage Vpc by transmitting the second voltage Vpc to the second node N2 for a second time period in response to the control signal PI. In some embodiments, the first voltage VSS can be a ground voltage or a negative voltage, and the second voltage Vpc can be a voltage higher than the power supply voltage VINTA of the high-voltage line LA of inverters 621 and 622. The second voltage Vpc can also be a voltage higher than the first voltage VSS. In some embodiments, the pre-charge circuit 623 may include transistors MN8, MN9, and MN10.

[0072] The first precharge transistor MN8 is connected between the second node N2 and the output node OUT, and can operate in response to the control signal PS. For example, the drain of transistor MN8 can be connected to the second node N2, and the source of the first precharge transistor MN8 can be connected to the output node OUT. The gate of the first precharge transistor MN8 can receive the control signal PS.

[0073] The second precharge transistor MN9 can be connected between the fifth node N5 and the ground terminal. The fifth node N5 is the contact point between the source of the second precharge transistor MN9 and the drain of the first precharge transistor MN8. The third precharge transistor MN10 can be connected between the fifth node N5 and the line supplying the second voltage Vpc. The second precharge transistor MN9 can transmit the first voltage VSS to the second node N2 in response to the control signal PE, and the third precharge transistor MN10 can transmit the second voltage Vpc to the second node N2 in response to the control signal PI.

[0074] For example, in the second precharge transistor MN9, the drain can be connected to the fifth node N5, the source can be connected to the ground terminal, and the gate can receive the control signal PE. Furthermore, in the third precharge transistor MN10, the drain is connected to the line providing the second voltage Vpc, the source is connected to the fifth node N5, and the gate can receive the control signal PI.

[0075] The first circuit 610 and the second circuit 620 can be connected to each other via the first control transistor MN2. Due to the potential difference between the first node N1 and the second node N2, charge can be transferred between the first circuit 610 and the second circuit 620. In this case, the amount of charge transferred between the first circuit 610 and the second circuit 620 can be changed based on the voltage applied to the gate of the first control transistor MN2.

[0076] The first control transistor MN2 can have a larger channel length (L) and channel width (W) than the other transistors MN1, MN3 to MN10, and MP1 to MP3. For example, the size of the first control transistor MN2 can be approximately twice the channel length (L) and channel width (W) of the other transistors MN1, MN3 to MN10, and MP1 to MP3. When the first control transistor MN2 is connected to a node shared by bit line BL and complementary bit line BLB, the layout area of ​​the first control transistor MN2 can be increased compared to the case where the first control transistor MN2 is connected to each of the bit line BL and complementary bit line BLB.

[0077] Since the process variation of a transistor is inversely proportional to its channel length (L) and channel width (W), the process variation of a transistor can be reduced as the channel length (L) and channel width (W) increase. When the process variation of a transistor decreases, the performance of the sense amplifier circuit 600 can be improved.

[0078] In some embodiments, Figure 6 The transistors MN1 to MN10 and MP1 to MP3 shown may be metal-oxide-semiconductor (MOS) transistors. In some embodiments, transistors MN1 to MN10 may be n-channel transistors, such as NMOS transistors, and transistors MP1 to MP3 may be p-channel transistors, such as PMOS transistors. Transistors MN1 to MN10 and MP1 to MP3 may have a source, a drain, and a gate. The source and drain may also be referred to as terminals, and the gate may also be referred to as a control terminal.

[0079] Figure 7 and Figure 15 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some embodiments. Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 13 and Figure 14 It shows the basis Figure 7 The circuit diagram shows the operation of the readout amplifier circuit with the indicated timing. For example, as... Figure 7 As shown, the readout amplifier circuit can sequentially perform the pre-charge operation PCG, offset compensation operation OC, charge sharing operation CS, charge transfer operation CT, sensing operation SEN, and recovery operation RST. Figure 7 In this context, data that is "1" (i.e., data with a logical value of "1") can be stored in the storage unit MC. Figure 15 In this context, data that is “0” (i.e., data with a logical value of “0”) can be stored in the storage unit MC.

[0080] refer to Figure 7 and Figure 8 The readout amplifier circuit can perform a precharge operation PCG to precharge bit line BL, complementary bit line BLB, and second node N2 to the first voltage VSS.

[0081] When bit line BL is precharged with a first voltage VSS, the sense amplifier circuit can sense the data stored in the memory cell MC connected to bit line BL more accurately than when bit line BL is precharged with an intermediate voltage VBL (a value between VDD and the first voltage VSS). For example, assuming data of "0" stored in memory cell MC is stored and bit line BL is precharged to the intermediate voltage VBL, bit line BL can output a voltage less than or equal to the intermediate voltage VBL after charge-sharing operation CS. Assuming data of "0" stored in memory cell MC is stored and bit line BL is precharged to the first voltage VSS, bit line BL can output the first voltage VSS after charge-sharing operation CS. Charge transfer operation CT, sensing operation SEN, and recovery operation RST can be performed after charge-sharing operation CS based on the level of the voltage output from bit line BL. Therefore, the sense margin of the sense amplifier circuit can be improved by precharging bit line BL to the first voltage VSS.

[0082] During the precharge operation PCG period, the second precharge transistor MN9 can be turned on based on the active level (e.g., high level) control signal PE, and the third precharge transistor MN10 can be turned off based on the inactive level (e.g., low level) control signal PI. Therefore, the first voltage VSS can be precharged to the second node N2 through the second precharge transistor MN9. In other words, the precharge circuit 623 (see...) Figure 6 The first voltage VSS can be transferred to the second node N2 through the second precharge transistor MN9.

[0083] During the precharge operation PCG period, the third control transistor MP1 can be turned on based on the active level (e.g., low level) control signal PR, and the second control transistor MN3 can be turned off based on the inactive level (e.g., low level) control signal PC. VDD (i.e., the supply voltage Va) is applied as the control signal PTG to the gate of the first control transistor MN2, causing the first control transistor MN2 to turn on. Therefore, the first voltage VSS can be precharged to the first node N1 through the second precharge transistor MN9, the second node N2, and the first control transistor MN2.

[0084] During the precharge operation PCG period, bit line transistor MN4 and complementary bit line transistor MN5 can be turned on based on the active level (e.g., high level) control signals RB and LB. Therefore, the first voltage VSS can be precharged to bit line BL and complementary bit line BLB via the second precharge transistor MN9, the second node N2, and the first node N1. In other words, the first voltage VSS can be applied to bit line BL and complementary bit line BLB from the second node N2. For example, when the first control transistor MN2 is turned on, the first voltage VSS can be transferred to bit line BL, complementary bit line BLB, the first node N1, and the second node N2. The capacitive component CBL present in bit line BL can also be precharged to the first voltage VSS.

[0085] During the precharge operation PCG period, the first precharge transistor MN8 can be turned on based on the active level (e.g., high level) control signal PS. Therefore, the first voltage VSS can be output from the output node OUT.

[0086] refer to Figure 7 and Figure 9 The sense amplifier circuit can perform offset compensation operation OC. The sense amplifier circuit can perform offset compensation operation OC by connecting bit line BL and second node N2 via first control transistor MN2 to the first control transistor MN2.

[0087] During the offset compensation operation OC period, the second precharge transistor MN9 can be turned off based on a non-active level (e.g., low level) control signal PE, and the third precharge transistor MN10 can be turned on based on an active level (e.g., high level) control signal PI. Therefore, the precharge voltage Vpc can be precharged to the second node N2 through the third precharge transistor MN10. In other words, the precharge circuit 623 (see...) Figure 6 The pre-charge voltage Vpc can be transferred to the second node N2 via the third pre-charge transistor MN10. In this case, the pre-charge voltage Vpc can be a voltage higher than the power supply voltage VINTA of the high-voltage line LA. The pre-charge voltage Vpc can also be a voltage higher than the first voltage VSS.

[0088] During the offset compensation operation OC period, the second control transistor MN3 can be turned on based on the active level (e.g., high level) control signal PC, and the third control transistor MP1 can be turned off based on the inactive level (e.g., high level) control signal PR. Therefore, a bias voltage Vb can be applied as a control signal PTG to the gate of the first control transistor MN2. The bias voltage Vb is a voltage between a high-level voltage used as the active level and a low-level voltage used as the inactive level, and can be a voltage higher than the threshold voltage Vth of the first control transistor MN2 (i.e., the gate threshold voltage Vth). However, the bias voltage Vb can be less than VDD. In some embodiments, the bias voltage Vb can be set by considering charge transfer in the charge transfer operation CT, which will be described below.

[0089] The first control transistor MN2, biased by a voltage Vb, can be in a weakly conducting state. Therefore, current can flow from the second node N2, pre-charged by a voltage Vpc, to the first node N1, which is subjected to a first voltage VSS. However, if the difference between the voltage at the first node N1 connected to the source of the first control transistor MN2 and the voltage at the second node N2 connected to the drain of the first control transistor MN2 is less than the threshold voltage Vth of the first control transistor MN2, then the first control transistor MN2 can be turned off. Therefore, the first control transistor MN2 can remain on until the difference between the voltage at the first node N1 and the voltage at the second node N2 reaches the threshold voltage Vth of the first control transistor MN2.

[0090] During offset compensation operation OC, complementary bitline transistor MN5 and first precharge transistor MN8 can be turned off based on inactive levels (e.g., low levels) control signals LB and PS. Bitline transistor MN4 can remain on based on an active level (e.g., high level) control signal RB. For example, when the first precharge transistor MN8 is turned off, the precharge voltage Vpc can be transferred to the second node N2.

[0091] Therefore, the pre-charge voltage Vpc applied to the second node N2 can be applied to the bit line BL through the first control transistor MN2, the first node N1, and the bit line transistor MN4. In other words, the pre-charge voltage Vpc can be applied to the bit line BL from the second node N2. However, the pre-charge voltage Vpc can be applied to the bit line BL until the difference between the voltage of the first node N1 and the voltage of the second node N2 reaches the threshold voltage Vth of the first control transistor MN2.

[0092] In other words, the voltage of bit line BL can be determined by the threshold voltage Vth of the first control transistor MN2. The voltage of bit line BL can be determined, for example, as Vb - Vth. When compensation for the threshold voltage Vth of the first control transistor MN2 is not required in bit line BL, the offset compensation operation OC can be omitted.

[0093] refer to Figure 7 and Figure 10 The sense amplifier circuit can perform a charge-sharing operation CS to share charge between the bit line BL and the memory cell MC. In this case, the word line WLi, which is connected to the gate of the memory cell MC, can be activated.

[0094] During the charge-sharing operation CS period, bit line transistor MN4 can be turned off based on a control signal RB that is at an inactive level (e.g., low). Because bit line transistor MN4 is off, bit line BL can be electrically disconnected from the first node N1 and the second node N2. In other words, during charge-sharing operation CS, bit line BL can be disconnected from the resistance of the first node N1 and the second node N2 (e.g., by turning off bit line transistor MN4). For example, when bit line transistor MN4 is off, the current path between bit line BL and the first node N1 and the second node N2 can be blocked.

[0095] Since the transistor TR of the memory cell MC is turned on by the activation of the word line WLi connected to the gate of the memory cell MC, charge can be shared between the capacitor CS of the memory cell MC and the capacitive component CBL of the bit line. For example, a charge sharing operation can be performed between the capacitive component CBL of the bit line BL and the memory cell MC. Since the data "1" is stored in the memory cell MC, charge (e.g., electrons) can be transferred from the capacitive component CBL of the bit line to the capacitor CS. Therefore, the voltage of the bit line BL can be increased.

[0096] Still referencing Figure 7 and Figure 10 When bit line BL is precharged to the first voltage VSS in the precharge operation PCG, the voltage of bit line BL can be increased more significantly compared to when bit line BL is precharged to the intermediate voltage between high and low levels in the precharge operation PCG.

[0097] Simultaneously, the third precharge transistor MN10 can be kept in the on state based on the control signal PI with an active level (e.g., high level). Therefore, the precharge voltage Vpc can be continuously applied to the second node N2.

[0098] In addition, since bit line transistor MN4 and complementary bit line transistor MN5 are turned off, current cannot flow through the first control transistor MN2, so the first control transistor MN2 can be turned off.

[0099] refer to Figure 7 and Figure 11 The readout amplifier circuit can perform a charge transfer operation CT, which transfers charge between the bit line BL and the second node N2 by connecting the bit line BL and the second node N2.

[0100] During the charge transfer operation (CT) period, the third precharge transistor MN10 can be turned off based on a control signal PI that is inactive (e.g., low). Therefore, no precharge voltage Vpc is applied to the second node N2. However, since the precharge voltage Vpc is applied to the second node N2 during the charge sharing operation (CS), the voltage of the second node N2 can be greater than the voltage of the first node N1.

[0101] During the charge transfer operation CT period, bit line transistor MN4 can be turned on based on the active level (e.g., high level) control signal RB. Therefore, the first node N1 can be electrically connected to bit line BL.

[0102] During the charge transfer operation (CT) period, a bias voltage Vb can be applied to the gate of the first control transistor MN2. In some embodiments, the bias voltage Vb used in the charge transfer operation (CT) can be the same as the bias voltage Vb used in the offset compensation operation (OC).

[0103] Then, by subtracting the voltage of bit line BL from the bias voltage Vb and the threshold voltage Vth of the first control transistor MN2 to obtain the voltage Vb-VBL-Vth, charge (e.g., electrons) can be transferred from bit line BL to the second node N2, thereby reducing the voltage of the second node N2. Furthermore, the transfer of charge (e.g., electrons) from bit line BL to the second node N2 allows the voltage of bit line BL to increase.

[0104] The voltage level of the second node N2 can be slightly lower than the previously pre-charged voltage Vpc. However, since the capacitive component of the second node N2 is greater than the capacitive component CBL of the bit line BL, the voltage reduction of the second node N2 can be less than the voltage increase of the bit line BL.

[0105] Meanwhile, since the bit line BL is charged with a voltage determined by the threshold voltage Vth in the offset compensation operation OC, the offset of the threshold voltage Vth of the first control transistor MN2 can be offset in the charge transfer operation CT.

[0106] Figure 12 It is a graph showing the offset variation, charge sharing period variation, and charge transfer period variation of the readout amplifier circuit according to some embodiments.

[0107] refer to Figure 12The variation 1220 of the first-first charge-sharing period CS is a graph showing the voltage of the second node N2 during the charge-sharing period CS when data "1" is stored in each of the multiple memory cells. The variation 1230 of the first-second charge-sharing period CS is a graph showing the voltage of the second node N2 during the charge-sharing period CS when data "0" is stored in each of the multiple memory cells. In this case, the horizontal axis can represent the voltage V, and the vertical axis can represent the number of memory cells (cell #).

[0108] The offset change 1210 of the sense amplifier circuit may partially overlap with the changes 1220 and 1230 of the first-first charge-shared CS period and the first-second charge-shared CS period, respectively. For example, based on the same voltage, there may be partially overlapping regions where the offset change 1210 of the sense amplifier circuit exceeds the changes 1220 or 1230 of the first-first charge-shared CS period.

[0109] During the sensing operation period, errors may occur when the sense amplifier circuit senses multiple memory cells corresponding to overlapping regions. For example, the sense amplifier circuit may sense a memory cell storing data "1" as data "0". Conversely, the sense amplifier circuit may sense a memory cell storing data "0" as data "1". This is because the voltage difference between the output voltage V1 of the second node N2 in the change 1220 of the first-first charge sharing CS period and the output voltage V2 of the second node N2 in the change 1230 of the first-second charge sharing CS period is relatively small.

[0110] Still referencing Figure 12 The variation 1240 of the second-to-first charge transfer CT period is a graph showing the voltage of the second node N2 during the charge transfer CT period when data "1" is stored in each of the plurality of memory cells. The variation 1250 of the second-to-second charge transfer CT period is a graph showing the voltage of the second node N2 during the charge transfer CT period when data "0" is stored in each of the plurality of memory cells. In this case, the horizontal axis can represent the voltage V, and the vertical axis can represent the number of memory cells (cell #).

[0111] The offset change 1210 of the readout amplifier circuit may not overlap with the change 1240 of the second-to-first charge transfer CT period and the change 1250 of the second-to-second charge transfer CT period. The voltage difference between the output voltage V3 of the second node N2 in the change 1240 of the second-to-first charge transfer CT period and the output voltage V4 of the second node N2 in the change 1250 of the second-to-second charge transfer CT period may be greater than the voltage difference between the output voltage V1 of the second node N2 in the change 1220 of the first-to-first charge sharing CS period and the output voltage V2 of the second node N2 in the change 1230 of the first-to-second charge sharing CS period.

[0112] refer to Figure 7 and Figure 12 When bit line BL, precharged to the first voltage VSS during the precharge operation PCG period, shares charge with the memory cell storing data "1" during the charge sharing operation CS period, the voltage of bit line BL can be increased. Additionally, the precharge voltage Vpc can be applied to the second node N2 during the charge sharing operation CS period. In this case, the precharge voltage Vpc of the second node N2 can be higher than the voltage of bit line BL.

[0113] During the charge transfer operation (CT) period, charge (e.g., electrons) is transferred from bit line BL to a second node N2 to which a pre-charge voltage Vpc is applied, allowing the voltage of the second node N2 to decrease. However, the voltage drop of the second node N2 during the charge transfer operation (CT) period can decrease proportionally to the voltage increase of bit line BL during the charge sharing operation (CS) period. Bit line BL, pre-charged to a first voltage VSS during the pre-charge operation (PCG) period, receives voltage from the memory cell during the charge sharing operation (CS) period, allowing the voltage of bit line BL to increase significantly. Therefore, the voltage drop of the second node N2 during the charge transfer operation (CT) period can be reduced.

[0114] refer to Figure 12 and Figure 15 When bit line BL, precharged to the first voltage VSS during the precharge operation PCG period, shares charge with a memory cell storing data "0" during the charge sharing operation CS period, the voltage of bit line BL can approach the first voltage VSS. Conversely, the precharge voltage Vpc can be applied to the second node N2 during the charge sharing operation CS period.

[0115] During the charge transfer operation CT period, charge (e.g., electrons) is transferred from the bit line BL, which is close to the first voltage VSS, to the second node N2, which is pre-charged with a voltage Vpc, such that the voltage of the second node N2 can be reduced. Therefore, the output voltage V4 of the second node N2 in the variation 1250 of the second-second charge transfer CT period can be lower than the output voltage V2 of the second node N2 in the variation 1230 of the first-second charge sharing CS period.

[0116] The output voltage V4 of the second node N2 can be lower than the output voltage V2, and the output voltage V3 of the second node N2 can be higher than the output voltage V1. During the charge transfer operation (CT) period, the voltage difference between the output voltages V3 and V4 of the second node N2 can be higher than the voltage difference between the output voltages V1 and V2 of the second node N2 during the charge sharing operation (CS) period.

[0117] Therefore, the offset change 1210 of the readout amplifier circuit can be kept separate from the change 1240 of the second-to-first charge transfer CT period and the change 1250 of the second-to-second charge transfer CT period. This reduces the likelihood of errors occurring when the readout amplifier circuit senses multiple memory cells during the charge transfer operation CT period.

[0118] refer to Figure 7 and Figure 13 The readout amplifier circuit can perform a sensing operation (SEN) that outputs the voltage of the output node OUT.

[0119] During the SEN phase of the sensing operation, transistor MN6 can be turned on by the voltage of the second node N2, and transistor MP2 can be turned off by the voltage of the second node N2. With transistor MN6 turned on, the voltages of the third node N3 and the fourth node N4 can be reduced to the first voltage VSS of the low-voltage line LAB. For example, during the SEN phase of the sensing operation, the high-voltage line LA, which transmits the power supply voltage VINTA, and the low-voltage line LAB, which transmits the first voltage VSS, can be turned on.

[0120] During the sensing operation SEN period, transistor MN7 can be turned off by the voltage at the fourth node N4, and transistor MP3 can be turned on by the voltage at the fourth node N4. With transistor MP3 on, the voltage at the output node OUT can be increased to the power supply voltage VINTA of the high-voltage line LA. The sense amplifier circuit can sense high-level (i.e., "1") data stored in the memory cell MC. For example, the data (e.g., high or low level) sensed by the sense amplifier circuit in the memory cell MC can be based on the voltage at the second node N2.

[0121] refer to Figure 7 and Figure 14 The readout amplifier circuit can perform a recovery operation (RST) to restore the voltage of the memory cell MC.

[0122] During the recovery operation RST period, the second control transistor MN3 can be turned off based on the inactive level (e.g., low level) control signal PC, and the third control transistor MP1 can be turned on based on the active level (e.g., low level) control signal PR. As a control signal PTG, the power supply voltage Va can be applied to the gate of the first control transistor MN2. The first control transistor MN2, powered by the power supply voltage Va, can be fully turned on.

[0123] During the recovery operation RST period, the first precharge transistor MN8 can be turned on based on the active level (e.g., high level) control signal PS. Furthermore, charge (e.g., electrons) can be transferred from the capacitor CS of the memory cell MC to the output node OUT via the bit line transistor MN4, the first node N1, the first control transistor MN2, the second node N2, and the first precharge transistor MN8. Therefore, the voltage at the output node OUT decreases, and the data "1" can be restored to the memory cell MC.

[0124] refer to Figure 15 The control signals PTG, PE, PI, LB, RB, PS, and WL can have the same characteristics as the reference signals. Figure 7 The control signals PTG, PE, PI, LB, RB, PS, and WL have the same timing sequence. Therefore, it can be referenced as follows. Figures 7 to 9 The pre-charge operation PCG and offset compensation operation OC are performed as described.

[0125] During the charge-sharing operation CS period, since data of type "0" is stored in the capacitor of the memory cell MC, the voltage of the bit line BL may decrease due to charge sharing between the memory cell MC and the bit line BL. In other words, since the data "0" is stored in the memory cell MC, charge (e.g., electrons) can be transferred from the capacitor CS to the capacitive component CBL of the bit line.

[0126] During the charge transfer operation CT period, charge (e.g., electrons) can transfer from the bit line BL to the second node N2, thereby reducing the voltage at the second node N2. In this case, since the voltage on the bit line BL is close to the ground voltage, it is related to... Figure 7 Compared to the voltage shown, the voltage at the second node N2 can be significantly reduced. Furthermore, charge (e.g., electrons) can be transferred from the bit line BL to the second node N2, allowing the voltage at the bit line BL to increase.

[0127] However, since the capacitive component of the second node N2 is greater than the capacitive component CBL of the bit line BL, the voltage drop of the second node N2 can be less than the voltage increase of the bit line BL.

[0128] refer to Figure 13 and Figure 15 During the SEN (sensing) operation period, transistor MN6 can be turned off by the voltage of the second node N2, and transistor MP2 can be turned on by the voltage of the second node N2. With transistor MP2 on, the voltages of the third node N3 and the fourth node N4 can be increased to the power supply voltage VINTA of the high-voltage line LA.

[0129] During the sensing operation SEN period, transistor MN7 can be turned on by the voltage of the fourth node N4 and transistor MP3 can be turned off by the voltage of the fourth node N4. With transistor MN7 turned on, the voltage at the output node OUT can be reduced to the supply voltage VSS of the low-voltage line LAB. The sense amplifier circuit can sense high-level (i.e., "0") data stored in the memory cell MC. For example, the data (e.g., high or low level) sensed by the sense amplifier circuit in the memory cell MC can be based on the voltage at the second node N2.

[0130] Because the supply voltage difference dVBL of the second node N2 becomes relatively large due to the charge sharing operation CS and / or charge transfer operation CT, accurate sensing can be performed. In this case, the supply voltage difference dVBL can be amplified by the ratio of the capacitive component CBL of the bit line BL to the capacitive component CBL of the second node N2.

[0131] refer to Figure 14 and Figure 15 During the recovery operation RST period, the first precharge transistor MN8 can be turned on based on the active level (e.g., high level) control signal PS. Furthermore, charge (e.g., electrons) can be transferred from the output node OUT to the capacitor CS of the memory cell MC via the bit line transistor MN4, the first node N1, the first control transistor MN2, the second node N2, and the first precharge transistor MN8. Therefore, the voltage of the output node OUT can be increased, and the data "0" can be restored to the memory cell MC.

[0132] Figure 16 It is a graph showing the magnitude of the current generated in a readout amplifier circuit according to some embodiments.

[0133] refer to Figure 16A differential sense amplifier circuit amplifies the voltage difference between bit line BL and complementary bit line BLB during the process of reading data from a memory cell. The differential sense amplifier circuit can increase one voltage and decrease the other to amplify the voltage difference between bit line BL and complementary bit line BLB.

[0134] For example, if the differential sense amplifier circuit increases the voltage of bit line BL, it can decrease the voltage of the complementary bit line BLB, and if the voltage of the complementary bit line BLB is increased, the voltage of bit line BL can be decreased. Therefore, regardless of the type of data ("0" or "1") stored in the memory cell MC, the current generated when the sense amplifier circuit reads the data from the memory cell can be approximately 250 mA.

[0135] According to some embodiments, the sense amplifier circuit is a single-ended method (e.g., a single-ended circuit) in which each of the bit line BL and the complementary bit line BLB is connected to the first node N1, and the single-ended sense amplifier circuit can operate differently depending on the type ("0" or "1") of the data stored in the memory cell MC.

[0136] For example, if the data stored in each of the multiple memory cells connected to the bit line BL is "0", then the single-ended sense amplifier circuit does not need to increase the voltage of the bit line BL. In this case, the current generated when the sense amplifier circuit reads the data from the memory cell can be approximately 100mA.

[0137] Furthermore, when half of the memory cells connected to bit line BL store data "0" and the remaining memory cells store data "1", the voltage of bit line BL storing data "1" can be increased only. In this case, the current generated when the sense amplifier circuit reads the data from the memory cell can be approximately 200 mA.

[0138] Therefore, single-ended sense amplifier circuits can be driven with lower power than differential sense amplifier circuits.

[0139] Figure 17 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some other embodiments, and Figure 18 This is a circuit diagram illustrating a third precharge transistor that is turned off during offset compensation operation OC according to some other embodiments.

[0140] refer to Figure 17 The control signals PTG, PE, LB, RB, PS, and WL can have the same characteristics as the reference signals. Figure 7 The control signals PTG, PE, LB, RB, PS, and WL have the same timing sequence. Therefore, it can be referred to as... Figure 7 and Figure 8The pre-charge operation PCG is performed as described. Figure 17 In this context, data with the value "1" can be stored in the storage unit MC.

[0141] refer to Figure 17 and Figure 18 The readout amplifier circuit can completely turn off the first control transistor MN2 during the offset compensation operation OC process to reduce the leakage current generated in the first control transistor MN2.

[0142] refer to Figure 9 and Figure 17 During the offset compensation operation (OC) period, the third precharge transistor MN10 can be turned on based on the active level (e.g., high level) control signal PI. Therefore, a precharge voltage Vpc is applied to the second node N2, such that the voltage of the second node N2 can be greater than the voltage of the first node N1. In the precharge operation (PCG), a first voltage VSS is applied to the first node N1, and the voltage difference between the second node N2 and the first node N1 can exceed the threshold voltage Vth of the first control transistor MN2.

[0143] refer to Figure 17 and Figure 18 During the offset compensation operation OC period, the active level (e.g., high level) control signal PI can be switched to an inactive level (e.g., low level) control signal PI. The third precharge transistor MN10 can be turned off, and the precharge voltage Vpc can no longer be applied to the second node N2. When the voltage applied to the second node N2 decreases to the voltage applied to the first node N1, the voltage difference between the first node N1 (which is the source terminal of the first control transistor MN2) and the second node N2 (which is the drain terminal of the first control transistor MN2) can approach zero. Furthermore, the difference between the voltage applied to the source terminal of the first control transistor MN2 and the voltage applied to the drain terminal of the first control transistor MN2 can be less than the threshold voltage Vth of the first control transistor MN2. Therefore, the first control transistor MN2 can be turned off.

[0144] In the off state of the first control transistor MN2, no conductive channel is formed compared to the on state, thus blocking the main path of current flow. Therefore, the leakage current generated in the first control transistor MN2 can be reduced. Furthermore, since the leakage current generated in the first control transistor MN2 is reduced, the voltage variability of the bit line BL electrically connected to the first node N1 can also be reduced.

[0145] During the charge-sharing operation (CS) period, because data of type "1" is stored in the capacitor of the memory cell MC, the voltage of the bit line BL may decrease due to charge sharing between the memory cell MC and the bit line BL. For example... Figure 10 and Figure 17 As shown, during the charge-sharing operation CS period, the pre-charge voltage Vpc is applied again to the second node N2 to prepare for the charge transfer operation CT of the sense amplifier circuit. For example, during the charge-sharing operation CS period, the third pre-charge transistor MN10 can be turned on.

[0146] Figure 19 This is a diagram illustrating the operating timing of a sense amplifier circuit according to some other embodiments.

[0147] refer to Figure 19 The control signals PTG, PE, PI, LB, RB, PS, and WL can have the same characteristics as the reference signals. Figure 17 The control signals PTG, PE, PI, LB, RB, PS, and WL have the same timing sequence. Therefore, it can be referenced as follows. Figures 17 to 18 The pre-charge operation (PCG) and offset compensation operation (OC) are performed as described. Figure 19 In this context, data that is "0" can be stored in the storage unit MC.

[0148] The first control transistor MN2 can be used during the offset compensation operation OC period (see...). Figure 18 It can be turned off during the charge-sharing operation CS period (see...). Figure 10 The transistor is turned on again. In the off state of the first control transistor MN2, no conductive channel is formed compared to the on state, thus blocking the main path of current flow. Therefore, the leakage current generated in the first control transistor MN2 can be reduced during the off-state period.

[0149] During the charge-sharing operation CS period, since data of value "0" is stored in the capacitor of memory cell MC, the voltage of bit line BL may decrease due to charge sharing between memory cell MC and bit line BL. During the charge-sharing operation CS period, the pre-charge voltage Vpc is applied again to the second node N2 to prepare for the charge transfer operation CT of the sense amplifier circuit.

[0150] Figure 20 This is a block diagram illustrating a computer device according to some embodiments.

[0151] refer to Figure 20The computing device 2000 includes a processor 2010, a memory 2020, a memory controller 2030, a storage device 2040, a communication interface 2050, and a bus 2060. The computing device 2000 may also include other general-purpose components.

[0152] The processor 2010 controls the overall operation of each component of the computing device 2000. The processor 2010 can be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphics processing unit (GPU).

[0153] The memory 2020 stores various data and commands. The memory 2020 can be implemented as a reference. Figure 1 and Figure 4 The memory device described. Memory controller 2030 controls the transfer of data or commands to and from memory 2020. In some embodiments, memory controller 2030 may be provided as a separate chip from processor 2010. In some embodiments, memory controller 2030 may be provided as an internal configuration of processor 2010.

[0154] Storage device 2040 stores programs and data non-temporarily. In some embodiments, storage device 2040 may be implemented as a non-volatile memory device. Communication interface 2050 supports wired and wireless Internet communication of computing device 2000. Additionally, communication interface 2050 may support various communication methods other than Internet communication. Bus 2060 provides communication functionality between components of computing device 2000. Bus 2060 may include at least one type of bus according to a communication protocol between components.

[0155] Although exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the embodiments described above. It will be understood that various modifications can be made to the present disclosure without departing from the scope of the appended claims. Therefore, it should be understood that the embodiments described above are not restrictive but illustrative in all respects.

Claims

1. A sense amplifier circuit, the sense amplifier circuit comprising: First line; Bit line transistor, the bit line transistor being electrically connected between the first bit line and the first node; A first control transistor is electrically connected between the first node and the second node; A first inverter, the first inverter including an input terminal electrically connected to the second node; The second inverter is electrically connected to the output node; as well as A pre-charge circuit, electrically connected to the second node, is configured to transfer a first voltage to the second node during a first time period and to transfer a second voltage greater than the first voltage to the second node during a second time period.

2. The sense amplifier circuit according to claim 1, further comprising: A complementary bit line pair, wherein the complementary bit line pair includes the first bit line and the second bit line; as well as A complementary bit-line transistor, which is electrically connected between the second bit line and the first node.

3. The readout amplifier circuit according to claim 2, wherein, The complementary bitline transistor and the bitline transistor are configured to be selectively turned on.

4. The readout amplifier circuit according to claim 2, wherein, The pre-charging circuit includes: A first precharge transistor is electrically connected between the second node and the output node; A second precharge transistor, the second precharge transistor including a first terminal electrically connected to the second node and a second terminal configured to receive the first voltage; and A third precharge transistor includes a first terminal electrically connected to the second node and a second terminal configured to receive the second voltage.

5. The readout amplifier circuit according to claim 4, wherein: The second node is configured to selectively receive the first voltage and the second voltage, and The first voltage is a first power supply voltage, and the second voltage is a pre-charge voltage.

6. The sense amplifier circuit according to claim 5, further comprising: The second control transistor includes a first terminal electrically connected to the gate of the first control transistor and a second terminal configured to receive a bias voltage. as well as A third control transistor includes a first terminal electrically connected to the gate of the first control transistor and a second terminal configured to receive a second power supply voltage.

7. The readout amplifier circuit according to claim 6, wherein: The bias voltage is greater than the gate threshold voltage of the first control transistor, and The second power supply voltage is greater than the bias voltage.

8. The readout amplifier circuit according to claim 7, wherein, The gate of the first control transistor is configured to selectively receive the bias voltage and the second power supply voltage.

9. The readout amplifier circuit according to claim 8, wherein: The first inverter is electrically connected between a first voltage line configured to transmit a third voltage and a second voltage line configured to transmit the first voltage. The second inverter is electrically connected between the first voltage line and the second voltage line, and The third voltage is greater than the first voltage and less than the second voltage.

10. The readout amplifier circuit according to claim 9, wherein: During the first time period, the first voltage is applied to the second node and the second power supply voltage is applied to the gate of the first control transistor, such that the first voltage is applied from the second node to the first bit line. During the second time period following the first time period, the second voltage is applied to the second node and the bias voltage is applied to the gate of the first control transistor, such that the second voltage is applied from the second node to the first bit line. During a third time period following the second time period, the bit line transistor is configured to be off. During a fourth time period following the third time period, the bit line transistor is configured to be turned on and the third precharge transistor is configured to be turned off. During the fifth time period following the fourth time period, the first voltage line transmitting the third voltage and the second voltage line transmitting the first voltage are configured to be on, and During a sixth time period following the fifth time period, the second power supply voltage is applied to the gate of the first control transistor, and the first precharge transistor is configured to be turned on.

11. The readout amplifier circuit according to claim 10, wherein, During the second time period, the complementary bit line transistor and the first precharge transistor are configured to be off, and the bit line transistor is configured to be on.

12. The readout amplifier circuit according to claim 10, wherein: During the second time period, the third pre-charge transistor is configured to be off, and During the third time period, the third precharge transistor is configured to be turned on.

13. A sense amplifier circuit, the sense amplifier circuit comprising: Storage unit; Bit lines, which are electrically connected to the memory cells; First node; Second node; Bit line transistor, the bit line transistor being electrically connected between the bit line and the first node; A first control transistor is electrically connected between the first node and the second node; A first inverter, the first inverter including an input terminal electrically connected to the second node; The second inverter includes an output terminal electrically connected to the output node; as well as A first precharge transistor is electrically connected between the second node and the output node. The readout amplifier circuit is configured as follows: During the first time period, when the first control transistor is turned on, a first voltage is transferred to the bit line, the first node, and the second node. During the second time period following the first time period, when the first pre-charge transistor is turned off, a second voltage greater than the first voltage is transferred to the second node. During a third time period following the second time period, a charge-sharing operation is performed between the capacitive component of the bit line and the memory cell, wherein the bit line transistor is configured to be turned off during the third time period, and During a fourth time period following the third time period, charge is transferred from the bit line to the second node, wherein the bit line transistor is configured to be turned on during the fourth time period. During a fifth time period following the fourth time period, the first and second voltage lines electrically connected to each of the first and second inverters are configured to be on, and During a sixth time period following the fifth time period, the first control transistor is configured to be turned on, and the first precharge transistor is configured to be turned on.

14. The readout amplifier circuit according to claim 13, wherein, During the second time period, the first control transistor is configured to be turned on, and the bit line transistor is configured to be turned on.

15. The readout amplifier circuit according to claim 13, wherein, During the third time period: The storage unit is configured to store data with a logical value of 1, and The charge-sharing operation includes transferring charge from the capacitive component of the bit line to the memory cell.

16. The readout amplifier circuit according to claim 13, wherein, During the third time period: The storage unit is configured to store data with a logic value of 0, and The charge-sharing operation includes transferring charge from the storage cell to the capacitive component of the bit line.

17. The readout amplifier circuit according to claim 13, wherein, The channel length of the first control transistor is greater than the channel length of the bit line transistor, and the channel width of the first control transistor is greater than the channel width of the bit line transistor.

18. A sensing method for a memory device, the method comprising: The bit line and the first node electrically connected to the bit line are pre-charged using a first voltage; Store the offset information of the transistors electrically connected between the first node and the second node; The second node is precharged with a second voltage greater than the first voltage and the charge is shared between the storage cell and the bit line; Transfer the charge from the bit line to the second node; as well as The data of the storage cell is sensed based on the voltage at the second node.

19. The sensing method according to claim 18, wherein, The first voltage is the ground voltage.

20. The sensing method according to claim 18, wherein, Sharing the charge between the storage cell and the bit line includes disconnecting the bit line from the first node resistor.

Images