Memory device and internal voltage measuring method thereof

Abstract

The invention provides a memory device and an internal voltage measuring method thereof. The master memory chip is coupled to the output pad of the slave memory chip. When one of the switching circuit of the master memory chip and the switching circuit of the slave memory chip is switched on, the other one of the switching circuit of the master memory chip and the switching circuit of the slave memory chip is switched off.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a memory device and a method for measuring its internal voltage. Background Technology

[0002] Current dynamic random access memory (DRAM) chips have limited area, so multiple DRAM chips must be coupled and stacked using through-silicon vias (TSVs) to increase capacity. However, stacking chips makes it difficult to measure the internal voltage of some chips, thus hindering chip testing. Summary of the Invention

[0003] This invention provides a memory device and a method for measuring its internal voltage, which can measure the internal voltage of stacked chips, improving the convenience of chip testing.

[0004] The memory device of the present invention includes a master memory chip and at least one slave memory chip. The master memory chip includes a first control circuit, a first output pad, and a first switching circuit. The first switching circuit is coupled between a first internal voltage output terminal of the master memory chip and the first output pad. The first control circuit controls the first switching circuit, and the first internal voltage output terminal is used to output a first internal voltage. The master memory chip and the slave memory chips are stacked on top of each other. Each slave memory chip includes a second control circuit, a second output pad, and a second switching circuit. The second output pad is coupled to the first output pad. The second switching circuit is coupled between a second internal voltage output terminal of the memory chip and the second output pad. The second internal voltage output terminal is used to output a second internal voltage. The second control circuit controls the second switching circuit; when one of the first and second switching circuits is turned on, the other of the first and second switching circuits is turned off.

[0005] In one embodiment of the present invention, the memory device includes a plurality of slave memory chips. When a plurality of second switching circuits of the plurality of slave memory chips are turned on with one of the first switching circuits of the master memory chip, the plurality of second switching circuits are turned off with the remaining switching circuits of the first switching circuit of the master memory chip.

[0006] In one embodiment of the present invention, the main memory chip further includes a first internal voltage output circuit, and the secondary memory chip further includes a second internal voltage output circuit. The first internal voltage output circuit is coupled to a first switching circuit and provides a first internal voltage. The second internal voltage output circuit is coupled to a second switching circuit and provides a second internal voltage.

[0007] In one embodiment of the present invention, the first internal voltage output circuit and the second internal voltage output circuit respectively include a plurality of selection transistors and an output transistor. The conduction state of each selection transistor is controlled by a corresponding selection signal. Each selection transistor is coupled between a corresponding internal voltage and an output transistor, and the output transistor is also coupled to the first internal voltage output terminal or the second internal voltage output terminal. The conduction state of the output transistor is controlled by an output control signal.

[0008] In one embodiment of the present invention, the above-mentioned memory chip outputs a second internal voltage through a first output pad.

[0009] In one embodiment of the present invention, the first output pad and the second output pad are coupled to each other through silicon vias.

[0010] In one embodiment of the present invention, the first control circuit and the second control circuit respectively include a first AND gate, a first NOT gate, a second NOT gate, a second AND gate, and an OR gate. The first input terminal and the second input terminal of the first AND gate respectively receive a first control signal and a second control signal. The input terminal of the first NOT gate is coupled to the first input terminal of the first AND gate. The input terminal of the second NOT gate is coupled to the second input terminal of the first AND gate. The first input terminal and the second input terminal of the second AND gate are respectively coupled to the output terminals of the first NOT gate and the second NOT gate. The first input terminal and the second input terminal of the OR gate are respectively coupled to the output terminals of the first NOT gate and the second NOT gate, and the output terminal of the OR gate is coupled to a first switching circuit or a second switching circuit.

[0011] The present invention also provides a method for measuring the internal voltage of a memory device. The memory device includes a master memory chip and at least one slave memory chip. The master memory chip includes a first output pad, and each slave memory chip includes a second output pad. The method for measuring the internal voltage of the memory device includes the following steps: A first internal voltage of the master memory chip is provided from the first output pad by controlling a first switching circuit. A second internal voltage of the slave memory chip is provided from the second output pad by controlling a second switching circuit, wherein the master memory chip and the slave memory chips are stacked on top of each other, and the first output pad is coupled to the second output pad. When measuring the second internal voltage of the slave memory chip, the first switching circuit is disconnected and the second switching circuit is turned on. When measuring the first internal voltage of the master memory chip, the second switching circuit is disconnected and the first switching circuit is turned on.

[0012] In one embodiment of the present invention, the above-mentioned memory chip outputs a second internal voltage through a first output pad.

[0013] In one embodiment of the present invention, the first output pad and the second output pad are coupled to each other through silicon vias.

[0014] Based on the above, embodiments of the present invention couple the output pads of the main memory chip and the slave memory chip, and control the conduction state of the switching circuits of the output pads and internal voltage output terminals of the main memory chip and the slave memory chip. When one of the switching circuits of the main memory chip and the slave memory chip is on, the other of the switching circuits of the main memory chip and the slave memory chip is off, so that the internal voltage of the main memory chip or the slave memory chip is output from the output pad of the main memory chip. In this way, the internal voltage of each stacked chip can be measured, improving the convenience of chip testing.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of an internal voltage output circuit according to an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of a control circuit according to an embodiment of the present invention;

[0019] Figure 4 This is a flowchart of an internal voltage measurement method for a memory device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the contents of this invention more readily apparent, the following specific embodiments are provided as examples on which this invention can indeed be practiced. Furthermore, wherever possible, components / members referred to by the same reference numerals in the drawings and embodiments represent the same or similar parts.

[0021] Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention. Please refer to... Figure 1The memory device 100 includes a main memory chip 101-1 and a slave memory chip 101-2, which are stacked on top of each other. The main memory chip 101-1 includes a control circuit 102-1, a switching circuit 104-1, an internal voltage output circuit 106-1, and an output pad P1. The switching circuit 104-1 is coupled between the output terminal (internal voltage output terminal) of the internal voltage output circuit 106-1 and the output pad P1. The control terminal of the switching circuit 104-1 is coupled to the control circuit 102-1. Similarly, the slave memory chip 101-2 includes a control circuit 102-2, a switching circuit 104-2, an internal voltage output circuit 106-2, and an output pad P2. The switching circuit 104-2 is coupled between the output terminal of the internal voltage output circuit 106-2 and the output pad P2. The control terminal of the switching circuit 104-2 is coupled to the control circuit 102-2. Furthermore, output pad P1 is coupled to output pad P2. More specifically, output pad P1 can be coupled to output pad P2, for example, via a through-silicon via (TSV1). The main memory chip 101-1 and the slave memory chip 101-2 can be, for example, dynamic random access memory chips, but are not limited thereto. In this embodiment, switching circuits 104-1 and 104-2 are implemented using transistors M1 and M2, respectively; however, this is not the case in other embodiments.

[0022] Internal voltage output circuits 106-1 and 106-2 are used to output the internal voltages of the main memory chip 101-1 and the slave memory chip 101-2, respectively. The implementation of internal voltage output circuits 106-1 and 106-2 can be, for example... Figure 2 As shown, the circuit includes multiple selection transistors MN1~MNn and an output transistor MNout, where n is a positive integer. One end of the selection transistors MN1~MNn is coupled to the corresponding internal voltages V1~Vn, and the other end of the selection transistors MN1~MNn is coupled to one end of the output transistor MNout. The selection transistors MN1~MNn are controlled by the corresponding selection signals TM1~TMn. The other end of the output transistor MNout is coupled to switching circuit 104-1 or 104-2. That is, if the output transistor MNout belongs to the internal voltage output circuit 106-1, then the other end of the output transistor MNout is coupled to switching circuit 104-1; and if the output transistor MNout belongs to the internal voltage output circuit 106-2, then the other end of the output transistor MNout is coupled to switching circuit 104-2. The output transistor MNout is controlled by the output control signal En. The selection signals TM1~TMn are used to select the internal voltages V1~Vn to be output, and the output control signal En is used to determine whether the internal voltage output circuits 106-1 and 106-2 output the selected internal voltage.

[0023] Control circuits 102-1 and 102-2 can control the conduction state of switch circuits 104-1 and 104-2, wherein when one of switch circuits 104-1 and 104-2 is on, the other of switch circuits 104-1 and 104-2 is off. The implementation of control circuits 102-1 and 102-2 can be, for example... Figure 3 As shown, the circuit includes AND gates AND1 and AND2, NOT gates INV1 and INV2, and OR gate OR1. The first and second inputs of AND gate AND1 receive control signals S1 and S2, respectively. The inputs of NOT gates INV1 and INV2 are coupled to the first and second inputs of AND gate AND1, respectively. The outputs of NOT gates INV1 and INV2 are coupled to the first and second inputs of AND gate AND1, respectively. The first and second inputs of OR gate OR1 are coupled to the outputs of AND gates AND1 and AND2, respectively. The output of OR gate OR1 is coupled to the control terminal of switch circuit 104-1 or 104-2. That is, if OR gate OR1 belongs to control circuit 102-1, the output of OR gate OR1 is coupled to the control terminal of switch circuit 104-1, and if OR gate OR1 belongs to control circuit 102-2, the output of OR gate OR1 is coupled to the control terminal of switch circuit 104-2.

[0024] In control circuit 102-1, control signal S1 is set to a low voltage level, while in control circuit 102-2, control signal S1 is set to a high voltage level. When switching circuit 104-1 is turned on and switching circuit 104-2 is turned off, switching circuit 104-1 can be turned on and switching circuit 104-2 can be turned off by setting control signal S2 in control circuits 102-1 and 102-2 to a low voltage level, so that the internal voltage provided by internal voltage output circuit 106-1 can be output from output pad P1 through switching circuit 104-1. When switching circuit 104-1 is turned off and switching circuit 104-2 is turned on, switching circuit 104-1 can be turned off and switching circuit 104-2 can be turned on by setting control signal S2 in control circuits 102-1 and 102-2 to a high voltage level, so that the internal voltage provided by internal voltage output circuit 106-2 can be output from output pad P1 through switching circuit 104-2 and output pad P2.

[0025] The internal voltage provided by the internal voltage output circuit 106-1 of the main memory chip 101-1 and the internal voltage provided by the internal voltage output circuit 106-2 of the slave memory chip 101-2 can both be output through the output pad P1 of the main memory chip 101-1, thereby enabling the measurement of the internal voltage of the stacked main memory chip 101-1 and slave memory chip 101-2, improving the convenience of chip testing.

[0026] It is worth noting that the above embodiment is illustrated using one main memory chip and one slave memory chip as an example. However, in other embodiments, the memory device 100 may include more slave memory chips stacked with the main memory chip, with the output pads of the multiple slave memory chips coupled to the output pads of the main memory chip. Similar to the above embodiment, when the switching circuits of the multiple slave memory chips are turned on by one of the switching circuits of the main memory chip, the switching circuits of the multiple slave memory chips are turned off by the remaining switching circuits of the main memory chip. In this way, the internal voltage of each slave memory chip can also be output from the output pad of the main memory chip as in the above embodiment.

[0027] Figure 4 This is a flowchart of a method for measuring the internal voltage of a memory device according to an embodiment of the present invention. The memory device includes a master memory chip and at least one slave memory chip, which are stacked on top of each other. The master memory chip includes a first output pad, and each slave memory chip includes a second output pad. The first output pad and the second output pad are coupled to each other, for example, through silicon vias. The method for measuring the internal voltage of the memory device may include at least the following steps: A first internal voltage of the master memory chip is provided from the first output pad by controlling a first switching circuit (step S402), and a second internal voltage of the slave memory chip is provided from the second output pad by controlling a second switching circuit (step S404). When measuring the first internal voltage, the second switching circuit can be turned off and the first switching circuit can be turned on (step S406) to output the first internal voltage on the first output pad. When measuring the second internal voltage, the first switching circuit can be turned off and the second switching circuit can be turned on (step S408) to output the second internal voltage of the slave memory chip on the first output pad.

[0028] In summary, the embodiments of the present invention couple the output pads of the main memory chip and the slave memory chip, and control the conduction state of the switching circuits of the output pads and internal voltage output terminals of the main memory chip and the slave memory chip. When one of the switching circuits of the main memory chip and the slave memory chip is on, the other of the switching circuits of the main memory chip and the slave memory chip is off, so that the internal voltage of the main memory chip or the slave memory chip is output from the output pad of the main memory chip. In this way, the internal voltage of each stacked chip can be measured, improving the convenience of chip testing.

[0029] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A memory device, characterized in that, include: Main memory chips, including: First control circuit; First output pad; and A first switching circuit is coupled between the first internal voltage output terminal of the main memory chip and the first output pad. A first control circuit controls the first switching circuit, and the first internal voltage output terminal is used to output the first internal voltage. At least one slave memory chip, wherein the master memory chip and the slave memory chips are stacked on top of each other, and each slave memory chip includes: Second control circuit; The second output pad is coupled to the first output pad; and The second switching circuit is coupled between the second internal voltage output terminal of the memory chip and the second output pad. The second internal voltage output terminal is used to output the second internal voltage. The second control circuit controls the second switching circuit. When one of the first switching circuit and the second switching circuit is turned on, the other of the first switching circuit and the second switching circuit is turned off.

2. The memory device according to claim 1, characterized in that, The memory device includes a plurality of slave memory chips. When a plurality of second switching circuits of the plurality of slave memory chips are turned on with one of the first switching circuits of the master memory chip, the plurality of second switching circuits are turned off with the remaining switching circuits of the first switching circuit of the master memory chip.

3. The memory device according to claim 1, characterized in that, The main memory chip further includes a first internal voltage output circuit, and the slave memory chip further includes a second internal voltage output circuit. The first internal voltage output circuit is coupled to the first switching circuit to provide the first internal voltage, and the second internal voltage output circuit is coupled to the second switching circuit to provide the second internal voltage.

4. The memory device according to claim 3, characterized in that, The first internal voltage output circuit and the second internal voltage output circuit each include: Multiple selection transistors, each with its on-state controlled by a corresponding selection signal; and The output transistor has a selection transistor that is coupled between the corresponding internal voltage and the output transistor. The output transistor is also coupled to the first internal voltage output terminal or the second internal voltage output terminal. The conduction state of the output transistor is controlled by the output control signal.

5. The memory device according to claim 1, characterized in that, The second internal voltage is output from the memory chip through the first output pad.

6. The memory device according to claim 1, characterized in that, The first output pad and the second output pad are coupled to each other through silicon vias.

7. The memory device according to claim 1, characterized in that, The first control circuit and the second control circuit each include: The first AND gate receives a first control signal and a second control signal at its first input terminal and a second input terminal, respectively. The first NOT gate has its input terminal coupled to the first input terminal of the first AND gate; The second NOT gate has its input terminal coupled to the second input terminal of the first AND gate; The second AND gate has its first and second input terminals coupled to the output terminals of the first and second NOT gates, respectively; and The OR gate has its first input terminal and second input terminal coupled to the output terminals of the first NOT gate and the second NOT gate, respectively, and the output terminal of the OR gate is coupled to the first switching circuit or the second switching circuit.

8. A method for measuring the internal voltage of a memory device, characterized in that, The memory device includes a main memory chip and at least one slave memory chip. The main memory chip includes a first output pad, and each slave memory chip includes a second output pad. The internal voltage measurement method of the memory device includes: By controlling the first switching circuit, a first internal voltage of the main memory chip is provided from the first output pad; By controlling the second switching circuit, a second internal voltage of the slave memory chip is provided from the second output pad, wherein the master memory chip and the slave memory chip are stacked on top of each other, and the first output pad is coupled to the second output pad; When measuring the second internal voltage from the memory chip, the first switching circuit is disconnected and the second switching circuit is turned on; and When measuring the first internal voltage of the main memory chip, the second switching circuit is disconnected and the first switching circuit is turned on.

9. The method for measuring the internal voltage of a memory device according to claim 8, characterized in that, The second internal voltage is output from the memory chip through the first output pad.

10. The method for measuring the internal voltage of a memory device according to claim 8, characterized in that, The first output pad and the second output pad are coupled to each other through silicon vias.

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