Memory, operation method of memory and memory system

Abstract

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory includes a memory array and a peripheral circuit including a page buffer coupled to the memory array through a bit line. The page buffer includes a sensing node, a first latch circuit, and a charge / discharge circuit. Wherein the first latch circuit is coupled to the sensing node, and the first latch circuit is configured to latch state information of memory cells in the memory array. The charging and discharging circuit is coupled with the bit line, and the charging and discharging circuit is also coupled with the first latch circuit; the charge and discharge circuit is configured to apply a bit line voltage to the bit line during a verification phase of the program operation, the bit line voltage being related to the state information. According to the embodiment of the invention, under the same verification voltage, verification of at least two adjacent programming states can be realized only through one sensing development duration, so that the time spent in a verification stage is reduced, and the programming speed is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip technology, and in particular relates to a memory, a memory operation method and a memory system. Background Technology

[0002] Flash memory is a type of storage device characterized by non-volatility, fast read / write speeds, low power consumption, and long lifespan. It is widely used in various electronic products, such as mobile phones, computers, smart sensors, and positioning devices. As consumers demand higher performance and reliability from electronic products, the market is placing greater demands on flash memory's read speed, write (or programming) speed, and lifespan. Summary of the Invention

[0003] In a first aspect, this application provides a memory. The memory includes a memory array and peripheral circuitry. The peripheral circuitry includes a page buffer, which is coupled to the memory array via bit lines. The page buffer includes a sensing node, a first latch circuit, and a charging / discharging circuit. The first latch circuit is coupled to the sensing node and configured to latch state information of memory cells in the memory array. The charging / discharging circuit is coupled to the bit lines and also to the first latch circuit; the charging / discharging circuit is configured to apply a bit line voltage to the bit lines during the verification phase of a programming operation, the bit line voltage being correlated with the state information.

[0004] In some possible implementations, the status information includes first information and second information, where the first information indicates that the target threshold voltage distribution range of the memory cell is a first interval, and the second information indicates that the target threshold voltage distribution range of the memory cell is a second interval, wherein the first interval and the second interval are adjacent. The charging / discharging circuit is configured to: during the verification phase of the programming operation, in response to the first information, apply a first voltage to the bit line; or, in response to the second information, apply a second voltage to the bit line. Wherein, the first voltage is less than the second voltage.

[0005] In some possible implementations, the charging and discharging circuit includes a first discharging circuit and a second discharging circuit. The first terminal of the first discharging circuit is coupled to a sensing node, and the second terminal of the first discharging circuit is coupled to a bit line. The sensing node is also coupled to a charging circuit for inputting the supply voltage. The first terminal of the second discharging circuit is coupled to the sensing node, the second terminal of the second discharging circuit is coupled to the bit line, and the control terminal of the second discharging circuit is coupled to a first latch circuit.

[0006] In some possible implementations, the first discharge circuit is configured to apply a first voltage to the bit line during the verification phase.

[0007] In some possible implementations, the second discharge circuit is configured to: disconnect the electrical connection from the bit line in response to the first information during the verification phase; or, apply a second voltage to the bit line in response to the second information.

[0008] In some possible implementations, the first discharge circuit includes a first transistor, a first terminal of which is coupled to a sensing node, and a second terminal of which is coupled to a bit line. During the verification phase, the control terminal of the first transistor is used to receive a first control voltage that controls the first transistor to turn on.

[0009] In some possible implementations, the second discharge circuit includes a second transistor and a third transistor. A first terminal of the second transistor is coupled to a sensing node, a second terminal of the second transistor is coupled to the first terminal of the third transistor, and a second terminal of the third transistor is coupled to a bit line. The control terminal of the second transistor is coupled to a first latch circuit. In response to a first message, the second transistor is turned off; in response to a second message, the second transistor is turned on. During the verification phase, the control terminal of the third transistor is used to receive a second control voltage that controls the third transistor to turn on, the second control voltage being greater than the first control voltage.

[0010] In some possible implementations, the page buffer also includes a charge pump circuit coupled to the sensing node.

[0011] In some possible implementations, during the verification phase, the charge pump circuit is configured to pump up the voltage of the sensing node during the discharge phase of the sensing node.

[0012] In some possible implementations, the charge pump circuit includes a capacitor, with a first end of the capacitor coupled to a sensing node; and a second end of the capacitor used as an input pump boost voltage during the discharge phase of the sensing node.

[0013] Secondly, this application provides a method for operating a memory. The memory includes memory cells, and the method includes: latching state information of the memory cells. During a verification phase of programming operations on the memory cells, a bit line voltage is applied to a bit line coupled to the memory cell. The bit line voltage is related to the state information.

[0014] In some possible implementations, the status information includes first information and second information, and the operation method includes: during the verification phase, in response to the first information, applying a first voltage to the bit line, wherein the first information indicates that the target threshold voltage distribution range of the memory cell is a first range; or, in response to the second information, applying a second voltage to the bit line, wherein the second information indicates that the target threshold voltage distribution range of the memory cell is a second range, wherein the first range and the second range are adjacent. Wherein, the first voltage is less than the second voltage.

[0015] In some possible implementations, the operation method specifically includes: during the verification phase, a first discharge circuit in the page buffer applies a first voltage to the bit line. During the verification phase, in response to first information, a second discharge circuit in the page buffer disconnects from the bit line; or, in response to second information, the second discharge circuit applies a second voltage to the bit line.

[0016] In some possible implementations, the first discharge circuit in the page buffer applies a first voltage to the bit line, including: during the verification phase, applying a first control voltage to the control terminal of the first transistor in the first discharge circuit to control the first transistor to turn on.

[0017] In some possible implementations, in response to the first information, the second discharge circuit in the page buffer is electrically disconnected from the bit line; in response to the second information, the second discharge circuit applies a second voltage to the bit line, including: during the verification phase, applying a second control voltage to the control terminal of the third transistor in the second discharge circuit to control the third transistor to turn on. Wherein, the second control voltage is greater than the first control voltage, the second transistor in the second discharge circuit turns off in response to the first information, and the second transistor turns on in response to the second information.

[0018] In some possible implementations, the voltage of the sensing node is also pumped up by a charge pump circuit coupled to the sensing node in the page buffer during the sensing development phase of the verification phase.

[0019] In some possible implementations, the sensing node in the page buffer is coupled to the charge pump circuit to pump up the voltage of the sensing node, specifically including: during the sensing development phase, applying a pump-up voltage to the second terminal of a capacitor in the charge pump circuit, the first terminal of which is coupled to the sensing node.

[0020] Thirdly, this application provides a page buffer. The page buffer includes a sensing node, a first latch circuit, a first transistor, a second transistor, and a third transistor. The first latch circuit is coupled to the sensing node. A first terminal of the first transistor is coupled to the sensing node, and a second terminal of the first transistor is used for coupling to a bit line of the memory. A first terminal of the second transistor is coupled to the sensing node, and a second terminal of the second transistor is coupled to the first terminal of the third transistor. The second terminal of the third transistor is used for coupling to a bit line. The control terminal of the second transistor is coupled to the first latch circuit.

[0021] In some possible implementations, the page buffer also includes a capacitor, with a first end of the capacitor coupled to the sensing node and a second end of the capacitor used as an input pump-up voltage.

[0022] Fourthly, this application provides a memory system. The memory system includes a memory controller and the memory of any one of the first aspects described above, the memory controller being coupled to the memory and configured to control the memory. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0024] Figure 1 This is a schematic diagram of the memory structure provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of a storage block provided in an embodiment of this application;

[0026] Figure 3 A partial cross-sectional schematic diagram of the storage string provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram of threshold voltage distribution in various storage modes of the storage unit provided in the embodiments of this application;

[0028] Figure 5 This is a schematic diagram of the memory and peripheral circuitry provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram of the structure of the page buffer provided in the embodiments of this application;

[0030] Figure 7 This is a schematic diagram of the voltage waveform of the sensing node during the verification stage, provided in an embodiment of this application.

[0031] Figure 8 A flowchart illustrating the operation method of the memory provided in an embodiment of this application;

[0032] Figure 9 A schematic diagram of a voltage waveform applied to a word line by a peripheral circuit provided in an embodiment of this application;

[0033] Figure 10 This is a schematic diagram of the memory system provided in an embodiment of this application.

[0034] Reference numerals: 100, Memory; 110, Memory array; 120, Peripheral circuit; 121, Control logic circuit; 122, I / O interface; 123, Voltage generator; 124, Column decoder; 125, Row decoder; 126, Page buffer; 127, Data bus; 128, Register; 200, Memory block; 210, Memory string; 211, Top select transistor; 212, Memory cell; 213, Bottom select transistor; 310, Semiconductor layer; 320, Stacked structure; 321, Gate conductive layer; 322, Dielectric layer; 410, Bit line; 420, Source line; 4 30. Top Select Line; 440. Word Line; 450. Bottom Select Line; 500. First Latch Circuit; 510. First Inverter; 520. Second Inverter; 530. Set Transistor; 540. Reset Transistor; 550. Pull-down Transistor; 600. Charge / Discharge Circuit; 610. First Transistor; 620. Second Transistor; 630. Third Transistor; 640. Fourth Transistor; 650. Fifth Transistor; 660. Sixth Transistor; 670. Seventh Transistor; 680. Connecting Transistor; 700. Charge Pump Circuit; 800. Memory System; 900. Memory Controller. Detailed Implementation

[0035] The following will combine Figures 1-10 The technical solutions in some embodiments of this application are clearly and completely described. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0036] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0037] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0038] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0039] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0040] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this application is shown. For example... Figure 1 As shown, the memory 100 may include a memory array 110 and peripheral circuits 120, with the memory array 110 coupled to the peripheral circuits 120. In some embodiments, the peripheral circuits 120 and the memory array 110 may be independently formed on two separate wafers using different semiconductor manufacturing processes. In some examples, the memory array 110 may be formed using mature process technologies (e.g., any process technology of 22nm, 28nm, and above) to ensure the stability of stored data. The peripheral circuits 120 may be formed using advanced process technologies (e.g., any process technology of 14nm, 10nm, and below) to help improve the speed of data reading / writing in the memory 100. The wafer on which the memory array 110 is formed (which may be called an array wafer) and the wafer on which the peripheral circuits 120 are formed (which may be called a CMOS wafer) are then bonded together using a bonding process, thereby coupling the peripheral circuits 120 to the memory array 110.

[0041] Storage array 110 may include memory blocks 200. For example... Figure 2As shown, in some embodiments, the memory block 200 may include multiple memory strings 210, one end of which is coupled to a bitline (BL) 410, and the other end of which is coupled to a source line (SL) 420. Each memory string 210 may include a top select transistor (TST) 211, multiple memory cells 212, and a bottom select transistor (BST) 213 stacked in series. In some embodiments, the memory cell 212 may be a floating gate transistor or a charge trap field-effect transistor, etc.

[0042] Figure 3 A partial cross-sectional schematic diagram of a possible memory string is shown. The memory string 210 may extend vertically above the semiconductor layer 310. The semiconductor layer 310 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0043] The memory string 210 may include a channel structure extending through the stacked structure 320, which may include alternating gate conductive layers 321 and dielectric layers 322. The number of gate conductive layers 321 and dielectric layers 322 in the stacked structure 320 is related to the number of memory cells 212 in the memory string 210.

[0044] The gate conductive layer 321 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 321 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 321 includes a doped polysilicon layer. Each gate conductive layer 321 may include a control gate surrounding the memory cell 212, and the gate conductive layer 321 at the top of the stacked structure 320 may extend laterally and be coupled to the top select line (TSL), the gate conductive layer 321 at the bottom of the stacked structure 320 may extend laterally and be coupled to the bottom select line (BSL), or the gate conductive layer 321 between the top select line and the bottom select line may extend laterally and be coupled to the word line (WL).

[0045] It should be understood that, despite Figure 3Additional components, not shown, can form the memory string 210. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0046] Please continue to refer to Figure 2 Multiple memory strings 210 can be arranged in a row along a first direction, and multiple rows of memory strings 210 can be arranged in a memory block 200 along a second direction perpendicular to the first direction. In some embodiments, in the same row of memory strings 210, the gate of the top select transistor 211 of each memory string 210 can be coupled to the same top select line 430; in some embodiments, the gates of the top select transistors 211 of some rows of memory strings 210 can be coupled to the same top select line 430; memory strings 210 whose gates of the top select transistors 211 are coupled to the same top select line 430 can constitute a memory chip. The gate of the bottom select transistor 213 in each memory string 210 can be coupled to the same bottom select line 450. In some embodiments, the selected memory string 210 can be activated during read operations, programming operations, and erase operations via the top select line 430 and the bottom select line 450.

[0047] Each memory string 210 is coupled to the peripheral circuit 120 via a corresponding bit line 410. For example, the drain of the top selection transistor 211 in the memory string 210 is coupled to the bit line 410. In order to reduce the number of bit lines 410, the memory string 210 in any memory chip can be coupled to the same bit line 410 with the corresponding memory string 210 in other memory chips.

[0048] For multiple memory strings 210 in memory block 200, the control gate of memory cell 212 in any memory string 210 and the control gate of memory cell 212 at the corresponding position in other memory strings 210 can be coupled to the same word line 440. The source of the bottom select transistor 213 in memory string 210 can be coupled to the source line 420 (or, common source line (CSL)).

[0049] It should be noted that the accompanying drawings of this application only exemplarily illustrate the structure of the storage block 200 in some embodiments, but in practice, the structure of the storage block 200 may also be in other ways.

[0050] like Figure 4As shown, the storage mode of storage cell 212 can include single-level cell (SLC) and multi-level cell (MLC). Storage cell 212 using the single-level cell mode can store one bit (i.e., 1 bit) and can have two states: an erase (E) state and a program (P) state. Storage cell 212 using the multi-level cell mode can store two bits (i.e., 2 bits) or more and can have four or more states. In some examples, storage cell 212 can adopt a two-level cell storage mode, with each storage cell 212 storing two bits and having four states: three program states (e.g., ...). Figure 4 (P1, P2, and P3 states) and an erase state (e.g., ... Figure 4 (E state). In some examples, memory cell 212 can also adopt a triple-level cell (TLC) storage mode, where each memory cell 212 can store three bits and has eight states; that is, seven programmable states (e.g., E state). Figure 4 (including states P1, P2, P3, P4, P5, P6, and P7) and an erase state (e.g., ...). Figure 4 (E state). In some implementations, each state of the storage unit 212 has a corresponding threshold voltage distribution range.

[0051] Peripheral circuitry 120 is used to control the memory array 110. In some embodiments, peripheral circuitry 120 is configured to perform programming, erasing, and reading operations on the memory cells 212 in the memory array 110. In some examples, peripheral circuitry 120 can program the memory cells 212 to store charge and erase or neutralize the stored charge in the memory cells 212. The electric field generated by the charge can affect the threshold voltage (Vt) of the memory cells 212. Generally, the more charge stored in the memory cells 212, the higher the threshold voltage of the memory cells 212. That is, peripheral circuitry 120 can control the amount of charge stored in the memory cells 212 in the memory array 110 through programming and erasing operations, thereby enabling the memory cells 212 to achieve a desired threshold voltage distribution range.

[0052] In some implementations, the programming operation may include multiple programming cycles, each programming cycle including a programming phase and a verification phase, with the verification phase following the programming phase within the same programming cycle. During the verification phase, the peripheral circuit 120 verifies one or more program levels. For example, as shown in Table 1 below, taking TLC mode as an example, in the verification phase of the first two programming cycles, the peripheral circuit 120 may only verify the P1 state of the program level. In the verification phase of the third and fourth programming cycles, the peripheral circuit 120 may verify both the P1 and P2 states of the program level. In the verification phase of the fifth programming cycle, the peripheral circuit 120 may verify the P1, P2, and P3 states of the program level. In the verification phase of the sixth and seventh programming cycles, the peripheral circuit 120 may verify the P2, P3, and P4 states of the program level. The verification strategies for subsequent programming cycles are detailed in Table 1 and will not be repeated here. It should be understood that the verification strategy is related to the programming voltage and the characteristics of the memory cell. In terms of verification strategies, there will be differences between memory cells in different memories, or between memory cells in the same memory that are coupled to different word lines.

[0053] Table 1

[0054]

[0055] In some implementations, the peripheral circuit 120 employs target-only verification, applying different verification voltages Vvfy to the word line 440 to verify different programming states, performing verification on only one programming state at a time. For example, the peripheral circuit 120 may apply a first verification voltage Vvfy1 to the word line 440 during the verification phase, verifying the P1 state after a sensing development period. Alternatively, the peripheral circuit 120 may apply a second verification voltage Vvfy2, greater than the first verification voltage Vvfy1, to the word line 440 during the verification phase, verifying the P2 state after a sensing development period.

[0056] As mentioned above, the programming operation involves multiple programming cycles, and the verification phase within each programming cycle requires verification of one or more programming states. However, single-target verification requires at least one sensing development time to verify each programming state, resulting in a significant time commitment for the verification phase and a longer overall programming operation time.

[0057] In this embodiment, the peripheral circuit applies different bit line voltages to the corresponding bit line 410 during the verification phase based on the state information of the storage cell 212, so as to equivalently replace the offset of the verification voltage. Thus, under the same verification voltage, verification of at least two adjacent programming states can be achieved after only one sensing development time, which reduces the time required for the verification phase, thereby shortening the time required for programming operations and improving programming speed.

[0058] like Figure 5 As shown, in some embodiments, the peripheral circuitry 120 includes control logic circuitry 121, I / O interface 122, voltage generator 123, column decoder 124, row decoder 125, page buffer 126, data bus 127, and register 128. It should be understood that in some examples, it may also include... Figure 5 Additional circuitry not shown.

[0059] The control logic circuit 121 can be coupled to the voltage generator 123, page buffer 126, column decoder 124, row decoder 125, and I / O interface 122, and is configured to control the operation of each peripheral circuit 120. The control logic circuit 121 can generate operation signals in response to commands (CMDs) or control signals received from the I / O interface 122 to control the operation of the row decoder 125, column decoder 124, page buffer 126, and voltage generator 123; wherein the command can be a programming command, a read command, etc.

[0060] I / O interface 122 can be coupled to control logic circuitry 121 and act as a control buffer to buffer control commands received from the host and relay them to control logic circuitry 121, as well as to buffer status information received from control logic circuitry 121 and relay it to the host. I / O interface 122 can also be coupled to page buffer 126 via data bus 127 and act as data I / O interface 122 and data buffer to buffer data and relay it to or from memory array 110.

[0061] Voltage generator 123 can use external or internal power supply voltages to generate various voltages for performing operations such as erasing, programming, reading, and verifying on memory array 110; for example, the programming voltage Vpgm, the erase voltage Vera, and the ground voltage V applied to word line 440. SS And their combinations.

[0062] The column decoder 124 can be controlled by the control logic circuit 121 and select one or more memory strings 210 in the memory array 110 by applying a bit line voltage generated from the voltage generator 123.

[0063] The row decoder 125, in response to control of the control logic circuit 121, supplies the word line 440 voltage generated from the voltage generator 123 to the selected word lines and non-selected word lines of the memory array 110. As described in detail below, the row decoder 125 is configured to perform programming operations on memory cells coupled to one or more select word lines in the memory array 110.

[0064] Register 128 can be coupled to control logic circuit 121 and includes a status register, a command register and an address register for storing status information, command opcode (OP code) and command address for controlling the operation of each peripheral circuit 120.

[0065] Page buffer 126 is coupled to memory array 110 via bit line 410. In some examples, page buffer 126 can read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic circuitry 121. In other examples, page buffer 126 can store programming data to be programmed into memory array 110 (write data). In still other examples, page buffer 126 can also perform programming verification operations to ensure that data has been correctly programmed into memory cells 212 coupled to select word lines.

[0066] like Figure 6 As shown in the embodiments of this application, the page buffer 126 includes a sensing node SO, a first latch circuit 500, and a charging / discharging circuit 600. Both the first latch circuit 500 and the charging / discharging circuit 600 are coupled to the sensing node SO. In some embodiments, a capacitor C for storing charge is provided between the sensing node SO and ground GND, or between the sensing node SO and any fixed potential. SO That is, capacitor C SO One end of the capacitor C is coupled to the sensing node SO. SO The other end is grounded (or coupled to any fixed potential node). In other embodiments, a parasitic capacitance for storing charge may also be formed between the sensing node SO and ground GND, or between the sensing node SO and any fixed potential. It should be understood that "grounding" as described in the embodiments of this application can also mean being coupled to any fixed potential node.

[0067] like Figure 7As shown, the verification phase includes a charging phase and a subsequent sensing development phase (also known as a discharging phase). During the charging phase, the charging / discharging circuit 600 charges the sensing node SO; during the sensing development phase, the charging / discharging circuit 600 discharges the sensing node SO. It should be understood that the charging (or discharging) of the sensing node SO described in this application essentially refers to the charging (or discharging) of the capacitor C coupled to the sensing node SO. SO (Or parasitic capacitance) is charged (or discharged). In some examples, if the voltage V of the sensing node increases after the sensing development stage... SO If the voltage Vtrip is greater than the threshold voltage, it indicates that the discharge rate of the sensing node SO is low during the sensing development phase, the threshold voltage of the storage cell 212 is greater than the verification voltage, and the threshold voltage of the storage cell 212 reaches the target threshold voltage distribution range; that is, the storage cell 212 reaches the target programming state, and the storage cell 212 passes verification. In other examples, if after the sensing development phase, the voltage Vtrip of the sensing node... SO If the voltage is less than the threshold voltage Vtrip, it indicates that the discharge rate of the sensing node SO is relatively high during the sensing development phase, the threshold voltage of the storage cell 212 is not greater than the verification voltage, and the threshold voltage of the storage cell 212 has not reached the target threshold voltage distribution range; that is, the storage cell 212 has not reached the target programming state and the storage cell 212 has not passed the verification.

[0068] Please continue to refer to Figure 6 In some embodiments, the first latch circuit 500 includes a first inverter 510, a second inverter 520, a setting transistor 530, a reset transistor 540, and a pull-down transistor 550. The output terminal of the first inverter 510 is coupled to the input terminal of the second inverter 520, serving as the first output terminal OUT1 of the first latch circuit 500. The input terminal of the first inverter 510 is coupled to the output terminal of the second inverter 520, serving as the second output terminal OUT2 of the first latch circuit 500. The first terminal of the setting transistor 530 is coupled to the output terminal of the first inverter 510, the first terminal of the reset transistor 540 is coupled to the output terminal of the second inverter 520, the control terminal of the pull-down transistor 550 is coupled to the sensing node SO, the first terminal of the pull-down transistor 550 is coupled to the second terminals of the setting transistor 530 and the reset transistor 540, and the second terminal of the pull-down transistor 550 is grounded to GND. The control terminal of the setting transistor 530 is configured to receive a setting voltage, and the control terminal of the reset transistor 540 is configured to receive a reset voltage.

[0069] In some examples, the set transistor 530, reset transistor 540, and pull-down transistor 550 can all be N-type transistors; for example, an N-channel metal-oxide-semiconductor field-effect transistor (NMOS). When the pull-down transistor 550 is at the voltage V at the sensing node... SO When the transistor 530 is turned on under control, if the control terminal of the setting transistor 530 receives a setting voltage, the setting transistor 530 turns on, the input terminal of the second inverter 520 is grounded, and the output terminal of the second inverter 520 outputs a high level. Since the output terminal of the second inverter 520 is coupled to the input terminal of the first inverter 510, the input terminal of the first inverter 510 receives a high level, causing the output terminal of the first inverter 510 to output a low level. Again, since the output terminal of the first inverter 510 is coupled to the input terminal of the second inverter 520, the input terminal of the second inverter 520 receives a low level, thus confirming and reinforcing the high level output of the second inverter 520. This cycle repeats, ensuring that the output terminal of the first inverter 510 stably outputs a low level, and the output terminal of the second inverter 520 stably outputs a high level. Similarly, when the voltage V at the sensing node of the pull-down transistor 550... SO When the control transistor 540 is turned on, if the control terminal of the reset transistor 540 receives a reset voltage, the reset transistor 540 will turn on, the input terminal of the first inverter 510 will be grounded, so that the output terminal of the first inverter 510 will stably output a high level, and the output terminal of the second inverter 520 will stably output a low level.

[0070] The first latch circuit 500 is configured to latch the state information of the memory cell 212 in the memory array 110. In some embodiments, a high-level output from the first inverter 510 and a low-level output from the second inverter 520 can indicate that the state information latched by the first latch circuit 500 is first information, which indicates that the target programming state of the memory cell 212 is the low state among two adjacent programming states. A low-level output from the first inverter 510 and a high-level output from the second inverter 520 can indicate that the state information latched by the first latch circuit 500 is second information, which indicates that the target programming state of the memory cell 212 is the high state among two adjacent programming states. It should be understood that in other embodiments, a greater number of first latch circuits 500 can be provided in the page buffer 126 to latch third information, fourth information, and other additional state information.

[0071] The charging / discharging circuit 600 is also coupled to the first latch circuit 500. In some embodiments, the charging / discharging circuit 600 includes a first discharging circuit and a second discharging circuit. The first terminal of the first discharging circuit is coupled to the sensing node SO, and the second terminal of the first discharging circuit is coupled to the bit line 410. The first discharging circuit includes a first transistor 610, the first terminal of which is coupled to the sensing node SO via a connecting transistor 680, and the second terminal of the first transistor 610 is coupled to the bit line 410.

[0072] The first terminal of the second discharge circuit is coupled to the sensing node SO, the second terminal of the second discharge circuit is coupled to the bit line 410, and the control terminal of the second discharge circuit is also coupled to the first latch circuit 500. The second discharge circuit includes a second transistor 620 and a third transistor 630. The first terminal of the second transistor 620 is coupled to the sensing node SO via a connecting transistor 680, the second terminal of the second transistor 620 is coupled to the first terminal of the third transistor 630, the control terminal of the second transistor 620 is coupled to the output terminal of the second inverter 520 in the first latch circuit 500, and the second terminal of the third transistor 630 is coupled to the bit line 410.

[0073] In this embodiment, the first transistor 610, the second transistor 620, the third transistor 630, and the connecting transistor 680 are all NMOS transistors. The first transistor 610 and the third transistor 630 can be identical transistors, such as having the same channel length, channel width, and gate oxide thickness. In some embodiments, the control terminals of the first transistor 610 and the third transistor 630 can be coupled to the control logic circuit 121. During the verification phase, the control logic circuit 121 applies a first control voltage Vctr1 to the control terminal of the first transistor 610, thereby controlling the first transistor 610 to conduct. Simultaneously, the control logic circuit 121 also applies a second control voltage Vctr2, which is greater than the first control voltage Vctr1, to the control terminal of the third transistor 630, thereby controlling the third transistor 630 to conduct. Because the second control voltage Vctr2 is greater than the first control voltage Vctr1, the on-resistance of the third transistor 630 is less than the on-resistance of the first transistor 610, and the voltage drop across the third transistor 630 is less than the voltage drop across the first transistor 610. This ensures that the loss of the supply voltage VDD by the second discharge circuit is less than the loss of the supply voltage VDD by the first discharge circuit.

[0074] At this time, if the state information latched by the first latch circuit 500 is the first information, the output terminal of the second inverter 520 in the first latch circuit 500 outputs a low level, thereby controlling the second transistor 620 to turn off, and the second discharge circuit disconnects from the bit line 410. Only the first discharge circuit applies the first voltage V1 to the bit line 410; that is, the charging and discharging circuit 600 applies the first voltage V1 to the bit line 410. If the state information latched by the first latch circuit 500 is the second information, the output terminal of the second inverter 520 in the first latch circuit 500 outputs a high level, thereby controlling the second transistor 620 to turn on. The second discharge circuit applies the second voltage V2 to the bit line 410, and the first discharge circuit applies the first voltage V1 to the bit line 410. Since the second voltage V2 is greater than the first voltage V1, the charging and discharging circuit 600 applies the second voltage V2 to the bit line 410.

[0075] To facilitate understanding of this application, the following example illustrates the voltage application of word lines and bit lines during the verification phase. As mentioned above, during the verification phase of the 3rd-4th programming cycle, the peripheral circuit 120 needs to verify the P1 and P2 states in the programming state. In this embodiment, the P1 and P2 states are verified simultaneously by applying a second verification voltage Vvfy2 to the word line 440 during the verification phase. For the memory cell 212 that needs to be verified for the P1 state, even if the threshold voltage of the memory cell 212 reaches the threshold voltage distribution range corresponding to the P1 state, the discharge rate of the sensing node SO in the page buffer 126 during the sensing development phase is still relatively large under the second verification voltage Vvfy2, resulting in the voltage V of the sensing node after the sensing development phase being lower. SO If the voltage is below the threshold voltage Vtrip, the verification of memory cell 212 fails.

[0076] Therefore, in this embodiment, the first latch circuit 500 in the page buffer 126 latches first information to instruct the memory cell coupled to the page buffer 126 to perform P1 state verification; or, latches second information to instruct the memory cell coupled to the page buffer 126 to perform P2 verification. For the memory cell 212 performing P2 state verification, the page buffer 126 applies a normal second voltage V2 (e.g., the second voltage V2 is 0.6V) to the bit line 410 during the verification phase; for the memory cell 212 performing P1 state verification, the page buffer 126 applies a first voltage V1 (e.g., the first voltage V1 is 0.2V) to the bit line 410 during the verification phase, which is less than the second voltage V2, to weaken or even overcome the increase in the discharge rate of the sensing node SO during the sensing development phase caused by increasing the verification voltage, thereby enabling the memory cell 212 whose threshold voltage reaches the threshold voltage distribution range corresponding to the P1 state to pass the P1 state verification.

[0077] In other words, during the verification phase, the charging and discharging circuit 600 applies different bit line voltages to the bit line 410 based on the state information latched by the first latch circuit 500, which is equivalent to replacing the offset of the verification voltage. Thus, under the same verification voltage, verification of at least two adjacent programming states can be achieved after only one sensing development time, reducing the time required for the verification phase, thereby shortening the time required for programming operations and improving programming speed.

[0078] Figure 6 Other circuit structures in the charging / discharging circuit 600 are also shown; for example, a charging circuit coupled to the sensing node SO. In some embodiments, the charging circuit may include a fourth transistor 640, a fifth transistor 650, a sixth transistor 660, and a seventh transistor 670. The fourth transistor 640, fifth transistor 650, and seventh transistor 670 are NMOS transistors. The sixth transistor 660 is a P-type transistor; for example, a P-channel metal-oxide-semiconductor field-effect transistor (PMOS). The first terminal of the fourth transistor 640 is used to input the supply voltage VDD, and the second terminal of the fourth transistor 640 is coupled to the sensing node SO. The first terminal of the fifth transistor 650 is used to input the supply voltage VDD, and the second terminal of the fifth transistor 650 is coupled to the sensing node SO via a connection transistor 680. The first terminal of the sixth transistor 660 is used to input the supply voltage VDD. The second terminal of the sixth transistor 660 is coupled to the first terminal of the seventh transistor 670. The control terminal of the sixth transistor 660 is coupled to the output terminal of the first inverter 510 in the first latch circuit 500. The second terminal of the seventh transistor 670 is coupled to the sensing node SO through the connecting transistor 680.

[0079] In some implementations, due to the limitation of the supply voltage VDD, the first voltage V1 cannot be significantly lower than the second voltage V2. Therefore, the effect of verifying the voltage offset by reducing the bit line voltage (i.e., reducing it from the second voltage V2 to the first voltage V1) is limited. In some cases, for example, if the threshold voltage of the memory cell 212 is exactly to the left of the target threshold voltage distribution range, verification may still fail. Therefore, in this embodiment, the page buffer 126 further includes a charge pump circuit 700, which is coupled to the sensing node SO. The charge pump circuit 700 includes a capacitor C1, the first end of which is coupled to the sensing node; during the discharge phase of the sensing node SO, the second end of the capacitor C1 is used to input the pump boost voltage Vboost, thereby pumping up the voltage V of the sensing node. SO This allows the lower state in two adjacent programming states to be verified normally.

[0080] Because of the charge pump circuit 700, the voltage V of the sensing node is... SO In the early stages of sensing development, the voltage will be higher than the supply voltage VDD. This is to reduce the voltage VDD of the sensing node. SO Isolated from the supply voltage VDD, at least one NMOS transistor is provided among one or more transistors coupled between the sensing node SO and the supply voltage VDD node; for example, the fourth transistor 640.

[0081] Additionally, the page buffer 126 may also include circuit structures not shown, such as a sense latch circuit, a cache latch circuit, and at least one data latch circuit. The sense latch circuit, cache latch circuit, and data latch circuit are all coupled to the sense node SO. Since the embodiments of this application do not improve these structures, these structures should not be construed as limitations on this application, but rather as one implementation method. In some examples, these structures may also take other specific circuit forms.

[0082] Those skilled in the art will understand that the operations performed by the line decoder 125, page buffer 126, control logic circuit 121, and voltage generator 123 described in this application can be performed by a processing circuit. This processing circuit may include, but is not limited to, hardware of logic circuits or a hardware / software combination of a processor executing software.

[0083] This application provides a method for operating a memory, such as... Figure 8 The operation method includes steps S110-S140, as follows:

[0084] S110, The first latch circuit latches the status information of the storage unit.

[0085] In some implementations, before the verification phase, the first latch circuit 500 latches the state information of the memory cell 212 according to the programming state to which the memory cell 212 needs to be programmed. In some examples, when the verification phase of a certain programming cycle requires verification of multiple programming states, the first latch circuit 500 can latch different state information according to the target programming state to which the memory cell 212 needs to be programmed before the verification phase. This application uses the state information including first information and second information as an example for further explanation. The first information can indicate that the target programming state of the memory cell 212 is a low state among two adjacent programming states, and the second information can indicate that the target programming state of the memory cell 212 is a high state among two adjacent programming states. As described above, each state of the memory cell 212 has a one-to-one corresponding threshold voltage distribution interval. That is, the first information indicates that the target threshold voltage distribution interval of the memory cell 212 is a first interval, and the second information indicates that the target threshold voltage distribution interval of the memory cell 212 is a second interval, and the first interval and the second interval are adjacent.

[0086] In some examples, a high-level output from the first inverter 510 and a low-high-level output from the second inverter 520 indicate that the state information latched by the first latch circuit 500 is the first information. Conversely, a low-level output from the first inverter 510 and a high-level output from the second inverter 520 indicate that the state information latched by the first latch circuit 500 is the second information.

[0087] S120. During the verification phase of programming the memory cell, the charging and discharging circuit responds to the first information and applies a first voltage to the bit line.

[0088] like Figure 9 As shown, at time t1, a control voltage is applied to the control terminal of the fourth transistor 640 to control the fourth transistor 640 to conduct, thereby charging the sensing node SO. At time t2, a ground voltage V is applied to the control terminal of the fourth transistor 640. SS The four transistors are turned off, thus stopping the charging of sensing node SO, and sensing node SO begins to discharge. At time t3, a ground voltage V is applied to the control terminal connected to transistor 680. SS The control connection transistor 680 is turned off, and the sensing node SO stops discharging. The period from time t1 to time t2 can be called the charging phase of the verification phase, and the period from time t2 to time t3 can be called the sensing development phase of the verification phase.

[0089] In some implementations, during the verification phase, control logic circuit 121 applies a first control voltage Vctr1 to the control terminal of the first transistor 610 in the first discharge circuit, thereby controlling the first transistor 610 to conduct; control logic circuit 121 also applies a second control voltage Vctr2 to the control terminal of the third transistor 630 in the second discharge circuit, thereby controlling the third transistor 630 to conduct. Simultaneously, corresponding control voltages are applied to the control terminals of the fifth transistor 650, the seventh transistor 670, and the connecting transistor 680 to control the control terminals of the fifth transistor 650, the seventh transistor 670, and the connecting transistor 680 to conduct.

[0090] When the state information latched by the first latch circuit 500 is the first information, the second transistor 620 in the second discharge circuit is turned off, thereby disconnecting the second discharge circuit from the bit line 410. At this time, only the first discharge circuit applies the first voltage V1 to the bit line 410, thereby causing the page buffer 126 to apply the first voltage V1 to the bit line 410.

[0091] S130. During the verification phase of programming the memory cell, the charging and discharging circuit responds to the second information and applies a second voltage to the bit line.

[0092] When the state information latched by the first latch circuit 500 is the second information, the second transistor 620 in the second discharge circuit is turned on, thereby applying a second voltage V2 to the bit line 410 by the second discharge circuit, and the first discharge circuit applies a first voltage V1 to the bit line 410. At this time, the second discharge circuit pulls up the bit line voltage applied to the bit line 410, thereby causing the page buffer 126 to apply the second voltage V2 to the bit line 410.

[0093] It should be understood that S120 and S130 have no logical order; they can be executed simultaneously, or either one can be executed first.

[0094] In this embodiment, the second control voltage Vctr2 is greater than the first control voltage Vctr1. When the gate-source voltage Vgs of the NMOS transistor is greater than the threshold voltage of the NMOS transistor, a conductive channel is formed between the drain and source of the NMOS transistor, and the NMOS transistor is turned on. Furthermore, the greater the voltage applied to the gate (i.e., the control terminal) of the NMOS transistor, the greater the gate-source voltage Vgs, and the smaller the on-resistance of the NMOS transistor. Therefore, the on-resistance of the third transistor 630 is less than the on-resistance of the first transistor 610, and the voltage drop across the third transistor 630 is less than the voltage drop across the first transistor 610. That is, the voltage drop of the second discharge circuit on the supply voltage VDD is less than the voltage drop of the first discharge circuit on the supply voltage VDD, thereby making the second voltage V2 greater than the first voltage V1.

[0095] S140. During the sensing development phase in the verification phase, the charge pump circuit pumps up the voltage of the sensing node.

[0096] Please continue to refer to Figure 9 During the sensing development phase of the verification phase; that is, between time t2 and t3, the control logic circuit 121 can apply a boost voltage Vboost to the second terminal of capacitor C1 in the charge pump circuit 700. The first terminal of capacitor C1 is coupled to the sensing node, thereby boosting the voltage V of the sensing node. SO This allows the lower state in two adjacent programming states to be verified normally.

[0097] like Figure 10 As shown, this application provides a memory system 800, which includes a memory controller 900 and a memory controller 900. Figure 1 The memory 100 shown; wherein, the peripheral circuitry of the memory 100 includes, for example... Figure 6 Page buffer 126 is shown. Memory controller 900 is coupled to memory 100. In some embodiments, memory controller 900 can send various commands (e.g., programming commands, read commands, and erase commands) to memory 100 based on instructions received from the host to control the operation of memory 100 (e.g., programming operations, read operations, and erase operations). Specifically, when memory 100 performs a programming operation, memory 100 can perform operations such as... Figure 8 The operating method is shown.

[0098] It should be understood that the memory controller 900 can also be configured to manage various functions related to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. Of course, the memory controller 900 can also perform any other suitable functions (e.g., formatting the memory), which will not be elaborated here.

[0099] In some implementations, the memory controller 900 and one or more memories 100 can be packaged into different types of electronic products. In some examples, the memory controller 900 and a single memory 100 can be integrated into a memory card. The memory card can include a PCMCIA card, a compact flash (CF) card, a smart media (SM) card, a memory stick, a multi-media card (MMC), and a secure digital (SD) card, etc. The memory card may further include a memory card connector that couples the memory card to a host. In other examples, the memory controller 900 and multiple memories 100 can be integrated into a solid state disk (SSD). The SSD may further include a solid state disk connector that couples the SSD to a host. In some implementations, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card.

[0100] The memory controller 900 can communicate with external devices (e.g., a host) via at least one of various interface protocols. The interface protocol can be at least one of the following: Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0101] In some implementations, the memory system 800 can be applied to different types of electronic devices, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and any other electronic device capable of storing data.

[0102] This application provides a memory, a memory operation method, and a memory system. The memory includes a memory array and peripheral circuitry. The peripheral circuitry includes a page buffer, which is coupled to the memory array via bit lines. The page buffer includes a sensing node, a first latch circuit, and a charging / discharging circuit. The first latch circuit is coupled to the sensing node and configured to latch state information of memory cells in the memory array. The charging / discharging circuit is coupled to the bit lines and also to the first latch circuit. The charging / discharging circuit is configured to apply a bit line voltage to the bit lines during the verification phase of the programming operation. The bit line voltage is related to the state information. In this application embodiment, different bit line voltages are applied to the bit lines during the verification phase based on the state information latched by the first latch circuit, effectively replacing the offset of the verification voltage. Therefore, under the same verification voltage, verification of at least two adjacent programming states can be achieved within one sensing development time, reducing the time required for the verification phase and thus shortening the programming operation time and improving the programming speed.

[0103] This application provides a computer-readable storage medium storing computer-executable instructions; when executed, the computer-executable instructions can achieve the following: Figure 8 The method shown.

[0104] This application provides a computer device including a processor and a readable storage medium coupled to the processor. The readable storage medium stores executable instructions, which, when executed by the processor, can achieve the following: Figure 8 The method shown.

[0105] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0106] In the embodiments provided in this application, it should be understood that the provided memory, memory operation method, and memory system can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0107] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, It includes a memory array and peripheral circuitry, the peripheral circuitry including a page buffer, the page buffer being coupled to the memory array via bit lines; The page buffer includes: Sensing nodes, and; A first latch circuit, coupled to the sensing node, is configured to latch the state information of the storage cells in the storage array; A charging / discharging circuit is coupled to the bit line and also coupled to the first latch circuit; the charging / discharging circuit is configured to apply a bit line voltage to the bit line during the verification phase of a programming operation, the bit line voltage being related to the state information.

2. The memory according to claim 1, characterized in that, The status information includes first information and second information. The first information indicates that the target threshold voltage distribution range of the storage unit is a first range, and the second information indicates that the target threshold voltage distribution range of the storage unit is a second range. The first range and the second range are adjacent. The charging and discharging circuit is configured to: in the verification phase of the programming operation, in response to the first information, apply a first voltage to the bit line; or, in response to the second information, apply a second voltage to the bit line; Wherein, the first voltage is less than the second voltage.

3. The memory according to claim 2, characterized in that, The charging and discharging circuit includes a first discharging circuit and a second discharging circuit; wherein... The first end of the first discharge circuit is coupled to the sensing node, the second end of the first discharge circuit is coupled to the bit line, and the sensing node is also coupled to a charging circuit for inputting the power supply voltage. The first end of the second discharge circuit is coupled to the sensing node, and the second end of the second discharge circuit is coupled to the bit line. The control terminal of the second discharge circuit is coupled to the first latch circuit.

4. The memory according to claim 3, characterized in that, The first discharge circuit is configured to apply the first voltage to the bit line during the verification phase.

5. The memory according to claim 4, characterized in that, The second discharge circuit is configured to disconnect from the bit line in response to the first information during the verification phase. Alternatively, in response to the second information, the second voltage is applied to the bit line.

6. The memory according to any one of claims 3-5, characterized in that, The first discharge circuit includes a first transistor, a first terminal of which is coupled to the sensing node, and a second terminal of which is coupled to the bit line. During the verification phase, the control terminal of the first transistor is used to receive a first control voltage that controls the first transistor to turn on.

7. The memory according to claim 6, characterized in that, The second discharge circuit includes a second transistor and a third transistor. The first terminal of the second transistor is coupled to the sensing node, the second terminal of the second transistor is coupled to the first terminal of the third transistor, and the second terminal of the third transistor is coupled to the bit line. The control terminal of the second transistor is coupled to the first latch circuit, and in response to the first information, the second transistor is turned off; In response to the second information, the second transistor is turned on; During the verification phase, the control terminal of the third transistor is used to receive a second control voltage that controls the third transistor to turn on, the second control voltage being greater than the first control voltage.

8. The memory according to claim 1, characterized in that, The page buffer also includes a charge pump circuit, which is coupled to the sensing node.

9. The memory according to claim 8, characterized in that, During the verification phase, the charge pump circuit is configured to pump up the voltage of the sensing node during the discharge phase of the sensing node.

10. The memory according to claim 9, characterized in that, The charge pump circuit includes a capacitor, the first end of which is coupled to the sensing node; during the discharge phase of the sensing node, the second end of the capacitor is used to input the pump boost voltage.

11. A method for operating a memory, characterized in that, include: The memory includes storage units, and the operation method includes: Latch the state information of the storage unit; During the verification phase of programming the memory cell, a bit line voltage is applied to the bit line coupled to the memory cell; The bit line voltage is related to the state information.

12. The operating method according to claim 11, characterized in that, The status information includes first information and second information, and the operation method includes: In the verification phase, in response to the first information, a first voltage is applied to the bit line, wherein the first information indicates that the target threshold voltage distribution range of the memory cell is a first range; or, In response to the second information, a second voltage is applied to the bit line, wherein the second information indicates that the target threshold voltage distribution range of the memory cell is a second range, and the first range is adjacent to the second range; Wherein, the first voltage is less than the second voltage.

13. The operating method according to claim 12, characterized in that, The specific operation method includes: During the verification phase, the first discharge circuit in the page buffer applies the first voltage to the bit line; During the verification phase, in response to the first information, the second discharge circuit in the page buffer is disconnected from the bit line; or, in response to the second information, the second discharge circuit applies the second voltage to the bit line.

14. The operating method according to claim 13, characterized in that, The first discharge circuit in the page buffer applies the first voltage to the bit line, including: During the verification phase, a first control voltage is applied to the control terminal of the first transistor in the first discharge circuit to control the first transistor to conduct.

15. The operating method according to claim 14, characterized in that, In response to the first information, the second discharge circuit in the page buffer is disconnected from the bit line. In response to the second information, the second discharge circuit applies the second voltage to the bit line, including: During the verification phase, a second control voltage is applied to the control terminal of the third transistor in the second discharge circuit to control the third transistor to conduct; wherein, the second control voltage is greater than the first control voltage; The second transistor in the second discharge circuit turns off in response to the first information, and turns on in response to the second information.

16. The operating method according to any one of claims 11-15, characterized in that, Also includes: During the sensing development phase of the verification phase, a charge pump circuit coupled to the sensing node in the page buffer pumps up the voltage of the sensing node.

17. The operating method according to claim 16, characterized in that, The charge pump circuit in the page buffer, coupled to the sensing node, pumps up the voltage of the sensing node, specifically including: During the sensing development phase, a pump-up voltage is applied to the second terminal of a capacitor in the charge pump circuit, wherein the first terminal of the capacitor is coupled to the sensing node.

18. A page buffer, characterized in that, It includes a sensing node, a first latch circuit, a first transistor, a second transistor, and a third transistor; wherein, The first latch circuit is coupled to the sensing node; The first terminal of the first transistor is coupled to the sensing node, and the second terminal of the first transistor is used to be coupled to the bit line of the memory. The first terminal of the second transistor is coupled to the sensing node, the second terminal of the second transistor is coupled to the first terminal of the third transistor, and the second terminal of the third transistor is used to couple to the bit line; The control terminal of the second transistor is coupled to the first latch circuit.

19. The page buffer according to claim 18, characterized in that, The page buffer also includes a capacitor, a first end of which is coupled to the sensing node, and a second end of which is used to input the pump-up voltage.

20. A memory system, characterized in that, The device includes a memory controller and the memory as described in any one of claims 1-10, wherein the memory controller is coupled to the memory and is configured to control the memory.

Images