SiCMOSFET switch loss collaborative optimization method and system based on dynamic threshold regulation

Abstract

The application provides a SiCMOSFET switching loss collaborative optimization method and system based on dynamic threshold regulation. By analyzing the transient slope evolution path of the gate-source voltage, the first-order inflection point moment is extracted as a time anchor point associated with the diode voltage drop to reverse the influence of the junction temperature. The net gate charge decay trend represents the process and aging effect, and then generates a double-point asymmetric judgment point that evolves with the real-time state of the device. Combined with the carrier transport phase characteristics, the opening is advanced and the closing is delayed, so that the driving action is accurately embedded in the real physical window of the channel conductance establishment and depletion. As a result, the opening trigger occurs at the critical point of the channel electron before the effective injection, and the closing trigger maintains to the end of the channel carrier dominant depletion stage, significantly compresses the overlapping area, suppresses the Miller platform tail and voltage overshoot, reduces the single switching energy loss from the root, and improves the operation robustness of the system in a wide temperature range and the whole life cycle.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a method and system for co-optimizing the switching losses of SiCMOSFETs based on dynamic threshold control. Background Technology

[0002] Currently, SiC MOSFET driver circuits generally use a fixed gate voltage threshold as the basis for turn-on and turn-off decisions. A typical implementation involves setting a uniform comparison level (e.g., +15V for turn-on and +8V for turn-off), using a high-speed comparator to judge the gate-source voltage level based on real-time sampling, and outputting a drive edge control signal when the conditions are met. This solution is simple in structure and has low hardware overhead, and has been incorporated into standard logic in most commercial gate driver chips. However, the threshold voltage of SiC MOSFETs is not a constant parameter—it exhibits a negative drift as junction temperature increases and a positive rise as gate oxide trap charge accumulates during device aging. Furthermore, due to manufacturing process variations, it can range from 2.8V to 4.2V within the same batch. When the driver system continuously uses the factory-preset fixed decision point, the actual turn-on action may lag behind the effective channel conduction time, leading to a severe misalignment between the drain-source voltage drop and the drain current rise; the turn-off action may terminate prematurely before the channel carriers are fully depleted, causing dv / dt overshoot and parasitic oscillations.

[0003] The above phenomena together prolong the voltage-current overlap time during the switching process, causing the turn-on loss and turn-off loss to increase simultaneously, and exhibiting a nonlinear deterioration trend under high frequency, high temperature, and heavy load conditions. Summary of the Invention

[0004] The present invention aims to provide a SiCMOSFET switching loss co-optimization method and system based on dynamic threshold control, which suppresses Miller plateau tail and voltage overshoot, reduces single-switch energy loss from the root cause, and improves the system's operational robustness over a wide temperature range and the entire life cycle.

[0005] To achieve the above objectives, the technical solution adopted in this invention is: a SiCMOSFET switching loss co-optimization method based on dynamic threshold control, comprising:

[0006] After the rising edge of the drive signal triggers the transient waveform of the gate-source voltage at a fixed sampling interval, calculate its first-order and second-order differential characteristics, and extract the first-order inflection point time.

[0007] Using the first inflection point as a time reference, the voltage between the anode and cathode of the bulk diode is sampled within the subsequent delay window, and the equivalent gate voltage offset is generated by combining the junction temperature-voltage drop mapping relationship.

[0008] The gate-source voltage value, equivalent gate voltage offset, and process discrete attenuation factor corresponding to the first inflection point are algebraically synthesized to form a dual-domain normalized threshold base point.

[0009] To address the carrier transport phase difference during the turn-on and turn-off processes of SiCMOSFETs, the dynamic decision points for asymmetric turn-on and asymmetric turn-off are obtained by subtracting the turn-on advance from the dual-domain normalized threshold base point and adding the turn-off delay.

[0010] Monitor the monotonic change of the gate-source voltage within the sliding time window. When the gate-source voltage crosses the asymmetric turn-on dynamic decision point or the asymmetric turn-off dynamic decision point, generate the corresponding turn-on trigger event and turn-off trigger event.

[0011] Calculate the time interval between the turn-on trigger event and the turn-off trigger event, generate an adaptive dead time using a hysteresis piecewise function, and convert the dead time deviation into the output resistance adjustment of the driver stage;

[0012] Cross-cycle low-pass filtering is applied to the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point. When the reference offset continuously exceeds the threshold, the initial dual-domain normalized threshold base point is updated.

[0013] Real-time detection of abnormal states such as sampling freeze, junction temperature exceeding limits, and loss of dynamic decision point hysteresis. During abnormal periods, a pre-stored safety-driven template is invoked. After the abnormality is recovered, the dynamic decision point is reconstructed starting from the long-term memory fitted prediction value.

[0014] Preferably, the extraction of the first inflection point time includes: extracting the gate-source voltage sequence within a preset early observation window after the rising edge of the driving signal; calculating the first-order forward difference sequence of the gate-source voltage sequence; performing a sliding window second-order difference operation on the first-order forward difference sequence to obtain the curvature response sequence; locating the first index in the curvature response sequence that changes from non-negative to negative and mapping it to the first inflection point time.

[0015] Preferably, generating the equivalent gate voltage offset includes: performing single-point sampling of the anode-cathode voltage of the body diode after a fixed delay following the first inflection point; substituting the anode-cathode voltage of the body diode into the quadratic polynomial junction temperature-voltage drop mapping relationship to obtain a junction temperature estimate; calculating the relative displacement of the channel conduction band bottom relative to the Fermi level based on the junction temperature estimate; and converting the relative displacement into an equivalent gate voltage offset via the voltage division relationship between the gate oxide layer and the depletion layer capacitance.

[0016] Preferably, the formation of the dual-domain normalized threshold base point includes: integrating the gate drive current to obtain the net gate injected charge during the time period from the end of the turn-off to the next turn-on in each switching cycle; comparing the net gate injected charge with the device's nominal maximum gate charge to obtain a process dispersion attenuation factor; multiplying the process dispersion attenuation factor by the process dispersion sensitivity coefficient to obtain a process-induced offset; and adding the gate-source voltage value, equivalent gate voltage offset, and process-induced offset at the first inflection point to form the dual-domain normalized threshold base point.

[0017] Preferably, obtaining the asymmetric turn-on dynamic determination point and the asymmetric turn-off dynamic determination point includes: multiplying the slope of the first-order forward differential sequence near the first inflection point time with a preset carrier injection delay time to calculate the turn-on advance; subtracting the turn-on advance from the dual-domain normalized threshold base point to obtain the asymmetric turn-on dynamic determination point; multiplying the absolute value of the slope of the first-order forward differential sequence in the turn-off stage with a preset turn-off tail time to calculate the turn-off delay; and adding the turn-off delay to the dual-domain normalized threshold base point to obtain the asymmetric turn-off dynamic determination point.

[0018] Preferably, generating the corresponding turn-on trigger event and turn-off trigger event includes: maintaining a sliding time window containing sixteen consecutive gate-source voltage sampling points; counting the number of positive and negative signs of the difference between adjacent sampling points within the sliding time window to determine whether the gate-source voltage is in a monotonically rising segment or a monotonically falling segment; in the monotonically rising segment, when the gate-source voltage first changes from below the asymmetric turn-on dynamic determination point to above the asymmetric turn-on dynamic determination point, generating a turn-on trigger event; in the monotonically falling segment, when the gate-source voltage first changes from above the asymmetric turn-off dynamic determination point to below the asymmetric turn-off dynamic determination point, generating a turn-off trigger event.

[0019] Preferably, the step of converting the dead time deviation into a driver stage output resistance adjustment includes: calculating the time interval between the turn-on trigger event timestamp and the turn-off trigger event timestamp; when the time interval is less than a first threshold, setting the dead time to a first fixed value; when the time interval is between the first threshold and a second threshold, setting the dead time to the time interval plus a fixed margin; when the time interval is greater than the second threshold, setting the dead time to a second fixed value; multiplying the difference between the dead time and the reference dead time value by a resistance-time conversion coefficient to obtain the driver stage output resistance adjustment; and adding the driver stage output resistance adjustment to the currently configured resistor of the driver stage to update the driver stage output impedance.

[0020] Preferably, updating the initial dual-domain normalized threshold base point includes: performing a first-order infinite impulse response filter on the asymmetric turn-on dynamic decision point to obtain the turn-on long-term memory value; performing a first-order infinite impulse response filter on the asymmetric turn-off dynamic decision point to obtain the turn-off long-term memory value; calculating the difference between the average of the turn-on long-term memory value and the turn-off long-term memory value and the initial dual-domain normalized threshold base point as a reference offset; when the absolute value of the reference offset exceeds 0.25 volts for 500 consecutive cycles, updating the initial dual-domain normalized threshold base point to the average of the current turn-on long-term memory value and the turn-off long-term memory value.

[0021] Preferably, the reconstructed dynamic decision point includes: setting the sampling freeze flag trigger condition to be that the variance of eight consecutive sampling points is less than 10 to the power of -4 volts squared; setting the junction temperature over-limit flag trigger condition to be that the estimated junction temperature is higher than 185 degrees Celsius or lower than -40 degrees Celsius; setting the dynamic decision point hysteresis loss flag trigger condition to be that the difference between the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point is less than 0.3 volts; when all abnormal flags are not triggered for three consecutive cycles, the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point are recalculated starting from the linear trend prediction value of the long-term memory value fitted during the abnormal period.

[0022] On the other hand, this invention proposes a SiCMOSFET switching loss collaborative optimization system based on dynamic threshold control, comprising:

[0023] The gate-source voltage slope feature extraction unit is used to acquire the transient waveform of the gate-source voltage after the rising edge of the drive signal, calculate the differential features and extract the first inflection point time.

[0024] The junction temperature response offset calculation unit is used to sample the body diode voltage using the first inflection point as a time reference to generate the equivalent gate voltage offset.

[0025] The dual-domain threshold fusion unit is used to fuse the first-order inflection point voltage value, the equivalent gate voltage offset, and the process discrete attenuation factor to form a dual-domain normalized threshold base point.

[0026] The asymmetric decision point generation unit is used to subtract the turn-on advance and add the turn-off delay from the dual-domain normalized threshold base point to obtain the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point, respectively, based on the carrier transport phase difference.

[0027] The edge-decision triggering unit is used to monitor the monotonicity change of the gate-source voltage and generate turn-on triggering events and turn-off triggering events when crossing the dynamic decision point.

[0028] The dead-time adaptive adjustment unit is used to calculate the trigger event time interval, generate the adaptive dead-time, and convert it into the output resistance adjustment of the driver stage;

[0029] The cross-cycle memory calibration unit is used to perform cross-cycle low-pass filtering on dynamic decision points and update the dual-domain normalized threshold base point when the reference offset continues to exceed the limit.

[0030] The dual-path fault-tolerant switching unit is used to detect abnormal states, call the safety-driven template during the abnormal period, and reconstruct the dynamic decision point starting from the long-term memory prediction value after the abnormality is recovered.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] This invention does not rely on external temperature sensors or aging monitoring modules, but instead starts from the measurable signals of the drive circuit itself: by analyzing the evolution path of the transient slope of the gate-source voltage to extract the first inflection point, it uses this as a time anchor point to correlate the body diode voltage drop to inversely determine the junction temperature effect. It integrates the net gate charge decay trend to characterize the process and aging effects, thereby generating a two-point asymmetric judgment point that evolves with the real-time state of the device. Furthermore, by combining the carrier transport phase characteristics, it implements turn-on advance and turn-off delay, allowing the drive action to be precisely embedded in the real physical window of channel conductance establishment and depletion. Thus, the turn-on trigger occurs at the critical point where effective channel electron injection begins, and the turn-off trigger is maintained until the end of the channel carrier-dominated depletion stage, significantly compressing the turn-on time. The overlapping area suppresses Miller plateau tailing and voltage overshoot, fundamentally reducing single-switch energy loss and improving system robustness over a wide temperature range and throughout its life cycle. Attached Figure Description

[0033] Figure 1 This is a flowchart of the SiCMOSFET switching loss collaborative optimization method based on dynamic threshold control according to the present invention;

[0034] Figure 2 This is a block diagram of the SiCMOSFET switching loss collaborative optimization system based on dynamic threshold control according to the present invention. Detailed Implementation

[0035] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0036] like Figure 1As shown, this invention proposes a method for co-optimizing switching losses of SiCMOSFETs based on dynamic threshold control. Its core lies in abandoning the fixed gate voltage determination point and instead constructing a dual-domain coupled threshold generation path that evolves with the real-time state of the device. On the one hand, it establishes a local slope feature mapping of the gate-source voltage evolution trajectory based on the intrinsic electrical response of the device; on the other hand, it inverts the channel carrier activation barrier offset through the junction thermal-electric coupling effect. The two are synchronously normalized on the time axis and then weighted and fused to form a unique turn-on trigger point within each switching cycle. With shutdown trigger point This dual-point asymmetric setting directly affects the edge sampling decision stage of the drive signal, enabling the turn-on action to initiate at the critical point of effective electron injection into the channel and the turn-off action to terminate at the stage dominated by channel carrier depletion. This avoids Miller plateau tailing, suppresses dv / dt overshoot, and compresses the current overlap range. The entire process does not rely on offline calibration or introduce external sensor redundancy; all information originates from the closed-loop feedback reconstruction of the measurable voltage / current differential signal of the drive circuit itself and the on-chip temperature-sensitive parameters. Specifically, it includes the following steps:

[0037] After the rising edge of the driving signal triggers the transient waveform of the gate-source voltage at a fixed sampling interval, its first-order and second-order differential characteristics are calculated, and the first inflection point time is extracted. Specifically, this includes: extracting the gate-source voltage sequence within a preset early observation window after the rising edge of the driving signal triggers the waveform; calculating the first-order forward differential sequence of the gate-source voltage sequence; performing a sliding window second-order differential operation on the first-order forward differential sequence to obtain the curvature response sequence; locating the first index in the curvature response sequence that changes from non-negative to negative, and mapping it to the first inflection point time.

[0038] Adaptive identification of the Miller effect initiation moment in the gate charging path of SiCMOSFET is achieved, so that the decision point no longer depends on the device nominal parameters or offline calibration, but directly responds to the current driving capability, PCB parasitic parameters and the intrinsic capacitance nonlinearity of the device. The first inflection point obtained in this way has strong physical significance - it characterizes the real electrical transition point at which channel electrons begin to be affected by Miller capacitance shunting, providing a time reference that is strictly synchronized with the actual switching behavior for the generation of all subsequent dynamic thresholds, fundamentally avoiding turn-on timing lag or false triggering caused by fixed timing delay or voltage threshold deviation.

[0039] Using the first inflection point as a time reference, the voltage between the anode and cathode of the body diode is sampled within a subsequent delay window. The equivalent gate voltage offset is generated by combining the junction temperature-voltage drop mapping relationship. Specifically, this includes: performing single-point sampling of the voltage between the anode and cathode of the body diode after a fixed delay following the first inflection point; substituting the voltage between the anode and cathode of the body diode into the quadratic polynomial junction temperature-voltage drop mapping relationship to obtain the estimated junction temperature; calculating the relative displacement of the channel conduction band bottom relative to the Fermi level based on the estimated junction temperature; and converting the relative displacement into the equivalent gate voltage offset through the voltage division relationship between the gate oxide layer and the depletion layer capacitance.

[0040] By utilizing the inherent electrical parameters of the device (body diode voltage drop), in-situ, non-invasive sensing is achieved without the need for additional temperature sensors. The impact of this sensing on the threshold voltage is quantified into an equivalent gate voltage offset that can be directly used in voltage domain calculations. This establishes a deterministic mapping relationship between junction temperature drift and the drive decision point, enabling the system to maintain the actual crossing accuracy of the channel turn-on barrier as the junction temperature rises from 25°C to 175°C. This effectively suppresses the risks of early turn-on, Miller plateau compression, and dv / dt runaway caused by thermally induced negative threshold drift.

[0041] The gate-source voltage value, equivalent gate voltage offset, and process discrete attenuation factor corresponding to the first inflection point are algebraically synthesized to form a dual-domain normalized threshold base point. Specifically, this includes: integrating the gate drive current to obtain the net gate injected charge during the time period from the end of turn-off to the next turn-on in each switching cycle; comparing the net gate injected charge with the device's nominal maximum gate charge to obtain the process discrete attenuation factor; multiplying the process discrete attenuation factor by the process discrete sensitivity coefficient to obtain the process-induced offset; and adding the gate-source voltage value, equivalent gate voltage offset, and process-induced offset corresponding to the first inflection point to form the dual-domain normalized threshold base point.

[0042] This method achieves unified quantification and coordinated normalization of three heterogeneous influences: geometric activation point, thermally induced barrier shift, and static parameter discreteness introduced by manufacturing / aging. This enables the dual-domain normalized threshold base point to simultaneously carry the device's current electrical response characteristics, real-time thermal state, and long-term degradation trend. The resulting base point is no longer an isolated voltage value, but becomes a comprehensive reference anchor spanning the transient, steady-state, and lifetime time scales. This provides a unified voltage reference with both physical interpretability and engineering robustness for the subsequent construction of asymmetric dynamic decision points, significantly improving the generalization consistency of threshold control across a wide range of process batches, multiple operating temperatures, and different aging stages.

[0043] To address the carrier transport phase difference during the turn-on and turn-off processes of SiCMOSFETs, the asymmetric turn-on dynamic determination points and asymmetric turn-off dynamic determination points are obtained by subtracting the turn-on advance from the dual-domain normalized threshold base point and adding the turn-off delay. Specifically, this involves: multiplying the slope of the first-order forward differential sequence near the first inflection point with a preset carrier injection delay time to calculate the turn-on advance; subtracting the turn-on advance from the dual-domain normalized threshold base point to obtain the asymmetric turn-on dynamic determination point; multiplying the absolute value of the slope of the first-order forward differential sequence during the turn-off stage with a preset turn-off tail time to calculate the turn-off delay; and adding the turn-off delay to the dual-domain normalized threshold base point to obtain the asymmetric turn-off dynamic determination point.

[0044] By differentiating the turn-on timing and turn-off timing, the driving action time axis is strictly aligned with the actual transport phase of the channel carriers: the turn-on decision point is moved forward to ensure that the gate voltage command is started before the channel conductance is effectively established, thus compressing the current ramp-up overlap during the voltage drop period; the turn-off decision point is moved backward to ensure that the gate control exits only after the channel is completely depleted, thus suppressing the wake oscillation in the early stage of the drain voltage rise.

[0045] The monotonicity of the gate-source voltage is monitored within a sliding time window. When the gate-source voltage crosses the asymmetric turn-on dynamic decision point or the asymmetric turn-off dynamic decision point, corresponding turn-on and turn-off trigger events are generated. Specifically, this includes: maintaining a sliding time window containing sixteen consecutive gate-source voltage sampling points; counting the number of positive and negative signs of the difference between adjacent sampling points within the sliding time window to determine whether the gate-source voltage is in a monotonically rising segment or a monotonically falling segment; in the monotonically rising segment, when the gate-source voltage first changes from below the asymmetric turn-on dynamic decision point to above the asymmetric turn-on dynamic decision point, a turn-on trigger event is generated; in the monotonically falling segment, when the gate-source voltage first changes from above the asymmetric turn-off dynamic decision point to below the asymmetric turn-off dynamic decision point, a turn-off trigger event is generated.

[0046] The decision-making process embeds real-time identification of the gate-source voltage evolution trend. The dynamic decision point is only activated when the voltage is confirmed to be in a real monotonic change phase, thereby naturally filtering out false crossover signals caused by PCB parasitic ringing, Miller capacitance coupling disturbances, or measurement noise. Its decision logic does not rely on absolute voltage accuracy or fixed delay, but is based on the sequential relationship between continuous sampling points. This ensures that the turn-on trigger event and the turn-off trigger event strictly correspond to the real moment when the device channel state undergoes a fundamental change, significantly improving the anti-interference capability and time resolution of the drive edge decision.

[0047] The process involves calculating the time interval between the turn-on and turn-off trigger events, generating an adaptive dead time using a hysteresis-type piecewise function, and converting the dead time deviation into a driver-stage output resistance adjustment. Specifically, this includes: calculating the time interval between the turn-on and turn-off trigger event timestamps; setting the dead time to a first fixed value when the time interval is less than a first threshold; setting the dead time to the time interval plus a fixed margin when the time interval is between the first and second thresholds; setting the dead time to a second fixed value when the time interval is greater than the second threshold; multiplying the difference between the dead time and the reference dead time value by a resistance-time conversion coefficient to obtain the driver-stage output resistance adjustment; and adding the driver-stage output resistance adjustment to the currently configured driver-stage resistor to update the driver-stage output impedance.

[0048] By incorporating dead time and driver stage output impedance into the same control loop, the system can dynamically avoid bridge arm shoot-through risk through dead time when dealing with device parameter drift, temperature changes, and parasitic differences, while simultaneously adjusting the gate charge and discharge rate to stabilize voltage jump characteristics. The hysteresis segmented design avoids frequent dead time jitter near the critical point, while continuous fine-tuning of the output resistance ensures that dv / dt control does not produce abrupt changes due to dead time adjustment. The synergistic effect of these two factors maintains the safety boundary of the power loop while suppressing the increase in body diode conduction loss caused by excessively long dead time and the transient current surge caused by excessively short dead time, achieving a unified balance between safety and efficiency.

[0049] A cross-cycle low-pass filter is applied to both the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point. When the reference offset continuously exceeds the threshold, the initial dual-domain normalized threshold base point is updated. Specifically, this includes: performing a first-order infinite impulse response filter on the asymmetric turn-on dynamic decision point to obtain the turn-on long-term memory value; performing a first-order infinite impulse response filter on the asymmetric turn-off dynamic decision point to obtain the turn-off long-term memory value; calculating the difference between the average of the turn-on long-term memory value and the turn-off long-term memory value and the initial dual-domain normalized threshold base point as the reference offset; when the absolute value of the reference offset exceeds 0.25 volts for 500 consecutive cycles, the initial dual-domain normalized threshold base point is updated to the average of the current turn-on long-term memory value and the turn-off long-term memory value.

[0050] Low-pass filtering effectively separates the threshold drift trend caused by slow physical processes such as gate oxide trap charge accumulation and interface state density growth, avoiding interference from fast-changing noise in long-term state estimation. Meanwhile, the benchmark update condition based on continuous periodic statistics ensures that the system benchmark is only reset when the drift reaches an engineering-confirmable level of aging significance, preventing miscalibration caused by transient disturbances or measurement fluctuations.

[0051] The system detects abnormal states such as sampling freeze, junction temperature exceeding limits, and loss of hysteresis at dynamic decision points in real time. During abnormal periods, it calls a pre-stored safety-driven template. After the abnormality is resolved, the dynamic decision points are reconstructed starting from the long-term memory fitted prediction value. Specifically, the system includes: setting the sampling freeze flag trigger condition to be that the variance of eight consecutive sampling points is less than 10^-4 volts squared; setting the junction temperature exceeding limits flag trigger condition to be that the estimated junction temperature is higher than 185 degrees Celsius or lower than -40 degrees Celsius; setting the dynamic decision point hysteresis loss flag trigger condition to be that the difference between the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point is less than 0.3 volts; when all abnormal flags are not triggered for three consecutive cycles, the asymmetric turn-on dynamic decision points and the asymmetric turn-off dynamic decision points are recalculated starting from the linear trend prediction value of the long-term memory value fitted during the abnormal period.

[0052] Without increasing hardware redundancy, a seamless integration of fault modes and safe operation is achieved: anomaly detection relies entirely on existing voltage, temperature, and judgment point calculation results, without the need for additional sensors or logic circuits; the safety drive template, as a deterministic response verified under all operating conditions, ensures that the power circuit remains controllable under extreme conditions such as signal failure, thermal runaway, or control instability; and using the long-term memory trend prediction value as the recovery starting point avoids the transient fluctuations caused by rebuilding the dynamic threshold from zero after anomaly clearing, enabling the system to smoothly return to the optimized operating range after experiencing disturbances.

[0053] On the other hand, this invention proposes a SiCMOSFET switching loss co-optimization system based on dynamic threshold control, such as... Figure 2 As shown, it includes:

[0054] The gate-source voltage slope feature extraction unit is used to acquire the transient waveform of the gate-source voltage after the rising edge of the drive signal, calculate the differential features and extract the first inflection point time.

[0055] The junction temperature response offset calculation unit is used to sample the body diode voltage using the first inflection point as a time reference to generate the equivalent gate voltage offset.

[0056] The dual-domain threshold fusion unit is used to fuse the first-order inflection point voltage value, the equivalent gate voltage offset, and the process discrete attenuation factor to form a dual-domain normalized threshold base point.

[0057] The asymmetric decision point generation unit is used to subtract the turn-on advance and add the turn-off delay from the dual-domain normalized threshold base point to obtain the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point, respectively, based on the carrier transport phase difference.

[0058] The edge-decision triggering unit is used to monitor the monotonicity change of the gate-source voltage and generate turn-on triggering events and turn-off triggering events when crossing the dynamic decision point.

[0059] The dead-time adaptive adjustment unit is used to calculate the trigger event time interval, generate the adaptive dead-time, and convert it into the output resistance adjustment of the driver stage;

[0060] The cross-cycle memory calibration unit is used to perform cross-cycle low-pass filtering on dynamic decision points and update the dual-domain normalized threshold base point when the reference offset continues to exceed the limit.

[0061] The dual-path fault-tolerant switching unit is used to detect abnormal states, call the safety-driven template during the abnormal period, and reconstruct the dynamic decision point starting from the long-term memory prediction value after the abnormality is recovered.

[0062] In addition, each unit in the above system is also used to implement other steps of the above-mentioned SiCMOSFET switching loss collaborative optimization method based on dynamic threshold control, as follows:

[0063] Step 1: Construct the transient slope feature sequence of the gate-source voltage and extract the position of the first inflection point;

[0064] This step initiates the entire dynamic threshold generation process, with the goal of obtaining the gate-source voltage. The most representative geometric inflection point in the initial rising phase after the pre-charging phase ends corresponds to the moment when the Miller capacitance begins to significantly participate in charge distribution, and serves as the time anchoring reference for all subsequent dynamic decision points.

[0065] Step 1.1: After the rising edge of the drive signal in each switching cycle is triggered, at a fixed sampling interval... Gate-source voltage Continuous data collection was performed, and data was extracted from... to The voltage sequence, where Defined as the driver stage output voltage exceeding At that moment, The preset observation window length is used; the obtained discrete sequence is... ,in This sequence covers everything from driver stage turn-on, gate parasitic inductor charging, to... The entire charging process is controlled, providing the original basis for subsequent slope evolution analysis.

[0066] Step 1.2: Based on the sequence obtained in Step 1.1 Calculate its first-order forward difference sequence Defined as:

[0067] ;

[0068] The differential result characterizes the rate of change of the gate-source voltage per unit time, i.e. The discrete approximation is used. Because the gate input capacitance of a SiC MOSFET has strong nonlinearity... exist The dominant region shows an approximately constant upward trend, but after entering the Miller plateau region... Parallel current sharing leads to a redistribution of the charging current. The first observable downward trend will emerge, starting at the electrical sign activated by the Miller effect.

[0069] Step 1.3: Apply the results obtained in Step 1.2 The sequence performs a sliding window second-order difference operation, with a window width of... The curvature response sequence was obtained. Defined as:

[0070]

[0071] This operation is essentially a... The change in acceleration is locally averaged and estimated, its physical meaning being the "bending degree" of the gate voltage rise process; when When a value first changes from positive to negative, it indicates that... The transition from accelerated ascent to decelerated ascent corresponds to... The curve transitions from a convex function to a concave function, marking the first inflection point in a mathematical sense. This inflection point is not a fixed voltage value, but rather a time coordinate that fluctuates with driving capability, PCB parasitics, and device parameter drift.

[0072] Step 1.4: The result obtained in Step 1.3 China is the first to meet the positioning requirements and index Mapping it back to the continuous time domain, we obtain the first inflection point time. And record the corresponding gate-source voltage values. ;Should It is not used as the final turn-on determination point, but rather as the time-voltage joint reference origin for dynamic threshold generation in subsequent steps. Its existence itself already reflects the actual electrical characteristics of the current gate charging path of the device, and no longer depends on the factory specifications. This completes the closed loop from original voltage sampling to geometric feature extraction, providing a rigid time reference for the timing alignment of the thermoelectric coupling offset in step two.

[0073] Step 2: Obtain junction temperature-sensitive voltage parameters and establish a time-varying model of channel barrier offset;

[0074] This step is based on the first inflection point obtained in step one. Extending the time reference to the internal physical field level of the device, utilizing the forward voltage drop of the SiC bulk diode. junction temperature The monotonic sensitivity of the channel threshold barrier is used to invert the actual change in the height of the channel at the current operating point. This change is caused by the enhanced shielding of ionized impurities and the band contraction effect resulting from the intensification of lattice thermal vibration. The quantization result will directly modulate the geometric reference point extracted in step one, forming the dynamic shift of the first dimension.

[0075] Step 2.1: As determined in step 1.4 Delay after time Initiate the voltage between the anode and cathode of the body diode under common-source configuration. Single-point sampling, denoted as This delay design ensures that sampling occurs during the sampling process. The post-Miller platform has been established stably, and the drain-source current has been measured. Within the window that achieves steady state and is free from commutation oscillation interference, make True reflection of the present The built-in potential and carrier recombination characteristics of the lower PN junction. Due to limitations in SiC Schottky contact technology, the forward voltage drop of the body diode changes with junction temperature at a rate as high as... It is far superior to silicon-based devices, therefore It has sufficient discernment.

[0076] Step 2.2: Take the result obtained in Step 2.1 Substituting the junction temperature-voltage drop mapping relationship calibrated by multiple temperature points: ;

[0077] Where the coefficient The quadratic polynomial in The fitting error is less than within the range This yields the current estimated junction temperature. The condition for this expression to be true is that in step 2.1... The sampling time is when the body diode is forward conducting and the current density is... Constant to Nearby, and the condition has already been The timing is automatically satisfied by the drive timing and load current, requiring no additional control.

[0078] Step 2.3: Based on the results obtained in Step 2.2 Calculate the relative displacement of the SiC conduction band bottom relative to the Fermi level in the channel. This displacement originates from the band gap caused by the thermal expansion of the crystal lattice. The empirical expression for the non-parabolic conduction band distortion caused by contraction and enhanced electron-phonon coupling is as follows: ;

[0079] in The thermal drift coefficient at the conduction band edge, The reference temperature is used; this formula shows that for every increase in junction temperature... The bottom of the guide band dropped approximately This is equivalent to reducing the energy required for electrons to overcome the potential barrier, which macroscopically manifests as a negative shift in the threshold voltage. The amount of this shift remains unchanged. The geometric position is changed, but the actual conduction capability of the channel at that voltage is altered, so a correction must be included.

[0080] Step 2.4: Take the result obtained in Step 2.3 Convert to equivalent gate voltage offset Based on the relationship between threshold voltage and surface potential in the charge control model:

[0081] ;

[0082] in For elementary charge, The capacitance per unit area of ​​the gate oxide layer, The depletion layer capacitance per unit area; for a typical planar SiC MOSFET. Therefore This conversion establishes a quantitative bridge between microscopic band structure changes and macroscopic driving voltage, and its results... This will be directly superimposed on step one. The above constitutes the thermally induced offset component, providing a voltage dimension correction term for the dual-domain fusion in step three.

[0083] Step 3: Integrate the process discreteness compensation factor and generate a dual-domain normalized threshold base point;

[0084] This step follows two dimensions -- geometric inflection points. thermal displacement Based on this, the static dispersion effect caused by unavoidable fluctuations in gate oxide thickness and channel doping concentration during the manufacturing process is further introduced; this effect cannot be directly perceived through real-time electrical measurements, but can be observed through the total gate charge during the device aging process. The slow decay trend is indirectly characterized, thereby achieving dynamic embedding of the process dimension without increasing hardware costs.

[0085] Step 3.1: Within each switching cycle, after the turn-off process ends... From this moment on, continuously monitor the gate drive current. The integral value is calculated until the next cycle's rising edge arrives. At the end, the net gate injected charge for this cycle is obtained. The integral path covers both the complete turn-off discharge and turn-on pre-charge stages, and its total amount reflects the equivalent charge storage capacity of the current device gate circuit, which monotonically decreases as the gate oxide trap charge increases.

[0086] Step 3.2: Take the result obtained in Step 3.1 With respect to the device's factory-nominated maximum gate charge Perform ratio calculations and define the process discreteness attenuation factor. for: ;

[0087] The physical meaning of this ratio is clear: when At that time, the device is at the ideal process center point and has not aged; when This indicates that the gate oxide quality has degraded or the interface state density has increased, leading to the same The reduction in adjustable channel charge is equivalent to a positive shift in the threshold voltage; this factor does not require absolute precision, only relative trend consistency. The average value of the batch can be used instead of the calibration value of a single tube.

[0088] Step 3.3: Take the result obtained in Step 3.2 Mapped to process-induced offset A linear proportional relationship is adopted: ;

[0089] in This is the sensitivity coefficient for process discreteness, a value derived from a 1000-hour high-temperature gate offset test. The drift mean is derived by inverse calculation, and its physical basis is the interface state charge. Each increase This will cause Positive offset approximately ,and Comprehensive coverage Fixed oxide layer charge and the collective effect of the trap energy level distribution; therefore It characterizes the static threshold rise of the current device under the combined effects of manufacturing and aging.

[0090] Step 3.4: [The text appears to be incomplete and contains several grammatical errors. A more accurate translation would require Step Two With step three Perform algebraic synthesis to generate normalized turn-on threshold base points. :

[0091] ;

[0092] In this formula, the three terms represent the geometric activation point, thermal pull-down amount, and process-induced rise amount, respectively. The dimensions of the three terms are unified as voltage. After being superimposed, they form a comprehensive reference level that reflects both transient electrical behavior and thermal state and manufacturing history. Its value is no longer a fixed constant, but becomes a dynamic quantity that evolves independently for each switching cycle, laying a unified benchmark for the differentiated generation of the on / off dual points in step four.

[0093] Step 4: Construct asymmetric turn-on and turn-off dynamic determination points based on the channel carrier transport phase difference;

[0094] This step is based on the aforementioned... Starting from a common point of view, this paper analyzes in depth the inherent time-scale asymmetry of channel carrier generation, transport, and recombination during the turn-on and turn-off processes of SiCMOSFETs: During turn-on, electrons injected from the source region into the channel must overcome the surface barrier and complete lateral diffusion, resulting in a significant delay; during turn-off, channel electrons are rapidly drawn away by the source-drain electric field, but the recombination of residual holes and the release of surface states require additional time, leading to a longer turn-off tail. Therefore, the turn-on trigger point should be slightly lower than [the specified value]. To initiate the injection early, the shutdown trigger point should be slightly higher than [the specified threshold]. By delaying the termination of pumping, the two constitute an asymmetric dynamic window.

[0095] Step 4.1: The result obtained in step 3.4 Based on this, a lead time for opening is introduced. It is defined as the voltage reaching a certain value during the turn-on process. to drain current Time delay between the start of effective ascent The corresponding equivalent gate voltage increment; this increment is determined by exist Local slope in the vicinity Reverse reasoning: ;

[0096] in For typical planar SiC MOSFETs in The carrier injection delay is calculated below, a value obtained through statistical convergence of device physical simulation and long-term lifetime testing; therefore Follow Dynamic changes, strong driving force Large, then It automatically increases the lead time to ensure that the lead time matches the actual charging rate.

[0097] Step 4.2: Take the result obtained in Step 4.1 from Subtracting from the middle, we get the dynamic turn-on trigger point voltage: ;

[0098] This setting allows the drive circuit to initiate the main turn-on operation before the gate voltage reaches the geometric inflection point voltage, thus enabling better timing synchronization between channel electron injection and drain voltage drop, compressing... Overlapping area; its value is lower than But not lower than Since this lower limit corresponds to the area where the channel is completely cut off, advancing it too early will lead to the risk of misleading traffic.

[0099] Step 4.3: Generate in step 4.2 Simultaneously, construct the shutdown delay amount This quantity represents the drop in voltage from the gate voltage to the gate voltage when the gate is turned off. arrive The time interval between actual decay to zero The corresponding gate voltage buffer width is calculated based on the end of the turn-off period. absolute value ,in Shutdown phase Index of the steepest slope; Definition: ;

[0100] in This is the average turn-off tail time of the same device at the same junction temperature; this value is greater than... This reflects the inherent characteristic of SiCMOSFETs that their turn-off dynamics are slower than their turn-on dynamics; therefore Always greater than This ensures that the shutdown action has a greater safety margin.

[0101] Step 4.4: Take the result obtained in Step 4.3 Add to The dynamic shutdown trigger point voltage is obtained from the above. ;

[0102] This setting ensures that the drive circuit maintains a low-resistance state even after the gate voltage has fallen below the geometric inflection point, guaranteeing sufficient depletion of channel carriers and preventing premature gate drive interruption. early stage of rise Voltage overshoot caused by wake current; its value is higher than But no more than This upper limit corresponds to the top of the Miller platform; exceeding it will cause the drive stage to enter the saturation region and lose linear control capability. Therefore, both the on and off dynamic decision points are based on... This enables the hub to complete the differentiation generation, providing a direct basis for the real-time edge judgment of the driving signal in step five.

[0103] Step 5: Execute real-time decision-making based on dynamic decision points for the driving edge and generate gate voltage jump instructions;

[0104] This step is based on the results obtained in step four. and By embedding both into the drive signal generation loop, nanosecond-level voltage comparison and state switching decisions are achieved without introducing additional delay. The core of this approach lies in abandoning the traditional comparator hard threshold latch method and instead constructing a system based on the current... A sliding window dynamic decision mechanism constrained by trajectory slope and curvature information ensures that... During rapid traversal, it only responds to monotonically changing segments near actual inflection points, avoiding noise disturbances and false triggering caused by ringing.

[0105] Step 5.1: Continuously acquire data at the output of the driver stage. And simultaneously maintain a length of Sliding time window ,in This is the current sampling index; this window covers... The time span is sufficient to include The complete transition process in the Miller platform area; the data within the window is used to reconstruct the local monotonicity features in real time, and its existence itself constitutes the temporal carrier for the two dynamic decision points generated in steps 4.2 and 4.4.

[0106] Step 5.2: Regarding the steps in step 5.1 Perform a monotonicity test: Calculate the sequence of differences between adjacent sampling points within the window. Count the number of positive signs. and the number of negative signs ;like Then determine exist The internal state is in a monotonically increasing phase; if If the condition is met, it is determined to be a monotonically decreasing segment; otherwise, it is considered a non-monotonic disturbance segment, and the judgment is not executed temporarily. This test threshold Corresponding to Monotonic coverage can filter out high-frequency ringing (usually manifested as alternating positive and negative), and can also accommodate the slight backlash caused by parasitic inductance during actual switching. Its judgment result directly determines whether to use dynamic judgment points for comparison in the future.

[0107] Step 5.3: When step 5.2 is confirmed When the system is in a monotonically increasing phase, the activation decision is initiated: continuous monitoring. Is it satisfied for the first time?

[0108] and ;

[0109] These two conditions ensure that the crossing action occurs at the actual crossing moment between discrete sampling points, avoiding false triggers caused by single-point transient overshoot; once satisfied, the activation trigger event is immediately marked. and will The record is the moment when the turn-on command is issued in this cycle; this event does not depend on absolute voltage accuracy, but only on the relative sequential relationship, so it has natural robustness to ADC quantization error and reference voltage temperature drift.

[0110] Step 5.4: When step 5.2 is confirmed When the system is in a monotonically decreasing phase, trigger the shutdown decision: continuous monitoring. Is it satisfied for the first time?

[0111] and ;

[0112] This condition is symmetrical to step 5.3, but because This naturally creates a voltage hysteresis, preventing oscillating and repetitive decisions in the middle of the Miller plateau; once the condition is met, a turn-off trigger event is marked. and will This serves as the moment the shutdown command is issued; from this point onward, all spatiotemporal decisions regarding the driving edge originate from the device's own electrical response evolution path, no longer relying on external timers or fixed delays, thus providing accurate data for the adaptive generation of the dead time in step six. Benchmark.

[0113] Step 6: Generate an adaptive dead time based on the deviation between the turn-on and turn-off trigger times and calibrate the output impedance of the driver stage;

[0114] This step is based on the aforementioned... and The timestamp is used as input to quantify the risk of overlap between the drive signals of the upper and lower transistors of the same bridge arm in the actual power circuit, and the gate output resistance of the drive stage is dynamically adjusted accordingly. This ensures that the dead time is neither too long, leading to increased commutation losses, nor too short, causing shoot-through current; its essence is to transform the switching phase uncertainty of power devices into closed-loop feedback regulation of the electrical parameters of the drive stage.

[0115] Step 6.1: Record the results obtained in step 5.3. The result obtained in step 5.4 Calculate the time interval between the two. This value represents the time margin between the issuance of the upper MOSFET turn-on command and the issuance of the lower MOSFET turn-off command. Its physical meaning is the net dead zone margin resulting from the combined effects of inherent delays in the drive chain, PCB trace asymmetry, and individual component differences. If... This indicates that the current settings are approaching the direct access boundary and immediate intervention is required.

[0116] Step 6.2: Take the result obtained in Step 6.1 Input a hysteresis dead time generator, output dead time. Defined as:

[0117] ;

[0118] The design basis of this piecewise function is: when If the dead zone is too small, forcibly increase it to a safe threshold. To avoid cumulative errors leading to straight-through; when in the intermediate range, the measured margin is used as the basis for superposition. Engineering redundancy balances efficiency and reliability; when sufficient margin is available, the upper limit is capped at [value missing]. To prevent excessively long dead zones from causing prolonged body diode conduction time and increased reverse recovery losses; this strategy is entirely based on... The driver is so efficient that it requires no table lookup or preset curves.

[0119] Step 6.3: Take the result obtained in Step 6.2 Mapped to the output resistance adjustment of the driver stage Based on the source follower structure of the driver stage With rise / fall time Approximate linear relationship: ;

[0120] in This is the resistance-to-time conversion factor. This is the reference dead zone value; the formula shows that for every deviation of the dead zone from the reference value... The output resistance increases or decreases accordingly. Thus fine-tuning Amplitude, indirectly affecting the next cycle The slope characteristic -- this is the slope characteristic in step one. Source control.

[0121] Step 6.4: Take the result obtained in Step 6.3 Superimposed on the current configuration resistor of the driver stage The updated output resistance command value is obtained above: ;

[0122] This value is fed into a driver-level programmable resistor array, and implemented through charge-sharing digital encoding. Blister-free switching; due to Direct impact The rise / fall rate, and its adjustment result will be fed back to step one in the next switching cycle. Calculation stage.

[0123] Step 7: Establish threshold drift trend memory across switching cycles and implement progressive benchmark calibration;

[0124] This step uses the generation results of all previous single-cycle dynamic decision points as the data source to construct a low-pass filter-type long-term memory structure for identification. and The slow drift trend on a scale of hundreds to thousands of cycles is mainly driven by the cumulative release of gate oxide trap charges and the irreversible growth of interface state density. Its time constant is much larger than that of a single switching process. Therefore, a slow update mechanism is required to avoid the rapid change interference from overwhelming the real aging signal.

[0125] Step 7.1: Define two independent first-order infinite impulse response (IIR) filters, corresponding to the historical memory of the turn-on and turn-off decision points respectively:

[0126] ;

[0127] superscript Indicates the first One switching cycle These are the filter coefficients, corresponding to the time constant. ,

[0128] like (Typical switching cycle), then This is equivalent to approximately 220 cycles. Response; this coefficient ensures that the filter tracks only slowly varying components, achieving a single-cycle noise rejection ratio of up to .

[0129] Step 7.2: Take the result obtained in Step 7.1 and Substitute into the base offset calculation formula:

[0130] ;

[0131] in The first one generated in step three when the device is initially powered on. The value serves as the voltage zero point throughout the entire lifespan; It represents the total threshold drift from the initial state to the present. Its sign reflects the drift direction (mainly negative values), and its magnitude reflects the degree of degradation. This quantity does not participate in real-time decision-making, but is only used for long-term health assessment and maintenance early warning.

[0132] Step 7.3: When the result obtained in step 7.2 The absolute value of continuous The number of cycles exceeded the threshold At this time, the reference calibration process is triggered; at this time, Replace with current and reset all historical filter states:

[0133] ;

[0134] This reset operation is not a zeroing process, but rather a shift of the memory center to the current drift steady-state point, allowing subsequent filtering to continue operating around the new benchmark and avoiding long-term integral saturation. The physical basis for this is: when the drift reaches... By then, the device has entered a significant aging stage, and the original factory reference value has lost its engineering significance. It must be replaced by the measured long-term average value.

[0135] Step 7.4: After completing the calibration in step 7.3 and Feedback to step three The generation stage serves as the next round. Initial value correction term for process discreteness compensation in calculation:

[0136] ;

[0137] in To ensure that long-term drift only affects the single-cycle dynamic benchmark in a weakly coupled manner, the memory weight coefficients are used to preserve real-time response capability while embedding aging trend guidance. Thus, the system gains dual adaptability across time scales: the fast-changing dimension is dominated by single-cycle electrical characteristics, while the slow-changing dimension is anchored by the cross-cycle memory structure.

[0138] Step 8: Construct a dual-redundant path fault tolerance mechanism and seamlessly switch to safety-driven mode under abnormal operating conditions;

[0139] This step uses all the previously dynamically generated results as the protection object to design an intrinsic fault-tolerant architecture that does not rely on external fault detection circuits: when any critical link (such as...) When logical contradictions occur (such as sampling failure, junction temperature estimation exceeding limits, or dynamic decision point exceeding limits), the system does not interrupt operation. Instead, it immediately activates the preset safety drive template and uses the accumulated cross-cycle memory data to reconstruct the temporary decision point, ensuring that the power circuit is always in a controllable state.

[0140] Step 8.1: Define three types of abnormal state flags: continuous Variance of each sampling point (determined to be frozen during sampling) (Results from step 2.2) or (outside the safe operating area of ​​SiCMOSFET) (Loss of basic backlash margin); setting any flag triggers the fault tolerance process, and this judgment is executed independently at the beginning of each cycle, without depending on historical state.

[0141] Step 8.2: When any of the exception flags in Step 8.1 is activated, all dynamic calculations in Steps 5 to 7 are paused, and instead, the security driver template pre-stored in the on-chip ROM is invoked. This template is a set of templates that have been validated under all operating conditions. Piecewise function, containing a linearly increasing open segment ( Miller platform maintenance ( ), linear decrease in the cutoff segment ( Its parameters do not change with external conditions, but ensure that shoot-through and oscillation are avoided even under the worst junction temperature and maximum parasitic parameters, forming a hardware-level safety baseline.

[0142] Step 8.3: Execute in step 8.2 At the same time, extract the most recent from step 7.1 Each cycle and The sequence is fitted with its linear trend:

[0143]

[0144] Where the coefficient Obtained by the least squares method; this prediction is not used for real-time decision-making, but as a guide for rapid recovery after anomaly resolution—once the anomaly flag is cleared, the system does not return to the original dynamic path, but instead... and Restart the calculation in step four with the initial value to avoid transient fluctuations caused by rebuilding the memory from scratch.

[0145] Step 8.4: When all exception flags in Step 8.1 are consecutive If none of the cycles are set, the operating condition is determined to have returned to normal, and a seamless switch is executed: The result obtained in step 8.3 is... and Assign values ​​to respectively and And reset step six nominal value Afterward, all calculations revert to the main process, but the starting point has incorporated the long-term trend estimate during the abnormal period, ensuring that there are no voltage jumps, current surges, or control interruptions during the switching process. This mechanism enables the system to maintain continuous controllability of the power loop even under single-point failures, sensor inaccuracies, or extreme environmental changes, completing a unified closed loop from dynamic optimization to intrinsic safety.

[0146] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A method for synergistic optimization of switching losses in SiC MOSFETs based on dynamic threshold control, characterized in that, include: After the rising edge of the drive signal triggers the transient waveform of the gate-source voltage at a fixed sampling interval, calculates its first and second order differential characteristics, and extracts the first inflection point. Using the first inflection point as a time reference, the voltage between the anode and cathode of the body diode is sampled within its subsequent delay window, and the equivalent gate voltage offset is generated by combining the junction temperature-voltage drop mapping relationship. The gate-source voltage value corresponding to the first inflection point, the equivalent gate voltage offset, and the process discrete decay factor are algebraically synthesized to form a dual-domain normalized threshold base point. For the carrier transport phase difference during the turn-on and turn-off processes of SiCMOSFET, the turn-on advance is subtracted from the dual-domain normalized threshold base point and the turn-off delay is added to obtain the asymmetric turn-on dynamic judgment point and the asymmetric turn-off dynamic judgment point. The monotonic change of the gate-source voltage is monitored within the sliding time window. When the gate-source voltage crosses the asymmetric turn-on dynamic judgment point or the asymmetric turn-off dynamic judgment point, the corresponding turn-on trigger event and turn-off trigger event are generated. The time interval between the turn-on trigger event and the turn-off trigger event is calculated. An adaptive dead time is generated through a hysteresis piecewise function, and the dead time deviation is converted into the output resistance adjustment of the driver stage. Cross-cycle low-pass filtering is performed on the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point. When the reference offset continuously exceeds the threshold, the initial dual-domain normalized threshold base point is updated. Sampling freeze, junction temperature exceeding the limit, and abnormal states of loss of hysteresis for the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point are detected in real time. During the abnormal period, the pre-stored safety driver template is called. After the abnormality is recovered, the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point are reconstructed starting from the long-term memory fitted prediction value.

2. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The extraction of the first inflection point time includes: extracting the gate-source voltage sequence within a preset early observation window after the rising edge of the driving signal; calculating the first-order forward difference sequence of the gate-source voltage sequence; performing a sliding window second-order difference operation on the first-order forward difference sequence to obtain the curvature response sequence; locating the first index in the curvature response sequence that changes from non-negative to negative, and mapping it to the first inflection point time.

3. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The process of generating the equivalent gate voltage offset includes: performing single-point sampling of the anode-cathode voltage of the body diode after a fixed delay following the first inflection point; substituting the anode-cathode voltage of the body diode into the quadratic polynomial junction temperature-voltage drop mapping relationship to obtain a junction temperature estimate; calculating the relative displacement of the channel conduction band bottom relative to the Fermi level based on the junction temperature estimate; and converting the relative displacement into an equivalent gate voltage offset via the voltage division relationship between the gate oxide layer and the depletion layer capacitance.

4. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The process of forming the dual-domain normalized threshold base point includes: integrating the gate drive current to obtain the net gate injected charge during the time period from the end of the turn-off to the next turn-on in each switching cycle; comparing the net gate injected charge with the device's nominal maximum gate charge to obtain the process dispersion attenuation factor; multiplying the process dispersion attenuation factor by the process dispersion sensitivity coefficient to obtain the process-induced offset; and adding the gate-source voltage value, equivalent gate voltage offset, and process-induced offset at the first inflection point to form the dual-domain normalized threshold base point.

5. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The process of obtaining the asymmetric turn-on dynamic determination point and the asymmetric turn-off dynamic determination point includes: multiplying the slope of the first-order forward differential sequence near the first inflection point time with a preset carrier injection delay time to calculate the turn-on advance; subtracting the turn-on advance from the dual-domain normalized threshold base point to obtain the asymmetric turn-on dynamic determination point; multiplying the absolute value of the slope of the first-order forward differential sequence in the turn-off stage with a preset turn-off tail time to calculate the turn-off delay; and adding the turn-off delay to the dual-domain normalized threshold base point to obtain the asymmetric turn-off dynamic determination point.

6. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The generation of corresponding turn-on and turn-off trigger events includes: maintaining a sliding time window containing sixteen consecutive gate-source voltage sampling points; counting the number of positive and negative signs of the difference between adjacent sampling points within the sliding time window to determine whether the gate-source voltage is in a monotonically rising segment or a monotonically falling segment; in the monotonically rising segment, when the gate-source voltage first changes from below the asymmetric turn-on dynamic determination point to above the asymmetric turn-on dynamic determination point, a turn-on trigger event is generated; in the monotonically falling segment, when the gate-source voltage first changes from above the asymmetric turn-off dynamic determination point to below the asymmetric turn-off dynamic determination point, a turn-off trigger event is generated.

7. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The step of converting the dead time deviation into a driver-level output resistance adjustment includes: calculating the time interval between the turn-on trigger event timestamp and the turn-off trigger event timestamp; when the time interval is less than a first threshold, setting the dead time to a first fixed value; when the time interval is between the first threshold and a second threshold, setting the dead time to the time interval plus a fixed margin; when the time interval is greater than the second threshold, setting the dead time to a second fixed value; multiplying the difference between the dead time and the reference dead time value by a resistance-time conversion coefficient to obtain the driver-level output resistance adjustment; and adding the driver-level output resistance adjustment to the currently configured driver-level resistor to update the driver-level output resistor.

8. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The process of updating the initial dual-domain normalized threshold base point includes: performing a first-order infinite impulse response filter on the asymmetric turn-on dynamic decision point to obtain the turn-on long-term memory value; performing a first-order infinite impulse response filter on the asymmetric turn-off dynamic decision point to obtain the turn-off long-term memory value; calculating the difference between the average of the turn-on long-term memory value and the turn-off long-term memory value and the initial dual-domain normalized threshold base point as the reference offset; and updating the initial dual-domain normalized threshold base point to the average of the current turn-on long-term memory value and the turn-off long-term memory value when the absolute value of the reference offset exceeds 0.25 volts for 500 consecutive cycles.

9. The SiCMOSFET switching loss co-optimization method based on dynamic threshold control according to claim 1, characterized in that, The reconstruction of the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point includes: setting the sampling freeze flag trigger condition as the variance of eight consecutive sampling points being less than 10 to the power of -4 volts squared; setting the junction temperature over-limit flag trigger condition as the estimated junction temperature being higher than 185 degrees Celsius or lower than -40 degrees Celsius; setting the dynamic decision point hysteresis loss flag trigger condition as the difference between the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point being less than 0.3 volts; when all abnormal flags are not triggered for three consecutive cycles, the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point are recalculated starting from the linear trend prediction value of the long-term memory value fitted during the abnormal period.

10. A SiCMOSFET switching loss co-optimization system based on dynamic threshold control for implementing the method as described in any one of claims 1-9, characterized in that, include: The gate-source voltage slope feature extraction unit is used to acquire the transient waveform of the gate-source voltage after the rising edge of the drive signal, calculate the differential features and extract the first inflection point time. The junction temperature response offset calculation unit is used to sample the body diode voltage using the first inflection point as a time reference to generate the equivalent gate voltage offset. The dual-domain threshold fusion unit is used to fuse the first-order inflection point voltage value, the equivalent gate voltage offset, and the process discrete attenuation factor to form a dual-domain normalized threshold base point; the asymmetric decision point generation unit is used to subtract the turn-on advance and add the turn-off delay from the dual-domain normalized threshold base point to obtain the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point, respectively, based on the carrier transport phase difference. The edge-decision triggering unit is used to monitor the monotonicity change of the gate-source voltage and generate turn-on triggering events and turn-off triggering events when crossing the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point. The dead-time adaptive adjustment unit is used to calculate the time interval between the turn-on trigger event and the turn-off trigger event, generate the adaptive dead-time, and convert it into the output resistance adjustment of the driver stage. The cross-cycle memory calibration unit is used to perform cross-cycle low-pass filtering on the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point, and update the dual-domain normalized threshold base point when the reference offset continues to exceed the limit; the dual-path fault-tolerant switching unit is used to detect abnormal states, call the safety-driven template during the abnormal period, and reconstruct the asymmetric turn-on dynamic decision point and the asymmetric turn-off dynamic decision point starting from the long-term memory prediction value after the abnormality is recovered.

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