A transistor testing system and method
By employing a transistor testing system with nanosecond-level delays, a switch-in-series-resistor structure, low-speed transistors, multiple Schottky diodes in series, and a spike absorption circuit, the problems of excessive delay and voltage spike breakdown in traditional circuits are solved, achieving accurate transistor characteristic testing and improving circuit safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHONGTIANWEI (TIANJIN) ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2026-05-13
- Publication Date
- 2026-06-09
AI Technical Summary
In traditional dual-pulse circuits, there is a long delay of 3 to 13 μs between the end of drain voltage stress and the measurement of transistor turn-on characteristics, which leads to distorted test results and cannot truly reflect the instantaneous characteristics of the device after stress is applied and removed. At the same time, there is a risk of voltage spikes breaking down the device under test.
A transistor testing system with nanosecond-level delay is adopted. By using a switch-series resistor structure, the direct series connection of two switching transistors is avoided, and the voltage spike at the drain of the transistor under test during switching transients is optimized. Low-speed transistors and multiple Schottky diodes are connected in series to reduce parasitic capacitance, and a spike absorption circuit is added to ensure circuit safety.
With nanosecond-level measurement delays, the transient and steady-state characteristics of the transistor under test can be accurately characterized, reducing the risk of high-voltage breakdown of the device, improving the safety and stability of the test system, simplifying the circuit structure, and avoiding safety hazards caused by false turn-on.
Smart Images
Figure CN122171973A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of transistor testing, specifically relating to a transistor testing system and method. It can suppress voltage overshoot of the transistor under test while ensuring the safety of the testing system and personnel, and characterize the transistor characteristics under arbitrary drain voltage stress values, drain voltage stress durations, and load currents based on nanosecond-level measurement delays. Background Technology
[0002] Dual-pulse test circuits can be used to characterize the hard-switching characteristics of power transistors under simultaneous drain voltage stress and load current conditions. The test principle is as follows: two consecutive pulse signals are applied to the gate of the transistor under test (DUT), causing the device to complete two switching actions. During the DUT's conduction period, a high-voltage power supply charges the load inductor; the inductor current amplitude can be precisely set by controlling the duration of the first conduction. During the second conduction, the device simultaneously experiences high voltage and high current switching, achieving the hard-switching process test. In traditional dual-pulse circuits, there is a relatively long measurement delay from the completion of drain voltage stress application to entering the measurement state. This delay mainly includes the initial conduction time of the DUT (typically 2–10 μs) and the duration of inductor freewheeling through the Schottky diode after the device is turned off (typically 1–3 μs). Studies have shown that power transistors fabricated from novel semiconductor materials are susceptible to drain voltage stress, leading to effects such as internal defect carrier trapping, threshold voltage drift, and on-resistance degradation. Furthermore, the time constant for defect carrier release after stress removal ranges from microseconds to seconds. The measurement delay of 3 to 13 μs in traditional circuits can lead to distorted test results, failing to accurately reflect the instantaneous characteristics of the device after stress is applied and removed. The measured switching and conduction characteristics deviate significantly from the actual operating conditions.
[0003] Patent (CN202511617182.1) discloses a high-security nanosecond delay transistor testing system and method. Its power circuit abandons the half-bridge structure with two directly connected switches, instead employing a series resistor between the switches to achieve high-speed, high-security testing. However, this circuit structure is prone to voltage spikes at the drain coupling of the transistor under test, and these overshooting voltage spikes can easily break down the device under test, causing a short circuit. Therefore, proposing a new circuit structure to further improve the safety of the testing system has become an urgent technical problem to be solved. Summary of the Invention
[0004] The purpose of this invention is to provide a transistor testing system and method. Addressing the issue of a long delay of 3–13 μs between the end of drain voltage stress and the measurement of transistor turn-on characteristics in traditional dual-pulse circuits, this testing system discloses a transistor testing scheme with a nanosecond-level delay. This scheme can test the turn-on transient and steady-state characteristics of the transistor under test under arbitrary drain voltage stress values, stress durations, and load currents with a nanosecond-level measurement delay. This circuit system does not contain a half-bridge structure with two directly connected switches, thus avoiding the large current conduction problem caused by mis-conductance of the two series switches. Simultaneously, it optimizes the voltage spike at the drain of the transistor under test during switching transients, reducing the risk of high-voltage breakdown, improving circuit safety to ensure the safety of experimental personnel and the testing system, and improving the stability of the drain voltage stress value, thereby enhancing the test quality.
[0005] To achieve the above objectives, the specific technical solution adopted is as follows:
[0006] Firstly, the present invention provides a transistor testing system.
[0007] The test system includes: switches S1, S2, and S3, and resistor R. A ,R C Schottky diodes D1, D2, D3; power inductor L; power supply V. DD The circuit connection of this system is as follows: one end of switch S1 is connected to the power supply V. DD The other end of switch S1 is connected to resistor R. A One end of the circuit, the cathode of Schottky diode D1, one end of power inductor L, the cathode of Schottky diode D3, and resistor R. C One end, resistor R A The other end is connected to GND. The positive terminal of Schottky diode D1 is connected to the other end of power inductor L, one end of switch S2, and the positive terminal of Schottky diode D2. The other end of switch S2 is connected to GND. The negative terminal of Schottky diode D2 is connected to the positive terminal of Schottky diode D3 and resistor R. C The other end of the switch is connected to GND.
[0008] Among them, the control switches S1, S2, and S3 are one of the following: insulated gate field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), or relays and gate drive chips.
[0009] The resistor can be replaced by a variety of equivalent devices, including but not limited to: (a) an enhancement-mode PMOS with gate-drain shorted as a load, (b) an enhancement-mode PMOS with fixed gate voltage as a load, (c) an enhancement-mode NMOS with gate-drain shorted as a load, or (d) a depletion-mode NMOS with gate-source shorted as a load.
[0010] Secondly, the present invention provides a transistor testing method, implemented using the system provided in the first aspect of the present invention, comprising the following steps:
[0011] 1) Determine the stress duration of switch S3 under voltage stress, and thereby determine the conduction duration of switch S1;
[0012] 2) Determine the initial current value at the instant switch S3 is closed, and thereby determine the conduction time of switch S2;
[0013] 3) Then, determine the conduction time of switch S3 based on the experimental objectives;
[0014] 4) Then determine the stress value when switch S3 is open, and thereby determine the parameters required for the high-voltage power supply;
[0015] 5) Set the high-voltage power supply parameters and control the switching states of switches S1, S2, and S3 in sequence;
[0016] 6) Obtain the voltage and current parameters of switch S3 using an oscilloscope;
[0017] 7) Obtain the transient and steady-state characteristics of switch S3 from the voltage and current parameters;
[0018] 8) Finally, the reliability parameters of switch S3 under nanosecond-level delay are obtained.
[0019] Furthermore, the switch S2 described in this invention is a slow switch, in which the drain voltage of switch S2 changes slowly during the switching transient. This is achieved by selecting a transistor with slow switching and increasing the gate drive resistance of switch S2.
[0020] Furthermore, the parasitic capacitance of the Schottky diode D2 described in this invention is very small. The parasitic capacitance is reduced by selecting a Schottky diode with very small parasitic capacitance and by connecting multiple Schottky diodes in series.
[0021] Furthermore, the drain of switch S3 in this invention is equipped with a "spiking absorption" circuit to effectively absorb the voltage spike generated at switch S3 by switch S2 during switching transients. The "spiking absorption" circuit is a Schottky diode or an RCD spike absorption circuit.
[0022] Furthermore, in the method of the present invention, when switch S1 is open, the subsequent circuit has no V. DD Voltage input, when turned on, the subsequent circuit obtains VDD Voltage input; by controlling the on-time of switch S1, the voltage V that the subsequent circuit can withstand can be adjusted. DD The duration; when switch S1 is on and switch S2 is on, the power inductor L experiences a voltage of V. DD The potential difference causes the current flowing through the inductor to gradually increase over time, satisfying the formula L×di / dt=V. DD When switch S2 is off, there is no high voltage potential difference across inductor L. Since the inductor current cannot change abruptly, it freewheels through the parallel Schottky diode D1. Schottky diode D2 connects the low-voltage side of inductor L to one end of switch S3. Due to its unidirectional conductivity, it is in the off state when the positive terminal potential is low, and will not pull down the potential of its negative terminal (one end of switch S3). This ensures that during the charging of inductor L through switch S2, the potential of one end of switch S3 is reduced through resistor R. C and the conducting S1 withstands high voltage V DD Stress. When switch S3 is off, one end of it is connected to resistor R. C and the conducting S1 withstands high voltage V DD Stress; When switch S3 is turned on, inductor L acts as an inductive load, and its terminals bear V. DD With a potential difference, the current gradually increases and satisfies the formula L×di / dt=V DD When switch S3 is turned off again, inductor L freewheels through Schottky diode D1. By testing the voltage and current of switch S3, its switching transient characteristics and on-resistance characteristics can be obtained.
[0023] To optimize the voltage spike at the drain of the transistor under test during switching transients, reduce the risk of high-voltage breakdown, and improve circuit safety to ensure the safety of experimental personnel and the test system, this invention improves the stability of the drain voltage stress value. The circuit structure of this invention optimizes the circuit from the perspectives of "noise source," "conduction path," and "test endpoint." The optimization principle is to reduce the drain voltage change rate of transistor S2, reduce the parasitic capacitance of Schottky diode D2, and add a "spiking absorption" circuit to the drain of transistor S3. Specifically, this is achieved by using a low-speed silicon-based transistor instead of a high-speed (gallium nitride, silicon carbide, etc.) transistor, while increasing the gate drive resistance of transistor S2 to reduce the switching speed; and by using multiple Schottky diodes in series instead of a single Schottky diode, with the series structure reducing the parasitic capacitance value. C A parallel "spiking absorption" circuit is used to absorb the voltage spike at the drain of the transistor S3 under test. Examples include a Schottky diode or an RCD spike absorption circuit, etc.
[0024] The beneficial effects of this invention are:
[0025] 1. This invention can optimize the voltage spike at the drain of the transistor under test during switching transients, reduce the risk of high-voltage breakdown of the device, improve circuit safety to ensure the safety of experimental personnel and the test system, and improve the stability of the drain voltage stress value. In contrast, the circuit structure proposed in the prior art (CN202511617182.1) has a large voltage spike at the drain of the transistor under test during switching transients, which poses a risk of high-voltage breakdown of the device.
[0026] 2. This invention relates to a transistor testing system and method. The main circuit structure is a switch-resistor series structure, eliminating the direct series connection of two switches. This avoids the safety hazards caused by mis-conduction of series switches, ensuring the safety of experimental personnel and the system. Only three switches, which can be replaced with transistors, are used, significantly simplifying the circuit, reducing complexity, and improving ease of use. In contrast, existing technology (CN202410251482.1) uses a half-bridge structure with two series-connected switches. Under high frequency and high voltage, this structure is prone to mis-conduction due to parasitic parameters, leading to high current, circuit board overheating, and explosion, posing safety risks. Furthermore, its circuit contains five or more transistors, making the structure more complex.
[0027] 3. This invention can test the transient turn-on and steady-state conduction characteristics of switch S3 (or transistor under test) under arbitrary voltage stress values, voltage stress durations, and currents, provided that the measurement delay is on the order of nanoseconds after the drain voltage stress is removed. In contrast, the measurement delay of traditional dual-pulse circuit structures is mostly above 3μs, which cannot accurately characterize the real-time characteristics of the transistor under test after the drain voltage stress is removed. Attached Figure Description
[0028] The invention will be better understood from the following description, which relates to a preferred embodiment given by way of non-limiting example and explained with reference to the accompanying schematic diagram, wherein:
[0029] Figure 1 This is the circuit schematic diagram of the background technology "A high-security transistor test system and method with nanosecond-level delay".
[0030] Figure 2 This is a test flowchart from the background technology "A high-security transistor test system and method with nanosecond-level delay".
[0031] Figure 3 Based on Figure 1 Experimental results for the circuit shown.
[0032] Figure 4 Based on Figure 3 Theoretical analysis of the experimental results shown.
[0033] Figure 5 The circuit schematic of this invention is based on Schemes 1 to 6 in Table 1.
[0034] Figure 6 The circuit diagram of this invention is based on Scheme 7 in Table 1.
[0035] Figure 7 yes Figure 5 and Figure 6 Several other equivalent alternatives to the resistance in the middle.
[0036] Figure 8 Based on Figure 6 An embodiment of the circuit shown.
[0037] Figure 9 Based on Figure 5 The experimental results of various circuits are shown in the comparison diagram. Detailed Implementation
[0038] The present invention will now be described in further detail with reference to the accompanying drawings. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.
[0039] This invention relates to a transistor testing system and method, which, while ensuring the safety of the testing system and experimental personnel, enables the transistor characteristics of the test transistor under arbitrary drain voltage stress values, drain voltage stress durations, and load currents based on nanosecond-level measurement delays.
[0040] Figure 1 This is the circuit schematic of the existing technology "A High-Security Transistor Test System and Method for Nanosecond-Level Delay" (Patent Publication No.: CN 121069149 B). The circuit includes switches S1, S2, and S3, and resistor R. A ,R C Schottky diodes D1 and D2, power inductor L, power supply V DD The control switches S1, S2, and S3 can be selected from transistors such as MOSFETs, JFETs, BJTs, IGBTs, and HEMTs, or relays and gate driver chips can be used. Circuit operating principle: When switch S1 is open, the subsequent circuit has no voltage. DD Input; When S1 is on, the subsequent circuit receives V DD The input, whose conduction time can control the subsequent circuit to withstand high voltage V. DD The duration. When S1 is on and S2 is on, the power inductor L experiences a potential difference V. DD The current flowing through L is calculated using the formula L×di / dt=V DD As the current gradually increases, di / dt represents the rate of change of the current flowing through the inductor with time. When S2 is turned off, since the inductor current cannot change abruptly, the power inductor L freewheels through the parallel Schottky diode D1 (freewheeling diode). Utilizing the unidirectional conductivity of the Schottky diode D2, it is ensured that during the charging of L by S2, its negative terminal (one end of switch S3) flows through resistor R.C and the conducting S1 withstands high voltage V DD Stress. When S3 is turned off, one end is connected to R. C and the conducting S1 withstands V DD Stress; When S3 is turned on, L acts as an inductive load, and its two ends bear V. DD The current gradually increases according to the above formula; when S3 is turned off again, L freewheels through D1. By testing the voltage and current of the transistor S3 under test, its switching transient characteristics, on-resistance characteristics, and other parameters can be obtained.
[0041] Figure 2 This is a test flowchart of the existing technology "A High-Safety Transistor Test System and Method with Nanosecond-Level Delay". It is divided into three stages: 1. Experiment Pre-setting Stage: The pulse widths of pulses 1, 2, and 3 are determined according to the drain voltage stress duration, current value, and turn-on duration of the transistor under test, and the high-voltage power supply parameters are set according to the drain voltage stress value; 2. Test Stage: The high-voltage power supply parameters are set, and pulses 1, 2, and 3 are input to drive the three transistors through the gate drive module. The test system includes a clamping circuit to improve test accuracy; 3. Data Analysis Stage: The voltage and current parameters of the transistor under test are acquired through an oscilloscope, and then its switching transient characteristics and conduction characteristics (conduction resistance) are obtained. After summarizing and organizing, the reliability parameters of the transistor under test under nanosecond-level delay are obtained.
[0042] Figure 3 Based on Figure 1 The experimental results for the circuit shown are as follows. The horizontal axis represents time, and the vertical axis, from top to bottom, represents the gate voltage V of transistor S1. G1 The gate voltage V of transistor S2 G2 The gate voltage V of transistor S3 G3 The drain voltage V of transistor S2 D2 The drain voltage V of transistor S3 D3 The drain-source current I of transistor S2 or S3 DS T1 to T6 are the key time points marked in the diagram. Initially, transistors S1, S2, and S3 are all off, and their gate voltages are all -5 V. At time T1, transistor S1 turns on, and at this time V... D2 V D3 Start bearing voltage V DD (i.e., a voltage stress of 100 V). At time T2, transistor S2 is turned on, and at this time, the drain-source voltage V of transistor S2 is... D2 Reduced to near 0 V, V DD A circuit is formed by transistor S1, power inductor L, and transistor S2. The potential difference across power inductor L is voltage V. DD (i.e., 100 V), satisfying the formula L×di / dt=V DD At this point, the current I in the power inductor can be observed.L Gradually increases. At time T3, transistor S2 is turned off, and voltage V... DD There is no circuit between the power inductor L and the transistor S3, so the power inductor L stops charging. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. At time T4, transistor S3 turns on, and at this time, the drain-source voltage V of transistor S3 is... D3 Reduced to near 0 V, V DD A circuit is formed by transistor S1, power inductor L, Schottky diode D2, and transistor S3. The potential difference across power inductor L is voltage V. DD (i.e., 100 V), satisfying the formula L×di / dt=V DD At this point, the current I in the power inductor can be observed. L The voltage gradually increases. At the instant transistor S3 turns on at time T4, transistor S3 simultaneously experiences a large drain voltage stress V. DD (i.e., 100 V), drain-source current (current I of the power inductor) L This is a hard switch. At time T5, transistor S3 is turned off, and the voltage V... DD There is no loop between the power inductor L and the transistor S1, so the power inductor L stops charging. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. The period between T4 and T5 is the key focus of this experiment. During this time, transistor S3 undergoes hard switching, and the switching transient and conduction steady-state characteristics of transistor S3 are of great significance for evaluating transistor characteristics. At T6, transistor S1 turns off, completing the test.
[0043] The initial intention of this circuit design was to measure the drain V of the transistor S3 under test during the first charging of the power inductor L. D3 It can still withstand stable voltage stress V DD Experimental results show that during the steady-state period of the first charge of the power inductor L, the drain voltage V of the transistor S3 under test is... D3 Stabilized at power supply voltage V DD The expected goal was achieved well. However, during the transient switching of transistor S2, the drain V of the transistor under test S3... D3 Voltage spikes appeared, one decreasing (at time T2) and the other increasing (at time T3). The increasing voltage spike (at time T3) posed the greatest threat to the transistor S3 under test. This high voltage spike could break down the transistor S3, leading to a short circuit in the circuit system and the explosion of components (transistors, capacitors, etc.).
[0044] Figure 4 Based on Figure 3 Theoretical analysis of the experimental results shown. Figure 1 Based on the circuit schematic, the parasitic capacitance C of the Schottky diode D2 was drawn. PParasitic capacitance C P This is introduced during the fabrication of the Schottky diode D2 based on the device structure and manufacturing process. When the drain voltage V of transistor S2... D2 When switching between high and low voltage, the parasitic capacitance C of the Schottky diode D2... P The changing voltage du / dt across the terminals will generate a current i. C Satisfying formula C P ×du / dt=i C Where du / dt is the parasitic capacitance C of the Schottky diode D2. P The rate of change of the voltage across the terminals with time. Current i C Passing through resistor R C Transistor S1 reaches voltage source V DD At this point (the curve marked by the dashed line in the figure), the charge is released. It is worth noting that, due to the circuit design, resistor R... C Typically in the thousands of ohms, the resistance R here is a large value. C Limit the current i C The discharge rate leads to the parasitic capacitance C P The charge release is slow, which in turn leads to a decrease in the drain voltage V of the transistor S3 under test. D3 Voltage spikes appeared, one decreasing (at time T2) and the other increasing (at time T3).
[0045] There are two approaches to further analyze the causes of voltage spikes:
[0046] The first approach involves the parasitic capacitance C. P The changing voltage du / dt across the terminals generates a current i C The current i C After passing through resistor R C A voltage is then generated, which is superimposed on the drain voltage V of the transistor S3 under test. D3 At this point, a voltage spike is generated.
[0047] The second approach involves the resistor R. C Limit the current i C The size, a larger resistance R C This results in a smaller current i C At the same time, the capacitance formula C must be satisfied. P ×du / dt=i C This further leads to a smaller du / dt, meaning the parasitic capacitance C is smaller. P The voltage difference across the two ends will remain within a small range, so when the parasitic capacitance C P When the voltage on the left side decreases (at time T2), the voltage on the right side must also decrease accordingly; when the parasitic capacitance C PWhen the voltage on the left increases (at time T3), the voltage on the right must also increase accordingly.
[0048] Table 1: Several Schemes for Optimizing the Circuit
[0049]
[0050] Table 1 is based on Figure 4 Several optimization schemes are proposed based on theoretical analysis. Figure 4 The drain voltage V of the transistor S3 under test has been analyzed in detail. D3 The cause of the spike, suppressing the drain voltage V of the transistor S3 under test. D3 The key to the peak is to reduce the parasitic capacitance C. P The generated current i C The table proposes the following seven solutions to mitigate the negative impact of noise. Solution 1: Optimize the circuit from the "noise source" perspective. Reduce the drain voltage change rate of transistor S2. Solution 2: Optimize the circuit from the "conduction path" perspective. Reduce the parasitic capacitance of diode D2. Solution 3: Optimize the circuit from the "test endpoint" perspective. Add a "spiking absorption" circuit to the drain of transistor S3 under test. Solution 4: Optimize the circuit from both the "noise source" and "conduction path" perspectives. Reduce the drain voltage change rate of transistor S2. Reduce the parasitic capacitance of Schottky diode D2. Solution 5: Optimize the circuit from both the "noise source" and "test endpoint" perspectives. Reduce the drain voltage change rate of transistor S2. Add a "spiking absorption" circuit to the drain of transistor S3 under test. Solution 6: Optimize the circuit from both the "conduction path" and "test endpoint" perspectives. Reduce the parasitic capacitance of Schottky diode D2. Add a "spiking absorption" circuit to the drain of transistor S3 under test. Solution 7: Optimize the circuit from both the "noise source" and "conduction path" perspectives. Reduce the rate of change of the drain voltage of transistor S2. Reduce the parasitic capacitance of Schottky diode D2. Add a "spiking absorption" circuit to the drain of transistor S3 under test.
[0051] Figure 5 This is a novel circuit schematic proposed based on Schemes 1 to 6 in Table 1.
[0052] Figure (a) shows the circuit optimization from the "noise source". The optimization principle is to reduce the drain voltage change rate of transistor S2. The specific method is to use a low-speed silicon-based transistor instead of a high-speed (gallium nitride, silicon carbide, etc.) transistor. At the same time, the gate drive resistance of transistor S2 is increased to reduce the switching speed.
[0053] Figure (b) shows the circuit optimized from the "conduction path". The optimization principle is to reduce the parasitic capacitance of diode D2. The specific implementation method is to replace a single Schottky diode with multiple Schottky diodes connected in series. The series structure reduces the value of parasitic capacitance.
[0054] Figure (c) shows the optimized circuit from the "test endpoint". The optimization principle is to add a "spiking absorption" circuit to the drain of the transistor S3 under test. The specific implementation method is R C A parallel "spiking absorption" circuit is used to absorb the voltage spike at the drain of the transistor S3 under test. Examples include a Schottky diode or an RCD spike absorption circuit, etc.
[0055] Figure (d) shows the circuit optimization from the perspective of "noise source" + "conduction path". The optimization principle is to reduce the drain voltage change rate of transistor S2 and reduce the parasitic capacitance of Schottky diode D2. Specifically, this is achieved by using a low-speed silicon-based transistor instead of a high-speed (gallium nitride, silicon carbide, etc.) transistor. Simultaneously, the gate drive resistance of transistor S2 is increased to reduce the switching speed. Multiple Schottky diodes are connected in series instead of a single Schottky diode. This series structure reduces the parasitic capacitance value.
[0056] Figure (e) shows the circuit optimization from the "noise source" + "test endpoint". The optimization principle is to reduce the drain voltage change rate of transistor S2. A "spiking absorption" circuit is added to the drain of transistor S3 under test. Specifically, a low-speed silicon-based transistor is used instead of a high-speed (gallium nitride, silicon carbide, etc.) transistor. At the same time, the gate drive resistance of transistor S2 is increased to reduce the switching speed. C A parallel "spiking absorption" circuit is used to absorb the voltage spike at the drain of the transistor S3 under test. Examples include a Schottky diode or an RCD spike absorption circuit, etc.
[0057] Figure (f) shows the circuit optimization from the perspective of "conduction path" + "test endpoint". The optimization principle is to reduce the parasitic capacitance of the Schottky diode D2. A "spiking absorption" circuit is added to the drain of the transistor under test S3. Specifically, this is achieved by replacing a single Schottky diode with multiple Schottky diodes connected in series. This series structure reduces the parasitic capacitance value. R C A parallel "spiking absorption" circuit is used to absorb the voltage spike at the drain of the transistor S3 under test. Examples include a Schottky diode or an RCD spike absorption circuit, etc.
[0058] Figure 6 This is a novel circuit schematic proposed based on Scheme 7 in Table 1. It optimizes the circuit from the perspectives of "noise source," "conduction path," and "test endpoint." The optimization principle is to reduce the drain voltage change rate of transistor S2, reduce the parasitic capacitance of Schottky diode D2, and add a "spiking absorption" circuit to the drain of transistor S3 under test. Specifically, it uses a low-speed silicon-based transistor instead of a high-speed (gallium nitride, silicon carbide, etc.) transistor. Simultaneously, it increases the gate drive resistance of transistor S2 to reduce the switching speed. Multiple Schottky diodes are connected in series instead of a single Schottky diode. This series structure reduces the parasitic capacitance value. R CA parallel "spiking absorption" circuit is used to absorb the voltage spike at the drain of the transistor S3 under test. Examples include a Schottky diode or an RCD spike absorption circuit, etc.
[0059] Figure 7 yes Figure 5 and Figure 6 Several other equivalent alternatives to silicon resistors are shown. In integrated circuit design, due to various considerations, silicon resistors are often not fabricated on the chip; instead, other electronic components are used to generate the equivalent resistance. This diagram is intended to illustrate... Figure 5 and Figure 6 The resistor in the image can be replaced by various equivalent devices, but as long as it functions as a resistor, it can be considered as such. Figure 5 and Figure 6 The same circuit. Figure 7 Several methods for equating other electronic components to resistors are demonstrated, with only a few examples listed. (a) An enhancement-mode PMOS with its gate and drain shorted as a load, (b) An enhancement-mode PMOS with its gate voltage fixed as a load, (c) An enhancement-mode NMOS with its gate and drain shorted as a load, and (d) A depletion-mode NMOS with its gate and source shorted as a load.
[0060] Figure 8 Based on Figure 6 The circuit shown is an example of an embodiment. Based on their functions, the power circuit can be divided into three parts: a voltage stress value and stress duration control module, a current control module, and a transient and on-resistance testing module.
[0061] The voltage stress value and stress duration control module includes an NMOS power transistor Q. A and resistance R A Among them, the NMOS power transistor Q A The source and resistor R A One end is connected to form a common terminal with V SA Connection, NMOS power transistor Q A Drain connection V DD Terminal, its gate is connected to V GA resistance R A The other end is grounded.
[0062] The current control module includes NMOS power transistor Q. B Schottky diodes D1 and D2, and power inductor L. The NMOS transistor Q... B The drain of the inductor is connected to one end of the power inductor L and the common terminal of the positive terminals of Schottky diodes D1 and D2. The other end of the power inductor L and the negative terminal of Schottky diode D1 are connected to the transistor Q of the voltage stress value and stress duration control module. A The source and V SAThe common connection terminals are connected; NMOS transistor Q B The source of the NMOS transistor is grounded; B gate connection V GB Terminal. Among them, the NMOS power transistor Q B For slow-switching transistors, the Schottky diode D2 is one or more connected in series to reduce parasitic capacitance.
[0063] The power circuit section of the transient and on-resistance testing module includes the NMOS power transistor Q. C Schottky diode D3, resistor R C And the clamping circuit. Among them, resistor R... C With NMOS transistor Q C The drain connection forms a common terminal that is connected to the cathode of the Schottky diode D2 in the current control module, and is connected to V. DC Connection; Resistor R C The other end connects to the cathode of the Schottky diode D1 in the current control module, the power inductor L, and the resistor R in the voltage stress value and stress duration control module. A One end, NMOS transistor Q A The source, V SA The common connection terminals are connected. The positive terminal of the Schottky diode D3 is connected to the NMOS transistor Q. C Drain, resistor R C One end of the diode is connected to the cathode of Schottky diode D2. The cathode of Schottky diode D3 is connected to resistor R. C The other end, the negative terminal of the Schottky diode D1 in the current control module, the power inductor L, and the resistor R in the voltage stress value and stress duration control module. A One end, NMOS transistor Q A The source, V SA The common connection terminals are connected. NMOS transistor Q C gate connection V GC NMOS power transistor Q C The NMOS transistor Q in the source-connected current control module B The source electrode and the resistor R of the voltage stress value and stress duration control module A One end. NMOS power transistor Q C The drain of the diode is connected to the negative terminal of Schottky diode D2, the positive terminal of Schottky diode D3, and the resistor R. C One end of the NMOS transistor Q. B The source and NMOS transistor Q C The common connection terminal of the source is connected to the resistor R. C One end, NMOS transistor Q CA clamping circuit is provided between the common connection terminal of the drain of the diode and the negative terminal of the Schottky diode D2.
[0064] The circuit working principle in this embodiment is as follows:
[0065] For the voltage stress value and stress duration control module, when Q A When V is turned off SA The voltage is 0 volts, and there is no high-voltage input to the subsequent circuit. When Q... A When conducting V SA2 The voltage is the supply voltage V of the high-voltage power supply. DD The subsequent circuit receives a high-voltage input. This controls the upper transistor Q. A The conduction time can control the voltage V that the subsequent circuit can withstand. DD Duration.
[0066] For the current control module, when transistor Q B When the circuit is turned on, the potential difference V across the power inductor L is... DD The current flowing through the power inductor L gradually increases, satisfying the formula L×di / dt=V DD When transistor Q B When switched off, there is no high voltage potential difference across the power inductor L. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. Therefore, the Schottky diode D1 is also called a freewheeling diode. The Schottky diode D2 is used to connect the low-voltage side of the power inductor L to the transistor Q under test. C Drain. Due to the unidirectional conductivity of the Schottky diode D2, when the positive potential of the Schottky diode D2 is low, it is in the cutoff state and will not drain the negative terminal of the Schottky diode D2 (the transistor Q under test). C The drain potential is pulled low to ensure that the power inductor L passes through the transistor Q. B During charging, the negative terminal of Schottky diode D2 (transistor Q under test) C The drain remains (through resistor R) C and the conducting Q A ) withstand high voltage V DD Voltage stress. Transistor Q B Slow-switching transistors are selected to reduce transistor Q during switching transients. B The rate of voltage change at the drain (positive terminal of Schottky diode D2) reduces the current generated at the parasitic capacitance of Schottky diode D2 due to this voltage change. Multiple Schottky diodes are connected in series to reduce the parasitic capacitance at Schottky diode D2, thereby reducing the current generated at the parasitic capacitance of Schottky diode D2 due to the voltage change at its positive terminal.
[0067] For transient and on-resistance testing modules, when Q...C Q when turned off C The drain is connected to resistor R C and the conducting Q A Withstand stable high voltage V DD When Q C When switched on, the power inductor L acts as an inductive load in the circuit, and the potential difference V across the power inductor L is... DD The current flowing through the power inductor L gradually increases, satisfying the formula L×di / dt=V DD When transistor Q C When turned off, there is no high voltage potential difference across the power inductor L. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. Transistor Q B During switching transients, the transistor Q under test will be... C Voltage spikes are generated at the drain. Using a spike absorption circuit can effectively absorb high-voltage spikes, thereby protecting the transistor under test, Q. C It will not break down. The voltage spike absorption circuit shown in the figure is a Schottky diode D3. According to experimental principles, this can be any other type of voltage spike absorption circuit. The clamping circuit is used to improve the Q of the transistor under test. C The accuracy of drain voltage testing will not be discussed further here. Testing the transistor Q under test. C From the gate voltage, drain voltage, and drain-source current, we can determine the transistor Q under test. C The transient characteristics and on-resistance characteristics of the switch during hard switching testing.
[0068] Figure 9 Based on Figure 5 The graph shows a comparison of experimental results for various circuits. The horizontal axis represents time, and the vertical axis, from top to bottom, represents the transistor Q. B Gate voltage V GB transistor Q C Gate voltage V GC transistor Q B Drain voltage V DB transistor Q B Or Q C Drain-source current I DS In scheme 0, transistor Q C Drain voltage V DC0 In Scheme 2, transistor Q C Drain voltage V DC2 In Scheme 3, transistor Q C Drain voltage V DC3 In Scheme 6, transistor Q C Drain voltage V DC6 T1 to T6 are the key time points marked in the diagram. Initial stage transistor Q... AQ B Q C Both transistors are off, and their gate voltages are -5 V. At time T1, transistor Q... A When it is turned on, V DB V DC Start bearing voltage V DD (i.e., a voltage stress of 100 V). At time T2, transistor Q... B When the transistor Q is turned on, it conducts. B Drain-source voltage V DB Reduced to near 0 V, V DD After transistor Q A Power inductor L, transistor Q B A circuit is formed, and the potential difference across the power inductor L is the voltage V. DD (i.e., 100 V), satisfying the formula L×di / dt=V DD At this point, the current flowing through transistor Q can be observed. B Or Q C Drain-source current I DS Gradually increases. At time T3, transistor Q... B Off, voltage V DD There is no circuit between the power inductor L and the transistor Q, so the power inductor L stops charging. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. At time T4, transistor Q... C When the transistor Q is turned on, it conducts. C Drain-source voltage V DC Reduced to near 0 V, V DD After transistor Q A Power inductor L, Schottky diode D2, transistor Q C A circuit is formed, and the potential difference across the power inductor L is the voltage V. DD (i.e., 100 V), satisfying the formula L×di / dt=V DD At this point, the current flowing through transistor Q can be observed. B Or Q C Drain-source current I DS Gradually increases. At time T4, transistor Q... C At the moment of conduction, transistor Q C Simultaneously withstands large drain voltage stress V DD (i.e., 100 V), drain-source current (current I of the power inductor) L This is a hard switch. At time T5, transistor Q... C Off, voltage V DDThere is no circuit between the power inductor L and the circuit, so the power inductor L stops charging. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. The period from time T4 to time T5 is the key focus of this experiment, during which transistor Q... C After hard switching, transistor Q C The switching transient and conduction steady-state characteristics are of great significance for evaluating transistor performance. At time T6, transistor Q... A Off, V DB V DC The voltage gradually decreased, completing the test.
[0069] This diagram primarily considers the scenario where transistor Q... B "Several optimization schemes when high-speed devices must be used", therefore no comparison transistor Q is provided. B The circuit structure is used for slow switching. The comparison focuses on the transistor Q under the circuit structures of schemes 0, 2, 3, and 6 presented in the table. C Drain voltage V DC0 V DC2 V DC3 V DC6 Option 0 corresponds to Figure 1 The circuit shown is the unoptimized circuit; Scheme 2 corresponds to the circuit optimized from the "conduction path" (reducing the parasitic capacitance of diode D2); Scheme 3 corresponds to the circuit optimized from the "test endpoint" (adding a "spiking absorption" circuit to the drain of transistor S3 under test); Scheme 6 corresponds to the circuit optimized from both the "conduction path" and the "test endpoint" (reducing the parasitic capacitance of Schottky diode D2 + adding a "spiking absorption" circuit to the drain of transistor S3 under test). The results show that in Scheme 0, without any optimization, transistor Q... C Drain voltage V DC0 The oscillation spike is most severe at this point. Scheme 2, which optimizes the circuit from the "conduction path" (reducing the parasitic capacitance of diode D2), can slightly reduce the transistor Q. C Drain voltage V DC2 The oscillation spike at the point. The structure of Scheme 3, which optimizes the circuit from the "test endpoint" (adding a "spike absorption circuit" to the drain of the transistor S3 under test), can significantly reduce the transistor Q. C Drain voltage V DC3 The oscillation spike at the point. Scheme 6, with its optimized circuit structure from the "conduction path" + "test endpoint" (reducing the parasitic capacitance of Schottky diode D2 + adding a "spike absorption circuit" to the drain of transistor S3 under test), can significantly reduce the transistor Q. C Drain voltage V DC6 The best results are achieved at the oscillation peak.
[0070] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A transistor testing system, characterized in that, The test system includes switches S1, S2, and S3, and resistor R. A ,R C Schottky diodes D1, D2, D3; power inductor L; power supply V. DD ; Wherein: one end of switch S1 is connected to power supply V. DD The other end of switch S1 is connected to resistor R. A One end of the circuit, the cathode of Schottky diode D1, one end of power inductor L, the cathode of Schottky diode D3, and resistor R. C One end, resistor R A The other end is connected to GND. The positive terminal of Schottky diode D1 is connected to the other end of power inductor L, one end of switch S2, and the positive terminal of Schottky diode D2. The other end of switch S2 is connected to GND. The negative terminal of Schottky diode D2 is connected to the positive terminal of Schottky diode D3 and resistor R. C The other end of the switch is connected to GND.
2. The transistor testing system according to claim 1, characterized in that, The control switches S1, S2, and S3 are either MOSFETs, JFETs, BJTs, IGBTs, HEMTs, or relays or gate drive chips; the resistors can be replaced by various equivalent devices, including but not limited to: (a) an enhancement-mode PMOS with its gate and drain shorted, (b) an enhancement-mode PMOS with its gate voltage fixed, (c) an enhancement-mode NMOS with its gate and drain shorted, or (d) a depletion-mode NMOS with its gate and source shorted.
3. A transistor testing method, characterized in that, The system described in claim 1 or 2 is implemented by comprising the following steps: 1) Determine the stress duration of switch S3 under voltage stress, and thereby determine the conduction duration of switch S1; 2) Determine the initial current value at the instant switch S3 is closed, and thereby determine the conduction time of switch S2; 3) Then, determine the conduction time of switch S3 based on the experimental objectives; 4) Then determine the stress value when switch S3 is open, and thereby determine the parameters required for the high-voltage power supply; 5) Set the high-voltage power supply parameters and control the switching states of switches S1, S2, and S3 in sequence; 6) Obtain the voltage and current parameters of switch S3 using an oscilloscope; 7) Obtain the transient and conduction characteristics of switch S3 from the voltage and current parameters; 8) Finally, the reliability parameters of switch S3 under nanosecond-level delay are obtained.
4. The transistor testing method according to claim 3, characterized in that, Switch S2 is a slow switch, meaning that the drain voltage of switch S2 changes slowly during the switching transient. This is achieved by selecting a transistor with slow switching and increasing the gate drive resistance of switch S2.
5. A transistor testing method according to claim 3, characterized in that, The parasitic capacitance of Schottky diode D2 is very small. The parasitic capacitance can be reduced by selecting Schottky diodes with very small parasitic capacitance or by connecting multiple Schottky diodes in series.
6. A transistor testing method according to claim 3, characterized in that, A "spiking absorption" circuit is added to the drain of switch S3 to effectively absorb the voltage spike generated at switch S3 by switch S2 during switching transients. The "spiking absorption" circuit is a Schottky diode or an RCD spike absorption circuit.
7. A transistor testing method according to claim 3, characterized in that, When switch S1 is open, there is no voltage in the subsequent circuit. DD Voltage input, when turned on, the subsequent circuit obtains V DD Voltage input; by controlling the on-time of switch S1, the voltage V that the subsequent circuit can withstand can be adjusted. DD The duration; when switch S1 is on and switch S2 is on, the power inductor L experiences a voltage of V. DD The potential difference causes the current flowing through the inductor to gradually increase over time, satisfying the formula L×di / dt=V. DD When switch S2 is off, there is no high voltage potential difference across inductor L. Since the inductor current cannot change abruptly, it freewheels through the parallel Schottky diode D1. Schottky diode D2 connects the low-voltage side of inductor L to one end of switch S3. Due to its unidirectional conductivity, it is in the off state when the positive potential is low, and will not pull down the potential at one end of switch S3. This ensures that during the charging of inductor L through switch S2, the potential at one end of switch S3 is reduced through resistor R. C and the conducting S1 withstands high voltage V DD Stress; When switch S3 is turned off, one end of it passes through resistor R C and the conducting S1 withstands high voltage V DD Stress; When switch S3 is turned on, inductor L acts as an inductive load, and its terminals bear V. DD With a potential difference, the current gradually increases and satisfies the formula L×di / dt=V DD When switch S3 is turned off again, inductor L freewheels through Schottky diode D1. By testing the voltage and current of switch S3, its switching transient characteristics and on-resistance characteristics can be obtained.
8. A transistor testing method according to claim 3, characterized in that, By reducing the drain voltage change rate of transistor S2, reducing the parasitic capacitance of Schottky diode D2, and adding a "spiking absorption" circuit to the drain of transistor S3 under test; specifically, this is achieved by using a low-speed silicon-based transistor, while increasing the gate drive resistance of transistor S2 to reduce the switching speed; and by using multiple Schottky diodes in series instead of a single Schottky diode, with the series structure reducing the parasitic capacitance value; R C A parallel "spiking absorption" circuit is used to absorb the voltage spike at the drain of the transistor S3 under test.
9. A transistor testing method according to claim 3, characterized in that, Under the premise of nanosecond-level measurement delay after the drain voltage stress is removed, test the transient and steady-state characteristics of switch S3 at arbitrary voltage stress values, voltage stress durations, and currents.