Power supply output voltage overshoot suppression control circuit

Abstract

The utility model discloses a power supply output voltage overshoot suppression control circuit, which comprises an operational amplifier U15 and a plurality of differential sampling resistors, the plurality of differential sampling resistors are a resistor R52, a resistor R56, a resistor R58 and a resistor R64, a pin 3 and a pin 4 of the operational amplifier U15 are connected with output voltage Vo + and Vo-through the resistor R56 and the resistor R58, and the operational amplifier U15 is connected with the output voltage Vo + and the output voltage Vo-through the resistor R56 and the resistor R58. A pin 5 of the operational amplifier U15 is connected with a power supply voltage Vcs5V and a power supply end capacitor C81, a pin 1 of the operational amplifier U15 outputs a voltage signal Vos through a first-order low-pass RC filter, an operational amplifier feedback capacitor C71 is connected between a pin 4 and the pin 1 of the operational amplifier U15, and two ends of the operational amplifier feedback capacitor C71 are connected in parallel with a differential sampling resistor R64. According to the utility model, the large drop of the output voltage of the module after wave sealing is greatly avoided, the under-voltage protection is not easy to trigger, and the drop of the output voltage to zero under the full-load working condition caused by the slow increase of the duty ratio after zero clearing is avoided.

Description

Technical Field

[0001] This utility model relates to a control circuit, specifically a power supply output voltage overshoot suppression control circuit. Background Technology

[0002] In military and industrial production, there is a huge demand for high power density and high reliability DC / DC module power supplies. However, when the input is dynamically switched from Vin_min to Vin_max or from full load to no load, the output voltage of the module power supply has a large overshoot, which frequently triggers overvoltage protection and reduces the reliability of the power supply.

[0003] The current approach is:

[0004] 1. Output overvoltage protection is adopted, and the overvoltage protection point is a fixed value. When the input dynamic Vin_min switches to Vin_max or the full load switches to no load, the output voltage has a large overshoot behavior, which can easily trigger the overvoltage protection. The module frequently triggers the overvoltage protection, which greatly reduces the stability of the product.

[0005] 2. Increasing the overvoltage protection time suppresses overvoltage protection by extending the timer setting when the output voltage reaches the protection point. However, this significantly increases the voltage stress on the secondary rectifier diodes, potentially causing device damage. Furthermore, extending the overvoltage protection time during dynamic Vin_min to Vin_max switching at the input and full-load output can lead to short-term over-power operation of the power supply module, drastically reducing reliability.

[0006] 3. The system employs overvoltage protection and a zero-duty-cycle blocking mode. When the voltage overshoot reaches the overvoltage protection value, the main power PWM is turned off and the pulse width is cleared. When the voltage drops to the voltage recovery value, the main power PWM is cleared and slowly turned on. However, when the input is dynamically switching between Vin_min and Vin_max and the system is operating at full load, the voltage blocking can cause a significant drop in output voltage, even to zero, and can easily trigger output undervoltage protection, greatly reducing the stability of the product output. Utility Model Content

[0007] To address the issue of unstable output voltage overshoot, this invention provides a power supply output voltage overshoot suppression control circuit.

[0008] This utility model provides the following technical solution:

[0009] An overshoot suppression control circuit for power output voltage includes an operational amplifier U15 and multiple differential sampling resistors, namely resistors R52, R56, R58, and R64. Pins 3 and 4 of the operational amplifier U15 are connected to the output voltages Vo+ and Vo- through resistors R56 and R58, respectively. Pin 5 of the operational amplifier U15 is connected to the supply voltage Vcs_5V and the supply capacitor C81. Pin 1 of the operational amplifier U15 outputs the voltage signal Vo_s through a first-order low-pass RC filter. An operational amplifier feedback capacitor C71 is connected between pins 4 and 1 of the operational amplifier U15, and the differential sampling resistor R64 is connected in parallel across the operational amplifier feedback capacitor C71.

[0010] Furthermore, the first-order low-pass RC filter consists of a resistor R57 and a capacitor C68.

[0011] Furthermore, pin 3 of the operational amplifier U15 is also connected to a parallel circuit of resistor R52 and capacitor C65.

[0012] Furthermore, the operational amplifier U15 samples the output voltage Vo, where Vo is the difference between Vo+ and Vo-, and the operational amplifier U15 samples the output voltage Vo1.

[0013] Furthermore, the operational amplifier U15 is model RS721PXF.

[0014] The main implementation steps are as follows:

[0015] The DSP's overvoltage protection point is initialized to 14.3V upon power-up, with a peak value of 14.5V and a peak recovery value of 14.2V. An ADC conversion is triggered every 100ns, and the program performs a conversion every 100ms and checks if the output voltage reaches the overvoltage point. If the output voltage exceeds the overvoltage point for 2ms, overvoltage protection is triggered. Under normal conditions, the output voltage will not exceed 12.12V, and the program loops repeatedly at this point. When the input fluctuates, if Vin_min switches to Vin_max under full load, the input voltage rises rapidly, and the transmission duty cycle does not decrease in time, leading to a significant overshoot in the output voltage. When switching from full load to no load, the output voltage will also overshoot. When the output voltage overshoots to the peak value, the overvoltage protection is not triggered due to the short duration, but peak sealing is triggered. The DSP shuts down the driving PWM wave. When the voltage recovers below the peak recovery value, the DSP provides a fixed duty cycle Dset, which is then incremented or adjusted based on Dset.

[0016] Compared with the prior art, the beneficial effects of this utility model are: the power output voltage overshoot suppression control circuit of this utility model includes an operational amplifier U15 and multiple differential sampling resistors. A first-order low-pass RC filter is used to filter out high-frequency components in the output signal. The suppression control circuit samples the output DC voltage, which greatly avoids the module output voltage from dropping significantly after the waveform is blocked, and it is not easy to trigger the undervoltage protection. It also avoids the output voltage from dropping to zero under full load conditions due to the slow increase after the duty cycle is cleared to zero. Attached Figure Description

[0017] Figure 1 This is a flowchart of the overvoltage protection process of this utility model;

[0018] Figure 2 This is a flowchart of the wave blocking protection process of this utility model;

[0019] Figure 3 This is the circuit diagram for the suppression control of this utility model. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Please see Figure 1-3 This utility model discloses a power supply output voltage overshoot suppression control circuit, including an operational amplifier U15 and multiple differential sampling resistors, namely resistors R52, R56, R58, and R64. Pins 3 and 4 of the operational amplifier U15 are connected to the output voltages Vo+ and Vo- through resistors R56 and R58. Pin 5 of the operational amplifier U15 is connected to the supply voltage Vcs_5V and the supply capacitor C81. Pin 1 of the operational amplifier U15 outputs the voltage signal Vo_s through a first-order low-pass RC filter. An operational amplifier feedback capacitor C71 is connected between pins 4 and 1 of the operational amplifier U15. The differential sampling resistor R64 is connected in parallel across the operational amplifier feedback capacitor C71.

[0022] A first-order low-pass RC filter consists of a resistor R57 and a capacitor C68.

[0023] Pin 3 of operational amplifier U15 is also connected to a parallel circuit of resistor R52 and capacitor C65.

[0024] Operational amplifier U15 samples the output voltage Vo, where Vo is the difference between Vo+ and Vo-, and operational amplifier U15 samples the output voltage Vo1.

[0025] The core controller DSP used in this application is TMS320F28035, which is connected via an appendix. Figure 3 The suppression control circuit shown, composed of operational amplifier U15, samples the output voltage Vo. Here, Vcs_5V is the op-amp's supply voltage, C81 is the op-amp's power supply capacitor, Vo is the difference between Vo+ and Vo-, resistors R52, R56, R58, and R64 are differential sampling resistors, the op-amp samples the output voltage Vo1 as ((Vo+)-(Vo-))*27 / 120, C71 is the op-amp feedback capacitor used to increase the loop's phase margin, R57 and C68 are first-order low-pass RC filters used to filter out high-frequency components in the output signal, and Vo_s is the output voltage signal obtained by the ADC sampling. Since the suppression control circuit samples the output DC voltage, the value of Vo_s is Vo*27 / 120.

[0026] The suppression control circuit composed of operational amplifier U15 monitors and collects the output voltage in real time, converts it into a voltage signal (i.e., Vo_s analog quantity) adapted to the DSP ADC sampling port, sends the sampled analog quantity to the DSP ADC sampling port, and performs AD conversion (i.e., analog-to-digital conversion, converting the analog quantity Vo_s into a digital quantity). The digital quantity is then processed and compared internally by the DSP to control the effective transmission duty cycle, thereby controlling the output voltage, blocking protection, etc.

[0027] Figure 3 In this context, the Vo_s signal will be sent to the DSP's ADC sampling port, i.e. Figure 3 The rightmost output Vo_s signal in the diagram is used as the input signal for the DSP.

[0028] The main implementation steps are as follows:

[0029] The DSP power-on output overvoltage protection point is initialized to 14.3V, the surge cap value is 14.5V, and the surge cap recovery value is 14.2V. An ADC conversion is triggered every 100ns. The program performs a conversion every 100ms and checks if the output voltage reaches the overvoltage point. If the output voltage exceeds the overvoltage point for 2ms, overvoltage protection is triggered. Under normal conditions, the output voltage will not exceed 12.12V, and the program loops repeatedly at this point. When the input fluctuates, if the input voltage rises rapidly when Vin_min switches to Vin_max under full load conditions, and the duty cycle is not reduced in time, the output voltage will overshoot significantly. When switching from full load to no load, the output voltage will also overshoot. When the output voltage overshoots to the PWM blocking point, the overvoltage protection is not triggered due to the short time, but the PWM blocking is triggered. The DSP shuts down the drive PWM wave. When the voltage recovers to below the PWM blocking recovery value, the DSP provides a fixed duty cycle Dset (the size of which is the duty cycle of the no-load output under the maximum input voltage), and increments or adjusts it based on Dset. This will prevent the output voltage from dropping to zero under full load conditions due to the slow increase of the duty cycle after it is cleared to zero.

[0030] This utility model is equipped with both overvoltage protection and wave blocking protection modes.

[0031] Figure 1 The overvoltage protection flowchart is shown below, and the steps are as follows:

[0032] S1. Beginning;

[0033] S2. Initialize and configure the ADC peripheral of the DSP;

[0034] S3. ADC sampling voltage;

[0035] S4. Determine if the sampling voltage exceeds 14.3V:

[0036] If the overvoltage period is exceeded, start the timer, accumulate the overvoltage time, and then execute step S5;

[0037] If the timeout is not exceeded, the timer is turned off, the accumulated overvoltage time is cleared to 0, and the process ends.

[0038] S5. Determine if the set overvoltage protection time of 42ms has been exceeded:

[0039] If the limit is exceeded, the protection mechanism is activated, the PWM driver is reset to null, and the process ends.

[0040] If the voltage is not exceeded, return to step S3 to continue sampling the voltage.

[0041] Figure 2 The flowchart for wave blocking protection is shown below, and the steps are as follows:

[0042] S1. Beginning;

[0043] S2. Initialize and configure the ADC peripheral of the DSP;

[0044] S3. ADC sampling voltage;

[0045] S4. Determine if the sampling voltage exceeds 14.5V:

[0046] If the limit is exceeded, immediately perform wave blocking, clear the PWM duty cycle to zero, and then proceed to step S5;

[0047] If the time limit is not exceeded, proceed directly to step S5;

[0048] S5. Determine if the sampling voltage is below 14.2V:

[0049] If it is lower than the threshold, immediately shut down the wave blocking; if it is not lower than the threshold, calculate Dbeat.

[0050] S6. PWM resumes with Dbeat as the initial duty cycle, and the process ends.

[0051] Dset (the duty cycle is the duty cycle of the no-load output under the maximum input voltage), which is a fixed duty cycle. The size of Dset is set as described in the patent protection content above.

[0052] This invention simultaneously sets up overvoltage protection and surge protection modes, with the surge protection value higher than the overvoltage protection value. When the output voltage overshoots to the protection value, the overvoltage protection is not triggered due to the short time. When the surge protection value is reached, the DSP quickly shuts off the PWM. When the voltage drops to the surge protection recovery value, it is reset to zero. Immediately afterwards, the DSP provides a fixed duty cycle Dset (the size of which is the duty cycle of the no-load output under the maximum input voltage). Experimental verification shows that when Dset is small, surge protection still causes a large drop in output voltage. When Dset is large, it causes overshoot and overextension of output voltage during surge protection recovery. Therefore, only when Dset is the duty cycle of the no-load output under the maximum input voltage will there be no large drop or overshoot during surge protection. Furthermore, Dset is incremented or adjusted based on Dset. This avoids the output voltage dropping to zero under full load conditions due to the slow increase of the duty cycle after it is reset to zero.

[0053] Compared with traditional protection blocking, the DSP program only needs to directly give a fixed duty cycle Dset (the size of which is the duty cycle of the no-load output under the maximum input voltage) when the output voltage reaches the blocking recovery value after the blocking value is triggered and cleared to zero. The Dset can be incremented or adjusted, which can greatly avoid the module output voltage dropping too much after blocking and make it less likely to trigger undervoltage protection.

[0054] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power supply output voltage overshoot suppression control circuit, characterized in that: The system includes an operational amplifier U15 and multiple differential sampling resistors, namely resistors R52, R56, R58, and R64. Pins 3 and 4 of the operational amplifier U15 are connected to the output voltages Vo+ and Vo- through resistors R56 and R58, respectively. Pin 5 of the operational amplifier U15 is connected to the supply voltage Vcs_5V and the supply capacitor C81. Pin 1 of the operational amplifier U15 outputs the voltage signal Vo_s through a first-order low-pass RC filter. The operational amplifier feedback capacitor C71 is connected between pins 4 and 1 of the operational amplifier U15, and the differential sampling resistor R64 is connected in parallel across the operational amplifier feedback capacitor C71.

2. The power supply output voltage overshoot suppression control circuit according to claim 1, characterized in that: The first-order low-pass RC filter consists of a resistor R57 and a capacitor C68.

3. The power supply output voltage overshoot suppression control circuit according to claim 1, characterized in that: Pin 3 of the operational amplifier U15 is also connected to a parallel circuit of resistor R52 and capacitor C65.

4. The power supply output voltage overshoot suppression control circuit according to claim 1, characterized in that: The operational amplifier U15 samples the output voltage Vo, where Vo is the difference between Vo+ and Vo-, and the operational amplifier U15 samples the output voltage Vo1.

5. The power supply output voltage overshoot suppression control circuit according to claim 1, characterized in that: The operational amplifier U15 is model RS721PXF.

Images