Systems and methods for GAN lossless current sensing for use in motor drive circuits

Abstract

The invention relates to a system and method for GaN lossless current sensing for use in a motor drive circuit. A circuit is disclosed that includes a first switch having a first source terminal and a first drain terminal; and a second switch having a second source terminal and a second drain terminal, the second drain terminal being connected to the first drain terminal, and the second source terminal being connected to the first source terminal. In one aspect, the second switch is arranged to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal. In another aspect, a sensing circuit is arranged to receive the first signal and to determine an amplitude and polarity of the current flowing from the first source terminal to the first drain terminal, the sensing circuit being further arranged to transmit a second signal based on the first signal.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 683,945, filed August 16, 2024, entitled “System and methods for GaN lossless current sensing used in Motor Drive Circuits,” which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The described implementations generally relate to power converters, and more specifically, this implementation relates to systems and methods for lossless current sensing of gallium nitride (GaN) for motor drive circuits. Background Technology

[0004] Electronic devices such as computers, servers, and televisions use one or more power conversion circuits to convert one form of electrical energy into another. Some power conversion circuits use circuit topologies called DC-DC converters to convert high (or low) DC voltages to lower (or higher) DC voltages. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, newer power converters can offer relatively high efficiency and a smaller size for newer electronic devices. Summary of the Invention

[0005] In some embodiments, a circuit is disclosed. The circuit includes a first switch having a first source terminal and a first drain terminal; a second switch having a second source terminal and a second drain terminal, the second drain terminal connected to the first drain terminal and the second source terminal connected to the first source terminal, wherein the second switch is arranged to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal; and a sensing circuit arranged to receive the first signal and determine the amplitude and polarity of the current flowing from the first source terminal to the first drain terminal, the sensing circuit being further arranged to transmit a second signal based on the first signal.

[0006] In some implementations, the first switch is a gallium nitride (GaN) based switch.

[0007] In some implementations, the second switch is a GaN-based switch.

[0008] In some implementations, the first switch and the second switch are monolithically formed on a single die.

[0009] In some embodiments, the circuit further includes a third switch having a third source terminal and a third drain terminal, the third source terminal being connected to the first drain terminal and connected to a first terminal of the load, and the third drain terminal being connected to a power input node.

[0010] In some embodiments, the circuit further includes a fourth switch having a fourth source terminal and a fourth drain terminal, the fourth drain terminal being connected to the third drain terminal, and the fourth source terminal being connected to the third source terminal.

[0011] In some implementations, the load is a motor.

[0012] In some embodiments, the first switch and the second switch are formed on a gallium nitride (GaN)-based die, and the sensing circuit is formed on a silicon-based die, wherein the GaN-based die and the silicon-based die are co-packaged in a single semiconductor die.

[0013] In some embodiments, the circuit further includes an overcurrent protection circuit arranged to receive the second signal, compare the second signal with a first threshold, and generate a disconnect signal when the second signal exceeds the first threshold.

[0014] In some embodiments, a level shifting circuit is disclosed. The level shifting circuit includes a transmitting circuit; a receiving circuit; and a first level shifting switch and a second level shifting switch; wherein the transmitting circuit is formed on a first silicon-based die, the receiving circuit is formed on a second silicon-based die, and the first level shifting switch and the second level shifting switch are formed on a gallium nitride (GaN)-based die.

[0015] In some implementations, the first silicon-based die, the second silicon-based die, and the GaN-based die are co-packaged in a single semiconductor package.

[0016] In some implementations, the source terminal of the first level shifting switch is connected to the source terminal of the second level shifting switch and connected to a current source.

[0017] In some implementations, the current source is disposed on the first silicon-based die.

[0018] In some implementations, the level shifting circuit further includes a common-mode feedback circuit.

[0019] In some embodiments, during manufacturing, the first silicon-based die and the second silicon-based die are disposed adjacently on a silicon wafer, wherein the first silicon-based die and the second silicon-based die are selected and co-encapsulated together in the monolithic semiconductor package.

[0020] In some embodiments, a method of operating a circuit is disclosed. The method includes providing a first switch having a first source terminal and a first drain terminal; providing a second switch having a second source terminal and a second drain terminal, the second drain terminal being connected to the first drain terminal and the second source terminal being connected to the first source terminal; generating a first signal by the second switch, the first signal corresponding to a current flowing from the first source terminal to the first drain terminal; receiving the first signal by a sensing circuit; determining the amplitude and polarity of the current flowing from the first source terminal to the first drain terminal by the sensing circuit; and transmitting a second signal by the sensing circuit based on the first signal.

[0021] In some embodiments of the disclosed method, the first switch and the second switch are gallium nitride (GaN) based switches, wherein the first switch and the second switch are monolithically formed on a single die.

[0022] In some embodiments, the method further includes providing a third switch having a third source terminal and a third drain terminal, the third source terminal being connected to the first drain terminal and connected to a first terminal of the load, and the third drain terminal being connected to a power input node.

[0023] In some embodiments, the method further includes providing a fourth switch having a fourth source terminal and a fourth drain terminal, the fourth drain terminal being connected to the third drain terminal, and the fourth source terminal being connected to the third source terminal.

[0024] In some implementations, the method further includes receiving the second signal by an overcurrent protection circuit, comparing the second signal with a first threshold, and generating a disconnect signal when the second signal exceeds the first threshold. Attached Figure Description

[0025] Figure 1 A simplified schematic diagram of an integrated power device with bidirectional current sensing according to certain embodiments is shown;

[0026] Figure 2 The use of an external resistor, according to some implementations, for sensing current through a power switch via an internal bidirectional current amplifier is demonstrated.

[0027] Figure 3 A system-level schematic diagram of a power converter with a controller and integrated power device according to certain implementation schemes is shown;

[0028] Figure 4 Showing Figure 3 A timing diagram of the voltages at each node within the circuit;

[0029] Figure 5 Demonstrates the use of some implementation schemes Figure 1 A simplified schematic diagram of an integrated power device with an internal current sensing amplifier based on a GaN die and bidirectional external current sensing circuitry.

[0030] Figure 6 This is a simplified flowchart illustrating the method for activating the Synchronous Rectification (SR) function;

[0031] Figure 7 and Figure 8 A diagram showing the timing of SR being turned on and off according to some implementation schemes is presented;

[0032] Figure 9 This is a simplified flowchart illustrating a method for prematurely disconnecting the power switch in SR mode, according to some implementation schemes; and

[0033] Figure 10 A simplified schematic diagram of a level converter system according to certain implementation schemes is shown. Detailed Implementation

[0034] The circuits, devices, and related technologies disclosed herein generally relate to power converters. More specifically, the systems, circuits, devices, and related technologies disclosed herein relate to GaN power switches with lossless current sensing for motor drive half-bridge and full-bridge applications. In some embodiments, the integrated power device may include a GaN power switch and an integrated bidirectional lossless current sensor, which eliminates the need for an external current sensing resistor, thereby improving system efficiency. The integrated bidirectional lossless current sensing also enables the integrated power device to autonomously turn on the GaN power switch during third-quadrant conduction, further improving system efficiency. The integrated power device with bidirectional lossless current sensing enables the sensing of the magnitude and direction of current flowing through the GaN power switch in both the positive (i.e., from drain to source) and negative (i.e., from source to drain) directions. The sensed current magnitude and direction can be transmitted to driver and / or controller circuitry, which can autonomously control the conduction state of the GaN power switch in response to the received sensed current magnitude and direction.

[0035] In some embodiments, the integrated power device may include sensing and driving circuitry co-packaged with the GaN power switch within an integral semiconductor package. The sensing and driving circuitry may include differential amplifier circuitry arranged to detect the amplitude and positive and / or negative direction of the current flowing through the GaN power switch. In various embodiments, an external resistor may be used to sense the current flowing through the GaN power switch. Embodiments of this disclosure enable the use of sensing and driving circuitry to amplify the voltage across an external sensing resistor. Utilizing internal sensing circuitry allows the use of an external resistor with a relatively small value compared to the external resistor values ​​used in current methods, because the disclosed circuitry and techniques can detect the amplitude and direction of the current flowing through the GaN power switch based on the relatively small voltage generated across the external resistor. In this way, converter power losses can be minimized. In some embodiments, the value of the external resistor may be, for example, 1 / 10 to 1 / 5 of the resistor value used in current methods.

[0036] Motor drive applications may require relatively accurate sensing of current through a power switch. These applications may include, but are not limited to, washing machine, dryer, or hair dryer applications. The circuitry and techniques disclosed herein enable relatively accurate sensing of current through a power switch, wherein the accuracy of the sensed current can be maintained at a relatively high level of precision throughout the appliance's lifespan. In some embodiments, a relatively small switch may be coupled to the power switch, wherein the small switch is arranged to sense the current flowing through the power switch. The circuitry and techniques disclosed herein enable mitigation of the effects of changes in the ratio of current in the main switch to that in the small switch over time. For example, the ratio of current through the main switch to that through the small switch may change by up to 7% over time. In motor drive applications, it is advantageous to keep the ratio relatively constant over time. Embodiments of this disclosure enable relatively accurate current sensing over time. Furthermore, embodiments of this disclosure enable bidirectional sensing of current through a power switch. Therefore, the circuitry and techniques disclosed herein enable bidirectional current sensing using a small switch and / or an external resistor to sense current.

[0037] In some implementations, the control methods for autonomous synchronous rectifier (SR) mode enable the power switch to operate as an ideal diode, or to have reverse-channel conduction when the current through the switch is negative (i.e., flowing from the source to the drain). In motor inverters and other applications where reverse current can flow through the power switch (also known as "freewheeling"), the combination of the voltage across the power switch and the reverse current can result in relatively high power dissipation. The circuitry and techniques disclosed herein enable the power switch to be driven as a synchronous rectifier. In some implementations, the power switch can be turned on when a significant reverse current is detected in the power switch, thereby reducing power losses as current flows from the source to the drain. Furthermore, the switch can autonomously turn off near zero current (SROFF) without the need for a controller.

[0038] In various implementations, the method for using the autonomous synchronous rectifier (SR) mode in a half-bridge circuit may include a disconnect intervention mode. In these implementations, the power switch may be disconnected in advance in SR mode.

[0039] The circuits and techniques disclosed herein enable lossless current sensing in multiphase motor driver circuits (e.g., 3-phase motor driver circuits). In some embodiments, the sensed current for each phase can be arranged in a wired OR configuration. In various embodiments, the IC may include positive and negative dV / dt control circuitry. In some embodiments, the dV / dt control circuitry may include external and / or internal impedance elements coupled to input pins of the IC. In various embodiments, the driver IC may include gate overdrive circuitry. Gate overdrive circuitry is disclosed in U.S. Patent Application No. 18 / 733,480, which is incorporated herein by reference. In various embodiments, the circuits and methods disclosed herein are suitable for driving or controlling GaN-based power switches, silicon-based and / or silicon carbide-based switches.

[0040] In some embodiments, the level shifting circuit may include a silicon-based transmitter circuit, a GaN-based level shifting switch, and a silicon-based receiver circuit. In various embodiments, during the manufacturing process, the silicon-based transmitter circuit and the silicon-based receiver circuit can be selected from adjacent locations on the silicon wafer to ensure a relatively high level of matching between the transmitter die and the receiver die. Various inventive embodiments, including methods, processes, systems, apparatuses, etc., are described herein.

[0041] Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part thereof. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of embodiments will provide those skilled in the art with a feasible description for implementing one or more embodiments. It should be understood that various changes may be made in terms of the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0042] Figure 1 A schematic diagram of an integrated power device with bidirectional current sensing circuitry according to some implementation schemes is shown. Figure 1 A schematic diagram of an integrated power device 100 is shown, which may include a gallium nitride (GaN)-based die 102 co-packaged with a silicon-based die 104 in a single semiconductor package. The GaN-based die 102 may include one or more GaN-based power switches. The silicon-based die 104 may include current sensing circuitry. In some embodiments, the silicon-based die may include additional circuitry, such as, but not limited to, driver and controller circuitry. The integrated power device may also be referred to as an electronic device.

[0043] In the illustrated embodiment, the GaN-based die 102 may include a GaN power switch 130 having a drain terminal 132, a gate terminal 136, and a source terminal 134. The GaN-based die 102 may further include a GaN switch 122 having a drain terminal 124, a gate terminal 128, and a source terminal 126. The drain terminal 132 may be connected to the drain terminal 124, and the gate terminal 136 may be connected to the gate terminal 128. In some embodiments, the GaN switch 122 may be relatively small. The source terminal 134 may be connected to ground 106. The source terminal 134 may also be connected to a Kelvin terminal 108. The source terminal 126 may be connected to an output terminal 110.

[0044] GaN switch 122 can be arranged to sense the current flowing through GaN power switch 130. Current 141 (Isw) can flow from drain terminal 132 of GaN switch 130 to source terminal 134. Current 140 (Isns) can flow from drain terminal 124 of GaN switch 122 to source terminal 126, where Isns can be generated based on Isw. In some embodiments, Isns can be proportional to Isw.

[0045] The silicon-based die 104 may include input terminals 112 and 114. Input terminals 112 and 114 may be connected to output terminals 110 and 108, respectively. In some embodiments, input terminals 112 and 114 may be connected to output terminals 110 and 108 via wire bonding. The wire bonding may be a single-wire bonding or a multi-wire bonding, or any other technique that can electrically interconnect. A resistor 116 may be connected between input terminals 112 and 114. In some embodiments, resistor 116 may have a value of, for example, 2000Ω to 6000Ω, while in other embodiments, the resistor may have a value of 4000Ω. Input terminal 112 may also be connected to resistor 118, and input terminal 114 may also be connected to resistor 120. Resistor 118 may be connected to switch 142, and resistor 120 may be connected to switch 144. In some implementations, resistor 118 may have a value of, for example, 396Ω, while resistor 120 may have a value of, for example, 400Ω.

[0046] Switch 142 can be connected to the first input terminal 146 of the current sensing amplifier 150. Switch 144 can be connected to the second input terminal 148 of the current sensing amplifier 150. In some embodiments, the current sensing amplifier 150 can be arranged to operate bidirectionally. The current sensing amplifier 150 can have a first output terminal 152 and a second output terminal 154. Switch 156 can be connected between the first output terminal 152 and the first input terminal 146 of the current sensing amplifier 150. Switch 158 can be connected between the second output terminal 154 and the first input terminal 148 of the current sensing amplifier 150.

[0047] The output of the current sensing amplifier 150 can be a current output and can indicate the bidirectional or unidirectional current flowing in the GaN power switch 130. In some embodiments, the current sensing amplifier 150 can sense the current through the switch 122, thereby improving accuracy and reducing lifetime drift. In various embodiments, the current sensing amplifier 150 can sense the current flowing through an external sensing resistor, thereby improving accuracy and reducing lifetime drift. In some embodiments, overcurrent detection can be performed internally within the silicon-based die IC 104. Embodiments of this disclosure allow users to set their own overcurrent thresholds in their microcontrollers.

[0048] The output terminal of the current sensing amplifier 150 can be connected to the current mirror circuit 160. In some embodiments, the current mirror 160 can be a 1:1 current mirror, meaning the amplitude of the current entering the current mirror can be substantially equal to the amplitude of the current leaving the current mirror. The output terminal of the current mirror circuit 160 can be connected to the current mirror and subtraction circuit 162. In various embodiments, the current mirror and subtraction circuit 162 can be 1:10, meaning the amplitude of the current entering the current mirror can be one-tenth the amplitude of the current leaving the current mirror.

[0049] The current mirror and subtraction circuit 162 can be connected to the overcurrent detection circuit 164, which is arranged to generate an overcurrent positive signal (OCP) and an overcurrent negative signal (OCN). The current mirror and subtraction circuit 162 can be connected to the output pin 174 (labeled CS). Switches 166 and 168 can also be connected to the CS pin. The CS pin can be connected to a resistor divider formed by the series connection of resistors 170 and 172.

[0050] In some embodiments, the integrated power device 100 may be formed of silicon, GaN, or any other suitable semiconductor material. In various embodiments, both the sensing circuitry and switches 130 and 122 may be formed in a silicon substrate. In some embodiments, both the sensing circuitry and switches may be formed in a GaN substrate. In some embodiments, the sensing circuitry may be formed in a silicon substrate, while switches 130 and 122 may be formed in a GaN substrate. In various embodiments, the sensing circuitry and switches 130 and 122 may be monolithically integrated onto a single die. In some embodiments, the sensing circuitry and switches may be formed on separate, individual dies. In various embodiments, the sensing circuitry and switches 130 and 122 may be integrated into an electronic package, such as, but not limited to, a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the sensing circuitry and switches may be separately packaged into an electronic package.

[0051] The current sensing amplifier 150 can detect the value of Isw by detecting Isns. Isns can generate a voltage across resistor 116. The generated voltage can be detected bidirectionally by amplifier 150, and a corresponding current signal I can be generated. N and I P The corresponding current signal is then transmitted to current mirror circuit 160. In some embodiments, current mirror circuit 160 may have a 1:1 ratio. Current mirror circuit 160 may transmit the corresponding signal to current mirror circuit 162, where the signal can be amplified. Current mirror circuit 162 may be arranged to drive output pin 174 (labeled CS). In various embodiments, overcurrent condition detection may be performed internally by the integrated power device 100. In some embodiments, the user can set their own OC threshold in their microcontroller.

[0052] The output stage of the current-sensing amplifier 150 can always operate with current, allowing the output stage to always operate with common-mode current. This enables a smooth and seamless transition from a negative sense voltage to a positive sense voltage. In the disclosed bidirectional amplifier architecture, a differential current can operate on one side depending on the polarity of the sense voltage. In some embodiments, resistor 120 can set the current in the output stage of amplifier 150. In various embodiments, sensing resistor 116 can have a value of, for example, 4Ω. For example, when sensing resistor 116 has a value of 4Ω and resistor 120 has a value of 400Ω, resistor 118 can have a value of 396Ω.

[0053] Figure 2 The use of an external resistor according to some embodiments for sensing current through a power switch via an internal bidirectional current amplifier is illustrated. The use of the internal sensing circuitry of the integrated power device 100 allows the use of an external resistor with a relatively small value compared to that used in current methods, because the internal sensing circuitry has relatively high sensitivity. In the illustrated embodiment, the external resistor 180 can be used to sense current through the power switch 130. The external resistor 180 can be connected between the source terminal 134 and ground.

[0054] The silicon-based die 104 can be connected to an external resistor 180 via resistors 182 and 184. In some implementations, switches 142 and 144 can be controlled by signal A, and switches 186 and 188 can be controlled by signal B. The current-sensing amplifier 150 can sense the current flowing through the external sensing resistor 180 with improved accuracy and lower lifetime drift. The external resistor 180 can have a relatively small value, thus resistors 182 and 184 can have similar values. When using the internal current-sensing amplifier 150, pins 199 (ICSP) and 197 (ICSN) can float. The following is I N and I P Example calculation:

[0055] When Isw > 0:

[0056]

[0057] I N =I CM

[0058] When Isw = 0:

[0059] I P =I CM

[0060] I N =I CM

[0061] When Isw < 0:

[0062]

[0063] Ip = IC M

[0064] To determine whether to use internal or external current sensing, the component can force current to flow from the ICSP and ICSN pins, and uses internal current sensing when the voltage is greater than approximately 1.5V. When the component is enabled, a pulsed current value of, for example, 200μA can be output from the ICSP and ICSN pins for a short period. During this determining period (the period for deciding between internal and external current sensing), the amplifier can use internal current sensing. Internal current sensing is used by default with internal resistor 116, as it is always connected.

[0065] Once the determination of whether to use internal current sensing (resistor 116) or external current sensing (resistor 180) is made, this determination is latched to prevent any changes to this determination during component operation. This latch can be cleared when the component is disconnected. In some embodiments, the latched data can only be switched to the amplifier input if gate terminal 136 is low. This prevents the amplifier from switching connections when gate terminal 136 is high. In various embodiments, current sensing can be performed internally during the first PWM pulse, and subsequently, current sensing can switch to external current sensing starting from the next PWM pulse. This only occurs when PWM is high when enable goes high. In some embodiments, for the use of internal current sensing, the ICSP and / or ICSN pins can be floated, or a capacitor or a relatively large resistor can be connected to the ICSP and / or ICSN pins.

[0066] Referring now to the current mirror section of the integrated power device 100, the current output at pin 174 (CS) can be gained, for example, by a factor of 10 relative to the amplifier output current (e.g., + / - 2.5 mA at Isw = + / - 100%). The gains of current mirror circuit 160 and current mirror circuit 162 can be adjusted to compensate for variations in the ratio of GaN power switch 130 to sensing switch 122. Offset adjustment can also be performed in current mirror circuits 160 and 162 such that the CS output current is zero when Isw = 0.

[0067] Even when Isw = 0, the output stage can continuously operate current to improve the response speed when the power switching current Isw passes 0. For bidirectional output, the user can place a resistor divider at the reference voltage or a single resistor at the reference voltage. The CS pin voltage can be maintained, for example, within 0.5V to 3.5V to ensure relatively accurate output current. For unidirectional output, the user can place a resistor between the CS pin and GND (adjusting the bit to configure unidirectional output). In some implementations, the CS pin voltage is maintained less than, for example, 3.5V to ensure relatively accurate output current. Positive and negative overcurrent detection can be performed internally within the integrated power device 100, and current in the current mirror circuit can be sensed. The CS pin can be set, for example, to approximately 3.5V (or 5V) for positive overcurrent and to GND for negative overcurrent.

[0068] Figure 3A system-level schematic diagram of a power converter with a controller and integrated power devices according to certain embodiments is shown. Circuit 300 may include a controller 304 connected to integrated power device 302. Integrated power device 302 is similar to integrated power device 100, except that integrated power device 302 includes two integrated power devices. Integrated GaN device 302 may be arranged to sense the magnitude and direction (in the positive direction (i.e., from drain to source) or the negative direction (i.e., from source to drain)) of the current flowing through GaN power switch 308. In some embodiments, integrated GaN device 302 may be arranged to sense the magnitude and direction (in the positive direction (i.e., from drain to source) or the negative direction (i.e., from source to drain)) of the current flowing through each of GaN power switches 306 and 308.

[0069] In various embodiments, the GaN power switch can be formed on a GaN-based die, and the sensing / driver circuitry can be formed on a silicon-based die. The GaN-based die and the silicon-based die can be co-packaged in a single semiconductor package. In some embodiments, the GaN power switch and the sensing / driver circuitry can be formed within a GaN-based die. In various embodiments, each GaN power switch can be coupled to a corresponding sensing circuit.

[0070] For many applications, sensing the cycle-by-cycle current flowing through a power switch can be useful. Current methods for current sensing may involve placing a sensing resistor between the source of the power switch and ground. This approach can increase system turn-on power losses, create hot spots on the PCB, and reduce overall system efficiency. To eliminate this external resistor and associated hot spots, and improve system efficiency, the integrated GaN device 302 can employ a relatively accurate integrated bidirectional lossless current sensing technique. In some implementations, the current flowing through the internal low-side GaN power switch can be sensed internally and then converted to a current at the current-sensing output pin (CS). An external resistor divider (R1, R2) can be connected to the CS pin and can be used to set the amplitude of the voltage signal at the CS pin. In this way, the CS pin signal can be enabled to work with different controllers having different current-sensing input thresholds. In some implementations, the resistor divider can be placed relatively close to the CS pin to improve robustness and reduce system noise.

[0071] In some implementations, the resistor divider can be driven by an external voltage, allowing it to set the midpoint voltage to an arbitrary level, for example, in an A / D converter operating a microcontroller at maximum resolution. A positive current through the GaN power FET can cause current to flow out of the CS pin, increasing the voltage at the midpoint of the resistor divider, and a negative current through the GaN power FET can cause current to flow into the CS pin, decreasing this voltage. The CS pin current can be a function of the gain factor and the magnitude of the current in the power transistor. The resistor value can be set such that the voltage range corresponding to the all-positive to all-negative current is adequately localized within the ADC input voltage range, and the maximum voltage at the CS pin can be set.

[0072] Compared to current methods, the embodiments of this disclosure can significantly reduce the total on-resistance R. ON (TOT). For example, for a 300W high-frequency boost PFC circuit, R ON (TOT) can be reduced from 340m ohms to 170m ohms. The power loss savings from eliminating the external resistor can result in, for example, an efficiency benefit of +0.5% for the entire system, and eliminate RCS PCB hotspots. The following equations show an example of the calculations for gain and Vcs:

[0073] Equation 1: Gain ratio of internal current sensing amplifier:

[0074] Gain = ICS / IDS = 1.25mA / 4.5A = 0.2778mA / A

[0075] Equation 2: Current sensing pin voltage - internal current sensing

[0076] VCS = RCS / 2 * Gain * IDS + VREF / 2

[0077] Where RCS = R1 = R2 / 2

[0078] Figure 4 Showing Figure 3 The timing diagram of the voltage at each node in the circuit. Figure 4 IN is shown L IN H V SW The voltage at the CS pin and the CS pin.

[0079] Figure 5A simplified schematic diagram of an integrated power device with bidirectional external current sensing circuitry according to some embodiments is shown, the integrated power device using an internal current-sensing amplifier integrated with a GaN-based die 102. In some embodiments, an external current-sensing resistor can be used, while the internal amplifier of the integrated power device is still used to gain the voltage across the external sensing resistor. The internal current-sensing amplifier is used to improve R... SNS The voltage across the terminals allows for a relatively small R. SNS The value allows the maximum voltage drop to be set to, for example, + / - 100mV, and R SNS Power loss can be minimized. The internal amplifier can sense R through two series resistors R3 and R4. SNS The voltage across the two ends of the series resistors can be set to the same value. The voltage at CS is given by the following formula:

[0080]

[0081] In various implementation schemes, the A / D converter of the PWM controller can directly sense R. SNS However, R SNS The maximum voltage drop across the terminals can be relatively high to achieve resolution for accurate current sensing. In various implementations, another external current sensing option could be to add an external amplifier to increase RA. SNS Signal, and allows bidirectional current sensing. This technology is... Figure 2 Similar, but using an external amplifier instead of an internal amplifier.

[0082] Autonomous synchronous rectification :

[0083] In the current approach, GaN HEMTs may lack a body diode, and therefore, in the third quadrant, the voltage across the HEMT can be, for example, four to five times the voltage of a comparable Si switch. The resulting conduction losses can be relatively high when the gate is kept low, which can eliminate GaN from consideration in power converters using this "freewheeling" method.

[0084] In some implementations, the control methods for autonomous synchronous rectifier (SR) mode enable the power switch to operate as an ideal diode, or to have reverse channel conduction when the current through the switch is negative (i.e., flowing from the source to the drain). In motor inverters and other applications where reverse current can flow through the power switch (also known as "freewheeling"), the combination of the voltage across the power switch and the reverse current can result in relatively high power dissipation. The circuitry and techniques disclosed herein enable the power switch to be driven as a synchronous rectifier when third-quadrant current conduction is detected. In some implementations, the power switch can be turned on when a significant reverse current is detected in the power switch, thereby reducing power losses as current flows from the source to the drain. Furthermore, the switch can autonomously disconnect near zero current (SROFF) without the need for a controller.

[0085] In various embodiments, a half-bridge circuit operating in buck mode with an inductive load can utilize a self-synchronizing rectification method. In such embodiments, the control signal for the low-side switch can be held at zero V, while the high-side control signal can switch the high-side switch on and off to generate current in the load inductor connected from the switching node of the half-bridge to ground. Once the high-side switch is off, the inductor current commutates to the low-side switch, where the low-side switch can begin to conduct in the third quadrant. Once the third quadrant current amplitude in the low-side switch exceeds a predetermined threshold (e.g., 700 mA), embodiments of this disclosure enable the integrated power device to autonomously boost the low-side switch gate terminal (i.e., turn on the gate). The low-side switch gate can remain boosted (high) until a high-side “on” control command is received or the current amplitude in the half-bridge decays to a predetermined detection threshold. A shoot-through protection circuitry ensures that the low-side GaN gate is turned off before a “on” control command is delivered to the high-side gate driver. A similar operating technique can also be used when the high-side switch is in “boost” mode.

[0086] Figure 6 Methods for activating SR functionality according to some implementation schemes are demonstrated. Figure 6A method 600 for activating SR functionality is illustrated, the method including arming, wherein an integrated power device can arm itself for SR operation if VDS exceeds a first threshold (602). The method also includes turn-on, wherein when the integrated power device is previously armed and VDS falls below a second threshold (SRON voltage, e.g., -1.05V) for more than a first predetermined period, a driver can activate and turn on a power switch (604). The gate can remain on for at least a minimum on-time to ensure that switching noise does not erroneously trip the disconnection detection circuitry. The first predetermined period can have a value such as 50 nanoseconds to 100 nanoseconds. In some embodiments, the first predetermined period can be 0.1 nanoseconds to 900 nanoseconds, while in other embodiments, the first predetermined period can be 10 nanoseconds to 200 nanoseconds.

[0087] The method also includes disconnection, wherein the integrated power device can disconnect the power switch (606) when the magnitude of the current flowing from the source to the drain drops below a predetermined threshold. The method further includes rearming, wherein the integrated power device can be prepared for the next SR cycle (608) when VDS rises above a third threshold (SRARM voltage, e.g., 9.8V).

[0088] It should be understood that Figure 6 The specific steps illustrated provide a particular method for activating the SR function according to one embodiment of this disclosure. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of this disclosure may perform the steps outlined above in a different order. Furthermore, Figure 6 The steps shown may include multiple sub-steps, which may be performed in various orders suitable for each step. Furthermore, depending on the specific application, additional steps may be added or removed. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0089] According to some implementations, the integrated power device 100 can be arranged in a programmable synchronous rectifier (SR) mode to allow the power switch to operate as an ideal diode and / or to have reverse-channel conduction when the current through the switch is negative (flowing from the source to the drain). When the INL or INH pin is low, and if the SR enable pin (SREN) is not set, the power switch will be off even if the switch current is negative. If the SREN enable pin is set and INL or INH is low, the power switch will be on if a negative current flows through the switch, thus acting as an ideal diode and improving system efficiency.

[0090] Figure 7 and Figure 8 A diagram showing the timing of SR being turned on and off according to some implementation schemes is presented.

[0091] In some implementations, the autonomous SR mode may include a method of preemptively disconnecting the power switch. Figure 9 This is a simplified flowchart illustrating a method 900 for prematurely disconnecting the power switch in SR mode, according to some implementation schemes. Figure 9 As shown, method 900 may include, when the low side operating in SR mode receives a request to turn on the high side, the integrated power device 100 may turn off the low-side gate before sending a high-side level-shifting turn-on signal (902). The method may further include, when the low side operating in SR mode receives a genuine INL command, and when the integrated power device 100 receives an INL signal during SR mode, prioritizing the signal even if the signal goes low before the normal SR turn-off current (904). The method further includes, when the high side operating in SR mode receives a turn-off signal via a level shifter, the low side may not know whether the high side is operating in SR mode; therefore, the low side may continuously send turn-off pulses to the high side via a level shifter before responding to the INL command (906).

[0092] It should be understood that, according to some implementation plans, Figure 9 The specific steps shown provide a particular method for prematurely disconnecting the power switch in SR mode. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of this disclosure may perform the steps outlined above in a different order. Furthermore, Figure 9 The steps shown may include multiple sub-steps, which may be performed in various orders suitable for each step. Furthermore, depending on the specific application, additional steps may be added or removed. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0093] In some implementations, SR disconnection may not necessarily have to be done in conjunction with current sensing. VSD can be sensed and disconnected when the voltage reaches a relatively small value (e.g., a few millivolts), rather than when the current is sensed to drop below a threshold.

[0094] In some implementations, the SR mode can achieve accurate negative current sensing using an internal bidirectional sensing method. When current flows in the third quadrant (i.e., from source to drain) and the gate remains low, the ratio of the main power FET to the CS sensing FET may differ from when the gate is high. Therefore, if the gate remains low, the CS output may have a relatively inaccurate gain. The autonomous SR mode mitigates this problem by ensuring that the gate is on and that the ratio of the main FET to the CS sensing FET is correct even in the absence of a PWM signal when the current is negative. In current methods, an external CS resistor may not have this problem because the voltage across the external CS resistor is always Rcs*Idrn. The disclosed autonomous SR method can achieve a "lossless" sensing method in applications where the user does not drive the PWM, thus allowing some users to eliminate external Rcs without modifying their firmware and / or control scheme.

[0095] Figure 10 A simplified schematic diagram of a level shifter system according to certain implementation schemes is shown. For example... Figure 10 As shown, the level shifter system 1000 can be used in a driver IC used in an integrated power device 100. The level shifter system 1000 may include a transmitting circuit 1002, a level shifting circuit 1004, and a receiving circuit 1006. In some embodiments, the transmitting circuit 1002 may reference a low voltage ground, while the receiving circuit 1006 may reference a floating voltage. In various embodiments, the transmitting circuit 1002 may be formed of silicon, the level shifting switch 1004 may be formed of GaN, and the receiving circuit 1006 may be formed of a silicon die. The level shifting switch circuit 1004 may include a first switch 1010 and a second switch 1012. The first switch 1010 and the second switch 1012 may be formed in a GaN-based die. In some embodiments, the transmitting circuit 1002 may be formed on a silicon die, wherein the transmitting circuit die and the receiving circuit die are separate. In various embodiments, the transmitting circuit 1002 may be formed on the same die as the receiving circuit 1006. In some embodiments, the level shifting switch 1004 may be a high-voltage switch. In various implementations, the level shifting switch 1004 can be a low-voltage or medium-voltage switch.

[0096] By using the same current source 1008 for both the receive-on (RX_ON) and receive-off (RX_OFF) portions, the matching of the network can be further improved compared to having independent current sources for each level shifting switch 1010 and 1012. By improving the matching in the level shifting circuit, the level shifting circuit can operate with relatively high immunity to spurious signal propagation. In some embodiments, the current source may be a resistor or a controlled impedance element. In various embodiments, the current source may be located in the GaN die 1014 or on the silicon die 1016.

[0097] In some embodiments, the level shifting system 1000 may include a transmitting circuit, a receiving circuit, a first level shifting switch, and a second level shifting switch, wherein the first and second level shifting switches are formed of gallium nitride (GaN). In various embodiments, the transmitting circuit and the receiving circuit are formed on the same silicon die. In some embodiments, the transmitting circuit is formed on a first die, the first and second level shifting switches are formed on a second die, and the receiving circuit is formed on a third die, wherein the first, second, and third dies are co-packaged in a single semiconductor package. In various embodiments, the first and third dies are disposed adjacent to each other on a silicon wafer, wherein the first and third dies are selected and placed together in a single semiconductor package.

[0098] The level shifting circuitry and techniques disclosed herein enable the formation of level shifting lines in driver ICs for GaN power devices, where the level shifting circuitry operates with relatively high precision, thereby allowing energy savings. By selecting the transmitter and receiver dies from the same silicon wafer, a relatively high level of matching can be achieved, enabling the level shifting circuitry to operate with relatively high accuracy. In some embodiments, the same die can be used for both transmitter and receiver dies by configuring on-chip under-bonding (DAP), whereby the DAP indicates whether the die is used for transmitter or receiver functions.

[0099] In some embodiments, the methods disclosed herein can be used to determine the corner operating conditions of the level-shifting system 1000 over the process and temperature variations of the low-side pulse width. In various embodiments, the data can be used to determine the slowest dV / dt for which low-side (LS) information can be successfully transmitted to the high-side (HS) without any intervention. For example, when dV / dT is slower than 13V / ns, the LS pulse width may not be guaranteed to pass through the level-shifting circuit; therefore, according to some embodiments, a common-mode feedback circuit (CMFB) can be used. A CMFB circuit can be advantageous because when the rising edge dV / dt causes (1) the amplitude of the common-mode current generated in the level-shifting FET (1004) to extend the receiver circuit (1006) beyond its operating dynamic range, and (2) the duration of dV / dt is longer than the current pulse transmitted from the transmitter circuit (1002), the receiver may miss the signal from the transmitter without intervention. Therefore, a CMFB circuit can be beneficial in mitigating these operating conditions. The CMFB circuit can sense common-mode current events at the receiver input and generate output currents through the RX_ON 1020 and RX_OFF 1022 nodes to cancel out the current. In this way, the CMFB circuit can bring the receiver input back to the appropriate range for sensing differential signals, i.e., current pulses on 1020 (RX_ON) or 1022 (RX_OFF). Therefore, when the transmitter sends a signal during a dV / dt event satisfying the two criteria described above, the receiver can still sense the signal and act upon it.

[0100] In some embodiments, combinations of the circuits and methods disclosed herein can be used to provide bidirectional lossless current sensing and autonomous SR-mode operation for integrated power devices having driver circuitry and at least a GaN power switch. Although circuits and methods are described and shown herein for several specific configurations of operating GaN power switches, embodiments of this disclosure are suitable for operating silicon-based and / or silicon carbide-based power switches. Furthermore, the circuits and methods described and shown herein are applicable to AC-DC, DC-DC, ACF, buck, boost, half-bridge, full-bridge, LLC, AHB, Class D, PFC, and motor-driven power converters.

[0101] In the foregoing description, numerous specific details have been described with reference to embodiments of this disclosure, which may vary depending on the specific implementation. Therefore, the description and drawings should be considered illustrative rather than restrictive. The unique and exclusive indication of the scope of this disclosure, and what the applicant wishes to define as the scope of this disclosure, is the literal and equivalent scope of the claims published in this application, taking the specific form published by those claims, including any subsequent amendments. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of this disclosure.

[0102] Additionally, spatially relative terms, such as “bottom” or “top,” may be used to describe the relationship of one element and / or feature to another, as illustrated in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use and / or operation than those depicted in the figures. For example, if the device in the figures is flipped, the element described as the “bottom” surface may then be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise) and may be interpreted accordingly by the spatially relative descriptors used herein.

[0103] As used herein, the terms “and,” “or,” and “and / or” can have a variety of meanings, which are also expected to depend at least in part on the context in which the terms are used. Generally, “or,” when used in a list of associations (such as A, B, or C), is intended to mean A, B, and C (used herein in an inclusive sense) and A, B, or C (used herein in an exclusive sense). Additionally, the term “one or more” as used herein can be used to describe any feature, structure, or property in the singular form, or can be used to describe some combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example and the claimed subject matter is not limited to this example. Furthermore, the term “at least one of…” when used in a list of associations (such as A, B, or C) can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0104] Throughout this specification, references to “an example,” “example,” “some examples,” or “exemplary embodiment” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the phrases “in an example,” “example,” “in some examples,” “in some embodiments,” or other similar phrases appearing throughout this specification do not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined into one or more examples and / or features.

[0105] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but rather includes all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A circuit comprising: A first switch, the first switch having a first source terminal and a first drain terminal; A second switch having a second source terminal and a second drain terminal, the second drain terminal being connected to the first drain terminal, and the second source terminal being connected to the first source terminal; The second switch is arranged to generate a first signal corresponding to the current flowing from the first source terminal to the first drain terminal; as well as A sensing circuit is arranged to receive the first signal and determine the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal, the sensing circuit being further arranged to transmit a second signal based on the first signal.

2. The circuit according to claim 1, wherein the first switch is a gallium nitride (GaN) based switch.

3. The circuit according to claim 2, wherein the second switch is a GaN-based switch.

4. The circuit according to claim 3, wherein the first switch and the second switch are monolithically formed on a single die.

5. The circuit of claim 1, further comprising a third switch having a third source terminal and a third drain terminal, the third source terminal being connected to the first drain terminal and connected to a first terminal of the load, and the third drain terminal being connected to a power input node.

6. The circuit of claim 5, further comprising a fourth switch having a fourth source terminal and a fourth drain terminal, the fourth drain terminal being connected to the third drain terminal, and the fourth source terminal being connected to the third source terminal.

7. The circuit according to claim 5, wherein the load is a motor.

8. The circuit of claim 1, wherein the first switch and the second switch are formed on a gallium nitride (GaN) based die, and the sensing circuit is formed on a silicon based die, wherein the GaN based die and the silicon based die are co-packaged in a single semiconductor die.

9. The circuit of claim 1, further comprising an overcurrent protection circuit arranged to receive the second signal, compare the second signal with a first threshold, and generate a disconnect signal when the second signal exceeds the first threshold.

10. A level conversion circuit, the level conversion circuit comprising: Transmitting circuit; Receiver circuit; as well as First level selector switch and second level selector switch; and The transmitting circuit is formed on a first silicon-based die, the receiving circuit is formed on a second silicon-based die, and the first level shifting switch and the second level shifting switch are formed on a gallium nitride (GaN)-based die.

11. The level conversion circuit of claim 10, wherein the first silicon-based die, the second silicon-based die, and the GaN-based die are co-packaged in an integrated semiconductor package.

12. The level shifting circuit according to claim 10, wherein the source terminal of the first level shifting switch is connected to the source terminal of the second level shifting switch and connected to a current source.

13. The level conversion circuit of claim 12, wherein the current source is disposed on the first silicon-based die.

14. The level conversion circuit according to claim 10, further comprising a common-mode feedback circuit.

15. The level shifting circuit of claim 11, wherein during manufacturing, the first silicon-based die and the second silicon-based die are disposed adjacently on a silicon wafer, and wherein the first silicon-based die and the second silicon-based die are selected and co-packaged together in the monolithic semiconductor package.

16. A method of operating a circuit, the method comprising: A first switch is provided, the first switch having a first source terminal and a first drain terminal; A second switch is provided, the second switch having a second source terminal and a second drain terminal, the second drain terminal being connected to the first drain terminal, and the second source terminal being connected to the first source terminal; The second switch generates a first signal, which corresponds to the current flowing from the first source terminal to the first drain terminal; as well as The first signal is received by the sensing circuit; as well as The amplitude and polarity of the current flowing from the first source terminal to the first drain terminal are determined by the sensing circuit. as well as The sensing circuit transmits a second signal based on the first signal.

17. The method of claim 16, wherein the first switch and the second switch are gallium nitride (GaN) based switches, and wherein the first switch and the second switch are monolithically formed on a single die.

18. The method of claim 16, further comprising providing a third switch having a third source terminal and a third drain terminal, the third source terminal being connected to the first drain terminal and connected to a first terminal of the load, and the third drain terminal being connected to a power input node.

19. The method of claim 18, further comprising providing a fourth switch having a fourth source terminal and a fourth drain terminal, the fourth drain terminal being connected to the third drain terminal, and the fourth source terminal being connected to the third source terminal.

20. The method of claim 16, further comprising receiving the second signal by an overcurrent protection circuit, comparing the second signal with a first threshold, and generating a disconnect signal when the second signal exceeds the first threshold.

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