Multi-layer control method for inverter using hybrid power semiconductor

Abstract

The invention relates to a multi-layer control method of an inverter using an MOSFET and SI IGBT hybrid power semiconductor. The multi-layer control method comprises the following steps: receiving an inverter output current; estimating, via a loss model, a first junction temperature and a second junction temperature based on the inverter output current; determining a temperature difference between the first junction temperature and the second junction temperature; generating a comparison value based on a comparison between the temperature difference and a temperature difference threshold; determining an operating mode based on the comparison value, where the operating mode is defined by the output current amplitude, and where the operating mode is associated with the first time difference and the second time difference; adjusting a first time difference to meet a temperature difference threshold, wherein the first time difference is a time difference between a time at which the first output stage is turned on and a time at which the second output stage is turned on; and adjusting a second time difference to satisfy a temperature difference threshold, where the second time difference is a time difference between a time at which the first output stage is turned off and a time at which the second output stage is turned off, and controlling the at least one output gate based on the first time difference and the second time difference.

Description

Technical Field

[0001] This disclosure relates to the field of controlling integrated circuits (ICs), and in particular to a method of controlling gate drivers to simultaneously or concurrently generate drive inputs for both silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) and silicon insulated gate bipolar transistors (SiIGBTs). Background Technology

[0002] Semiconductors containing different transistors can cause intolerable junction temperature differences between the different transistors.

[0003] SiC MOSFETs are gaining popularity due to their fast switching speed, tolerance to relatively high junction temperatures compared to Si IGBTs, and relatively high thermal conductivity. In particular, the automotive industry has found several applications for SiC MOSFETs. However, SiC MOSFETs are significantly more expensive than Si-based power devices such as Si IGBTs.

[0004] Devices that combine both SiC MOSFETs and Si IGBTs have been developed to take advantage of the performance of SiC MOSFETs and offset their costs with the relatively inexpensive Si IGBTs.

[0005] Using only SiC MOSFET devices may unnecessarily increase costs. Using only Si IGBT devices may lead to undesirable performance problems. For example, performance degradation needs to be avoided.

[0006] Instead of using only Si IGBT devices or only SiC MOSFET devices, Si IGBT devices can operate in parallel with SiC MOSFET devices. Hybrid semiconductor power modules containing parallel Si IGBT devices and SiC MOSFET devices produce the desired on-resistance.

[0007] However, hybrid semiconductor power modules can lead to unbalanced junction temperatures because SiC MOSFET devices and SiIGBT devices are different semiconductor devices with different temperature tolerances. Therefore, in the IC field, there is a need for a method to control the gate sequence to provide drive inputs for both the SiC MOSFET and SiIGBT devices in a hybrid device. This method can control the gate of the gate driver to achieve the desired switching losses in the hybrid device.

[0008] Methods or digital control algorithms can control the gate sequence to maintain the temperature difference between the SiC MOSFET and Si IGBT in a hybrid semiconductor power module within a desired temperature range, thereby maintaining the current delivery capability of the power module. The temperature difference between the SiC MOSFET and Si IGBT in a hybrid semiconductor power module can also be referred to as the junction temperature of the hybrid semiconductor power module.

[0009] The background section relating to methods for controlling ICs (particularly in automotive inverter applications) is intended only to provide a contextual overview of some current problems and is not intended to be exhaustive. Further contextual information may become apparent to those skilled in the art after reviewing the following detailed description. Summary of the Invention

[0010] According to an embodiment, a method may include receiving an inverter output current and estimating a first junction temperature of a first transistor and a second junction temperature of a second transistor based on the inverter output current via a loss model. The method may further include: determining a temperature difference between the first junction temperature and the second junction temperature; generating a comparison value based on a comparison between the temperature difference and a temperature difference threshold; determining an operating mode based on the comparison value, wherein the operating mode is defined by the output current amplitude, and wherein the operating mode is associated with a first time difference and a second time difference. In response to the above determination and generation, adjusting the first time difference to satisfy the temperature difference threshold, wherein the first time difference is the time difference between the turn-on time of the first output stage and the turn-on time of the second output stage, and / or adjusting the second time difference to satisfy the temperature difference threshold, wherein the second time difference is the time difference between the turn-off time of the first output stage and the turn-off time of the second output stage, and controlling at least one output gate based on the first time difference and the second time difference if the comparison value is above a predetermined temperature range; and / or adjusting a first current and / or a second current if the comparison value is within the predetermined temperature range.

[0011] Hybrid semiconductor devices require two distinct voltages. Controlling the different currents of the SiC MOSFETs and Si IGBTs in the hybrid device and / or the switching output stage gates maintains the appropriate junction temperature of the hybrid semiconductor device. Therefore, one approach can be configured to control one or more gate drivers that control the transmission of two distinct voltages to the hybrid semiconductor device. A digital control algorithm approach can be configured to modulate the two distinct voltages to the hybrid semiconductor device without risking performance degradation or damage to the hybrid semiconductor device.

[0012] According to an embodiment, the method may further include a temperature difference within an allowable operating range, wherein the operating mode is the currently active operating mode. When the temperature difference is within the allowable operating range, the hybrid device operates with the desired performance. Because the hybrid device operates within the desired performance range, the method can continue with its currently active operating mode. The desired performance can be defined by several key performance indicators.

[0013] According to an embodiment, the method may further include: the temperature difference is outside the permissible operating range, and the operating mode is different from the current operating mode. When the temperature difference is outside the permissible operating range, the hybrid device may operate with degraded performance. Because the hybrid device operates with degraded performance, the method may further determine whether the temperature difference can be corrected using current variations or changes in the output stage gate.

[0014] If it is determined that the temperature difference can be corrected by changing the current, then the first layer of this method can change the first current of the SiCMOSFET and / or change the second current of the Si IGBT.

[0015] Alternatively, if it is determined that the temperature difference cannot be corrected by changing the current, the second layer of the method can change at least one of the gates in the output stage.

[0016] The step of changing at least one of the first current and the second current or changing at least one output stage gate reduces the temperature difference to within an acceptable temperature range.

[0017] According to an embodiment, the method may further include: controlling at least one output gate to be configured to generate a first time difference and a second time difference between a first output stage and a second stage.

[0018] Controlling the first time difference and / or the second time difference controls the time difference between turning on the first transmitter and turning on the second transmitter. For example, one output stage delivers voltage to a SiC MOSFET, and another output stage delivers another voltage to a Si IGBT. Managing the simultaneous turn-on time of the two transistors in the hybrid semiconductor power module manages the junction temperature of the hybrid semiconductor power module. Maintaining the junction temperature of the hybrid semiconductor power module maintains the desired operating performance. If the junction temperature rises above a threshold temperature, the performance of the semiconductor power module may degrade.

[0019] According to an implementation method, the method may further include: a first time difference is set to simultaneously turn on the first output stage and the second output stage.

[0020] According to an implementation, the method may further include: setting a first time difference to turn on the first output stage before the second output stage.

[0021] According to an implementation, the method may further include: setting a first time difference to turn on the first output stage after the second output stage.

[0022] According to an implementation, the method may further include: the second time difference is set to simultaneously turn off the first output stage and the second output stage.

[0023] According to an implementation, the method may further include: setting a second time difference to turn off the first output stage before the second output stage.

[0024] According to an implementation, the method may further include: setting a second time difference to turn off the first output stage after the second output stage.

[0025] Hybrid semiconductor power modules can be available in different configurations. For example, they can have different numbers of SiC MOSFETs and Si IGBTs. For instance, a hybrid semiconductor power module can include an equal number of SiC MOSFETs and Si IGBTs, more SiC MOSFETs than Si IGBTs, or fewer SiC MOSFETs than Si IGBTs. Different first time differences and different second time differences can be configured for different hybrid semiconductor power module configurations. For example, because SiC MOSFETs can operate at higher temperatures without performance degradation compared to Si IGBTs, the number of SiC MOSFETs and Si IGBTs can be a factor in determining the first time difference and / or the second time difference.

[0026] According to an implementation, the method may further include increasing the first current.

[0027] According to an implementation, the method may further include reducing the first current.

[0028] According to an implementation, the method may further include increasing the second current.

[0029] According to an implementation, the method may further include reducing the second current.

[0030] The multilayer approach can determine that the junction temperature of the hybrid semiconductor is higher than the desired junction temperature, but adjusting the first and second time differences is not necessary. If the junction temperature is higher than the permissible junction temperature but lower than the temperature difference threshold, the method can select a path to adjust the first current of the SiC MOSFET and / or the second current of the Si IGBT. Adjusting the first and / or second currents can be a less resource-intensive operation than adjusting the output stage gate. Furthermore, adjusting the first and / or second currents can be a faster operation than adjusting the output stage gate. Therefore, the multilayer approach can effectively maintain the junction temperature of the hybrid semiconductor power module without sacrificing its performance. Attached Figure Description

[0031] The present disclosure will now be described in more detail with reference to the accompanying drawings, which illustrate one embodiment of the present disclosure:

[0032] Figure 1 A device comprising at least one Si IGBT and at least one SiC MOSFET connected in parallel is shown;

[0033] Figure 2 A comparison chart of the on-state voltages of Si IGBT devices, SiC MOSFET devices, and hybrid (Si IGBT and SiC MOSFET in parallel) devices for different currents is shown.

[0034] Figure 3 A graph showing the current amplitude of the inverter output current is displayed;

[0035] Figure 4 Five possibilities for gate sequences to simultaneously supply voltage to Si IGBT devices and SiC MOSFET devices are shown;

[0036] Figure 5 A control architecture diagram is shown that is configured to adjust the gate driver according to a control method to maintain the temperature difference between Si IGBT and SiC MOSFET in a hybrid semiconductor power module;

[0037] Figure 6 The proposed flow of a method for controlling a gate driver IC according to some embodiments is shown;

[0038] Figure 7 The time difference between the two output stages of the IC's gate driver is shown;

[0039] Figure 8 A flowchart of a method for controlling the gate driver of a control IC according to some embodiments is shown. Detailed Implementation

[0040] This disclosure relates to a method for controlling the output gate of at least one gate driver. Specifically, the method involves controlling the output gate to deliver two different drive inputs (voltages) to a hybrid semiconductor power module. For example, a first drive input of a SiC MOSFET and a second drive input of a Si IGBT for the hybrid semiconductor power module. The hybrid semiconductor power module may include multiple SiC MOSFETs and multiple Si IGBTs. The SiC MOSFETs and Si IGBTs may be arranged in parallel within the hybrid semiconductor power module.

[0041] Multilayer methods can control the gate to supply power to hybrid semiconductor power modules (such as...) Figure 1 The hybrid semiconductor device provides two different drive inputs.

[0042] Figure 1 The hybrid semiconductor device 100 includes at least one SiC MOSFET 102 and at least one SiIGBT 104 connected in parallel. The SiC MOSFET 102 can receive a MOSFET voltage 112, such as a gate-source voltage. When receiving the MOSFET voltage 112, such that the MOSFET voltage 112 is greater than or equal to the MOSFET threshold of the SiC MOSFET 102, a MOSFET current 122 flows through the SiC MOSFET 102. The Si IGBT 104 can receive an IGBT voltage 114, such that the IGBT voltage 114 is greater than or equal to the IGBT threshold of the SiIGBT 104, and an IGBT current 124 flows through the Si IGBT 104. As a result of currents 122 and 124 flowing through their respective transistors, the hybrid semiconductor device 100 can generate a forward voltage 106 and a forward current 108.

[0043] The hybrid semiconductor device 100 may include a plurality of SiC MOSFETs 102 and a plurality of Si IGBTs 104. The hybrid semiconductor device 100 may include an equal number of SiC MOSFETs 102 and Si IGBTs 104. The hybrid semiconductor device 100 may include more SiC MOSFETs 102 than Si IGBTs 104. The hybrid semiconductor device 100 may include fewer SiC MOSFETs 102 than Si IGBTs 104.

[0044] Figure 2 Chart 200 shows a comparison of the measured on-state voltages of multiple semiconductor power module devices for different currents. Line 202 shows the measured on-state voltage of a hybrid device, such as hybrid semiconductor power module device 100. Line 204 shows the measured on-state voltage of a fully IGBT semiconductor power module device. Line 206 shows the measured on-state voltage of a fully MOSFET semiconductor power module device.

[0045] As shown in Table 200, at the same current, line 202 of the hybrid Si / SiC device has a lower on-resistance compared to line 204 of a pure Si IGBT device and / or line 206 of a pure SiC MOSFET device. The benefits of the hybrid device become apparent as the load increases. Therefore, the hybrid Si / SiC device offers lower conduction power losses when compared to both pure Si IGBT and pure SiC MOSFET devices. The switching speed of SiC MOSFETs, combined with gate sequence control between the Si IGBT and SiC MOSFET devices in the hybrid device, enables significantly lower switching power losses compared to pure Si IGBT devices. Therefore, the hybrid device provides a high-efficiency and high-power-density energy conversion system without incurring the higher cost of pure SiC MOSFET devices compared to pure Si IGBT devices.

[0046] Figure 3 An exemplary current cycle diagram 300 of the inverter output current of a hybrid semiconductor device (such as hybrid semiconductor device 100) is shown. The current cycle 300 can be an alternating current having a positive maximum value 302 and a negative maximum value 304. Control of the switching gate can be based on the amplitude of the current. A first positive current amplitude 306 and a first negative current amplitude 308 can represent the load current of the hybrid semiconductor device. The first current can be represented having a first positive current amplitude 306 and a first negative current amplitude 308. The first positive current amplitude 306 and the first negative current amplitude 308 can represent the safe operating current of a Si IGBT device of the hybrid semiconductor device. A second current can be represented having a second positive current amplitude 310 and a second negative current amplitude 312. The second positive current amplitude 310 and the second negative current amplitude 312 can represent the safe operating current of a SiC MOSFET device of the hybrid semiconductor device. A method can control one or more gates based on the inverter output current of the hybrid semiconductor device.

[0047] As shown in region 314, the current can be lower than or equal to the first positive current amplitude 306 and higher than or equal to the first negative current amplitude 308. This method can control one or more gates such that, during the time period represented by region 314, only the SiC MOSFET of the hybrid device is turned on and off. During the time period represented by region 314, the Si IGBT of the hybrid device can be in the off state.

[0048] As shown in region 316, the current can be lower than or equal to the amplitude of the second positive current amplitude 310, and higher than or equal to the second negative current amplitude 312. The current can be higher than or equal to the amplitude of the second positive current amplitude 306, and lower than or equal to the second negative current amplitude 308. This method can control one or more gates such that, during the time period indicated by region 316, the SiC MOSFET of the hybrid device is turned on before the Si IGBT of the hybrid device is turned on, and during the time period indicated by region 316, the SiC MOSFET of the hybrid device is turned off after the Si IGBT of the hybrid device is turned off.

[0049] As shown in region 318, the current can be greater than or equal to the amplitude of the second positive current amplitude 310, and less than or equal to the second negative current amplitude 312. This method can control one or more gates such that, during the time period indicated by region 318, the Si IGBT of the hybrid device is turned on before the SiC MOSFET of the hybrid device is turned on. During the time period indicated by region 318, the Si IGBT of the hybrid device is turned off after the SiC MOSFET of the hybrid device is turned off.

[0050] like Figure 3 As shown, this method can control the gate sequence between the SiC MOSFET and the Si IGBT of the hybrid device based on the inverter output current of the hybrid device. This method can determine the gate sequence defined by the time difference between turning the SiC MOSFET and the Si IGBT on / off of the hybrid device. Regarding... Figure 4 The gate sequence will be explained in further detail.

[0051] Figure 4 A sample of available switching patterns between a SiC MOSFET device and a Si IGBT device in a hybrid semiconductor device configuration is shown. Each pattern can be defined by the time difference between turning the SiC MOSFET device and the Si IGBT device on / off. A first pattern 410 can represent a scenario where a method controls one or more gate drivers to simultaneously turn the SiC MOSFET device and the Si IGBT device on and off. In other words, there is no time difference between turning the SiC MOSFET device and the Si IGBT device on / off.

[0052] The second pattern 420 can represent a scenario where a method controls one or more gate drivers to simultaneously turn on a SiC MOSFET device and a Si IGBT device. However, the method controls one or more gate drivers to turn off the SiC MOSFET after the Si IGBT device. The turn-off time difference 424 represents the amount of time between turning off the Si IGBT device and turning off the SiC MOSFET device. Depending on the perspective, the turn-off time difference 424 can be represented as a positive or negative value. For example, if the turn-off time difference 424 is taken from the perspective of the SiC MOSFET device, then the turn-off time difference 424 can have a negative value because the turn-off time of the Si IGBT device will be in the past compared to the turn-off time of the SiC MOSFET device. Alternatively, if the turn-off time difference 424 is taken from the perspective of the Si IGBT device, then the turn-off time difference 424 can have a positive value because the turn-off time of the SiC MOSFET will be in the future compared to the turn-off time of the Si IGBT device.

[0053] The third pattern 430 can represent a scenario where a method controls one or more gate drivers to turn on a SiC MOSFET before a Si IGBT device. Alternatively, the method controls one or more gate drivers to turn off the SiC MOSFET device after a Si IGBT device. The turn-on time difference 432 represents the amount of time between turning on the SiC MOSFET device and turning on the Si IGBT device. The turn-off time difference 434 represents the amount of time between turning off the Si IGBT device and turning off the SiC MOSFET device. The turn-on time difference 432 and the turn-off time difference 434 can be represented as positive or negative values ​​depending on the angle as previously explained.

[0054] The fourth pattern 440 can represent a scenario where a method controls one or more gate drivers to turn on a SiC MOSFET after a Si IGBT device. Alternatively, the method controls one or more gate drivers to turn off the SiC MOSFET after a Si IGBT device. The turn-on time difference 442 represents the amount of time between turning on the Si IGBT device and turning on the SiC MOSFET device. The turn-off time difference 444 represents the amount of time between turning off the Si IGBT device and turning off the SiC MOSFET device. The turn-on time difference 442 and the turn-off time difference 444 can be represented as positive or negative values ​​depending on the angle as previously explained.

[0055] The fifth pattern 450 can represent a scenario where a method controls one or more gate drivers to turn on a SiC MOSFET after a Si IGBT device. Alternatively, the method controls one or more gate drivers to turn off the SiC MOSFET before a Si IGBT device. The turn-on time difference 452 represents the amount of time between turning on the Si IGBT device and turning on the SiC MOSFET device. The turn-off time difference 454 represents the amount of time between turning off the SiC MOSFET device and turning off the Si IGBT device. The turn-on time difference 452 and the turn-off time difference 454 can be represented as positive or negative values ​​depending on the angle as previously explained.

[0056] The on-time differences 432, 442, and 452, and the off-time differences 424, 434, 444, and 454, can be determined to maintain the junction temperature of the hybrid semiconductor device within acceptable limits. In other words, the on-time and off-time differences maintain the temperature difference between the SiC MOSFET and the Si IGBT in the hybrid semiconductor device within acceptable temperature ranges. It should be noted that other configurations may be available.

[0057] This method can control one or more gate driver ICs to implement gate sequences according to, for example, regarding Figure 4 The described pattern, such as the one described above, delivers a first voltage to a SiC MOSFET device in a hybrid power semiconductor device and a second voltage to a Si IGBT device.

[0058] Figure 5 Control diagram 500 is shown, including a digital logic controller 506 capable of storing methods. The method can be configured to, when executed by the digital logic controller 506, according to, such as... Figure 8 The method is a control method to maintain the temperature difference between Si IGBTs and SiC MOSFETs in a hybrid semiconductor power module.

[0059] The control architecture diagram 500 may include a temperature balance controller 504. The temperature balance controller 504 can determine the temperatures of the Si IGBT and SiC MOSFET in the hybrid semiconductor device. The temperature balance controller 504 can further determine whether the temperature difference between the Si IGBT and the SiC MOSFET is within an acceptable range.

[0060] The control architecture diagram 500 may also include a current modulator 502 that modulates the inverter output current received from the hybrid semiconductor device.

[0061] Digital controller 506 can perform a method of controlling the gate of gate driver 508 based on the determination of temperature balance controller 504 and current modulation of current modulator 502. This method can be stored in digital controller 506 and connected to gate driver 508. Digital controller 506 can execute this method to control the gate of gate driver 508 based on signals from temperature balance controller 504 and current modulator 502. This method can determine a time difference based on the signals from temperature balance controller 504 and current modulator 502. This method can generate a time difference between at least two gates of gate driver 508 to be turned on and / or off based on the time difference.

[0062] The control architecture diagram 500 may include one or more methods to determine the temperature and control the gate to generate the desired pattern, such as Figure 4 The style discussed in the text.

[0063] Figure 6 Figure 600 illustrates three different modes of an exemplary multilayer method, where the three different modes are based on inverter output current. The inverter output current is received from a hybrid semiconductor device, and the multilayer method can control the gate driver based on the inverter output current. Based on the received information, the multilayer method can determine the temperature difference between the junction temperature of the SiCMOSFET and the junction temperature of the Si IGBT in the hybrid semiconductor device. This temperature difference can then be compared to predetermined values, such as a temperature difference threshold. For example, the hybrid semiconductor device may have a maximum tolerance parameter. If the temperature difference is less than the maximum tolerance, the multilayer method can determine that when the hybrid semiconductor device operates below the maximum tolerance, the performance of the hybrid semiconductor device will benefit from regulating a first current and / or a second current.

[0064] The multilayer method can determine the incremental current added to the first current and / or the second current. For example, the first current or the second current can be represented by a positive current amplitude 602 and a negative current amplitude 604. The multilayer method can determine that, in order to maintain the operating performance of the hybrid semiconductor device, the first current or the second current needs to be regulated by the incremental current. In other words, the method can regulate the first current and / or the second current by the amount determined by the incremental current to reduce the temperature difference of the hybrid semiconductor device.

[0065] For example, the difference between the first current represented by positive current amplitude 602 and negative current amplitude 604 can be adjusted by incremental current to generate positive changing current amplitude 606 and negative changing current amplitude 608. The difference between positive current amplitude 602 and positive changing current amplitude 606 is the value of the incremental current. Similarly, the difference between negative current amplitude 604 and negative changing current amplitude 608 is the value of the incremental current. The multilayer method will determine the incremental current to define the positive changing first current amplitude 606 and the negative changing first current amplitude.

[0066] For example, a multi-layer approach can determine the incremental current (dI) based on a pre-characterized regulation table. This pre-characterized regulation table can be stored in a register. A multi-layer approach can also determine the operating mode based on the inverter output current. The operating mode can similarly be stored in a table, where the operating mode is based on the relationship between the inverter output current and a first current and / or the incremental current.

[0067] If the difference between the SiC MOSFET and Si IGBT of the hybrid semiconductor device is greater than (or equal to) the maximum permissible difference, then the SiC MOSFET and Si IGBT have a temperature difference that cannot be corrected by adjusting the first current and / or the second current.

[0068] Figure 600 illustrates three operating modes. Mode 610 shows the time when the inverter output current is within the normal range and no adjustment is required. During the region represented by Mode 610, the multilayer method will generate a pulse width modulation (PWM) signal according to Mode 610. In other words, the switching pattern will remain the same.

[0069] During the time periods represented by modes 620 and 630, the multilayer method can determine the relationship between the junction temperature and the maximum permissible temperature difference. If the junction temperature difference is within the permissible range, no adjustment of the operating mode is required. If the junction temperature is outside the permissible range, the multilayer method can adjust the first time difference and / or the second time difference according to different operating modes. Adjusting the first time difference and / or the second time difference will maintain the temperature difference within the permissible range by reducing the time that the SiC MOSFET and Si IGBT in the hybrid semiconductor device are simultaneously turned on. In this way, the SiC MOSFET, which tolerates a higher junction temperature than the Si IGBT, will not be turned on for too long when the Si IGBT is operating.

[0070] Figure 7 The switching pattern is illustrated, where the Si IGBT 702 is turned on before the SiC MOSFET 704 and turned off after the SiC MOSFET 704. For example, when the SiC MOSFET is in operation, it can raise the junction temperature of the hybrid semiconductor device. At some point, at the beginning of the second time difference 714, the junction temperature of the hybrid semiconductor device may become too high for the Si IGBT to operate without performance degradation. Therefore, the first time difference 712 and the second time difference 714 are defined to maintain the junction temperature of the hybrid semiconductor so that both the Si IGBT 702 and the SiC MOSFET 704 can operate without degradation.

[0071] Time differences 712 and 714 can be the relative time between two or more gates of two or more output stages of the gate driver. Pattern 700 can be associated with an operating mode, and a multilayer approach is configured to control the gates to generate pattern 700 and deliver voltage via the output stages. The output stages can delay the delivery of the second voltage to the SiC MOSFET 704 until time difference 712 has elapsed relative to the delivery of the first voltage to the Si IGBT 702. Additionally, the multilayer approach can control the output stages to terminate the delivery of the second voltage to the SiC MOSFET 704 before terminating the first voltage to the Si IGBT 702.

[0072] The multi-layer approach can control the output stage based on junction temperature and inverter output current. For example, the multi-layer approach can adjust the first time difference 712 and / or the second time difference 714 based on the inverter output current.

[0073] Those skilled in the art will understand that the first and second time differences can be configured to create many different patterns. For example, two output stages may start and stop transmitting voltage simultaneously. A multi-level approach can control the output stages such that the first output stage can be turned on earlier, later, or simultaneously compared to the second output stage. The same applies to shutdown; the first output stage can be turned off earlier, later, or simultaneously compared to the second output stage. When controlled by a second controller performing the multi-level approach, any two output stages among the multiple output stages can have the same performance.

[0074] Figure 8 An exemplary method 800 for controlling a gate driver based on received information about a hybrid semiconductor device is illustrated. Method 800 may include two layers. The first layer may include elements 802-820 to determine whether it is possible to utilize, as referenced... Figure 6 The described current regulation is used to maintain the permissible junction temperature of the hybrid semiconductor device. Intermediate elements 824-830 may be intermediate steps between the first and second layers and determine the operating mode. The second layer may include elements 832-836 to adjust the first time difference and / or the second time difference based on the operating mode.

[0075] Steps 808 and 816 correspond to the first operating mode 824. The first operating mode 824 corresponds to the operating mode when the inverter output current is within current amplitudes 602 and 604, such as... Figure 6 As shown. Therefore, operation mode 824 can correspond to Figure 6 Pattern 610.

[0076] Steps 810 and 818 correspond to the second operating mode 826. The second operating mode 826 corresponds to the operating mode when the inverter output current is within current amplitudes 606 and 602 or current amplitudes 604 and 608, such as... Figure 6 As shown. Therefore, operating mode 826 can correspond to Figure 6 The pattern is 620.

[0077] Steps 812 and 820 correspond to the third operating mode 828. The third operating mode 828 corresponds to the operating mode when the inverter output current is greater than the current amplitudes 606 and 608, such as... Figure 6 As shown. Therefore, operation mode 828 can correspond to Figure 6 Pattern 630.

[0078] After determining that the temperature difference of the hybrid semiconductor devices is greater than a temperature difference threshold, method 800 proceeds to steps 804, 806, 808, 810, and 812. After determining that the temperature difference of the hybrid semiconductor devices is less than a temperature difference threshold, method 800 proceeds to steps 816, 818, and 820. When the temperature difference equals the temperature difference threshold, method 800 may proceed to steps 804, 806, 808, 810, and 812 or steps 816, 818, and 820.

[0079] Step 802 can compare the hybrid semiconductor temperature difference with a temperature difference threshold, where the hybrid semiconductor temperature difference is the difference between the junction temperatures of the Si IGBT and the SiC MOSFET in the hybrid semiconductor.

[0080] If the temperature difference is greater than the temperature difference threshold, step 804 determines whether the first current and / or the second current can be adjusted to maintain the temperature difference within the allowable temperature difference. Step 804 determines the incremental current from the adjustment table 814.

[0081] Step 806 will be conducted as per the above. Figure 6 The incremental current value of the described adjustment table is used to adjust the first current and / or the second current.

[0082] Steps 808 and 816 determine whether the inverter output current is within the current amplitude range. For example, it is between current amplitudes 602 and 604. Figure 6 As shown. If so, the current adjustment is sufficient to maintain the junction temperature of the hybrid semiconductor device within an effective operating temperature range and maintain the operating mode. Adjustment of the first time difference and / or the second time difference is not necessary. Step 830 generates a PWM signal according to the first operating mode 824.

[0083] If steps 808 and 816 determine that the inverter output current is not within current amplitudes 602 and 604, the multilayer method can proceed to steps 810 and 818, respectively. Steps 810 and 818 determine whether the inverter output current is within the regulated current amplitude. For example, between amplitudes 606 and 602, or between 604 and 608, such as... Figure 6As shown. If so, method 800 determines that the operation should be performed according to the second operation mode 826 and proceeds to step 832. Step 832 determines whether the temperature difference is greater than the allowable temperature difference. If the temperature difference is greater than the allowable temperature difference, the multilayer method 800 proceeds to step 836. Step 836 adjusts the first time difference and / or the second time difference according to the second operation mode 826. After adjusting the first time difference and / or the second time difference at step 836 or determining that the temperature difference is lower than the temperature difference threshold, method 800 proceeds to step 830. Step 830 generates a PWM signal according to the second operation mode 826.

[0084] If steps 810 and 818 determine that the inverter output is not within the regulated current amplitudes 606 and 602 or 604 and 608, then method 800 proceeds to steps 812 and 820. Steps 812 and 820 determine whether the inverter output current is greater than the regulated current amplitude. For example, amplitudes 606 and 608, such as... Figure 6 As shown. If so, method 800 determines that the operation should be performed according to the third operation mode 828 and proceeds to step 834. Steps 834 and 832 can be combined into one step. Step 834 determines whether the temperature difference is greater than the allowable temperature difference. If the temperature difference is greater than the allowable temperature difference, the multilayer method 800 proceeds to step 836. Step 836 adjusts the first time difference and / or the second time difference according to the third operation mode 828. After adjusting the first time difference and / or the second time difference at step 836, or after determining that the temperature difference is lower than the temperature difference threshold, method 800 proceeds to step 830. Step 830 generates a PWM signal according to the third operation mode 828.

[0085] Those skilled in the art will understand that comparing the inverter output current with the current amplitude in steps 808, 810, 812, 816, 818, and 820 may include comparisons and equality. For example, when determining whether the inverter output current is greater than the current amplitude, the current amplitude may be expressed as greater than or equal to.

[0086] Method 800 can be stored and executed on a microcontroller unit (MCU) that communicates with one or more gate drivers. The MCU can process the digital signals generated by the method and control one or more gate drivers based on the instructions generated by method 800.

[0087] While this disclosure has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes can be made and elements can be substituted with equivalents without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of this disclosure without departing from the basic scope of this disclosure. Therefore, it is intended that this disclosure be limited to the specific embodiments disclosed, but rather that it encompass all embodiments falling within the scope of the appended claims.

Claims

1. A method comprising: Receives the inverter output current; The first junction temperature and the second junction temperature are estimated based on the inverter output current using a loss model. Determine the temperature difference between the first junction temperature and the second junction temperature; A comparison value is generated based on the comparison between the temperature difference and the temperature difference threshold. An operating mode is determined based on the comparison value, wherein the operating mode is defined by the output current amplitude, and wherein the operating mode is associated with a first time difference and a second time difference. The first time difference is adjusted to meet the temperature difference threshold, wherein the first time difference is the time difference between the turn-on time of the first output stage and the turn-on time of the second output stage; and The second time difference is adjusted to meet the temperature difference threshold, wherein the second time difference is the time difference between the time when the first output stage is turned off and the time when the second output stage is turned off, and at least one output gate is controlled based on the first time difference and the second time difference.

2. The method according to claim 1, wherein, The temperature difference is within the permissible operating range, and the operating mode is the operating mode in progress.

3. The method according to claim 1, wherein, The temperature difference is outside the permissible operating range, and the operating mode is different from the operating mode being performed.

4. The method according to claim 3, wherein, The at least one output gate is configured to generate the first time difference and the second time difference between the first output stage and the second stage.

5. The method according to claim 3 or 4, wherein, The first time difference is set to simultaneously turn on the first output stage and the second output stage.

6. The method according to claim 3, wherein, The first time difference is set to turn on the first output stage before the second output stage.

7. The method according to claim 3, wherein, The first time difference is set so that the first output stage is turned on after the second output stage.

8. The method according to claim 3, wherein, The second time difference is set to simultaneously shut down the first output stage and the second output stage.

9. The method according to claim 3, wherein, The second time difference is set to turn off the first output stage before the second output stage.

10. The method according to claim 3, wherein, The second time difference is set to turn off the first output stage after the second output stage.

11. The method of claim 2, further comprising increasing the first current.

12. The method of claim 2, further comprising reducing the first current.

13. The method of claim 2, further comprising increasing the second current.

14. The method of claim 2, further comprising reducing the second current.

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