Harmonic conversion gain reduction for mixer circuits

Abstract

The invention relates to harmonic conversion gain reduction for mixer circuits. The mixer circuit may include a first mixer transistor configured to receive a first oscillation signal, a second mixer transistor configured to receive a second oscillation signal, and a harmonic conversion gain suppression filter coupled between a source terminal of the first mixer transistor and a source terminal of the second mixer transistor. The harmonic conversion gain suppression filter may be configured to suppress a harmonic conversion gain of the mixer circuit. The mixer circuit may also include a third mixer transistor configured to receive the first oscillation signal, a fourth mixer transistor configured to receive the second oscillation signal, and another harmonic conversion gain suppression filter coupled between a source terminal of the third mixer transistor and a source terminal of the fourth mixer transistor. The mixer circuit may also include an output transformer and a notch filter interposed between coils of the output transformer.

Description

[0001] This application claims priority to U.S. Patent Application No. 19 / 202,644, filed May 8, 2025, and U.S. Provisional Patent Application No. 63 / 684,600, filed August 19, 2024, which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates in general to electronic devices, and more specifically to electronic devices having wireless communication circuitry. Background Technology

[0003] Electronic devices often possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuits, which include one or more antennas for transmitting and receiving radio frequency signals.

[0004] Wireless communication circuits may include transceivers with one or more mixers. A mixer in the transmit path can be used to modulate a signal from a baseband frequency to a radio frequency (RF), while a mixer in the receive path can be used to demodulate a signal from the RF frequency back to the baseband frequency. The mixer receives a clock signal generated from a local oscillator. Designing a satisfactory mixer for electronic devices can be challenging. Summary of the Invention

[0005] One aspect of this disclosure provides a mixer circuit comprising: a first mixer transistor configured to receive a first oscillation signal; a second mixer transistor configured to receive a second oscillation signal different from the first oscillation signal; and a harmonic conversion gain suppression filter coupled between a source terminal of the first mixer transistor and a source terminal of the second mixer transistor, wherein the harmonic conversion gain suppression filter is configured to suppress the harmonic conversion gain of the mixer circuit. The harmonic conversion gain suppression filter may include: an inductor coupled between the source terminals of the first mixer transistor and the second mixer transistor; an adjustable capacitor coupled between the source terminals of the first mixer transistor and the second mixer transistor; a pair of cross-coupled transistors coupled between the source terminals of the first mixer transistor and the second mixer transistor and coupled to the tail node; and a current source coupled to the tail node. The current source may be selectively activated to enable the pair of cross-coupled transistors and selectively deactivated to disable the pair of cross-coupled transistors.

[0006] The mixer circuit may further include: a first output coil coupled between the drain terminal of the first mixer transistor and the drain terminal of the second mixer transistor; a second output coil magnetically coupled to the first output coil and having opposite terminals configured as differential output ports of the mixer circuit; and an additional harmonic conversion gain suppression filter inserted between the first output coil and the second output coil, wherein the additional harmonic conversion gain suppression filter is configured to suppress the harmonic conversion gain of the mixer circuit. The additional harmonic conversion gain suppression filter may include: a filter coil at least magnetically coupled to the second output coil; and an adjustable filter capacitor coupled in parallel with the filter coil.

[0007] One aspect of this disclosure provides a mixer circuit comprising: a first input transistor and a second input transistor; a first pair of mixer transistors configured to receive an oscillation signal; a second pair of mixer transistors configured to receive the oscillation signal; and a first filter circuit coupled to the source terminals of the first pair of mixer transistors, wherein the first filter circuit includes an inductor and a capacitor. The first filter circuit may further include: a pair of cross-coupled transistors coupled to the inductor and the capacitor; and an adjustable current source coupled to the pair of cross-coupled transistors. The mixer circuit may further include: an output transformer having a primary coil coupled between the first pair of mixer transistors and between the second pair of mixer transistors, and having a secondary coil; and an output filter circuit inserted between the primary and secondary coils of the output transformer. The output filter may include a filter coil and a filter capacitor coupled in parallel with the filter coil.

[0008] One aspect of this disclosure provides a mixer circuit comprising: a first pair of mixer transistors configured to receive an oscillation signal; a second pair of mixer transistors configured to receive the oscillation signal; an output transformer coupled to the first pair of mixer transistors and the second pair of mixer transistors, the output transformer having a primary coil and a secondary coil; and a notch filter inserted between the primary coil and the secondary coil. The notch filter can be configured to suppress the harmonic conversion gain of the mixer circuit. The mixer circuit may further include: a first LC filter coupled to the source terminals of the first pair of mixer transistors; a first active quality factor enhancement component coupled to the first LC filter; a second LC filter coupled to the source terminals of the second pair of mixer transistors; and a second active quality factor enhancement component coupled to the second LC filter. Attached Figure Description

[0009] Figure 1 These are illustrations of exemplary electronic devices with wireless circuitry according to some implementation schemes.

[0010] Figure 2 This is a diagram illustrating an exemplary wireless circuit with a transceiver according to some implementation schemes.

[0011] Figure 3 This is a diagram illustrating an exemplary mixer in the transmission path according to some implementation schemes.

[0012] Figure 4 This is an illustration of how an intermediate frequency signal can be upconverted to the radio frequency range of interest by the third harmonic conversion gain of a transmitting mixer, according to some implementation schemes.

[0013] Figure 5 This is a block diagram of an exemplary mixer circuit coupled to a single-phase local oscillator according to some implementation schemes.

[0014] Figure 6 It is based on some implementation plans. Figure 5 The circuit diagram shows an example mixer circuit of the type shown.

[0015] Figure 7 It is a diagram showing the forward conversion gain of various types of mixers as a function of frequency, based on some implementation schemes. Detailed Implementation

[0016] Electronic devices, such as Figure 1The electronic device 10 may include wireless circuitry. The wireless circuitry may include one or more mixers, such as a mixer in the transmission path for up-converting (modulating) a signal from a lower frequency to a higher frequency, and a mixer in the receiving path for down-converting (demodulating) a signal from a higher frequency to a lower frequency. The mixer may receive an oscillation (clock) signal from a local oscillator (LO). The oscillation signal may have an oscillation frequency, sometimes referred to herein as the LO frequency. The mixer may shift the signal of interest near the LO frequency and its corresponding harmonics (e.g., at associated harmonic frequencies equal to integer multiples of the LO frequency). For example, the mixer may unintentionally shift the signal of interest near the third harmonic LO frequency, a phenomenon sometimes referred to herein as the mixer's "third harmonic conversion gain."

[0017] According to some implementations, a mixer may include two transistor pairs, a passive LC (inductor- and capacitor-based) filter coupled to the source terminals of the transistor pairs to suppress or reduce the mixer's third harmonic conversion gain, an active quality (Q) factor booster circuit configured to improve the third harmonic conversion gain suppression capability of the LC filter, and an output notch filter coupled to the mixer output terminals to further reduce the mixer's third harmonic conversion gain. The term "LC filter" can refer to a filter circuit having at least inductor and capacitor components. Mixer circuits configured in this way are technically advantageous and beneficial for suppressing unwanted in-band spurious emissions without causing excessive area and power consumption, and do not require additional trimming and component matching requirements.

[0018] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses; or other equipment worn on a user's head; or other wearable or micro-devices, televisions, computer monitors without embedded computers, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with a display is installed in a kiosk or car), voice-controlled speakers connected to the wireless Internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0019] like Figure 1As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some embodiments, housing 12 may be partially or entirely formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0020] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0021] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0022] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). ), such as Protocols for other short-range wireless communication links, such as protocols for wireless personal area networks (WPANs) or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G protocols, etc.), sixth-generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired distance detection protocols for signals transmitted at millimeter-wave and centimeter-wave frequencies), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0023] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to displays to detect pressure applied to displays), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0024] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communication. Wireless circuitry 24 (sometimes referred to herein as wireless communication circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using antennas.

[0025] Wireless circuit 24 can transmit and / or receive radio frequency signals within a corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). The frequency band processed by wireless circuit 24 may include wireless local area network (WLAN) bands (e.g., (IEEE 802.11) or other WLAN communication bands), such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands, such as 2.4GHz. Frequency bands or other WPAN communication bands; cellular telephone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); cellular sidebands; 6G bands between 100 GHz and 1000 GHz (e.g., sub-THz, THz, or THF bands, etc.); other centimeter or millimeter wave bands between 10 GHz and 300 GHz; near-field communication bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); in IEEE Ultra-wideband (UWB) bands operating under the 802.15.4 protocol and / or other ultra-wideband communication protocols; communication bands under the 3GPP wireless communication standard family; communication bands under the IEEE 802.XX standard family; and / or any other desired bands of interest.

[0026] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. (e.g.) Figure 2As shown, wireless circuitry 24 may include processing circuitry such as processing circuitry 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processing circuitry 26 may include a baseband processor, application processor, digital signal processor, microcontroller, microprocessor, central processing unit (CPU), programmable device, combinations of these circuits, and / or one or more processors within circuitry 18. Processing circuitry 26 may be configured to generate digital (transmit or baseband) signals. Processing circuitry 26 may be coupled to transceiver 28 via path 34 (sometimes referred to as the baseband path). Transceiver 28 may be coupled to antenna 42 via RF transmit line path 36. RF front-end module 40 may be disposed along RF transmit line path 36 between transceiver 28 and antenna 42.

[0027] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0028] exist Figure 2 In the example, for clarity, wireless circuit 24 is illustrated as including only a single processing unit 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processing units 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processing unit 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry configured to output uplink signals to antenna 42, may include receiver circuitry configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmission line path 36. If desired, one or more RF transmission line paths 36 in wireless circuit 24 may be implemented without any front-end modules inserted thereon.

[0029] The front-end module (FEM) 40 may include radio frequency (RF) front-end circuitry that operates on RF signals transmitted (transmitted and / or received) via RF transmission line path 36. The FEM may include, for example, FEM components such as RF filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more RF switches), RF amplifier circuitry 48 (e.g., one or more power amplifiers and one or more low-noise amplifiers), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 to the impedance of RF transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the RF signals transmitted and / or received by antenna 42. Each of the FEM components may be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If needed, various front-end module components can also be integrated into a single integrated circuit chip.

[0030] Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be inserted within the RF transmit line path 36, integrated into the FEM 40, and / or integrated into the antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to regulate the frequency response and wireless performance of the antenna 42 over time.

[0031] The RF transmit line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path coupled to the positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may have a ground transmit line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0032] RF transmission path 36 may include a means for communication with device 10 ( Figure 1The transmitting lines in device 10 route the radio frequency antenna signals within the device. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. The transmitting lines in device 10 (such as the transmitting lines in RF transmitting line path 36) may be integrated into rigid and / or flexible printed circuit boards. In a suitable arrangement, the RF transmitting line path (such as RF transmitting line path 36) may also include transmitting line conductors integrated within a multilayer laminate structure (e.g., layers of conductive materials (such as copper) and dielectric materials (such as resin) laminated together without the intervention of adhesives). If desired, the multilayer laminate structure may be folded or bent in multiple dimensions (e.g., two-dimensional or three-dimensional) and may retain its bent or folded shape after bending (e.g., the multilayer laminate structure may be folded into a specific three-dimensional structural shape to wire around other device components and may be rigid enough to retain its shape after folding without being held in place by reinforcements or other structures). All the multiple layers of a laminated structure can be laminated together in batches without adhesive (e.g., in a single pressing process) (e.g., in contrast to performing multiple pressing processes to laminate multiple layers together with adhesive).

[0033] Transceiver circuitry 28 may include processing WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz. Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits for processing cellular phone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); ultra-wideband (UWB) transceiver circuits for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuits for covering any other desired communication frequency bands of interest.

[0034] During wireless transmission, processing circuitry 26 provides digital signals to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting baseband signals received from processing circuitry 26 into corresponding intermediate frequency (IF) or radio frequency (RF) signals. For example, transceiver circuitry 28 may include mixer circuitry 50 for up-converting (or modulating) the baseband signal to IF or RF before transmission via antenna 42. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 may include transmitter components to transmit RF signals via RF transmission line path 36 and front-end module 40 through antenna 42. Antenna 42 transmits the RF signal to external wireless equipment by radiating the RF signal into free space.

[0035] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission path 36 and front-end module 40. Transceiver 28 may include circuitry for converting the received RF signals into corresponding intermediate frequency (IF) or baseband signals. For example, before transmitting the received RF signals via path 34 to processing circuitry 26, transceiver 28 may use mixer circuitry 50 to downconvert (or demodulate) the received signals to a baseband frequency. Mixer circuitry 50 may include local oscillator circuitry, such as local oscillator (LO) circuitry 52. ​​Local oscillator circuitry 52 can generate oscillator (oscillation) signals, which mixer circuitry 50 uses to modulate the transmitted signals from baseband frequency to RF and / or demodulate the received signals from RF frequency to baseband frequency.

[0036] Figure 3This is a diagram illustrating an exemplary mixer in the transmit (TX) path of a wireless circuit. (Example...) Figure 3 As shown, mixer 51 outputs radio frequency (RF) signals, which are ultimately radiated by antenna 42. Mixer 51 in the transmit (uplink) path can be referred to as the transmit mixer. Mixer 51 can represent... Figure 2 One or more transmit mixers are shown in the mixer circuit 50. Transmit mixer 51 may have a first input configured to receive a signal in the intermediate frequency (IF) range, a second input configured to receive an oscillation signal LO, and an output on which a modulated signal (for example) up-converted to the radio frequency (RF) range is generated. The oscillation signal (sometimes referred to as the LO signal) may have a frequency f, sometimes referred to herein as the LO frequency. LO The oscillation frequency. One or more components (such as RF couplers, filter circuits, antenna tuning elements, matching networks, switching circuits, amplifier circuits, other RF front-end components, other transceiver components, and / or other wireless components) may be disposed in the transmission path between the transmit mixer 51 and the antenna 42. The transmit mixer 51 that outputs the RF signal may be referred to as an RF mixer.

[0037] Figure 4 This is an illustration demonstrating how the third harmonic conversion gain of the transmitter mixer 51 can generate unwanted in-band emissions at the mixer output. Generally, mixer 51 enables the signal of interest (e.g., at the IF frequency f) to emit signals into the desired frequency range. IF The signal at LO frequency f LO Nearby shift. As an example, at frequency (f LO ±f IF The signal amplitude at frequency f IF The ratio of the signal amplitudes can be defined in this paper as the mixer's "basic conversion gain" or transfer function. As another example, at a frequency (3*f... LO ±f IF The signal amplitude at frequency f IF The ratio of the signal amplitudes can be defined in this paper as the mixer's "third harmonic conversion gain" or transfer function. More generally, at frequency (N*f) LO ±f IF The signal amplitude at frequency f IF The ratio of the signal amplitudes can be defined in this paper as the Nth-order “harmonic conversion gain” or transfer function of the mixer (or more generally as “harmonic conversion gain”). It is generally desirable to maximize the basic conversion gain while minimizing the Nth-order harmonic conversion gains greater than 1 (e.g., to mitigate or suppress the second-order, third-order, fourth-order, fifth-order, etc. harmonic conversion gains).

[0038] like Figure 4As shown, the intermediate frequency signal 60 received at the first input terminal of mixer 51 can be located at frequency f. IF The LO signal 62 received at the second input terminal of mixer 51 can be located at frequency f. LO Furthermore, the modulation signal 68 generated at the output of mixer 51 can be located at radio frequency f. RF In fact, the local oscillator at the second input of the feed-transmitter mixer 51 can exhibit nonlinear behavior, which causes a frequency of 2*f LO The second harmonic component 64, at a frequency of 3*f LO The generation of the third harmonic component 66 and / or other harmonic components. Figure 4 In the example, the third harmonic LO component 66 can be mixed with the signal of interest 60 to generate a corresponding interference signal 70 that falls within the radio frequency range of interest (e.g., see at frequency f). 3LOmIF Landing arrow 72, where f 3LOmIF Equals 3*f LO minus f IF As mentioned above, this phenomenon can be attributed to the third harmonic conversion gain of mixer 51. If the RF f... RF and local oscillator frequency f LO The selection of the frequency f of the interference signal 70 causes the interference signal 70 to fall within or near the radio frequency (RF) range of interest. 3LOmIF There may be problems, such as Figure 4 As illustrated in the examples. In some examples, signal 70 may interfere at the output of the transmitting mixer 51 at f RF The radio frequency signal 68 of interest could lead to a transmission path that violates performance standards.

[0039] Figure 3 and Figure 4 The scenario illustrated in relation to mixer 51 in the transmit path is exemplary. The embodiments described herein may be additionally or alternatively applied to mixers in the receive path (e.g., a path for receiving and processing radio frequency signals received by antenna 42). Mixers in the receive path may also exhibit harmonic conversion gain, such as third harmonic conversion gain, which generates spurious in-band signals that can potentially degrade the performance of the receive path.

[0040] According to the implementation scheme, mixer circuit 50 has harmonic conversion gain suppression capability (e.g., see...). Figure 5 ).like Figure 5As shown, mixer circuit 50 may include mixer circuit 51 and one or more filters such as filter 54 and filter 56. Mixer circuit 51 may include two pairs of mixing transistors. Mixer circuit 51 may be configured to receive a differential LO signal, which may include LO+ and LO-. Filter 54 may include one or more harmonic conversion gain suppression filters coupled to the source terminals of the mixing transistors. Therefore, filter 54 may sometimes be referred to herein as a harmonic conversion gain suppression “source” filter. Filter 56 may be coupled to the output (load) of mixer circuit 51. Therefore, filter 56 may sometimes be referred to herein as a harmonic conversion gain suppression “output” filter. The term “harmonic conversion gain suppression” may refer to and is defined herein as the action of suppressing, filtering, suppressing, or otherwise reducing the Nth harmonic conversion gain of a mixer, where N may be equal to 2, 3, 4, 5, or other integer values.

[0041] Figure 5 The implementation scheme (where circuit 50 includes only one mixer circuit 51 having two pairs of mixer transistors configured to receive a differential LO signal) is sometimes referred to as a "single-phase" mixer circuit. In contrast, a multiphase mixer can be configured to receive multiple LO signals of different phases. For example, a multiphase mixer may include a first portion configured to receive a first LO signal, a second portion configured to receive a second LO signal phase-shifted by 120 degrees relative to the first LO signal, and a third portion to receive a third LO signal phase-shifted by 240 degrees relative to the first LO signal. This type of "multiphase" mixer can be configured to suppress the mixer's third harmonic conversion gain, but requires multiple local oscillators to drive the buffer, multiple digital-to-analog converters (DACs) for gain scaling, multiphase calibration, additional trimming of DC offset between various mixer sections, additional area to accommodate more mixing components, and consumes more power.

[0042] Figure 6 It is at least a combination Figure 5 A circuit diagram of an exemplary single-phase mixer circuit 50 of the described type. Mixer circuit 50 may represent a transmitting mixer (e.g., a mixer in the transmitting path) or a receiving mixer (e.g., a mixer in the receiving path). Figure 6As shown, mixer circuit 50 may include a first input transistor 80-1 and a second input transistor 80-2, which are coupled to an input transformer, such as transformer 82. Transformer 82 may include a primary coil (winding) 81 and a secondary coil (winding) 83. Primary coil 81 may have a center tap shorted to the center tap of secondary coil 83, as shown by center tap connection 79. Connecting the center tap terminals of coils 81 and 83 together in this manner allows current to be shared or reused between the two coils. Therefore, transformer 82 configured in this way is sometimes referred to as a "current reuse" transformer. Current reuse transformer 82 is optional and may be omitted if necessary.

[0043] Input transistors 80-1 and 80-2 can be n-channel devices such as n-type metal-oxide-semiconductor (NMOS) transistors. The first input transistor 80-1 may have a drain terminal coupled to a first terminal of coil 81, a source terminal coupled to a ground power supply line 99 (e.g., a ground line providing a ground voltage), and a gate terminal configured to receive an input voltage Vin+. The second input transistor 80-2 may have a drain terminal coupled to a second terminal of coil 81, a source terminal coupled to ground line 68, and a gate terminal configured to receive an input voltage Vin-. The increments of voltages Vin+ and Vin- may represent the differential RF input signal of mixer circuit 50. When referring to the conductive terminals of a metal-oxide-semiconductor transistor, the terms "source" and "drain" are sometimes used interchangeably. Therefore, the source terminal and drain terminal are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal). Therefore, the drain terminal of transistor 80-1 can sometimes be referred to as the first source-drain terminal, and the source terminal of transistor 80-1 can be referred to as the second source-drain terminal (or vice versa).

[0044] The term "activation" in this document refers to or is defined as the action of placing the switch in a "conducting" or low-impedance state, such that the two terminals of the switch are electrically connected to conduct current. Activating a switch may sometimes be referred to as turning on or closing a switch. The term "deactivation" in this document refers to or is defined as the action of placing the switch in a "de-off" or high-impedance state, such that the two terminals of the switch / transistor are electrically disconnected with minimal leakage current. Deactivating a switch may sometimes be referred to as turning off or opening a switch.

[0045] Transformer 82 may be coupled to mixer subcircuits 53-1 and 53-2. Mixer subcircuit 53-1 may include a first pair of mixer transistors 76-1a and 76-1b (e.g., a first transistor pair). Mixer transistor 76-1a may have a source terminal, a gate terminal configured to receive signal LO+, and a drain terminal coupled to node o1. Mixer transistor 76-1b may have a source terminal, a gate terminal configured to receive signal LO-, and a drain terminal cross-coupled to node o2. Signals LO+ and LO- represent the positive and negative polarities of the differential signal and may be collectively referred to as the local oscillator (LO) signal or oscillation signal. The gate terminals of mixer transistors 76-1a and 76-1b together form a differential input port for receiving the LO signal. A load inductor (coil) 100p may be coupled across nodes o1 and o2. Specifically, the load inductor 100p may have a first terminal coupled to node o1 and a second terminal coupled to node o2.

[0046] The mixer sub-circuit 53-2 may include a second pair of mixer transistors 76-2a and 76-2b (e.g., a second transistor pair). Mixer transistor 76-2a may have a source terminal, a gate terminal configured to receive the signal LO+, and a drain terminal coupled to node o2. Mixer transistor 76-2b may have a source terminal, a gate terminal configured to receive the signal LO-, and a drain terminal cross-coupled to node o1. The gate terminals of mixer transistors 76-2a and 76-2b together form a differential input for receiving the LO signal.

[0047] According to the implementation, capacitor 110 and inductor 112 may be coupled across the source terminals of mixer transistors 76-1a and 76-1b. Specifically, capacitor 110 may have a first terminal coupled to the source terminal of transistor 76-1a and a second (opposite) terminal coupled to the source terminal of transistor 76-1b. Similarly, inductor 112 may have a first terminal coupled to the source terminal of transistor 76-1a, a second (opposite) terminal coupled to the source terminal of transistor 76-1b, and a center tap terminal coupled to the secondary coil 83 via path 113. If transformer 82 is omitted, the center tap of inductor 112 will be directly coupled to the drain terminal of the first input transistor 80-1. Capacitor 110 may be, for example, an adjustable capacitor implemented as a set of switchable capacitors (e.g., an array of capacitors, each of which is selectively activated by a corresponding switch), a variable capacitor sometimes referred to as a varactor diode, a varactor diode, a metal-oxide-semiconductor capacitor (MOSCAP), and / or other components configured to provide variable capacitance. Components 110 and 112, coupled to the source terminals of transistors 76-1a and 76-1b, can form part of a harmonic conversion gain suppression source filter 54-1 within the mixer circuit 50. In other words, components 110 and 112 can be configured as an LC filter (slot) circuit for reducing the third harmonic conversion gain of the mixer.

[0048] On the other side, another capacitor 110 and another inductor 112 may be coupled across the source terminals of mixer transistors 76-2a and 76-2b. Specifically, capacitor 110 may have a first terminal coupled to the source terminal of transistor 76-2a and a second (opposite) terminal coupled to the source terminal of transistor 76-2b. Similarly, inductor 112 may have a first terminal coupled to the source terminal of transistor 76-2a, a second (opposite) terminal coupled to the source terminal of transistor 76-2b, and a center tap terminal coupled to coil 83 via path 113. If transformer 82 is omitted, the center tap of inductor 112 will be directly coupled to the drain terminal of the second input transistor 80-2. Capacitor 110 may be, for example, an adjustable capacitor implemented as a set of switchable capacitors (e.g., an array of capacitors, each of which is selectively activated by a corresponding switch), a variable capacitor sometimes referred to as a varactor diode, a metal-oxide-semiconductor capacitor (MOSCAP), and / or other components configured to provide variable capacitance. Components 110 and 112 coupled to the source terminals of transistors 76-2a and 76-2b may form part of another harmonic conversion gain suppression source filter 54-2 within the mixer circuit 50. In other words, components 110 and 112 may be configured as an LC filter (slot) circuit for reducing the third harmonic conversion gain of the mixer.

[0049] Using purely passive LC components 110 and 112 for harmonic conversion gain filtering exhibits a limited filter quality (Q) factor. To further improve the filter Q factor, the harmonic conversion gain suppression source filter 54 may optionally be provided with active circuitry, including active components 114, 116, and 118. Shown as part of the harmonic conversion gain suppression source filter 54-1, transistor 114 (e.g., an n-type or NMOS device) may have a gate terminal coupled to the source terminal of mixer transistor 76-1a, a drain terminal cross-coupled to the source terminal of mixer transistor 76-1b, and a source terminal coupled to tail node T1; transistor 116 (e.g., an n-type or NMOS device) may have a gate terminal coupled to the source terminal of mixer transistor 76-1b, a drain terminal cross-coupled to the source terminal of mixer transistor 76-1a, and a source terminal coupled to tail node T1; and a current source 118 coupled between tail node T1 and ground line 99. Current source 118 can be an adjustable current source that is selectively activated to enable operation of the pair of cross-coupled transistors 114 and 116, and selectively deactivated to disable operation of the pair of cross-coupled transistors 114 and 116. When current source 118 is activated, harmonic conversion gain suppression source filter 54-1 provides an improved filter Q factor, which improves third harmonic conversion gain suppression while increasing the fundamental gain. Therefore, components 114, 116, and 118 are sometimes collectively referred to herein as active quality factor enhancement components.

[0050] On the other side, and shown as part of another harmonic conversion gain suppression source filter 54-2, transistor 114 (e.g., an n-type or NMOS device) may have a gate terminal coupled to the source terminal of mixer transistor 76-2a, a drain terminal cross-coupled to the source terminal of mixer transistor 76-2b, and a source terminal coupled to tail node T2; transistor 116 (e.g., an n-type or NMOS device) may have a gate terminal coupled to the source terminal of mixer transistor 76-2b, a drain terminal cross-coupled to the source terminal of mixer transistor 76-2a, and a source terminal coupled to tail node T2; and a current source 118 coupled between tail node T2 and ground line 99. Current source 118 may be selectively activated to enable operation of the associated cross-coupled transistors 114 and 116, and may be selectively deactivated to disable operation of the associated cross-coupled transistors 114 and 116. When the current source 118 is activated, the harmonic conversion gain suppression source filter 54-2 provides an improved filter Q factor, which improves the third harmonic conversion gain suppression while increasing the basic gain.

[0051] At the output side of mixer circuit 50, load inductor 100p may be magnetically coupled to a corresponding output inductor 100s. Output inductor 100s may have opposite terminals coupled to the differential output port OUT of mixer circuit 50. Arranged in this way, inductors 100p and 100s may operate as part of an output transformer, wherein inductor 100p is part of the primary winding of the output transformer, and inductor 100s is part of the secondary winding of the output transformer. Load inductor 100p may have a center tap configured to receive a positive supply voltage Vdd (e.g., inductor 100p has a center tap terminal coupled to a power supply line, such as a positive supply terminal).

[0052] According to some implementation schemes, the output transformer may also include a harmonic conversion gain suppression output filter 56. For example... Figure 6 As shown in the example, the harmonic conversion gain suppression output filter 56 may include an inductor 57 and a capacitor 58. The inductor (coil) 57 may be magnetically coupled to inductors 100s and / or inductor 100p. The inductor 57 may have opposite terminals respectively coupled to opposite terminals of the capacitor 58 (e.g., the inductor 57 and capacitor 58 are coupled together in parallel). The capacitor 58 may be, for example, an adjustable capacitor implemented as a set of switchable capacitors (e.g., an array of capacitors, each of which is selectively activated by a corresponding switch), a variable capacitor sometimes referred to as a varactor, a varactor diode, a metal-oxide-semiconductor capacitor (MOSCAP), and / or other components configured to provide variable capacitance.

[0053] In this configuration, the harmonic conversion gain suppression output filter 56 helps to further suppress the third harmonic conversion gain of the mixer. Operating in this manner, the inductor 57 may be referred to herein as a filter coil or harmonic conversion gain suppression coil, and the capacitor 58 may be referred herein as a filter capacitor or harmonic conversion gain suppression capacitor. The filter 56 may be a notch filter (as an example), and the capacitor 58 may be adjusted to tune the notch frequency of the filter 56, sometimes also referred to as the suppression frequency or zero frequency.

[0054] Figure 7This is a diagram illustrating the forward conversion gain of various types of mixers as a function of output frequency, based on some implementation schemes. Curve 200 can represent the forward conversion gain distribution of a mixer without any harmonic conversion gain suppression source filter 54 and without harmonic conversion gain suppression output filter 56. Curve 202 can represent the forward conversion gain distribution of a mixer circuit that includes a harmonic conversion gain suppression output filter 56 but does not include any harmonic conversion gain suppression source filter 54. Curve 204 can represent the forward conversion gain distribution of a mixer circuit that includes a harmonic conversion gain suppression source filter 54 but does not include a harmonic conversion gain suppression output filter 56. Curve 206 can represent a mixer circuit that includes a harmonic conversion gain suppression source filter 54 and also includes a harmonic conversion gain suppression output filter 56 (e.g., ...). Figure 6 The forward conversion gain distribution of mixer circuit 50 (as shown in the example).

[0055] like Figure 7 As shown, curve 202, relative to curve 200, maintains the output fundamental frequency f. RF At the same time as the gain at frequency f 3LOmIF It provides improved third harmonic conversion gain suppression. Furthermore, curve 204, relative to curve 202, maintains the output fundamental frequency f. RF At the same time as the gain at frequency f 3LOmIF Further improved third harmonic conversion gain suppression is provided. Finally, curve 206, relative to curve 204 (as noted by arrow 210), maintains the output fundamental frequency f. RF At the same time as the gain at frequency f 3LOmIF Further improvements in third harmonic conversion gain suppression are provided. In other words, it is technically advantageous and beneficial to maximize (third) harmonic conversion gain suppression by using a harmonic conversion gain suppression source filter 54 and / or a harmonic conversion gain suppression output filter 56 within the mixer circuit 50.

[0056] The above combination Figures 1 to 7 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1The storage device circuitry 16 and / or wireless communication circuitry 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless communication circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0057] According to the implementation scheme, the mixer circuit includes: a first mixer transistor configured to receive a first oscillation signal; a second mixer transistor configured to receive a second oscillation signal different from the first oscillation signal; and a harmonic conversion gain suppression filter coupled between the source terminals of the first mixer transistor and the second mixer transistor, wherein the harmonic conversion gain suppression filter is configured to suppress the harmonic conversion gain of the mixer circuit.

[0058] According to another embodiment, the mixer circuit optionally includes: a third mixer transistor configured to receive the first oscillation signal; a fourth mixer transistor configured to receive the second oscillation signal; and an additional harmonic conversion gain suppression filter coupled between the source terminals of the third mixer transistor and the fourth mixer transistor.

[0059] According to another embodiment, the mixer circuit optionally includes: a first input transistor configured to receive a first input voltage and coupled to the harmonic conversion gain suppression filter; and a second input transistor configured to receive a second input voltage and coupled to the additional harmonic conversion gain suppression filter.

[0060] According to another embodiment, the mixer circuit optionally includes: an input transformer including a primary coil having a first terminal coupled to the first input transistor and a second terminal coupled to the second input transistor; and a secondary coil having a first terminal coupled to the harmonic conversion gain suppression filter and a second terminal coupled to the additional harmonic conversion gain suppression filter.

[0061] According to another embodiment, the first terminal of the secondary coil is optionally coupled to the center tap of the inductor in the harmonic conversion gain suppression filter, and the second terminal of the secondary coil is optionally coupled to the center tap of the inductor in the additional harmonic conversion gain suppression filter.

[0062] According to another embodiment, the harmonic conversion gain suppression filter optionally includes an inductor coupled between the source terminal of the first mixer transistor and the source terminal of the second mixer transistor.

[0063] According to another embodiment, the harmonic conversion gain suppression filter further includes an adjustable capacitor coupled between the source terminal of the first mixer transistor and the source terminal of the second mixer transistor.

[0064] According to another embodiment, the harmonic conversion gain suppression filter optionally further includes a pair of cross-coupled transistors coupled between the source terminals of the first mixer transistor and the second mixer transistor and coupled to the tail node.

[0065] According to another embodiment, the harmonic conversion gain suppression filter optionally further includes a current source coupled to the tail node, the current source being configured to be selectively activated to enable the pair of cross-coupled transistors and selectively deactivated to disable the pair of cross-coupled transistors.

[0066] According to another embodiment, the mixer circuit optionally includes: a first output coil having a first terminal coupled to the drain terminal of the first mixer transistor, a second terminal coupled to the drain terminal of the second mixer transistor, and a center tap configured to receive a power supply voltage; a second output coil magnetically coupled to the first output coil and having opposite terminals configured as differential output ports of the mixer circuit; and an additional harmonic conversion gain suppression filter, the additional harmonic conversion gain suppression filter being inserted between the first output coil and the second output coil, wherein the additional harmonic conversion gain suppression filter is optionally configured to suppress the harmonic conversion gain of the mixer circuit.

[0067] According to another embodiment, the additional harmonic conversion gain suppression filter optionally includes a filter coil that is at least magnetically coupled to the second output coil.

[0068] According to another embodiment, the additional harmonic conversion gain suppression filter optionally further includes an adjustable filter capacitor coupled in parallel with the filter coil.

[0069] According to another embodiment, the harmonic conversion gain suppression filter is optionally configured to suppress the third harmonic conversion gain of the mixer circuit.

[0070] According to the implementation scheme, the mixer circuit includes: a first input transistor and a second input transistor; a first pair of mixer transistors configured to receive an oscillation signal; a second pair of mixer transistors configured to receive the oscillation signal; and a first filter circuit coupled to the source terminals of the first pair of mixer transistors, wherein the first filter circuit includes an inductor and a capacitor.

[0071] According to another embodiment, the mixer circuit optionally includes a second filter circuit coupled to the source terminals of the second pair of mixer transistors, wherein the second filter circuit includes an inductor and a capacitor.

[0072] According to another embodiment, the inductor of the first filter circuit optionally has a center tap coupled to the first input transistor, and the inductor of the second filter circuit optionally has a center tap coupled to the second input transistor.

[0073] According to another embodiment, the first filter circuit optionally further includes: a pair of cross-coupled transistors coupled to the inductor and the capacitor; and an adjustable current source coupled to the pair of cross-coupled transistors.

[0074] According to another embodiment, the mixer circuit optionally includes: an output transformer having a primary coil coupled between the first pair of mixer transistors and the second pair of mixer transistors, and having a secondary coil; and an output filter circuit inserted between the primary coil and the secondary coil of the output transformer, wherein the output filter includes a filter coil and a filter capacitor coupled in parallel with the filter coil.

[0075] According to the implementation scheme, the mixer circuit includes: a first pair of mixer transistors configured to receive an oscillation signal; a second pair of mixer transistors configured to receive the oscillation signal; an output transformer coupled to the first pair of mixer transistors and the second pair of mixer transistors, the output transformer having a primary coil and a secondary coil; and a notch filter inserted between the primary coil and the secondary coil, wherein the notch filter is configured to suppress the harmonic conversion gain of the mixer circuit.

[0076] According to another embodiment, the mixer circuit optionally includes: a first LC filter, the first LC filter optionally coupled to the source terminals of the first pair of mixer transistors; a first active quality factor enhancement component, the first active quality factor enhancement component optionally coupled to the first LC filter; a second LC filter, the second LC filter coupled to the source terminals of the second pair of mixer transistors; and a second active quality factor enhancement component, the second active quality factor enhancement component coupled to the second LC filter.

[0077] The foregoing is illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

[0078] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A mixer circuit, including: A first mixer transistor, configured to receive a first oscillation signal; The second mixer transistor is configured to receive a second oscillation signal that is different from the first oscillation signal; and A harmonic conversion gain suppression filter is coupled between the source terminal of the first mixer transistor and the source terminal of the second mixer transistor, wherein the harmonic conversion gain suppression filter is configured to suppress the harmonic conversion gain of the mixer circuit.

2. The mixer circuit according to claim 1 further includes: A third mixer transistor is configured to receive the first oscillation signal; A fourth mixer transistor, the fourth mixer transistor being configured to receive the second oscillation signal; and An additional harmonic conversion gain suppression filter is coupled between the source terminal of the third mixer transistor and the source terminal of the fourth mixer transistor.

3. The mixer circuit according to claim 2 further includes: A first input transistor is configured to receive a first input voltage and is coupled to the harmonic conversion gain suppression filter; and The second input transistor is configured to receive a second input voltage and is coupled to the additional harmonic conversion gain suppression filter.

4. The mixer circuit according to claim 3 further includes: Input transformer, the input transformer includes A primary coil having a first terminal coupled to the first input transistor and a second terminal coupled to the second input transistor, and The secondary coil has a first terminal coupled to the harmonic conversion gain suppression filter and a second terminal coupled to the additional harmonic conversion gain suppression filter.

5. The mixer circuit according to claim 4, wherein: The first terminal of the secondary coil is coupled to the center tap of the inductor in the harmonic conversion gain suppression filter; and The second terminal of the secondary coil is coupled to the center tap of the inductor in the additional harmonic conversion gain suppression filter.

6. The mixer circuit according to claim 1, wherein the harmonic conversion gain suppression filter comprises: An inductor coupled between the source terminal of the first mixer transistor and the source terminal of the second mixer transistor.

7. The mixer circuit according to claim 6, wherein the harmonic conversion gain suppression filter further comprises: An adjustable capacitor is coupled between the source terminal of the first mixer transistor and the source terminal of the second mixer transistor.

8. The mixer circuit according to claim 7, wherein the harmonic conversion gain suppression filter further comprises: A pair of cross-coupled transistors, the pair of cross-coupled transistors being coupled between the source terminal of the first mixer transistor and the source terminal of the second mixer transistor and coupled to the tail node.

9. The mixer circuit according to claim 8, wherein the harmonic conversion gain suppression filter further comprises: A current source coupled to the tail node, the current source being configured to be selectively activated to enable the pair of cross-coupled transistors and selectively deactivated to disable the pair of cross-coupled transistors.

10. The mixer circuit according to claim 1, further comprising: A first output coil has a first terminal coupled to the drain terminal of the first mixer transistor, a second terminal coupled to the drain terminal of the second mixer transistor, and a center tap configured to receive a power supply voltage. A second output coil is magnetically coupled to the first output coil and has opposite terminals configured as a differential output port of the mixer circuit. and An additional harmonic conversion gain suppression filter is inserted between the first output coil and the second output coil, wherein the additional harmonic conversion gain suppression filter is configured to suppress the harmonic conversion gain of the mixer circuit.

11. The mixer circuit of claim 10, wherein the additional harmonic conversion gain suppression filter comprises: A filter coil, which is at least magnetically coupled to the second output coil.

12. The mixer circuit of claim 11, wherein the additional harmonic conversion gain suppression filter further comprises: An adjustable filter capacitor is coupled in parallel with the filter coil.

13. The mixer circuit of claim 1, wherein the harmonic conversion gain suppression filter is configured to suppress the third harmonic conversion gain of the mixer circuit.

14. A mixer circuit, including: First input transistor and second input transistor; The first pair of mixer transistors is configured to receive an oscillation signal; A second pair of mixer transistors is configured to receive the oscillation signal; and A first filter circuit is coupled to the source terminals of the first pair of mixer transistors, wherein the first filter circuit includes an inductor and a capacitor.

15. The mixer circuit according to claim 14, further comprising: A second filter circuit is coupled to the source terminals of the second pair of mixer transistors, wherein the second filter circuit includes an inductor and a capacitor.

16. The mixer circuit according to claim 15, wherein: The inductor of the first filter circuit has a center tap coupled to the first input transistor; and The inductor of the second filter circuit has a center tap coupled to the second input transistor.

17. The mixer circuit of claim 14, wherein the first filter circuit further comprises: A pair of cross-coupled transistors, the pair of cross-coupled transistors being coupled to the inductor and the capacitor; and An adjustable current source is coupled to the pair of cross-coupled transistors.

18. The mixer circuit according to claim 14, further comprising: An output transformer having a primary coil coupled between the first pair of mixer transistors and the second pair of mixer transistors, and having a secondary coil; and An output filter circuit is inserted between the primary coil and the secondary coil of the output transformer, wherein the output filter includes a filter coil and a filter capacitor coupled in parallel with the filter coil.

19. A mixer circuit, including: The first pair of mixer transistors is configured to receive an oscillation signal; A second pair of mixer transistors is configured to receive the oscillation signal; An output transformer coupled to the first pair of mixer transistors and the second pair of mixer transistors, the output transformer having a primary coil and a secondary coil; and A notch filter is inserted between the primary coil and the secondary coil, wherein the notch filter is configured to suppress the harmonic conversion gain of the mixer circuit.

20. The mixer circuit according to claim 19, further comprising: A first LC filter, the first LC filter being coupled to the source terminals of the first pair of mixer transistors; A first active quality factor enhancement component is coupled to the first LC filter. A second LC filter is coupled to the source terminals of the second pair of mixer transistors; and The second active quality factor enhancement component is coupled to the second LC filter.

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