Dynamic impedance matching method and system for radio frequency switch and attenuator

Abstract

The invention relates to the technical field of communication, discloses a dynamic impedance matching method and system for a radio frequency switch and an attenuator, and aims to solve the technical problems that signal reflection is increased, insertion loss is increased and system performance is reduced due to the fact that a traditional fixed impedance matching network cannot adapt to port impedance change during state switching of the radio frequency switch and the attenuator. The method comprises the following steps: monitoring control signal changes of a radio frequency switch and an attenuator in real time, and generating a state identification code representing a current working state; and taking the identification code as an index, and retrieving a corresponding optimal tunable network control parameter from a pre-stored calibration parameter lookup table. By means of the scheme, rapid and accurate impedance matching can be achieved under all working state combinations, reflection loss and insertion loss are remarkably reduced, signal integrity and linearity are improved, and the overall performance and environmental adaptability of the system under broadband and multi-state application are improved.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a method and system for dynamic impedance matching of radio frequency switches and attenuators. Background Technology

[0002] Radio frequency (RF) technology serves as a core support for modern wireless communication, radar detection, and electronic measurement, and its performance directly determines the stability and reliability of the entire system. In complex RF systems, RF switches and RF attenuators are two fundamental and critical components, used to control the transmission path selection of RF signals and precisely adjust the power level of the signals, respectively.

[0003] To ensure minimal power loss and signal distortion during RF signal transmission between different components, impedance matching between ports is crucial. Good impedance matching effectively suppresses signal reflections, improving the transmission efficiency and signal quality of the entire RF link.

[0004] Existing impedance matching networks typically employ fixed passive components, and their design is optimized only for specific operating frequencies and single operating states. First, the performance of this fixed matching network deteriorates drastically when the system operating frequency changes or in broadband applications. Second, the port impedance of RF switches varies significantly between on and off states, or between different attenuation levels of digital step attenuators. Traditional static matching methods cannot accommodate all operating states, leading to severe impedance mismatches in some conditions. Furthermore, this mismatch causes a series of problems, including increased signal reflection, increased insertion loss, and decreased isolation. These issues collectively contribute to the overall performance degradation and insufficient adaptability of RF systems under dynamic operating conditions, constituting a pressing technical challenge that needs to be addressed. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a method and system for dynamic impedance matching between RF switches and attenuators. Existing RF systems, especially signal links containing RF switches and attenuators, commonly employ fixed-parameter impedance matching networks. These fixed networks can only achieve optimal impedance matching when the RF switch or attenuator is in a specific operating state. When the RF switch switches the signal path or the attenuator adjusts its attenuation, the equivalent impedance of the entire signal link changes, causing the original fixed matching network to fail, resulting in severe impedance mismatch. This mismatch leads to signal reflection, increased insertion loss, deteriorated in-band flatness, and reduced system linearity, severely limiting the overall performance of broadband RF systems under multiple operating states. This invention effectively solves the problems in the prior art by constructing a dynamic adjustment mechanism to ensure that the RF link maintains accurate matching with the system's characteristic impedance in real time under any combination of switching and attenuator operating states, thereby significantly improving the all-state performance of the RF front-end.

[0006] To achieve the above objectives, the present invention provides the following technical solution: In one aspect, a dynamic impedance matching system for an RF switch and attenuator, comprising the following components: The radio frequency signal processing unit includes a radio frequency switch and a radio frequency attenuator connected in series, which are used to perform path selection and amplitude adjustment of radio frequency signals. The status detection module, whose signal input terminal is connected to the control terminal of the RF switch and RF attenuator, is used to monitor the current combined operating status of the RF switch and RF attenuator in real time and generate a unique status identification code that represents the combined operating status. The data storage module pre-stores an impedance matching calibration parameter lookup table, which accurately records the deterministic mapping relationship between all possible combined operating states and a set of optimal tunable network control parameters. The control processing module, which is communicatively connected to the status detection module and the data storage module, is used to receive status identification codes and use them as indexes to retrieve the corresponding optimal tunable network control parameters from the lookup table in the data storage module, and finally generate hardware control instructions based on these parameters. A tunable impedance matching network is connected in series or parallel in the signal path of the RF signal processing unit and connected to the output of the control processing module. It is used to receive hardware control commands and precisely adjust the parameters of its internal variable reactance components, so that the input or output impedance of the RF signal processing unit in the current combined operating state can be dynamically matched with the system's preset characteristic impedance (e.g., 50 ohms).

[0007] Preferably, the status detection module determines the current combined operating state by monitoring the logic level state of the multi-bit digital control bus driving the RF switch and RF attenuator. The status identification code is a direct binary combination of the logic values ​​of all control bits on the multi-bit digital control bus or a unique digital code generated by a specific encoding algorithm.

[0008] Furthermore, the status detection module includes a set of logic level buffers and latches connected in parallel with the digital control bus. When a transition in any logic level on the control bus is detected, the status detection module latches the complete logic state on the current bus, generates a new status identification code, and sends an interrupt request signal to the control processing module or updates the status register to trigger a new impedance matching adjustment process.

[0009] Preferably, the data storage module is a non-volatile memory, specifically an electrically erasable programmable read-only memory (EEPROM) or flash memory. The impedance matching calibration parameter lookup table is generated during the system production phase using an automated calibration test platform.

[0010] Furthermore, the method for generating the impedance matching calibration parameter lookup table includes the following steps: connecting the RF signal processing unit and the tunable impedance matching network to a vector network analyzer; traversing every possible combination of operating states of the RF switch and RF attenuator through control logic; in each combination of operating states, systematically adjusting the control parameters of the tunable impedance matching network through an optimization algorithm (e.g., gradient descent or particle swarm optimization), and monitoring the reflection coefficient measured by the vector network analyzer in real time (S11); when the amplitude of the reflection coefficient in the target operating frequency band reaches the minimum value or is lower than a preset threshold (e.g., -25dB), recording the status identification code of the current combination of operating states and the corresponding optimal tunable network control parameters, and storing this mapping relationship as a record in the lookup table.

[0011] Preferably, the control processing module is a microcontroller (MCU), digital signal processor (DSP), or field-programmable gate array (FPGA). Upon receiving a new state identification code, the control processing module performs address mapping or table lookup operations to read the corresponding tunable network control parameters from the data storage module. The entire time delay from the detection of a state change to the completion of control command generation is controlled at the microsecond level, ensuring that the adjustment speed of the matching network is much faster than the envelope change rate of the radio frequency signal.

[0012] Preferably, the tunable impedance matching network is a passive network with variable reactance elements, and its topology is a π-type network, a T-type network, or a higher-order ladder network. The variable reactance elements are selected from at least one of the following: variable capacitors based on microelectromechanical systems (MEMS) technology, semiconductor varactor diodes, switched capacitor arrays controlled by PIN diodes or RF MEMS switches, or switched inductor arrays controlled by PIN diodes or RF MEMS switches. The tunable network control parameters are a set of digital codes used to set the specific reactance values ​​of these variable reactance elements.

[0013] Furthermore, the format of the hardware control instructions generated by the control processing module is matched to the driving method of the variable reactance elements in the tunable impedance matching network. If a MEMS variable capacitor is used, the hardware control instructions are converted into precise analog tuning voltages via a digital-to-analog converter (DAC); if a switched capacitor array is used, the hardware control instructions are parallel or serial (e.g., SPI or I2C protocol) digital logic signals that directly drive the switching on and off of each switch in the array.

[0014] In addition, the system also includes a closed-loop feedback correction unit, which includes: a directional coupler disposed at the input of the radio frequency signal processing unit; a power detector connected to the coupling port of the directional coupler for measuring the power of the reflected signal; and an analog-to-digital converter (ADC) for converting the analog voltage output by the power detector into a digital quantity and transmitting it to the control processing module.

[0015] Furthermore, after executing the lookup table-based open-loop control, the control processing module initiates a real-time fine-tuning program. This program uses the parameters provided by the lookup table as initial values, applies small perturbations to the control parameters of the tunable network, and iteratively optimizes the control parameters using a hill-climbing algorithm or a least mean square algorithm based on the reflected power changes fed back from the closed-loop feedback correction unit, until the reflected power reaches a local minimum. This closed-loop feedback mechanism is used to compensate for impedance drift caused by changes in ambient temperature, device aging, or manufacturing process deviations.

[0016] On the other hand, a method for dynamic impedance matching between an RF switch and an attenuator is described, the specific steps of which are as follows: Step S110: The digital control signals of the RF switch and RF attenuator in the RF signal processing unit are monitored in real time by the state detection module. When the digital control signal changes, the current combinational logic state is captured and a corresponding unique state identification code is generated. Step S120: The control processing module receives the status identification code and uses it as an index to query and retrieve the optimal tunable network control parameter that uniquely corresponds to the status identification code in the impedance matching calibration parameter lookup table pre-stored in the data storage module. In step S130, the control processing module parses the retrieved optimal tunable network control parameters and converts them into a set of precise digital or analog hardware control instructions according to the hardware interface specifications of the variable elements inside the tunable impedance matching network. In step S140, the control processing module outputs the generated hardware control command to the tunable impedance matching network, driving one or more variable reactance elements inside it to change their parameter values, thereby reconstructing the reactance characteristics of the matching network, so that the port impedance of the RF signal processing unit in the current new working state is accurately matched with the system characteristic impedance.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention achieves high performance across all operating states. By dynamically adjusting the impedance matching network, it ensures that the RF link maintains extremely low reflection and insertion losses in all combinations of its switching and attenuator operating states. This overcomes the technical bottleneck of traditional fixed matching networks being effective only in a single state, significantly improving the performance consistency and availability of the RF front end throughout its entire operating range.

[0018] Signal integrity and linearity are enhanced. Precise impedance matching is achieved in all states, significantly suppressing signal reflections and reducing signal distortion, group delay ripple, and multipath effects caused by reflections. This directly improves system linearity metrics such as the third-order intermodulation intercept (IP3) and the 1dB compression point (P1dB), which are crucial for ensuring the transmission quality of complex modulated signals.

[0019] It features high-speed response and high integration. The entire dynamic matching and adjustment process is controlled by high-speed digital logic, with response times ranging from nanoseconds to microseconds, fully meeting the application requirements of modern communication systems such as frequency hopping and time division duplex (TDD) for rapid state switching. Furthermore, all functional modules can be integrated into a single chip or system-in-package (SiP) module, achieving miniaturization and low cost.

[0020] It offers excellent robustness and adaptability. The open-loop control mode based on the pre-calibrated lookup table ensures the accuracy and speed of basic matching, while the optional closed-loop feedback correction unit can further compensate for impedance drift caused by factors such as temperature and aging in real time, enabling the system to maintain optimal performance in complex and variable working environments, and has extremely strong environmental adaptability and long-term stability. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall technical solution architecture of a dynamic impedance matching system for radio frequency switches and attenuators proposed in this invention. Figure 2This is a logic flowchart of a dynamic impedance matching method for radio frequency switches and attenuators proposed in this invention. Detailed Implementation

[0022] Please refer to Figure 1 and Figure 2 To further illustrate the technical means and effects of the present invention in order to achieve the intended purpose, the following detailed description of the specific implementation methods, structures, features and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0023] Example 1 This embodiment aims to illustrate in detail a dynamic impedance matching system and method for RF switches and attenuators based on open-loop control using a microcontroller (MCU). Please refer to [link to relevant documentation]. Figure 1 The figure illustrates the overall technical architecture of the system described in this embodiment. This system is applied to a wireless communication transceiver front-end module operating in the frequency range of 1.8 GHz to 2.2 GHz, with a target characteristic impedance of 50 ohms.

[0024] The dynamic impedance matching system physically consists of five core components: an RF signal processing unit, a status detection module, a data storage module, a control processing module, and a tunable impedance matching network. These five components work together to form a complete, high-speed, and precise dynamic impedance matching solution.

[0025] The RF signal processing unit is the core component of this system, integrating a single-pole quad-throw (SP4T) RF switch and a 6-bit digital step attenuator. The SP4T RF switch selects between four different signal links, and its operating state is determined by a 2-bit digital control bus (named SW_CTRL[1:0]). The 6-bit digital step attenuator provides an attenuation range of 0 to 31.5 dB with a step accuracy of 0.5 dB, and its attenuation is precisely set by a 6-bit digital control bus (named ATT_CTRL[5:0]). Under different switching paths and attenuation combinations, the input port impedance of the RF signal processing unit will undergo significant, non-linear changes, deviating from the standard 50 ohms. For example, when the switch selects path 1 and the attenuator is set to 0 dB, its input impedance at 2.0 GHz may be measured as (65 + j15) ohms; while when the switch is switched to path 3 and the attenuator is set to 16 dB, its input impedance may become (40 - j25) ohms. These changes are the targets that this system needs to dynamically compensate for.

[0026] In this embodiment, the status detection module is designed as a pure hardware logic circuit. Its core function is to monitor and capture changes in the operating status of the RF signal processing unit without delay. The input of this module is connected in parallel with the 8-bit (2-bit + 6-bit) digital control bus (SW_CTRL[1:0] and ATT_CTRL[5:0]) that drives the RF switch and attenuator. To ensure signal integrity and avoid load effects on the original control signal, a high-speed logic level buffer is connected in series on each bus line. The logic level state of this 8-bit bus uniquely defines the current combined operating state of the RF signal processing unit. The status detection module directly combines these 8 parallel logic level values ​​to form an 8-bit binary status identification code. For example, when SW_CTRL[1:0] is binary '01' (selecting path 2) and ATT_CTRL[5:0] is binary '010000' (attenuation of 16 dB), the generated status identification code is binary '01010000', corresponding to decimal 80. To capture any changes in state in real time, the module also integrates an edge detection circuit, which consists of an 8-input XOR gate and an OR gate cascaded together. Any transition in the control bus level (from 0 to 1 or from 1 to 0) generates a brief pulse at the output of the XOR gate. This pulse passes through the OR gate and triggers a D-type latch, precisely latching the currently stable 8-bit logic state on the bus, and simultaneously sending a rising-edge valid interrupt signal to the dedicated interrupt request pin (IRQ) of the control processing module.

[0027] The data storage module uses an electrically erasable programmable read-only memory (EEPROM) with an I2C serial interface, specifically model 24LC256, which has a storage capacity of 32 kilobytes. The core task of this module is to permanently store an impedance matching calibration parameter lookup table. This lookup table is generated during the automated calibration phase before the system leaves the factory, and its content contains a complete mapping relationship between all possible operating states of the RF signal processing unit and the optimal matching network control parameters. Since the status identification code is 8 bits, there are 2^8, or 256 possible combinations of operating states. Therefore, logically, the lookup table is a one-dimensional array containing 256 records. The index address of each record directly corresponds to a status identification code (from 0 to 255), and the content stored at that address is a set of optimal control parameters for configuring the tunable impedance matching network. In this embodiment, the tunable network requires 18 bits of digital control, so the data width of each record is 18 bits, actually occupying 3 bytes (24 bits, with the high 6 bits reserved) during storage. The entire lookup table occupies 256 * 3 = 768 bytes of storage space.

[0028] The lookup table generation process is completed on an automated test platform equipped with a Vector Network Analyzer (VNA). The specific process is as follows: First, the RF signal processing unit is cascaded with an unconfigured tunable impedance matching network and connected to the VNA's test port. The test control software sequentially iterates through 256 possible operating states via a digital I / O card. In each state, an optimization algorithm based on gradient descent is initiated. This algorithm starts with all zeros in the tunable network control parameters and systematically adjusts these 18-bit control parameters, essentially fine-tuning the reactive components within the tunable network. After each adjustment, the VNA rapidly scans the target frequency band (1.8 to 2.2 GHz), measures and returns the amplitude of the input reflection coefficient (S11). The optimization algorithm calculates the gradient based on the returned S11 value and continues adjusting the control parameters along the direction that causes the S11 amplitude to decrease the fastest. This iterative process continues until the maximum value of S11 is below a preset -25 dB threshold across the entire target frequency band. At this point, the algorithm terminates, and the test control software records the current status identification code and the corresponding 18-bit optimal control parameters, and writes this mapping relationship into the corresponding address unit of the EEPROM via the I2C interface. This process is automatically repeated 256 times until the entire lookup table is constructed.

[0029] The control processing module is the intelligent hub of the entire system. In this embodiment, a microcontroller (MCU) based on the ARM Cortex-M4 core, model STM32F401, is used. This MCU is responsible for executing the entire dynamic matching logic flow. During normal system operation, the MCU is in a low-power interrupt waiting state. When the status detection module detects a change in the control signal of the RF switch or attenuator and issues an interrupt request, the MCU is woken up and immediately executes the preset interrupt service routine (ISR). In this routine, the MCU first reads the 8-bit status identification code latched by the status detection module through its parallel port input pin. Subsequently, the MCU uses this status identification code as an address index to initiate a read operation to the data storage module (EEPROM) through its hardware I2C peripheral controller. The specific I2C communication protocol sequence is as follows: send start bit, send the 7-bit device address and write operation bit of the EEPROM, send the status identification code as the high and low byte addresses of the storage unit, send repeat start bit, send the device address and read operation bit again, then read 3 bytes of data continuously, and finally send stop bit. These 3 bytes of data represent the 18-bit optimal tunable network control parameters retrieved from the lookup table. The entire process, from receiving the interrupt signal to fully reading the 18-bit control parameters into the MCU's internal register, is strictly controlled within 5 microseconds, ensuring the system's high-speed response capability.

[0030] The tunable impedance matching network in this embodiment employs a π-type topology, consisting of two parallel branches and one series branch. To achieve parameter tunability, each branch comprises a switched capacitor array. Specifically, the switched capacitor arrays of the two parallel branches have identical structures, each array containing six binary-weighted capacitors (e.g., C, 2C, 4C, 8C, 16C, 32C), each grounded via an RF PIN diode switch. The switched capacitor array of the series branch also uses a similar six-binary-weighted capacitor and PIN diode switch. Thus, each capacitor array can have its equivalent capacitance value precisely set by a 6-bit digital control word, requiring a total of 18 bits of control signal for the three arrays. These 18 bits of control signal are directly provided by the 18 general purpose input / output (GPIO) pins of the MCU. The PIN diode driver circuit converts the CMOS level (0V or 3.3V) output from the MCU into the high or negative bias voltage required to drive the diodes forward or reverse.

[0031] Next, combined Figure 2 This paper details the specific execution steps of the dynamic impedance matching method for the RF switch and attenuator in this embodiment. The method flow closely corresponds to the functions of each module in the above system.

[0032] Step S110: Status Monitoring and Identification Code Generation. After the system powers on, the status detection module continuously performs hardware-level parallel monitoring of the eight signal lines connected to the RF switch control bus SW_CTRL[1:0] and the attenuator control bus ATT_CTRL[5:0]. At a certain moment, the external master control system needs to switch the RF link from its current state (e.g., switch path 2, attenuation 8 dB) to a new state (e.g., switch path 4, attenuation 20.5 dB). The master control system will change the logic level on these eight buses. The edge detection circuit inside the status detection module will immediately capture these level transitions and latch the new 8-bit parallel logic state within a very short time (nanosecond level) after the bus level stabilizes. At the same time, a valid interrupt request signal is sent to the IRQ pin of the MCU. At this time, the new 8-bit binary value stored in the latch is the unique status identification code representing the new working state.

[0033] Step S120: Look up the optimal control parameters in the table. After receiving an interrupt signal, the MCU's processor core suspends the currently executing main program and jumps to the interrupt service routine entry point. The program first clears the interrupt flag, and then reads the 8-bit status identification code into an internal working register by reading the GPIO port connected to the output of the status detection module's latch. Next, the MCU uses this 8-bit identification code as a memory address offset to start the I2C communication protocol stack and initiate an address read operation on the EEPROM in the data storage module. For example, if the read status identification code is decimal 150, the MCU will start reading 3 bytes of data from address 150*3=450 in the EEPROM. These 3 bytes (24 bits, with 18 effective bits) are the pre-calibrated and stored optimal tunable network control parameters that enable the RF signal processing unit to achieve optimal impedance matching in status 150.

[0034] Step S130: Control Parameter Parsing and Hardware Instruction Conversion. After successfully reading 3 bytes of data from the EEPROM, the MCU stores it in its internal RAM. Next, the MCU parses this data. Since the tunable impedance matching network consists of three independent 6-bit controlled switched capacitor arrays, the 18-bit control parameters are correspondingly divided into three 6-bit fields. For example, bits [5:0] correspond to the first parallel capacitor array, bits [11:6] correspond to the series capacitor array, and bits [17:12] correspond to the second parallel capacitor array. The MCU firmware performs bit operations to extract these three fields and prepares to map them to specific GPIO pins. The essence of this step is to convert the abstract control parameters into physical level signals that are fully compatible with the hardware interface specifications and can be directly driven.

[0035] In step S140, the matching network is reconfigured. After parameter parsing, the MCU outputs the 18-bit control logic level in parallel to its 18 GPIO pins through one or more write operations. These GPIO pins are connected to the PIN diode switch control terminals of the three switched capacitor arrays in the tunable impedance matching network via a driver circuit. A high level (3.3V) output from the GPIO causes the corresponding PIN diode to conduct in the forward direction, connecting its series capacitor to the circuit; a low level (0V) output causes the PIN diode to cut off in the reverse direction, disconnecting the capacitor. In this way, the equivalent capacitance value of the three switched capacitor arrays is precisely set to the value specified by the lookup table parameters. This causes a change in the overall reactance characteristics of the π-type network, and its input impedance is reconfigured to accurately compensate for the impedance changes generated by the RF signal processing unit in the new operating state. Finally, looking from the input port of the tunable network, the input impedance of the entire cascaded network is dynamically adjusted back to the system's characteristic impedance of 50 ohms, thus achieving precise impedance matching in the new combined operating state. The entire closed-loop time from state change to matching completion is less than 10 microseconds, which is much faster than the rate of change of the communication signal envelope, ensuring seamless signal transmission.

[0036] Example 2 This embodiment, based on Embodiment 1, introduces a closed-loop feedback correction unit to construct a hybrid control system combining open-loop coarse adjustment and closed-loop fine adjustment. This enhanced system aims to compensate for impedance drift caused by factors such as ambient temperature changes, component aging, or batch-to-batch variations in manufacturing processes, thereby maintaining optimal matching accuracy over longer timescales and under more complex operating conditions. The basic system architecture, including an RF signal processing unit, a status detection module, a data storage module, a control processing module, and a tunable impedance matching network, maintains the same structure and basic operating principle as Embodiment 1. This embodiment will focus on the structure and operating principle of the newly added closed-loop feedback correction unit, as well as the related improved dynamic impedance matching method.

[0037] In this embodiment, the closed-loop feedback correction unit consists of three key components: a directional coupler, a power detector, and an analog-to-digital converter (ADC).

[0038] The directional coupler is precisely positioned between the input of the RF signal processing unit and the output of the tunable impedance matching network. It is a passive microstrip line device with a coupling strength of -20 dB and a directivity greater than 25 dB. Its main path is connected in series in the main RF signal link, resulting in minimal insertion loss (less than 0.1 dB). The coupling port's function is to "sample" a small portion of the signal from the main path without interference. Due to its high directivity, when the signal is transmitted in the forward direction (from the input to the RF signal processing unit), the signal power output from the coupling port is extremely low. However, when the signal is reflected at the input of the RF signal processing unit due to impedance mismatch, the reflected signal power is coupled back to its coupling port by the directional coupler at a ratio of -20 dB. Therefore, the magnitude of the signal power output from the coupling port directly and monotonically reflects the severity of the port impedance mismatch.

[0039] The power detector is connected to the coupling port of the directional coupler. This embodiment uses a logarithmic amplifier detector, model ADL5902. This detector can convert the input RF signal power into a DC voltage with a linear logarithmic relationship over a wide dynamic range (e.g., 60 dB). Its output voltage V_out is related to the input power P_in (in dBm) as V_out = k * P_in + V_offset, where k is the slope (mV / dB) and V_offset is the intercept voltage. By using the logarithmic detector, the system can monitor a wide range of power variations, from weak to severe reflections, with near-constant sensitivity.

[0040] The analog-to-digital converter (ADC) is responsible for converting the analog DC voltage output from the power detector into a digital value for processing by the control processing module (MCU). In this embodiment, the 12-bit successive approximation ADC integrated within the STM32F401 MCU is directly utilized. This ADC has an input range of 0 to 3.3 volts and can quantize the detector output voltage into a digital code between 0 and 4095. ADC sampling is precisely triggered by a timer within the MCU, ensuring data acquisition only after the matching network has stabilized.

[0041] Based on the newly added hardware unit, the dynamic impedance matching method in this embodiment is extended from the first embodiment, forming a two-stage adjustment process: the first stage is a fast open-loop coarse adjustment based on a lookup table, and the second stage is a closed-loop fine adjustment based on real-time feedback.

[0042] The execution flow of the method is as follows: Initial State Switching and Open-Loop Coarse Adjustment Stage: This stage is exactly the same as steps S110 to S140 in Embodiment 1. When the state of the RF switch or attenuator changes, the state detection module captures the new state and interrupts the MCU. The MCU responds to the interrupt by retrieving the corresponding 18-bit initial control parameters from the EEPROM lookup table by querying the state identification code, and immediately outputs them to the tunable impedance matching network. This step is completed within 10 microseconds, rapidly adjusting the port impedance to a preset state close to the ideal matching point, ensuring the system's performance remains basically stable during state switching and avoiding large signal surges.

[0043] Initiation and execution of the closed-loop fine-tuning phase: After completing the open-loop coarse-tuning, the MCU does not return to the main loop to wait for the next state change, but immediately starts a closed-loop fine-tuning subroutine. The goal of this subroutine is to use the parameters provided by the lookup table as the starting point for optimization, and further reduce the reflected power to a minimum through small-scale perturbations and real-time feedback. This embodiment uses an improved hill-climbing algorithm to achieve this closed-loop optimization.

[0044] The specific steps for closed-loop fine-tuning are as follows: First, a baseline measurement is performed. After outputting the initial control parameters, the MCU delays for a short period (e.g., 1 microsecond) to ensure that the outputs of the matching network and the power detector have stabilized. Then, the MCU triggers its internal ADC to sample the output voltage of the power detector and stores the converted 12-bit digital value (denoted as P_base) as the current optimized baseline reflected power level.

[0045] Secondly, parameter perturbation. The MCU selects one bit from the 18-bit control parameters of the tunable network for perturbation; for example, it selects the least significant bit (LSB) of the first switched capacitor array control word (6 bits). The MCU toggles this bit (changing it from 0 to 1 and from 1 to 0) and outputs this slightly modified 18-bit parameter to the matching network via a GPIO port. This operation is equivalent to adding or subtracting a minimum unit of capacitance from a capacitor branch of the matching network.

[0046] Next, feedback evaluation. The MCU delays again and triggers the ADC to sample, obtaining a new reflected power value (denoted as P_new). Subsequently, the MCU compares P_new with P_base.

[0047] Then comes the decision-making and iteration. The decision-making logic of the hill-climbing algorithm is reflected here: if P_new is less than P_base, it means that the perturbation is beneficial, as it improves impedance matching and reduces reflected power. Therefore, the MCU will retain this change and update the value of P_base to P_new. Next, the algorithm will continue to explore along this "beneficial direction," for example, by continuing to flip the second least significant bit of the same control word. If P_new is greater than or equal to P_base, it means that the perturbation is ineffective or harmful, as it leads to worsening of the matching or no change. Therefore, the MCU will undo this change, that is, restore the bit that was just flipped to its original state, and re-output the corresponding control parameters to the matching network. Subsequently, the algorithm will try other perturbation directions, for example, flipping the LSB of another switched capacitor array control word, or flipping the same LSB in the opposite direction (if the first time was 0->1, then this time try 1->0, but this is equivalent to restoration in binary control).

[0048] Finally, convergence terminates. This iterative "perturbation-evaluation-decision" loop systematically traverses all 18 control bits, or more complex perturbation combinations. When the MCU finds that no possible small perturbation to any of the control bits can further reduce the reflected power value, the algorithm determines that a local optimum has been reached. At this point, the closed-loop fine-tuning process ends, the MCU locks the final optimized set of 18-bit control parameters at the output, and can enter a low-power mode until the next interruption caused by a change in the state of the RF switch or attenuator. The entire closed-loop fine-tuning process typically takes tens to hundreds of microseconds to complete, depending on the magnitude of the initial deviation.

[0049] By combining open-loop and closed-loop approaches, the system in this embodiment not only possesses the high-speed response capability of Embodiment 1, but also gains adaptive compensation capabilities against environmental and device aging factors. The lookup table ensures that regardless of the initial state, the system can always quickly converge to a satisfactory performance state, while the closed-loop feedback refines this process, ensuring that the system maintains its optimal performance point at all times, greatly improving the system's long-term stability and robustness.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A dynamic impedance matching system for radio frequency switches and attenuators, characterized in that, include: The radio frequency signal processing unit includes a radio frequency switch and a radio frequency attenuator connected in series. The status detection module has its signal input terminal connected to the control terminal of the RF switch and RF attenuator. It is used to monitor the current combined working state of the RF switch and RF attenuator in real time, and generate a status identification code that represents the current combined working state when the combined working state changes. The data storage module pre-stores an impedance matching calibration parameter lookup table, which records the deterministic mapping relationship between all preset combined operating states and a set of corresponding optimal tunable network control parameters. The control processing module establishes a communication connection with the status detection module and the data storage module. After receiving the status identification code generated by the status detection module, the control processing module uses the status identification code as an index to retrieve the optimal tunable network control parameters corresponding to the status identification code from the impedance matching calibration parameter lookup table in the data storage module, and generates hardware control instructions based on the retrieved optimal tunable network control parameters. A tunable impedance matching network is provided, with its signal path connected in series or parallel to the signal path of the radio frequency signal processing unit, and its control input terminal connected to the output terminal of the control processing module.

2. The system according to claim 1, characterized in that, The status detection module determines the current combined operating state by monitoring the logic level state of a multi-bit digital control bus that drives the RF switch and the RF attenuator; the status identification code is a unique digital code generated by directly combining the current logic level values ​​of all control bits on the multi-bit digital control bus into binary, or by performing a preset encoding algorithm.

3. The system according to claim 2, characterized in that, The state detection module includes a set of logic level buffers and a set of digital latches connected in parallel with the multi-bit digital control bus. The state detection module also includes an edge detection circuit, which is used to trigger the digital latches to latch the current stable complete logic state on the bus to generate a new state identification code when a logic level change of any control bit on the multi-bit digital control bus is detected. At the same time, it sends an interrupt request signal to the control processing module to start a new impedance matching adjustment process.

4. The system according to claim 1, characterized in that, The tunable impedance matching network contains variable reactance elements to receive hardware control commands generated by the control processing module. Based on these commands, the reactance parameters of the variable reactance elements are precisely adjusted to reconstruct the reactance characteristics of the tunable impedance matching network. The tunable impedance matching network is a passive network with a topology of π-type, T-type, or higher-order ladder network. The variable reactance elements include: a variable capacitor based on a microelectromechanical system (MEMS), a semiconductor varactor diode, a switched capacitor array controlled by a set of PIN diodes or RF MEMS switches, or a switched inductor array controlled by a set of PIN diodes or RF MEMS switches. The optimal tunable network control parameters are a set of digital codes used to set the specific reactance value of the variable reactance elements.

5. The system according to claim 1, characterized in that, It also includes a closed-loop feedback correction unit, which comprises: A directional coupler, the main path of which is located between the signal input terminal of the radio frequency signal processing unit and the signal output terminal of the tunable impedance matching network; A power detector, whose input is connected to the coupling port of the directional coupler, is used to measure the power of the reflected signal caused by impedance mismatch and output an analog voltage signal related to the power of the reflected signal. An analog-to-digital converter is used to convert the analog voltage signal output by the power detector into a digital quantity and transmit it to the control processing module so that the control processing module can perform closed-loop feedback fine-tuning of the optimal tunable network control parameters after executing the open-loop control based on the lookup table.

6. A matching method applied to the dynamic impedance matching system of the RF switch and attenuator as described in any one of claims 1-5, characterized in that, Includes the following steps: The digital control signals of the RF switch and RF attenuator in an RF signal processing unit are monitored in real time by a state detection module. When the digital control signals change, the current combinational logic state is captured and a unique state identification code representing the combinational logic state is generated. A control processing module receives the status identification code and uses it as an index to query and retrieve the optimal tunable network control parameters that uniquely correspond to the status identification code from an impedance matching calibration parameter lookup table pre-stored in a data storage module. The control processing module parses the retrieved optimal tunable network control parameters and converts them into a set of hardware control instructions according to the hardware interface specifications of the variable reactance elements contained in a tunable impedance matching network. The control processing module outputs the generated hardware control commands to the tunable impedance matching network, driving at least one variable reactance element inside it to change its parameter value, thereby reconstructing the reactance characteristics of the tunable impedance matching network, so that the port impedance of the radio frequency signal processing unit in the current new working state matches the system's preset characteristic impedance.

7. The method according to claim 6, characterized in that, The step of real-time monitoring of the digital control signals of the RF switch and RF attenuator specifically includes: Parallel monitoring of all signal lines on a multi-bit digital control bus that drives the RF switch and the RF attenuator; The specific steps for generating the status identification code include: directly combining the current logic level states of all signal lines on the multi-bit digital control bus into binary form to generate the status identification code; The method further includes sending an interrupt request to the control processing module when a logic level change is detected on any signal line of the multi-bit digital control bus, so as to trigger subsequent table lookup and matching network reconstruction steps.

8. The method according to claim 6, characterized in that, The impedance matching calibration parameter lookup table is generated through a pre-calibration process, which includes the following steps: The radio frequency signal processing unit is cascaded with the tunable impedance matching network and connected to the test port of a vector network analyzer. Through a control logic, each preset combination of the RF switch and RF attenuator is systematically traversed. In each combined operating state, the control parameters of the tunable impedance matching network are iteratively adjusted through an optimization algorithm, and the reflection coefficient measured by the vector network analyzer is monitored in real time. When the amplitude of the reflection coefficient in the target operating frequency band reaches a preset minimum value or falls below a preset threshold, the state identification code corresponding to the current combined operating state and the corresponding current optimal tunable network control parameters are recorded, and this set of mapping relationships is stored as a record in the impedance matching calibration parameter lookup table.

9. The method according to claim 6, characterized in that, After the control processing module drives the tunable impedance matching network to complete reconstruction, the following closed-loop fine-tuning steps are also included: The reflected signal caused by residual impedance mismatch is sampled through a directional coupler located at the input of the radio frequency signal processing unit. The power of the reflected signal is measured by a power detector, and the power is converted into a digital reflected power feedback value by an analog-to-digital converter. The control processing module receives the digitized reflected power feedback value and starts a real-time fine-tuning program. Using the optimal tunable network control parameters provided by the impedance matching calibration parameter lookup table as the initial values, the control parameters are iteratively optimized until the reflected power feedback value reaches a local minimum.

10. The method according to claim 9, characterized in that, The iterative optimization steps of the real-time fine-tuning program specifically include: The control processing module uses the parameters provided by the impedance matching calibration parameter lookup table as the initial control parameters and measures the corresponding reference reflected power feedback value at this time. The control processing module applies a preset small perturbation to the initial control parameters, generates a new set of control parameters, and drives the tunable impedance matching network to update to the new state. Measure and obtain a new reflected power feedback value under the new state, and compare it with the reference reflected power feedback value; Based on the decision logic of a hill-climbing algorithm or a least mean square algorithm, if the new reflected power feedback value is lower than the reference reflected power feedback value, then the perturbation is retained and the reference value is updated; otherwise, the perturbation is cancelled. Repeatedly execute the iterative loop of parameter perturbation, feedback evaluation, and decision-making until all preset perturbations fail to further reduce the reflected power feedback value.

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