Delay-locked loop and memory

Abstract

The invention provides a delay-locked loop and a memory. The delay phase-locked loop includes: a first adjustable delay line that delays a first clock signal based on a control code and outputs a first delayed clock signal; a second adjustable delay line which delays a second clock signal based on the control code and outputs a second delayed clock signal; a first clock distribution network transmitting the first delayed clock signal to an output port region of the memory; a second clock distribution network transmitting a second delayed clock signal to an output port region of the memory; the multi-phase clock generation circuit is electrically connected with the first clock distribution network and generates a first phase clock signal and a second phase clock signal; when the working frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line and the second clock distribution network are not enabled; and when the working frequency of the memory is smaller than the preset frequency, the multiphase clock generation circuit is not enabled. The power consumption of the delay phase-locked loop can be reduced, and the clock jitter can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a delay phase-locked loop and a memory. Background Technology

[0002] In storage systems, data is typically transmitted in a specific timing sequence. The proper functioning of a memory depends on accurate timing of its internal commands and clock. In Dynamic Random Access Memory (DRAM), a delay-locked loop (PLL) needs to synchronize and lock the four-phase clock signals (i.e., four clock signals with phases differing by 90 degrees) to generate the data strobe signal DQS, which is used for sampling the data signal DQ. However, as the operating frequency of the memory increases, the power consumption of the circuit increases, and the internal clock signal may experience significant jitter, leading to a deterioration in signal quality. Summary of the Invention

[0003] This disclosure provides a delay phase-locked loop and a memory, which at least helps to reduce circuit power consumption, reduce clock signal jitter, and improve clock signal quality.

[0004] In a first aspect, embodiments of this disclosure provide a delay-locked loop (PLL) applied to a memory, comprising:

[0005] The first adjustable delay line is configured to receive a first clock signal and a control code, perform delay processing on the first clock signal based on the control code, and output a first delayed clock signal.

[0006] The second adjustable delay line is configured to receive a second clock signal and the control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the second clock signal based on the control code, and output a second delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line is disabled.

[0007] A first clock distribution network, electrically connected to the first adjustable delay line, is configured to receive the first delayed clock signal and transmit it to the output port area of ​​the memory to output a first target clock signal.

[0008] The second clock distribution network, electrically connected to the second adjustable delay line, is configured to receive the second delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than a preset frequency, and output a second target clock signal, wherein the phase difference between the second target clock signal and the first target clock signal is a preset value; when the operating frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network is disabled.

[0009] A multi-phase clock generation circuit, electrically connected to the first clock distribution network, is configured to receive the first target clock signal when the operating frequency of the memory is greater than or equal to a preset frequency, and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal, wherein the first phase clock signal and the first target clock signal are in phase, and the phase difference between the second phase clock signal and the first target clock signal is the preset value; when the operating frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit is disabled.

[0010] In some embodiments, the delay phase-locked loop further includes,

[0011] The copy adjustable delay line is configured to, when the operating frequency of the memory is less than a preset frequency, simulate the delay of the first adjustable delay line, receive the copy clock signal, perform delay processing on the copy clock signal based on the control code, and output a copy delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the copy adjustable delay line is disabled.

[0012] The replication clock distribution network, electrically connected to the replication adjustable delay line, is configured to receive the replication delay clock signal, simulate the delay of the first clock distribution network, and output the replication target clock signal when the operating frequency of the memory is less than a preset frequency; and to disable the replication clock distribution network when the operating frequency of the memory is greater than or equal to the preset frequency.

[0013] In some embodiments, the delay phase-locked loop further includes,

[0014] The selection circuit, electrically connected to the multi-phase clock generation circuit and the replication clock distribution network, is configured to receive the replication target clock signal and the first phase clock signal; when the operating frequency of the memory is less than a preset frequency, output the replication target clock signal; and when the operating frequency of the memory is greater than or equal to the preset frequency, output the first phase clock signal.

[0015] In some embodiments, the delay phase-locked loop further includes,

[0016] A delay simulation circuit, electrically connected to the output of the selection circuit, is used to simulate the delay of the clock input path and clock output path in the memory and output a feedback clock signal; the clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driver circuit;

[0017] A phase detector, electrically connected to the delay analog circuit, is configured to receive the feedback clock signal and the reference clock signal, and output an indication signal based on the phase order of the two.

[0018] A control code generation circuit, electrically connected to the phase detector, is configured to adjust and output the control code based on the indication signal.

[0019] In some embodiments, when the operating frequency of the memory is less than a preset frequency, the delay-locked loop has completed phase locking, and the memory does not perform a read operation, the first adjustable delay line, the second adjustable delay line, the first clock distribution network, and the second clock distribution network are not enabled, and only the copy adjustable delay line and the copy clock distribution network are enabled.

[0020] In some embodiments, the multiphase clock generation circuit is adjacent to the output port region of the memory.

[0021] In some embodiments, the first adjustable delay line, the second adjustable delay line, and the replicated adjustable delay line have the same circuit structure.

[0022] In some embodiments, the first adjustable delay line, the second adjustable delay line, and the copy adjustable delay line each include a coarse-tuning delay line, a fine-tuning delay line, and a driver.

[0023] In some embodiments, the first adjustable delay line, the second adjustable delay line, and the copy adjustable delay line each further include a duty cycle correction circuit and a quadrant error correction circuit; when the operating frequency of the memory is greater than or equal to a preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are disabled; when the operating frequency of the memory is less than the preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are enabled.

[0024] In some embodiments, the first clock distribution network, the second clock distribution network, and the replicated clock distribution network have the same circuit structure.

[0025] In some embodiments, the first adjustable delay line and the second adjustable delay line are located in a first voltage domain, and the first clock distribution network and the second clock distribution network are located in a second voltage domain; the power supply voltage of the first voltage domain and the power supply voltage of the second voltage domain are the same.

[0026] In some embodiments, the delay phase-locked loop further includes:

[0027] The third adjustable delay line is configured to receive a third clock signal and the control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the third clock signal based on the control code, and output a third delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line is disabled.

[0028] The fourth adjustable delay line is configured to receive a fourth clock signal and the control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the fourth clock signal based on the control code, and output a fourth delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth adjustable delay line is disabled.

[0029] The third clock distribution network, electrically connected to the third adjustable delay line, is configured to receive the third delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than a preset frequency, and output the third target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third clock distribution network is disabled.

[0030] The fourth clock distribution network, electrically connected to the fourth adjustable delay line, is configured to receive the fourth delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than a preset frequency, and output the fourth target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth clock distribution network is disabled.

[0031] The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees apart in phase.

[0032] In some embodiments, the clock frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are half the clock frequency of the initial clock signal received by the memory, wherein the clock frequency of the initial clock signal is equal to the operating frequency of the memory.

[0033] In some embodiments, the delay phase-locked loop further includes:

[0034] The mode control circuit is configured to, when the operating frequency of the memory is less than a preset frequency, send the first clock signal to the first adjustable delay line, send the second clock signal to the second adjustable delay line, send the third clock signal to the third adjustable delay line, and send the fourth clock signal to the fourth adjustable delay line; when the operating frequency of the memory is greater than or equal to the preset frequency, only send the first clock signal to the first adjustable delay line; and do not send the second clock signal, the third clock signal, and the fourth clock signal.

[0035] In some embodiments, when the operating frequency of the memory is greater than or equal to a preset frequency, the multi-phase clock generation circuit also generates a third-phase clock signal and a fourth-phase clock signal; the phases of the first-phase clock signal, the second-phase clock signal, the third-phase clock signal, and the fourth-phase clock signal are sequentially 90 degrees apart.

[0036] In some embodiments, the output port region of the memory includes a high-order output port region and a low-order output port region; the multi-phase clock generation circuit includes a high-order multi-phase clock generation circuit and a low-order multi-phase clock generation circuit; the high-order multi-phase clock generation circuit is adjacent to the high-order output port region and is configured to provide at least the first phase clock signal and the second phase clock signal to the high-order output port; the low-order multi-phase clock generation circuit is adjacent to the low-order output port region and is configured to provide at least the first phase clock signal and the second phase clock signal to the low-order output port; when one of the high-order output port and the low-order output port is not enabled, the corresponding multi-phase clock generation circuit is disabled.

[0037] In a second aspect, embodiments of this disclosure provide a memory that includes at least the delay phase-locked loop described in the first aspect.

[0038] The technical solutions provided in this disclosure have at least the following advantages:

[0039] When the memory is operating at high speed, i.e., when the operating frequency is greater than or equal to the preset frequency, the second adjustable delay line and the second clock distribution network are turned off, and only the first adjustable delay line and the first clock distribution network are enabled. At least the first phase clock signal and the second phase clock signal are generated through the multi-phase clock generation circuit. This can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter and improving the quality of the clock signal. Attached Figure Description

[0040] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of a delay-locked loop (DLL).

[0042] Figure 2 This is a schematic diagram of a delay phase-locked loop provided in an embodiment of the present disclosure;

[0043] Figure 3 This is a schematic diagram of another delayed phase-locked loop provided in an embodiment of the present disclosure;

[0044] Figure 4 This is a schematic diagram of another delayed phase-locked loop provided in an embodiment of the present disclosure;

[0045] Figure 5 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0046] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] Dynamic Random Access Memory (DRAM)

[0048] Synchronous Dynamic Random Access Memory (SDRAM)

[0049] Double Data Rate SDRAM (DDR)

[0050] Low-power DDR (LPDDR)

[0051] The nth generation DDR standard (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6.

[0052] The nth generation LPDDR standard (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0053] Delay Locked Loop (DLL)

[0054] In storage systems, data is typically transmitted in a specific timing sequence. The proper functioning of a memory depends on the accurate timing of its internal commands and clock. For example, when a memory receives a read command, it needs to output the data from the data port after the expected delay time. When a memory receives a write command, it also needs to receive the data from the data port after the expected delay time.

[0055] The aforementioned expected latency, also known as "latency," is a crucial parameter defined in the DRAM design specifications. This parameter is configured by the DRAM controller and stored in the DRAM's registers. It specifies that after receiving a read or write command from the DRAM, data (DQ) and data strobe signal (DQS) transmission or reception must occur after a fixed time interval that is an integer multiple of the clock cycle. For example, setting the read latency (RL) to 28 means that after the DRAM receives a read command, data (DQ) and data strobe signal (DQS) transmission must occur after 28 clock cycles. RL can be configured in many ways by the DRAM controller. In this disclosure, one clock cycle, denoted as tck, is the clock cycle of the initial clock signal CK_t received by the DRAM. The purpose of setting the latency is to meet the timing constraints during master-slave communication and to give the DRAM time to prepare data. During DRAM-host communication, latency errors can lead to communication failures or data loss.

[0056] To establish timing constraints, DRAM design specifications require that the latency must be an integer multiple of the clock cycle (N*tck, where N is a positive integer). However, in actual circuits, due to variations in process technology, voltage, and temperature, the actual delay is full of uncertainties and is also affected by external noise. Designers must convert the actual circuit delay into an integer multiple of the clock cycle, and this operation is achieved through a delay-locked loop (PLL).

[0057] refer to Figure 1This diagram illustrates the structure of a delay-locked loop (DLL). The clock input buffer (CLK IB) receives the initial clock signal CK_t, which is then divided by a divider to generate four-phase clock signals CLKI, CLKQ, CLKIB, and CLKQB. Currently, memory is increasingly moving towards higher speeds. Taking DDR5 as an example, due to its increased speed and process limitations, the high-speed clock signal at the interface needs to be internally converted to a lower-speed clock signal. Therefore, the phases of CLKI, CLKQ, CLKIB, and CLKQB differ by 90 degrees, and their frequencies are half the frequency of the initial clock signal CK_t. Subsequently, the four-phase clock signals CLKI, CLKQ, CLKIB, and CLKQB are fed into four adjustable delay lines. Each adjustable delay line includes a coarse delay line (CDL), a fine delay line (FDL), a duty cycle corrector (DCC), a quadrant error corrector (QEC), and a driver (DRV). These four-phase clock signals are then transmitted to the output port area via four read clock distribution networks (RD CLK CDN) for sampling the data signal DQ. The output port area is shown in the diagram as LDQ and UDQ, where LDQ represents the output port area for low-order data and UDQ represents the output port area for high-order data. This delay-locked loop also includes a replica adjustable delay line to simulate the delay of the aforementioned adjustable delay lines. The replica adjustable delay line receives CLKI and also includes the same CDL, FDL, DCC+QEC, and DRV modules. The clock signal output from the replicated adjustable delay line passes through a replicated read clock distribution network (RD CLK CDN Replica) to simulate the delay of the read clock distribution network. The clock signal output from the replicated read clock distribution network then passes through an input / output replica (I / O Replica) to generate a feedback clock signal FBCLK. A phase detector (PD) compares the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK, and then the delay control module (CDL / FDL Control) controls the delays of CDL and FDL so that the phase difference between the final reference clock signal REFCLK and the feedback clock signal FBCLK is approximately zero, thus locking the DLL.Ideally, when the DLL is locked, the rising edges of the reference clock signal REFCLK and the feedback clock signal FBCLK are aligned, and their phase difference is equal to 0. However, in practice, as long as the phase difference between REFCLK and FBCLK is approximately 0 within the allowable error range, the DLL can be considered to be in a locked state. CLKI can be used as the reference clock signal REFCLK.

[0058] As described above, the initial clock signal CK_t enters the delay-locked loop (DLL) via four paths. The four adjustable delay lines, four read clock distribution networks, and the copy adjustable delay line and copy read clock distribution network need to operate simultaneously for phase synchronization and locking. However, this architecture has a long delay path, leading to clock signal jitter when the memory operates at high speed. Furthermore, the simultaneous operation of multiple adjustable delay lines and read clock distribution networks results in very high power consumption and introduces additional power supply noise, further exacerbating clock signal jitter. When the memory operates at high speed, the delays between the four paths may mismatch, causing a phase difference deviation (Skew) between the four-phase clock signals, which is detrimental to the subsequent generation of the data strobe signal DQS and the sampling processing of the data signal DQ.

[0059] Based on this, the present disclosure provides a delay-locked loop (PLL) applied to a memory, comprising: a first adjustable delay line configured to receive a first clock signal and a control code, perform delay processing on the first clock signal based on the control code, and output a first delayed clock signal; a second adjustable delay line configured to receive a second clock signal and a control code when the memory's operating frequency is less than a preset frequency, perform delay processing on the second clock signal based on the control code, and output a second delayed clock signal; and to disable the second adjustable delay line when the memory's operating frequency is greater than or equal to the preset frequency; a first clock distribution network electrically connected to the first adjustable delay line, configured to receive the first delayed clock signal and transmit it to the memory's output port area to output a first target clock signal; and a second clock distribution network electrically connected to the second adjustable delay line, configured to receive the first delayed clock signal and transmit it to the memory's output port area to output a first target clock signal; and a second clock distribution network electrically connected to the second adjustable delay line. The configuration is as follows: when the operating frequency of the memory is less than a preset frequency, a second delayed clock signal is received and transmitted to the output port area of ​​the memory to output a second target clock signal. The phase difference between the second target clock signal and the first target clock signal is a preset value. When the operating frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network is disabled. A multiphase clock generation circuit, electrically connected to the first clock distribution network, is configured to: when the operating frequency of the memory is greater than or equal to the preset frequency, receive the first target clock signal and, based on the first target clock signal, generate at least a first phase clock signal and a second phase clock signal. The first phase clock signal and the first target clock signal are in phase, and the phase difference between the second phase clock signal and the first target clock signal is a preset value. When the operating frequency of the memory is less than the preset frequency, the multiphase clock generation circuit is disabled. In this way, when the memory is operating at high speed, that is, when the operating frequency is greater than or equal to the preset frequency, the second adjustable delay line and the second clock distribution network are turned off, and only the first adjustable delay line and the first clock distribution network are enabled. At least the first phase clock signal and the second phase clock signal are generated through the multi-phase clock generation circuit, which can reduce circuit power consumption, reduce power supply noise, thereby reducing clock jitter and improving the quality of clock signal.

[0060] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0061] In one embodiment of this disclosure, see Figure 2 This illustrates a schematic diagram of the structure of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 2 As shown, the delay phase-locked loop 10 includes:

[0062] The first adjustable delay line 11 is configured to receive a first clock signal and a control code, perform delay processing on the first clock signal based on the control code, and output a first delayed clock signal.

[0063] The second adjustable delay line 13 is configured to receive a second clock signal and a control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the second clock signal based on the control code, and output a second delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line 13 is disabled.

[0064] The first clock distribution network 12 is electrically connected to the first adjustable delay line 11 and is configured to receive the first delayed clock signal and transmit it to the output port area 31 of the memory to output the first target clock signal.

[0065] The second clock distribution network 14, electrically connected to the second adjustable delay line 13, is configured to receive the second delayed clock signal and transmit it to the output port area 31 of the memory when the operating frequency of the memory is less than the preset frequency, and output the second target clock signal. The phase difference between the second target clock signal and the first target clock signal is a preset value. When the operating frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network 14 is disabled.

[0066] The multiphase clock generation circuit 15 is electrically connected to the first clock distribution network 12 and is configured to receive a first target clock signal when the operating frequency of the memory is greater than or equal to a preset frequency, and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal. The first phase clock signal and the first target clock signal are in phase, and the phase difference between the second phase clock signal and the first target clock signal is a preset value. When the operating frequency of the memory is less than the preset frequency, the multiphase clock generation circuit 15 is disabled.

[0067] It should be noted that the delay-locked loop 10 of this embodiment can be applied to, but is not limited to, memory, such as DRAM, SDRAM, etc. Furthermore, in other analog / digital circuits, such as controllers and processors, the delay-locked loop 10 provided in this embodiment can generate a set of clock signals with different phases.

[0068] When the operating frequency of the memory is lower than the preset frequency, the first adjustable delay line 11, the second adjustable delay line 13, the first clock distribution network 12, and the second clock distribution network 14 all operate. Based on the control code, the first and second clock signals are delayed. Subsequently, the first and second target clock signals are transmitted to the memory's output port area 31 through the first clock distribution network 12 and the second clock distribution network 14. This is used to generate the data strobe signal DQS and to sample the data signal DQ. The output port area 31 refers to the circuit area near the data pin (DQ Pad) in the memory, which is used for output data-related circuitry, including the data DQ sampling circuit and the output drive circuit.

[0069] When the memory's operating frequency is greater than or equal to a preset frequency, the second adjustable delay line 13 and the second clock distribution network 14 are disabled, while only the first adjustable delay line 11 and the first clock distribution network 12 are enabled. The multiphase clock generation circuit 15 generates at least a first-phase clock signal and a second-phase clock signal based on the first target clock signal. These signals are then used to generate the data strobe signal DQS and to sample and process the data signal DQ. Because the adjustable delay line and clock distribution network consume a significant amount of power when the memory operates at high speed, reducing the clock transmission path lowers circuit power consumption, reduces power supply noise, and thus reduces clock jitter, improving the quality of the clock signal.

[0070] Understandably, the multi-phase clock generation circuit 15, when the memory's operating frequency is greater than or equal to a preset frequency, generates at least a first-phase clock signal and a second-phase clock signal based on a first target clock signal. The first-phase clock signal and the first target clock signal are in phase, and the phase difference between the second-phase clock signal and the first target clock signal is a preset value. In some examples, this preset value can be 90 degrees, 180 degrees, or 270 degrees. The multi-phase clock generation circuit can be a four-phase clock generation circuit, also generating a third-phase clock signal and a fourth-phase clock signal, wherein the phases of the first-phase clock signal, the second-phase clock signal, the third-phase clock signal, and the fourth-phase clock signal differ by 90 degrees sequentially. When the memory's operating frequency is less than the preset frequency, the multi-phase clock generation circuit 15 is disabled, further saving circuit power consumption.

[0071] In simple terms, when the memory operates at low speed, multiple adjustable delay lines and the clock distribution network are enabled to generate multiple phase-locked clock signals, which are used to generate the data strobe signal DQS and the sampling processing of the data signal DQ. When the memory operates at high speed, only one adjustable delay line and the clock distribution network are enabled. A multi-phase clock generation circuit is used to generate multiple phase-locked clock signals in the output port area. This reduces circuit power consumption, reduces power supply noise, thereby reducing clock jitter and improving the quality of the clock signal.

[0072] It should be understood that the phase difference limits in this disclosure are all subject to a certain degree of error. That is, the phases of the first-phase clock signal, the second-phase clock signal, the third-phase clock signal, and the fourth-phase clock signal are successively 90 degrees apart within the allowable error range. Subsequent limitations regarding phase values, signal edge alignment, or identical signal waveforms all refer to the allowable error range.

[0073] In some embodiments, the multiphase clock generation circuit 15 is adjacent to the output port region 31 of the memory. When the operating frequency of the memory is greater than or equal to a preset frequency, only the first adjustable delay line 11 and the first clock distribution network 12 are enabled, and the first target clock signal is transmitted to the output port region 31 of the memory. Since the multiphase clock generation circuit 15 is adjacent to the output port region 31 of the memory, it can receive the first target clock signal at the output port region 31. The generated first phase clock signal and second phase clock signal can also be directly transmitted to the output port region 31, avoiding phase deviation (Skew) caused by long-distance signal transmission.

[0074] It is understandable that the operating frequency of the memory is equal to the clock frequency of the initial clock signal CK_t received by the memory. The aforementioned preset frequency can be set to the required value according to the actual scenario. For example, in DDR5, the preset frequency can be set to 5.6Gbps. In some embodiments, the multiphase clock generation circuit 15 can be an analog phase generator (APG). The APG can generate a first phase clock signal, a second phase clock signal, a third phase clock signal, and a fourth phase clock signal, which are sequentially 90 degrees out of phase with each other. However, the APG can only operate in a specific frequency band and cannot cover a sufficiently wide operating frequency band. For example, when the APG is designed to operate at a higher frequency, it may not be able to generate the correct four-phase clock signal at a lower frequency. Therefore, the setting of the preset frequency also needs to take into account the operating frequency band of the multiphase clock generation circuit 15 to ensure that the multiphase clock generation circuit 15 can work normally when the operating frequency of the memory is greater than or equal to the preset frequency.

[0075] In some embodiments, such as Figure 3 As shown, the delay phase-locked loop 10 also includes:

[0076] The copy adjustable delay line 16 is configured to, when the operating frequency of the memory is less than the preset frequency, simulate the delay of the first adjustable delay line 11, receive the copy clock signal, perform delay processing on the copy clock signal based on the control code, and output the copy delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the copy adjustable delay line 16 is disabled.

[0077] The copy clock distribution network 17, electrically connected to the copy adjustable delay line 16, is configured to receive the copy delay clock signal, simulate the delay of the first clock distribution network 12, and output the copy target clock signal when the operating frequency of the memory is less than the preset frequency; when the operating frequency of the memory is greater than or equal to the preset frequency, the copy clock distribution network 17 is disabled.

[0078] When the memory's operating frequency is lower than a preset frequency, the copy adjustable delay line 16 receives the copy clock signal, simulating the delay of the first adjustable delay line 11. This copy clock signal can be the first clock signal or a signal with the same phase waveform as the first clock signal. Simulating the delay of the first adjustable delay line 11 means making the delay of the copy adjustable delay line 16 as similar as possible to the first adjustable delay line 11, thereby reducing phase error during DLL locking. It is understood that the delay of the second adjustable delay line 13 is the same as the delay of the first adjustable delay line 11, so the delay of the copy adjustable delay line 16 is also the same as the delay of the second adjustable delay line 13. All three can achieve the same delay using the same circuit structure and the same control code. The copy clock distribution network 17 receives the copy delay clock signal, simulating the delay of the first clock distribution network 12, that is, making the delay of the copy clock distribution network 17 as similar as possible to the delay of the first clock distribution network 12, thereby reducing phase error during DLL locking. It is understandable that the delay of the second clock distribution network 14 is the same as the delay of the first clock distribution network 12, therefore the delay of the replica clock distribution network 17 is also the same as the delay of the second clock distribution network 14. It should be noted that the "same delay" mentioned here refers to the same delay within the allowable error range.

[0079] When the operating frequency of the memory is greater than or equal to the preset frequency, the copy adjustable delay line 16 and the copy clock distribution network 17 are disabled, which can further save the circuit power consumption of the memory when it is operating at high speed.

[0080] In some embodiments, when the operating frequency of the memory is lower than a preset frequency, the delay-locked loop 10 has achieved phase locking, and the memory is not performing a read operation, the first adjustable delay line 11, the second adjustable delay line 13, the first clock distribution network 12, and the second clock distribution network 14 are not enabled; only the copy adjustable delay line 16 and the copy clock distribution network 17 are enabled. At this time, because no read operation is performed, there is no need to transmit the clock signal to the output port area 31 to generate the data strobe signal DQS. The first adjustable delay line 11, the second adjustable delay line 13, the first clock distribution network 12, and the second clock distribution network 14 can all be turned off to save power. Because the delay-locked loop 10 has achieved phase locking, only the copy adjustable delay line 16 and the copy clock distribution network 17 need to be enabled to maintain the locked state of the delay-locked loop 10. In some cases, when the delay-locked loop 10 is in a locked state, the copy adjustable delay line 16 and the copy clock distribution network 17 can also operate at a lower frequency, that is, receive the lower-frequency copied clock signal, which can further save the circuit power consumption of the delay-locked loop.

[0081] In some embodiments, such as Figure 3 As shown, the delay phase-locked loop 10 also includes:

[0082] Selection circuit 18, electrically connected to multiphase clock generation circuit 15 and replication clock distribution network 17, is configured to receive replication target clock signal and first phase clock signal, output replication target clock signal when the operating frequency of the memory is less than the preset frequency, and output first phase clock signal when the operating frequency of the memory is greater than or equal to the preset frequency.

[0083] In some embodiments, such as Figure 3 As shown, the delay phase-locked loop 10 also includes:

[0084] The delay simulation circuit 19 is electrically connected to the output terminal of the selection circuit 18. It is used to simulate the delay of the clock input path and the clock output path in the memory and output a feedback clock signal. The clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driver circuit.

[0085] Phase detector 20, electrically connected to delay analog circuit 19, is configured to receive a feedback clock signal and a reference clock signal, and output an indication signal based on the phase order of the two.

[0086] The control code generation circuit 21, electrically connected to the phase detector 20, is configured to adjust and output a control code based on an indication signal.

[0087] When the memory's operating frequency is lower than a preset frequency, the selection circuit 18 selects to send the copy target clock signal output from the copy clock distribution network 17 into the DLL feedback loop, thereby generating a feedback clock signal. When the memory's operating frequency is greater than or equal to the preset frequency, the selection circuit 18 selects to send the first phase clock signal into the DLL feedback loop, thereby generating a feedback clock signal. In this way, when the memory is operating at high speed, the copy adjustable delay line 16 and the copy clock distribution network 17 can be turned off to save power, thereby reducing power supply noise and reducing clock jitter.

[0088] It should be noted that the delay simulation circuit 19 simulates the delay of the clock input path and clock output path within the memory, that is, it makes the delay of the delay simulation circuit 19 as similar as possible to the delay of the clock input path and clock output path, in order to reduce the phase error during DLL locking. The clock input path includes a clock receiver CLKIB that receives the initial clock signal CK_t and a frequency divider Divider, and the clock output path includes an output driver circuit that outputs the data signal DQ and the data strobe signal DQS.

[0089] Phase detector 20 receives a feedback clock signal and a reference clock signal. The reference clock signal can be either the first clock signal or a signal with the same phase waveform as the first clock signal. Phase detector 20 compares the phases of the reference clock signal and the feedback clock signal, and then uses control code generation circuit 21 to control the delay of the first adjustable delay line, the second adjustable delay line, and / or the replicated adjustable delay line. Under the action of the closed-loop feedback mechanism, the phase difference between the final reference clock signal and the feedback clock signal is approximately 0, and the DLL reaches a locked state. Ideally, when the DLL is locked, the rising edges of the reference clock signal and the feedback clock signal are aligned, and their phase difference is equal to 0. However, in practice, as long as the phase difference between the reference clock signal and the feedback clock signal is approximately 0 within the allowable error range, the DLL can be considered to have reached a locked state.

[0090] Understandably, when the memory's operating frequency is less than the preset frequency, the DLL feedback loop consists of the adjustable delay line 16, the clock distribution network 17, the selection circuit 18, the delay simulation circuit 19, the phase detector 20, and the control code generation circuit 21. When the memory's operating frequency is greater than or equal to the preset frequency, the DLL feedback loop consists of the first adjustable delay line 11, the first clock distribution network 12, the multi-phase clock generation circuit 15, the selection circuit 18, the delay simulation circuit 19, the phase detector 20, and the control code generation circuit 21. Thus, when the memory is operating at high speed, the adjustable delay line 16 and the clock distribution network 17 can be turned off, greatly saving power consumption, thereby reducing power supply noise and clock jitter.

[0091] In some embodiments, the first adjustable delay line 11, the second adjustable delay line 13, and the replicated adjustable delay line 16 have the same circuit structure. In some embodiments, the first clock distribution network 12, the second clock distribution network 14, and the replicated clock distribution network 17 have the same circuit structure. This ensures that the delays of different paths are the same, making the phase difference between the first target clock signal and the second target clock signal a preset value, reducing the deviation (skew) of this phase difference, and reducing the phase error during DLL locking.

[0092] In some embodiments, such as Figure 4 As shown, the first adjustable delay line 11, the second adjustable delay line 13, and the copy adjustable delay line 16 all include a coarse adjustment delay line CDL, a fine adjustment delay line FDL, and a driver DRV.

[0093] The coarse-adjustment delay line (CDL) and the fine-adjustment delay line (FDL) receive control codes output from the control code generation circuit and adjust the delay time in response to the control codes. The adjustment step size of the coarse-adjustment delay line (CDL) is larger than that of the fine-adjustment delay line (FDL). The first adjustable delay line 11, the second adjustable delay line 13, and the duplicate adjustable delay line 16 mainly rely on the coarse-adjustment delay line (CDL) and the fine-adjustment delay line (FDL) to adjust their own delay times. The driver (DRV) is generally located at the end of the first adjustable delay line 11, the second adjustable delay line 13, and the duplicate adjustable delay line 16, and is used to enhance the driving capability of the output signal, which can improve the quality of the clock signal transmitted to subsequent circuits. The driver (DRV) can be constructed using an even number of inverters, and the size of the inverters can be set according to the length of the subsequent transmission path and the load size.

[0094] In some embodiments, such as Figure 4 As shown, the first adjustable delay line 11, the second adjustable delay line 13, and the copy adjustable delay line 16 all include a duty cycle correction circuit DCC and a quadrant error correction circuit QEC. When the operating frequency of the memory is greater than or equal to the preset frequency, the duty cycle correction circuit DCC and the quadrant error correction circuit QEC of the first adjustable delay line 11 are disabled; when the operating frequency of the memory is less than the preset frequency, the duty cycle correction circuit DCC and the quadrant error correction circuit QEC of the first adjustable delay line 11 are enabled.

[0095] Because clock signals undergo long-distance transmission, rising and falling edge offsets may occur, causing duty cycle distortion and phase shift. The duty cycle correction circuit (DCC) adjusts the clock signal's duty cycle to bring it as close to 50% as possible, which is beneficial for accurate sampling of the subsequent data signal (DQ). The quadrant error correction circuit (QEC) adjusts the phase difference between clock signals on different paths to bring it as close as possible to a preset value, reducing the phase difference deviation (Skew) between clock signals on different paths, which also benefits accurate sampling of the subsequent data signal (DQ).

[0096] When the memory's operating frequency is greater than or equal to a preset frequency, because the multi-phase clock generation circuit 15 is enabled and is adjacent to the memory's output port area, the first-phase clock signal and the second-phase clock signal generated by it can be directly transmitted to the output port area 31. This avoids duty cycle distortion and phase shift caused by long-distance signal transmission, so the duty cycle correction circuit DCC and the quadrant error correction circuit QEC can be disabled. This shortens the path of the first adjustable delay line 11, reduces the number of logic gates operating on the first adjustable delay line 11, and helps reduce clock signal jitter. Simultaneously, it also reduces circuit power consumption, lowers power supply noise, and further reduces clock signal jitter.

[0097] In some embodiments, the first adjustable delay line 11 and the second adjustable delay line 13 are located in a first voltage domain, and the first clock distribution network 12 and the second clock distribution network 14 are located in a second voltage domain; the power supply voltage of the first voltage domain and the power supply voltage of the second voltage domain are the same. For example, the first voltage domain can be a voltage domain VDLL specifically provided inside the memory for the delay phase-locked loop (DLL), and the second voltage domain can be a voltage domain VDD shared with other circuits, such as read / write paths, output drive circuits, etc. The power supply in the first voltage domain is cleaner and has less noise than the power supply in the second voltage domain, resulting in more accurate delay adjustment and reducing clock signal jitter.

[0098] In some embodiments, such as Figure 4 As shown, the delay phase-locked loop 10 also includes:

[0099] The third adjustable delay line 23 is configured to receive the third clock signal CLKIB and the control code when the operating frequency of the memory is less than the preset frequency, perform delay processing on the third clock signal CLKIB based on the control code, and output the third delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line 23 is disabled.

[0100] The fourth adjustable delay line 25 is configured to receive the fourth clock signal CLKQB and the control code when the operating frequency of the memory is less than the preset frequency, perform delay processing on the fourth clock signal CLKQB based on the control code, and output the fourth delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth adjustable delay line 25 is disabled.

[0101] The third clock distribution network 24, electrically connected to the third adjustable delay line 23, is configured to receive the third delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than the preset frequency, and output the third target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third clock distribution network 24 is disabled.

[0102] The fourth clock distribution network 26, electrically connected to the fourth adjustable delay line 25, is configured to receive the fourth delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than the preset frequency, and output the fourth target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth clock distribution network 26 is disabled.

[0103] Among them, the phases of the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB and the fourth clock signal CLKQB are 90 degrees apart.

[0104] refer to Figure 4The first adjustable delay line 11, the second adjustable delay line 13, the third adjustable delay line 23, the fourth adjustable delay line 25, and the copy adjustable delay line 16 all have the same circuit structure, including a coarse adjustment delay line CDL, a fine adjustment delay line FDL, a duty cycle correction circuit DCC, a quadrant error correction circuit QEC, and a driver DRV. The second adjustable delay line 13, the third adjustable delay line 23, the fourth adjustable delay line 25, and the copy adjustable delay line 16 are indicated by dashed boxes to show that they are disabled when the memory's operating frequency is greater than or equal to a preset frequency, and are only enabled when the memory's operating frequency is less than the preset frequency. The first adjustable delay line 11 is indicated by a solid box to show that it is enabled at any operating frequency. The duty cycle correction circuit DCC and the quadrant error correction circuit QEC in the first adjustable delay line 11 are indicated by dashed boxes to show that they are disabled when the memory's operating frequency is greater than or equal to a preset frequency. This reduces circuit power consumption during high-frequency memory operation, decreases power supply noise, and reduces clock signal jitter.

[0105] Continue to refer to Figure 4 The first clock distribution network 12, the second clock distribution network 14, the third clock distribution network 24, the fourth clock distribution network 26, and the replicated clock distribution network 17 all have the same circuit structure to reduce delay deviations between different paths. The second clock distribution network 14, the third clock distribution network 24, the fourth clock distribution network 26, and the replicated clock distribution network 17 are indicated by dashed boxes to show that they are disabled when the memory's operating frequency is greater than or equal to a preset frequency, and are only enabled when the memory's operating frequency is less than the preset frequency. The first clock distribution network 12 is indicated by a solid box to show that it is enabled at any operating frequency. This reduces circuit power consumption during high-frequency memory operation, reduces power supply noise, and lowers clock signal jitter.

[0106] In some embodiments, the clock frequencies of the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB are half the clock frequency of the initial clock signal CK_t received by the memory, wherein the clock frequency of the initial clock signal CK_t is equal to the operating frequency of the memory.

[0107] like Figure 4As shown, the clock receiver (Clock Input Buffer, CLK IB) 27 receives the initial clock signal CK_t, and then the frequency divider (Divider) 28 generates the first clock signal CLKI, the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB, which are respectively sent to four adjustable delay lines for transmission.

[0108] In some embodiments, reference Figure 4 When the memory's operating frequency is greater than or equal to a preset frequency, the multi-phase clock generation circuit can be a four-phase clock generation circuit (4-Phase Generator, 4-PhaseGen), generating a third-phase clock signal and a fourth-phase clock signal. The phases of the first-phase clock signal, second-phase clock signal, third-phase clock signal, and fourth-phase clock signal differ by 90 degrees sequentially. Thus, when the memory operates at high speed, it is only necessary to enable the first adjustable delay line 11 and the first clock distribution network 12 to transmit the first clock signal CLKI to the four-phase clock generation circuit, and then generate the required four-phase clock signals for sampling the data signal DQ. This significantly saves circuit power consumption, reduces power supply noise, and consequently reduces clock jitter.

[0109] In some embodiments, such as Figure 4 As shown, the delay phase-locked loop 10 also includes:

[0110] The mode control circuit 29 is configured to, when the memory's operating frequency is less than a preset frequency, send a first clock signal CLKI to the first adjustable delay line 11, a second clock signal CLKQ to the second adjustable delay line 13, a third clock signal CLKIB to the third adjustable delay line 23, and a fourth clock signal CLKQB to the fourth adjustable delay line 25; when the memory's operating frequency is greater than or equal to the preset frequency, only the first clock signal CLKI is sent to the first adjustable delay line 11; the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB are not sent. This is because when the memory's operating frequency is greater than or equal to the preset frequency, the second adjustable delay line 13, the third adjustable delay line 23, and the fourth adjustable delay line 25 are disabled. If the second clock signal CLKQ, the third clock signal CLKIB, and the fourth clock signal CLKQB are still received at this time, the circuit devices at the beginning, such as the inverter, will still generate current. The mode control circuit 29 ensures that when the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line 13, the third adjustable delay line 23, and the fourth adjustable delay line 25 do not receive any clock signals, which can further reduce the power consumption of the circuit.

[0111] In some embodiments, such as Figure 4 As shown, the memory output port region 31 includes a high-order output port region 312 and a low-order output port region 311; the multi-phase clock generation circuit 15 includes a high-order multi-phase clock generation circuit 152 and a low-order multi-phase clock generation circuit 151; the high-order multi-phase clock generation circuit 152 is adjacent to the high-order output port region 312 and is configured to provide at least a first-phase clock signal and a second-phase clock signal for the high-order output port UDQ; the low-order multi-phase clock generation circuit 151 is adjacent to the low-order output port region 311 and is configured to provide at least a first-phase clock signal and a second-phase clock signal for the low-order output port LDQ; when one of the high-order output port UDQ and the low-order output port LDQ is not enabled, the corresponding multi-phase clock generation circuit is disabled.

[0112] Understandably, memory, such as DDR5, has various configurations, such as x4, x8, and x16. Different configurations require different enabled output ports. By setting up separate multi-phase clock generation circuits for the high-order and low-order output ports, power can be saved by enabling them individually according to actual usage. Furthermore, the output ports can be grouped further, with each group having its own multi-phase clock generation circuit, achieving more precise control.

[0113] Continue to refer to Figure 4 The delay-locked loop 10 also includes a selection circuit (Mux) 18, an input / output replica (I / O replica) circuit 19, a phase detector (PD) 20, and a delay control module (CDL / FDL Control) 21. When the memory's operating frequency is lower than a preset frequency, the Mux selects to send the replication target clock signal output from the replication clock distribution network 17 into the DLL feedback loop, thereby generating a feedback clock signal. When the memory's operating frequency is greater than or equal to the preset frequency, the Mux selects to send the first phase clock signal into the DLL feedback loop, thereby generating a feedback clock signal. The DLL feedback loop includes the I / O replica, PD, and CDL / FDL Control. Thus, when the memory is operating at high speed, the replication adjustable delay line 16 and the replication clock distribution network 17 can be turned off to save power, thereby reducing power supply noise and clock jitter.

[0114] In summary, the delay-locked loop provided in this embodiment reduces circuit power consumption and power supply noise, thereby reducing clock jitter and improving the quality of the clock signal, by disabling the second adjustable delay line and the second clock distribution network when the memory is operating at high speed, and only enabling the first adjustable delay line and the first clock distribution network, and generating at least a first phase clock signal and a second phase clock signal through a multi-phase clock generation circuit.

[0115] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 5 This illustrates a schematic diagram of the composition structure of a memory 40 provided in an embodiment of this disclosure. For example... Figure 5 As shown, the memory 40 includes at least the aforementioned delay phase-locked loop 10.

[0116] In some embodiments, the memory conforms to at least one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, LPDDR6.

[0117] The memory includes a delay-locked loop (PLL) that, during high-speed operation, disables the second adjustable delay line and the second clock distribution network, enabling only the first adjustable delay line and the first clock distribution network. This, combined with a multi-phase clock generation circuit, generates at least a first-phase clock signal and a second-phase clock signal. This reduces circuit power consumption, power supply noise, and clock jitter, improving clock signal quality. Consequently, it allows for accurate generation of the data strobe signal DQS and more precise sampling of the data signal DQ, enhancing the signal quality of the memory's output DQS and DQ signals.

[0118] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A delay-locked loop, characterized in that, Applied to memory, including: The first adjustable delay line is configured to receive a first clock signal and a control code, perform delay processing on the first clock signal based on the control code, and output a first delayed clock signal. The second adjustable delay line is configured to receive a second clock signal and the control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the second clock signal based on the control code, and output a second delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the second adjustable delay line is disabled. A first clock distribution network, electrically connected to the first adjustable delay line, is configured to receive the first delayed clock signal and transmit it to the output port area of ​​the memory to output a first target clock signal. The second clock distribution network, electrically connected to the second adjustable delay line, is configured to receive the second delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than a preset frequency, and output a second target clock signal, wherein the phase difference between the second target clock signal and the first target clock signal is a preset value; when the operating frequency of the memory is greater than or equal to the preset frequency, the second clock distribution network is disabled. A multi-phase clock generation circuit, electrically connected to the first clock distribution network, is configured to receive the first target clock signal when the operating frequency of the memory is greater than or equal to a preset frequency, and generate at least a first phase clock signal and a second phase clock signal based on the first target clock signal, wherein the first phase clock signal and the first target clock signal are in phase, and the phase difference between the second phase clock signal and the first target clock signal is the preset value; when the operating frequency of the memory is less than the preset frequency, the multi-phase clock generation circuit is disabled.

2. The delay phase-locked loop according to claim 1, characterized in that, It also includes, The copy adjustable delay line is configured to, when the operating frequency of the memory is less than a preset frequency, simulate the delay of the first adjustable delay line, receive the copy clock signal, perform delay processing on the copy clock signal based on the control code, and output a copy delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the copy adjustable delay line is disabled. The replication clock distribution network, electrically connected to the replication adjustable delay line, is configured to receive the replication delay clock signal, simulate the delay of the first clock distribution network, and output the replication target clock signal when the operating frequency of the memory is less than a preset frequency; and to disable the replication clock distribution network when the operating frequency of the memory is greater than or equal to the preset frequency.

3. The delay phase-locked loop according to claim 2, characterized in that, It also includes, The selection circuit, electrically connected to the multi-phase clock generation circuit and the replication clock distribution network, is configured to receive the replication target clock signal and the first phase clock signal; when the operating frequency of the memory is less than a preset frequency, output the replication target clock signal; and when the operating frequency of the memory is greater than or equal to the preset frequency, output the first phase clock signal.

4. The delay phase-locked loop according to claim 3, characterized in that, It also includes, A delay simulation circuit, electrically connected to the output of the selection circuit, is used to simulate the delay of the clock input path and clock output path in the memory and output a feedback clock signal; the clock input path includes a clock receiver and a frequency divider, and the clock output path includes an output driver circuit; A phase detector, electrically connected to the delay analog circuit, is configured to receive the feedback clock signal and the reference clock signal, and output an indication signal based on the phase order of the two. A control code generation circuit, electrically connected to the phase detector, is configured to adjust and output the control code based on the indication signal.

5. The delay phase-locked loop according to claim 2, characterized in that, When the operating frequency of the memory is less than the preset frequency, the delay-locked loop has completed phase locking, and the memory does not perform a read operation, the first adjustable delay line, the second adjustable delay line, the first clock distribution network, and the second clock distribution network are not enabled, and only the copy adjustable delay line and the copy clock distribution network are enabled.

6. The delay phase-locked loop according to claim 1, characterized in that, The multiphase clock generation circuit is adjacent to the output port area of ​​the memory.

7. The delay phase-locked loop according to claim 2, characterized in that, The first adjustable delay line, the second adjustable delay line, and the replicated adjustable delay line have the same circuit structure.

8. The delay phase-locked loop according to claim 7, characterized in that, The first adjustable delay line, the second adjustable delay line, and the copy adjustable delay line all include a coarse-tuning delay line, a fine-tuning delay line, and a driver.

9. The delay phase-locked loop according to claim 7, characterized in that, The first adjustable delay line, the second adjustable delay line, and the copy adjustable delay line all include a duty cycle correction circuit and a quadrant error correction circuit; when the operating frequency of the memory is greater than or equal to a preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are disabled; when the operating frequency of the memory is less than the preset frequency, the duty cycle correction circuit and the quadrant error correction circuit of the first adjustable delay line are enabled.

10. The delay phase-locked loop according to claim 2, characterized in that, The first clock distribution network, the second clock distribution network, and the replicated clock distribution network have the same circuit structure.

11. The delay phase-locked loop according to claim 1, characterized in that, The first adjustable delay line and the second adjustable delay line are located in the first voltage domain, and the first clock distribution network and the second clock distribution network are located in the second voltage domain; the power supply voltage of the first voltage domain and the power supply voltage of the second voltage domain are the same.

12. The delay phase-locked loop according to claim 1, characterized in that, Also includes: The third adjustable delay line is configured to receive a third clock signal and the control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the third clock signal based on the control code, and output a third delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third adjustable delay line is disabled. The fourth adjustable delay line is configured to receive a fourth clock signal and the control code when the operating frequency of the memory is less than a preset frequency, perform delay processing on the fourth clock signal based on the control code, and output a fourth delayed clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth adjustable delay line is disabled. The third clock distribution network, electrically connected to the third adjustable delay line, is configured to receive the third delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than a preset frequency, and output the third target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the third clock distribution network is disabled. The fourth clock distribution network, electrically connected to the fourth adjustable delay line, is configured to receive the fourth delayed clock signal and transmit it to the output port area of ​​the memory when the operating frequency of the memory is less than a preset frequency, and output the fourth target clock signal; when the operating frequency of the memory is greater than or equal to the preset frequency, the fourth clock distribution network is disabled. The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially 90 degrees apart in phase.

13. The delay phase-locked loop according to claim 12, characterized in that, The clock frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are half the clock frequency of the initial clock signal received by the memory, wherein the clock frequency of the initial clock signal is equal to the operating frequency of the memory.

14. The delay phase-locked loop according to claim 12, characterized in that, Also includes: The mode control circuit is configured to, when the operating frequency of the memory is less than a preset frequency, send the first clock signal to the first adjustable delay line, send the second clock signal to the second adjustable delay line, send the third clock signal to the third adjustable delay line, and send the fourth clock signal to the fourth adjustable delay line; when the operating frequency of the memory is greater than or equal to the preset frequency, only send the first clock signal to the first adjustable delay line; and do not send the second clock signal, the third clock signal, and the fourth clock signal.

15. The delay phase-locked loop according to claim 1, characterized in that, When the operating frequency of the memory is greater than or equal to a preset frequency, the multi-phase clock generation circuit also generates a third-phase clock signal and a fourth-phase clock signal; the phases of the first-phase clock signal, the second-phase clock signal, the third-phase clock signal and the fourth-phase clock signal are successively 90 degrees apart.

16. The delay phase-locked loop according to claim 6, characterized in that, The memory's output port area includes a high-order output port area and a low-order output port area; the multi-phase clock generation circuit includes a high-order multi-phase clock generation circuit and a low-order multi-phase clock generation circuit; the high-order multi-phase clock generation circuit is adjacent to the high-order output port area and is configured to provide at least the first phase clock signal and the second phase clock signal to the high-order output port; the low-order multi-phase clock generation circuit is adjacent to the low-order output port area and is configured to provide at least the first phase clock signal and the second phase clock signal to the low-order output port; when one of the high-order output port and the low-order output port is not enabled, the corresponding multi-phase clock generation circuit is disabled.

17. A memory, characterized in that, Including the delay phase-locked loop as described in any one of claims 1-16.

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