Method and apparatus for transmitting a request in a system on chip, system on chip

Abstract

The present disclosure provides a method and device for transmitting a request in a system chip, and a system chip. The method comprises: obtaining a plurality of sending requests; the sending requests enter a normal channel cache after entering a network on chip; obtaining a request delay time of the sending requests; performing a time delay threshold determination on the request delay time to obtain sending requests exceeding the time delay threshold; obtaining a flow control packet of the sending requests exceeding the time delay threshold; the flow control packet is transmitted in a virtual channel in the network on chip, and is compared with the identity code of the cache sending requests located in the normal channel, when the comparison result is consistent, the emergency request packet is dispatched to the virtual channel through an escape channel in the network on chip, and is preferentially dispatched to a plurality of downstream nodes of the network on chip through the virtual channel, and is transmitted in the downstream nodes by using the virtual channel. The present disclosure can improve the real-time performance of the virtual channel escape.

Description

Technical Field

[0001] This disclosure pertains to the field of chip technology, and relates to complex system-on-a-chip (SoC), and particularly to a method and apparatus for transmitting requests in a SoC, and a SoC itself. Background Technology

[0002] A System-on-Chip (SoC) is an integrated circuit that integrates an entire electronic system or subsystem onto a single chip. Virtual channel escape is a flow management technique used in SoC systems. Within an SoC, different modules communicate via Network-on-Chip (NOC). Virtual channel technology divides the physical channel into multiple logical channels, each capable of independently transmitting data streams. When a virtual channel becomes congested or fails, the escape mechanism allows data to continue transmitting through other available virtual channels, ensuring uninterrupted system communication. Summary of the Invention

[0003] This disclosure provides methods, systems, and electronic devices for transmitting requests in a system-on-a-chip, which can improve the real-time performance of virtual channel escape.

[0004] In a first aspect, this disclosure provides a method for transmitting requests in a system-on-a-chip (SoC). The method includes: sending at least one request to an on-chip network (SoC) within the SoC, and caching the at least one request in a normal channel within a node of the SoC; obtaining a request delay time for the at least one request, the request delay time being the time from sending a request to receiving a response to the request; if the request delay time exceeds a latency threshold, sending a flow control packet to the SoC for the request, and caching the flow control packet in a virtual channel within a node of the SoC, the flow control packet having the same identity code as the request; comparing the identity codes of the flow control packet in the virtual channel with those of each request in the normal channel within a node of the SoC; identifying the request having the same identity code as the flow control packet as an emergency request packet; and scheduling the emergency request packet to the virtual channel via an escape channel within a node of the SoC, and preferentially scheduling the emergency request packet to a downstream node of the SoC via the virtual channel, so that the emergency request packet is transmitted using the virtual channel in all subsequent downstream nodes. In one implementation of the first aspect, if the flow control packet in the virtual channel of the node in the on-chip network is inconsistent with the identity codes of each request in the normal channel, the flow control packet is transmitted through the virtual channel to the downstream node of the on-chip network for further comparison until a request with the same identity code as the flow control packet is found.

[0005] In one implementation of the first aspect, the method further includes: when the downstream node has space to receive a request, the downstream node sends a credit signal to the upstream node in the on-chip network; and the upstream node sends a request to the downstream node based on the credit signal.

[0006] In one implementation of the first aspect, the method further includes: after finding a request with the same identity code as the flow control packet in the virtual channel from among the requests in the normal channel, destroying the flow control packet in the virtual channel in place.

[0007] In one implementation of the first aspect, the method further includes: a proxy module issuing the at least one request, wherein the proxy module assigns a unique identity code to each of the at least one request.

[0008] In one implementation of the first aspect, obtaining the request delay time of the at least one request includes: the proxy module starting a timer when the at least one request is sent to the on-chip network, and stopping the timer when a response to the at least one request is received.

[0009] In one implementation of the first aspect, the method further includes: the proxy module processing the at least one request to obtain a request without dependencies.

[0010] In one implementation of the first aspect, the method further includes: monitoring the latency of a request that has been sent to the on-chip network but for which no response has been received by using a counter in each of a plurality of timers set within the proxy module.

[0011] In one implementation of the first aspect, sending a flow control packet to the on-chip network in response to the request includes: when the timer detects that the delay time of the request exceeds a delay threshold, the proxy module sends a flow control packet having the same identity code as the request that exceeds the delay threshold.

[0012] Secondly, this disclosure provides an apparatus for transmitting requests in a system-on-a-chip (SoC). The apparatus includes: a normal channel, disposed at each node of the SoC's on-chip network, including a first-in-first-out (FIFO) buffer unit of depth N, where N represents the round-trip delay between the current node and a downstream node, and configured to receive and buffer at least one request sent by a proxy module to the SoC; and a virtual channel, disposed at each node of the SoC's SoC, including a FIFO buffer unit of depth 1, and configured to receive and buffer a flow control packet sent by the proxy module to the SoC for a request when the request delay time exceeds a latency threshold, wherein the flow control packet has the same identification code as the request, and the request delay time is from sending the request to receiving the response to the request. The system includes: a time-based escape route, located at each node of the system-on-a-chip network (SoC) and coupled between the normal channel and the virtual channel; and a logic module located at each node of the SoC, configured to compare the flow control packets in the virtual channel with each request in the normal channel using identity codes, identify the request with the same identity code as the flow control packet as an emergency request packet, schedule the emergency request packet to the virtual channel via the escape route, and prioritize scheduling the emergency request packet to the downstream node of the SoC node via the virtual channel, so that the emergency request packet is transmitted in all subsequent downstream nodes using the virtual channel in the downstream node.

[0013] Thirdly, this disclosure provides a system-on-a-chip (SoC). The SoC includes: an on-chip network; a normal channel disposed in each node of the on-chip network and including a first-in-first-out (FIFO) buffer unit of depth N, where N represents the round-trip latency between the current node and the downstream node; a virtual channel disposed in each node of the on-chip network and including a FIFO buffer unit of depth 1; an escape channel disposed in each node of the on-chip network and coupled between the normal channel and the virtual channel; and a proxy module configured to: send at least one request to the on-chip network; obtain the request latency of the at least one request, the request latency being the time from sending a request to receiving a response to the request; and if the request latency exceeds a latency threshold, send a flow control packet to the on-chip network for the request. The flow control packet has the same identity code as the request; a logic module is set in each node of the on-chip network and configured to: cache the at least one request in the normal channel of the node of the on-chip network; cache the flow control packet in the virtual channel of the node of the on-chip network; compare the identity codes of the flow control packet in the virtual channel with those of each request in the normal channel; determine the request with the same identity code as the flow control packet as an emergency request packet; and schedule the emergency request packet to the virtual channel through the escape channel, and prioritize scheduling the emergency request packet to the downstream node of the node of the on-chip network through the virtual channel, so that the virtual channel in the downstream node is used to transmit the emergency request packet in all subsequent downstream nodes.

[0014] In the method and apparatus for transmitting requests in a system-on-a-chip (SoC) according to this disclosure, and in the SoC itself, the request delay time of a transmission request cached in a normal channel is obtained, and a delay threshold is determined for this delay time. When a transmission request exceeds the delay threshold, a flow control packet with the same identification code is sent to the on-chip network (SoC) to salvage the transmission request. The flow control packet is transmitted through a virtual channel of the SoC. The flow control packet is compared with the cached transmission requests in the normal channel. When the comparison is consistent, the emergency request packet of the cached transmission request is scheduled to the virtual channel through an escape channel, and then preferentially scheduled to multiple downstream nodes of the SoC for processing through the virtual channel. The flow control packet transmitted in the virtual channel ensures that even in the case of request congestion, the emergency request packet can be caught up in time. The emergency request packet is separately pushed into the virtual channel from the escape channel instead of being blocked in the physical channel, thus ensuring high real-time performance and efficiency, and meeting the requirements of high real-time requests. It also ensures that the emergency request packet, after being scheduled to the virtual channel, will not cause out-of-order issues if it exceeds the previous requests. Attached Figure Description

[0015] Figure 1The diagram shown is an application scenario illustration of Embodiment 1 of this disclosure.

[0016] Figure 2 The flowchart shown is a method for transmitting requests in a system chip according to an embodiment of this disclosure.

[0017] Figure 3 The diagram shows a schematic representation of the request delay time for obtaining the sending request as described in an embodiment of this disclosure.

[0018] Figures 4 to 6 The diagram illustrates a process of a method for transmitting a request in a system chip according to an embodiment of this disclosure.

[0019] Figure 7 The diagram shown is a structural schematic of an apparatus for transmitting requests in a system chip according to an embodiment of this disclosure.

[0020] Figure 8 The diagram shown is a structural schematic of the system chip described in an embodiment of this disclosure. Detailed Implementation

[0021] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. Therefore, the drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] A System-on-Chip (SoC) is an integrated circuit that integrates an entire electronic system or subsystem onto a single chip. Virtual channel escape is a flow management technique used in SoC systems. Within an SoC, different modules communicate via Network-on-Chip (NOC). Virtual channel technology divides the physical channel into multiple logical channels, each capable of independently transmitting data streams. When a virtual channel becomes congested or fails, the escape mechanism allows data to continue transmitting through other available virtual channels, ensuring uninterrupted system communication.

[0024] In complex SOC systems, some technical solutions employ flow control signals and packets to prioritize urgent requests. During virtual channel escape in a NOC system, flow control packets dynamically adjust priorities for flow control. When an urgent request is detected as being blocked in the NOC, the priority of all preceding requests blocking that urgent request is increased, allowing these preceding requests to be received by lower-level nodes first, thus enabling the urgent request to reach the lower level faster. However, this solution cannot make urgent requests take effect immediately; preceding requests must be received first. In extreme cases, such as when lower-level nodes are heavily loaded with DDR (Double Data Rate) requests, they cannot quickly process so many preceding requests, and processing these requests may further increase the workload on lower-level nodes. Furthermore, some requests that are forcibly pushed forward among the preceding requests may include many non-urgent requests, easily leading to a waste of consumer resources.

[0025] Other technical solutions employ on-chip network routing control, which allocates virtual channels according to the destination of transmission packets, ensuring that transmissions on different paths do not block each other. However, this solution can only guarantee that requests are not sent to the wrong address range, but cannot guarantee the latency of requests to the destination, and therefore cannot guarantee real-time performance.

[0026] In response to at least the above-mentioned problems, the present disclosure provides the following embodiments for transmitting requests in a system chip.

[0027] The technical solutions in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0028] Figure 1 The diagram illustrates an application scenario of one embodiment of this disclosure. As shown, a System-on-Chip (SoC) integrates a processor, memory, and other functional modules into a single chip. In the SoC architecture, a Network-on-Chip (NOC) connects the various modules within the SoC via routers and links, forming a communication network. In the NOC, each NOC node connects to one or more SoC functional modules, enabling data transmission, reception, and forwarding. When a functional module in the SoC needs to send a request, the request is encapsulated into a data packet and transmitted to the NOC node through the network interface. Upon receiving the request, the NOC node matches the request ID with the node's ID. If a match is found, the request is processed; otherwise, it is forwarded to the next node.

[0029] Figure 2 This is a flowchart illustrating a method for transmitting a request in a system-on-a-chip according to an embodiment of this disclosure. Figure 2As shown, the method includes the following steps S11 to S16.

[0030] Step S11: Send at least one request to the on-chip network in the system chip, and cache the at least one request in the normal channel of the node in the on-chip network.

[0031] In some embodiments, the source is the starting point for initiating data requests and is the origin of the data stream. In a System-on-Chip (SoC), the source actively initiates data transmission requests, which are received by the destination. In end-to-end latency monitoring, the source is the starting point for timestamp recording, used to mark the precise moment the data stream reaches the SoC. Furthermore, the source may include, for example, a processor, controller, peripheral interface, memory management unit, and interrupt controller. Within the SoC, different modules communicate via a Network-on-Chip (NOC). The source master device in the SoC sends communication requests to the NOC to access slave devices.

[0032] In some embodiments, the at least one request is issued by a proxy module at the source end, and the proxy module assigns a unique identity code to each of the at least one request. The proxy module processes the multiple sending requests to obtain multiple sending requests that are independent of each other.

[0033] For example, a proxy module, which is a hardware module, is set up at the source end of the request sending. This proxy module starts timing each request sent to the NOC and continues until a response is received, thereby monitoring each packet. Simultaneously, the proxy module assigns a unique ID to each request packet sent to the NOC for identification. The request packet is the carrier of the request and includes all information about the request, such as address, data, and priority.

[0034] For example, each chip node internally has a normal channel and a virtual channel. The normal channel consists of a FIFO data structure of depth N, used to temporarily store data packets to be transmitted, ensuring that data is processed sequentially according to the order of transmission. Depth N represents the round-trip delay between the current node and the downstream node, used to match the path bandwidth. The virtual channel consists of a FIFO data structure of depth 1. Since the virtual channel is used for request escape, a depth of 1 does not require matching the path bandwidth. The FIFO data structure ensures the sequential order of data packets, avoiding data errors caused by out-of-order transmission.

[0035] Step S12: Obtain the request delay time of the at least one request, wherein the request delay time is the time from sending a request to receiving the request response.

[0036] In some embodiments, obtaining the request latency of the at least one request includes: the proxy module starting a timer when the at least one request is sent to the on-chip network, and stopping the timer when a response to the at least one request is received. The proxy module monitors the latency of a request that has been sent to the on-chip network but has not received a response by using counters from multiple sets of timers. For details, please refer to [link to relevant documentation]. Figure 3 Request 0, Request 1 and Request 2 are the sending requests, and 400ns, 900ns and 100ns are the delays of Request 0, Request 1 and Request 2 obtained by the timer, respectively.

[0037] Step S13: If the request delay time exceeds the delay threshold, a flow control packet is sent to the on-chip network for the request, and the flow control packet is cached in the virtual channel of the node of the on-chip network. The flow control packet has the same identity code as the request.

[0038] In some embodiments, sending a flow control packet to the on-chip network in response to the request includes: when the timer detects that the request delay time exceeds a latency threshold, the proxy module sends a flow control packet with the same identity code as the request exceeding the latency threshold. The maximum latency threshold is a preset time limit used to determine whether the transmission of a data packet sending a request in the NOC has timed out. When the total delay of a data packet sending a request from entering the NOC to reaching the target node exceeds the maximum latency threshold, it indicates that the packet cannot meet the real-time requirements. At this time, the proxy module marks the packet as an urgent packet (a high-priority packet) and sends a flow control packet to the NOC.

[0039] In some embodiments, the proxy module sets a maximum latency threshold for request packets. When the latency of any request packet exceeds this threshold, it is defined as an emergency request packet at the proxy module. Simultaneously, the proxy module sends a flow control packet with the same ID as the emergency request packet to the NOC to salvage the emergency request packet. The flow control packet is control information sent by the proxy module to the NOC, including the ID of the emergency packet, the target node, and other information.

[0040] Step S14: In the nodes of the on-chip network, the flow control packet in the virtual channel is compared with each request in the normal channel by identity encoding.

[0041] In some embodiments, the virtual channel is a communication channel that allows multiple data packets to share the same physical link by dividing the physical link into multiple logical paths. The flow control packet is transmitted along the same path as the emergency request packet within the on-chip network, and utilizes the virtual channel of the on-chip network for transmission at each node of the on-chip network, thereby catching up with the emergency request packet in time when the ordinary channel is congested.

[0042] Step S15: The request with the same identity code as the flow control packet is identified as an emergency request packet.

[0043] Step S16: The emergency request packet is scheduled to the virtual channel through the escape channel in the node of the on-chip network, and the emergency request packet is preferentially scheduled to the downstream node of the node of the on-chip network through the virtual channel, so that the virtual channel in the downstream node is used to transmit the emergency request packet in all subsequent downstream nodes.

[0044] In some embodiments, when a flow control packet passes through each on-chip network node, the ID identification code carried by the flow control packet is compared with each transmission request cached in the node using the ID comparison logic within the node. If the comparison matches, the transmission request is marked as an emergency request packet and scheduled to be allocated to a virtual channel. When the emergency request packet is scheduled to the virtual channel through the escape channel within the node, the flow control packet located in the virtual channel will be automatically destroyed in place. Requests marked as emergency request packets in the on-chip network can be directly transmitted on each level of node through virtual channels, thereby reaching the destination node at the fastest speed.

[0045] In some embodiments, if the flow control packet in the virtual channel of the node in the on-chip network does not match the identity code of any of the requests in the normal channel, the flow control packet is transmitted through the virtual channel to the downstream node of the on-chip network for further comparison until a request with the same identity code as the flow control packet is found. By using the virtual channel as a high-real-time escape channel and as a transmission channel for network flow control packets, it is ensured that global flow control scheduling can take effect in a timely manner, and emergency request packets can be separately advanced through the escape channel, achieving high real-time performance and efficiency of requests.

[0046] It should be noted that the method for transmitting requests in a system chip according to this disclosure requires the following preconditions to be met during the emergency request scheduling process.

[0047] 1) When the downstream node has space to receive the transmission request, it sends a credit signal to the upstream node in the on-chip network; and the upstream node sends the transmission request to the downstream node based on the credit signal. That is, each node in the on-chip network uses a credit mechanism for transmission. A downstream node sends a credit signal to the upstream node only when it has space to receive the transmission request. When the upstream node receives the credit signal, it sends its own transmission request to the downstream node. This credit mechanism ensures that the transmission request sent by a node will reach the downstream node and will not be blocked in the virtual channel, further guaranteeing the real-time performance of the virtual channel and meeting high real-time requirements. For example, when a display device retrieves data, it can guarantee that the data will be returned with very small deviation within a preset time.

[0048] 2) The proxy module processes the at least one request to obtain requests without dependencies. That is, if there is an order-preserving dependency between the sending requests, the request initiator needs to maintain the order of sending requests at the source end to ensure that there is no order-preserving dependency between all requests sent to the on-chip network. This ensures that urgent request packets are scheduled to the virtual channel and surpass previous requests without causing out-of-order problems. Access to other devices in the complex system is not affected, and a high DDR utilization rate can still be guaranteed.

[0049] The method provided in this application will now be described in detail through a specific example. It should be noted that the content of this example is only for explaining and illustrating the method provided in this application, and is not intended to limit the scope of protection of this application in any way. In specific applications, corresponding steps can be added or deleted based on this example according to actual needs. Figures 4 to 6 This diagram illustrates the process of transmitting requests within the system chip in this example. (Example:) Figures 4 to 6 As shown, the method includes the following steps S100 to S106.

[0050] Step S100: The source proxy module initiates a sending request.

[0051] In step S101, after a normal transmission request enters the on-chip network node, it queues in the normal channel to wait for transmission.

[0052] In step S102, the timer of the proxy module detects whether the delay time of sending the request exceeds the maximum delay threshold.

[0053] Step S103: When the maximum delay threshold is exceeded, the proxy module sends a flow control packet with the same identity code as the sending request.

[0054] In step S104, after the flow control packet enters the on-chip network, it enters the virtual channel and is compared with the ID of all queuing transmission requests in the normal channel.

[0055] In step S105, when no request with the same identity code is found, the flow control packet is prioritized and scheduled to the downstream node to continue ID comparison until a request with the same identity code is found.

[0056] In step S106, when a request with the same identity code is found, the request is marked as an emergency request packet. The flow control packet is destroyed in place, and the emergency request packet escapes directly to the virtual channel through the escape channel in the node. It is then prioritized and scheduled to the downstream node, where it is transmitted within the virtual channel of the downstream node.

[0057] It should be noted that the labels S100 to S106 are only used to indicate different steps, and not to restrict the execution order of these steps.

[0058] The scope of protection of the methods described in this disclosure is not limited to the execution order of the steps listed in this disclosure. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this disclosure is included within the scope of protection of this disclosure.

[0059] In another aspect, this disclosure also provides an apparatus for transmitting requests in a system-on-a-chip. Figure 7 The diagram shown is a structural schematic of an apparatus for transmitting requests in a system-on-a-chip according to an embodiment of this disclosure. (Refer to...) Figure 7 The device includes a normal channel, a virtual channel, an escape channel, and a logic module.

[0060] The normal channels are configured in each node of the on-chip network of the system chip. Each normal channel includes a first-in, first-out (FIFO) buffer unit of depth N, where N represents the round-trip latency between the current node and the downstream node. The normal channels are configured to receive and buffer at least one request sent by the proxy module to the on-chip network.

[0061] The virtual channels are set at each node of the on-chip network of the system chip. Each virtual channel includes a first-in, first-out (FIFO) cache unit with a depth of 1. The virtual channel is configured to receive and cache flow control packets sent to the on-chip network by the proxy module for a request when the request delay time exceeds a latency threshold. The flow control packets have the same identification code as the request, and the request delay time is the time from sending the request to receiving the response to the request.

[0062] The escape routes are located at various nodes of the on-chip network of the system chip. The escape routes are coupled between the normal channels and the virtual channels.

[0063] The logic module is located in each node of the on-chip network of the system chip. The logic module is configured to compare the flow control packets in the virtual channel with each request in the normal channel using an identity code, identify requests with the same identity code as the flow control packets as emergency request packets, schedule the emergency request packets to the virtual channel through the escape channel, and prioritize scheduling the emergency request packets to downstream nodes of the on-chip network nodes through the virtual channel, so that the virtual channels in all subsequent downstream nodes utilize the emergency request packets for transmission.

[0064] The device can implement the method for transmitting requests in a system chip as described in this disclosure. However, the implementation device of the method described in this disclosure includes, but is not limited to, the structure of the device listed in this embodiment. Any structural modifications and substitutions of the prior art made in accordance with the principles of this disclosure are included within the protection scope of this disclosure.

[0065] In another aspect, this disclosure also provides a system-on-a-chip (SoC). Figure 8 The diagram shown is a structural schematic of a system chip according to an embodiment of this disclosure. (Refer to...) Figure 8 The system chip includes an on-chip network, a normal channel, a virtual channel, an escape channel, a proxy module, and a logic module.

[0066] The ordinary channels are set in each node of the on-chip network and include a first-in-first-out buffer unit with a depth of N, where N represents the round-trip delay between the current node and the downstream node.

[0067] The virtual channels are set at each node of the on-chip network and include a first-in-first-out cache unit with a depth of 1.

[0068] The escape routes are located at each node of the on-chip network and are coupled between the normal channels and the virtual channels.

[0069] The proxy module is configured to send at least one request to the on-chip network and obtain the request latency of the at least one request, wherein the request latency is the time from sending a request to receiving a response to the request. Furthermore, the proxy module is configured to send a flow control packet to the on-chip network for the request if the request latency exceeds a latency threshold; the flow control packet has the same identity code as the request.

[0070] The logic module is located in each node of the on-chip network. The logic module is configured to cache the at least one request in the normal channel of the on-chip network node and cache the flow control packet in the virtual channel of the on-chip network node. The logic module is configured to compare the flow control packet in the virtual channel with each request in the normal channel using an identity code, and identify the request with the same identity code as the flow control packet as an emergency request packet. Furthermore, the logic module is configured to schedule the emergency request packet to the virtual channel through the escape channel, and to prioritize scheduling the emergency request packet to the downstream node of the on-chip network node through the virtual channel, so that the virtual channel in the downstream node is used to transmit the emergency request packet in all subsequent downstream nodes.

[0071] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules / units is only a logical functional division, and other division methods may exist in actual implementation. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections between devices, modules, or units through some interfaces, and may be electrical, mechanical, or other forms.

[0072] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this disclosure, depending on actual needs. For example, the functional modules / units in the various embodiments of this disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0073] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0074] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0075] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A method for transmitting requests in a system-on-a-chip, characterized in that, include: Send at least one request to the on-chip network in the system chip, and cache the at least one request in the normal channel of the node in the on-chip network; Obtain the request delay time of the at least one request, where the request delay time is the time from sending a request to receiving a response to the request; If the request delay time exceeds the delay threshold, a flow control packet is sent to the on-chip network for the request, and the flow control packet is cached in the virtual channel of the node of the on-chip network. The flow control packet has the same identity code as the request. In the nodes of the on-chip network, the flow control packets in the virtual channel are compared with the individual requests in the normal channel using identity encoding. The request with the same identity code as the flow control packet is identified as an emergency request packet; as well as The emergency request packet is scheduled to the virtual channel through the escape channel in the node of the on-chip network, and the emergency request packet is preferentially scheduled to the downstream node of the node of the on-chip network through the virtual channel, so that the virtual channel in the downstream node is used to transmit the emergency request packet in all subsequent downstream nodes.

2. The method according to claim 1, characterized in that, Also includes: If the flow control packet in the virtual channel of the node in the on-chip network does not match the identity code of each request in the normal channel, the flow control packet is transmitted through the virtual channel to the downstream node of the on-chip network for further comparison until a request with the same identity code as the flow control packet is found.

3. The method according to claim 1, characterized in that, Also includes: When the downstream node has space to receive requests, the downstream node sends a credit signal to the upstream node in the on-chip network. as well as The upstream node sends the request to the downstream node based on the credit signal.

4. The method according to claim 1, characterized in that, Also includes: After finding the request with the same identity code as the flow control packet in the virtual channel among the requests in the normal channel, the flow control packet in the virtual channel is destroyed in place.

5. The method according to claim 1, characterized in that, Also includes: The proxy module issues at least one request, and the proxy module assigns a unique identity code to each of the at least one request.

6. The method according to claim 5, characterized in that, Obtaining the request latency of the at least one request includes: The proxy module starts timing when the at least one request is sent to the on-chip network, and stops timing when a response to the at least one request is received.

7. The method according to claim 5, characterized in that, Also includes: The proxy module processes the at least one request to obtain a request without dependencies.

8. The method according to claim 5, characterized in that, Also includes: The latency of a request that has been sent to the on-chip network but has not received a response is monitored by using each of the multiple timers set within the proxy module.

9. The method according to claim 8, characterized in that, Sending a flow control packet to the on-chip network in response to the request includes: When the timer detects that the request delay time exceeds a set delay threshold, the proxy module sends a flow control packet with the same identity code as the request that exceeds the delay threshold.

10. An apparatus for transmitting a request in a system-on-a-chip, characterized in that, include: A normal channel is set in each node of the on-chip network of the system chip, including a first-in-first-out buffer unit of depth N, where N represents the round-trip delay between the current node and the downstream node, and is configured to receive and buffer at least one request sent by the proxy module to the on-chip network. The virtual channel is set at each node of the on-chip network of the system chip, including a first-in-first-out cache unit with a depth of 1, and is configured to receive and cache the flow control packet sent by the proxy module to the on-chip network for the request when the request delay time exceeds the latency threshold. The flow control packet has the same identity code as the request, and the request delay time is the time from sending the request to receiving the response to the request. Escape routes are located at various nodes of the on-chip network of the system chip and are coupled between the normal channel and the virtual channel; as well as A logic module is disposed in each node of the on-chip network of the system chip and configured to compare the flow control packet in the virtual channel with each request in the normal channel by identification code, identify the request with the same identification code as the flow control packet as an emergency request packet, schedule the emergency request packet to the virtual channel through the escape channel, and prioritize the scheduling of the emergency request packet to the downstream node of the node of the on-chip network through the virtual channel, so that the virtual channel in the downstream node is used to transmit the emergency request packet in all subsequent downstream nodes.

11. A system-on-a-chip (SoC), characterized in that, include: On-screen network; A normal channel is set up in each node of the on-chip network and includes a first-in-first-out buffer unit of depth N, where N represents the round-trip delay between the current node and the downstream node. Virtual channels are set at each node of the on-chip network and include first-in-first-out buffer units with a depth of 1. Escape routes are set at each node of the on-chip network and coupled between the normal channels and the virtual channels; The proxy module is configured as follows: Send at least one request to the on-chip network; Obtain the request delay time of the at least one request, where the request delay time is the time from sending a request to receiving a response to the request; as well as If the request delay time exceeds the delay threshold, a flow control packet is sent to the on-chip network for the request, and the flow control packet has the same identity code as the request; The logic modules are located in each node of the on-chip network and are configured as follows: The at least one request is cached in the normal channel of the node in the on-chip network; The flow control packets are cached in the virtual channels of the nodes in the on-chip network; The flow control packet in the virtual channel is compared with each request in the normal channel by identity encoding; The request with the same identity code as the flow control packet is identified as an emergency request packet; as well as The emergency request packet is scheduled to the virtual channel through the escape channel, and the emergency request packet is preferentially scheduled to the downstream node of the node of the on-chip network through the virtual channel, so that the virtual channel in the downstream node is used to transmit the emergency request packet in all subsequent downstream nodes.

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