Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a glass layer; a first insulating layer covering each of an upper surface and a lower surface of the glass layer; the first conductor layer is arranged on the upper surface of the first insulating layer; the second conductor layer is arranged on the lower surface of the first insulating layer; and a via hole penetrating a region between the first conductor layer and the second conductor layer, in which a through via including a via conductor is disposed, and which is connected to the first conductor layer and the second conductor layer, in which a wall surface of the via hole has at least one offset region.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0114402, filed on August 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] Recently, improving the performance of printed circuit boards (PCBs) has necessitated larger area, more multilayered, and miniaturized structures. Copper-clad laminates (CCLs) can be used as core layers included in PCBs; however, due to their low modulus and high coefficient of thermal expansion, CCLs are prone to warping and may present limitations in the implementation of microcircuits. Therefore, there is a need for core layers formed from new materials that can suppress warping and facilitate the implementation of microcircuits. Furthermore, a PCB may be required that, while utilizing core layers formed from new materials, reduces the number of processes, lowers costs, and ensures process stability. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that facilitates warpage control and allows for easy implementation of microcircuits therein.

[0005] One aspect of this disclosure is to provide a printed circuit board that can reduce the number of processes and lower costs.

[0006] One aspect of this disclosure is to provide a printed circuit board that ensures process stability and in which through-holes can have improved reliability.

[0007] One aspect of this disclosure is that: an insulating layer is stacked on a glass layer to embed the glass layer as a core layer within the insulating layer; a through-hole is formed by a single process after embedding the glass layer; a through-hole is formed by filling the through-hole with a conductor; and at least one offset region is formed on the wall surface of the through-hole during the formation of the through-hole.

[0008] According to an example embodiment, a printed circuit board includes: a glass layer; a first insulating layer covering each of an upper surface and a lower surface of the glass layer; a first conductor layer disposed on the upper surface of the first insulating layer; a second conductor layer disposed on the lower surface of the first insulating layer; and a through-hole penetrating a region located between the first conductor layer and the second conductor layer, wherein the through-hole has a through-hole including a via conductor and the through-hole connects to the first conductor layer and the second conductor layer, wherein the wall surface of the through-hole has at least one offset region.

[0009] According to an example embodiment, a printed circuit board includes: an insulating layer; a glass layer embedded in the insulating layer; a first conductor layer disposed on an upper surface of the insulating layer; a second conductor layer disposed on a lower surface of the insulating layer; and a through-hole penetrating the insulating layer and the glass layer located between the first conductor layer and the second conductor layer, and connecting the first conductor layer and the second conductor layer to each other, wherein the side surface of the through-hole has at least one offset region. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will be more clearly understood through the following specific embodiments in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating an example of an electronic device system; Figure 2 This is a perspective view showing an example of an electronic device; Figure 3 This is a cross-sectional view showing an example of a printed circuit board according to an exemplary embodiment; Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H It is shown Figure 3 Enlarged cross-sectional views of various examples of through-holes forming the printed circuit board shown in region A; Figure 5 This is a cross-sectional view showing another example of a printed circuit board according to an example embodiment; and Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H It is shown Figure 5 The enlarged cross-sectional view shows various examples of the formation of the printed circuit board in region B through the vias. Detailed Implementation

[0011] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. Some elements may be exaggerated, omitted, or simplified, and the dimensions of the elements do not necessarily reflect their actual dimensions.

[0012] Figure 1 This is a block diagram illustrating an example of an electronic device system.

[0013] Reference Figure 1The electronic device 1000 may house a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the motherboard 1010. These components may be connected to other electronic components described below via various signal lines 1090.

[0014] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, encryption processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other.

[0015] Network-related components 1030 may include components that are compatible with or communicate with protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, LAN, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this, and may also include components that are compatible with or communicate with various other wireless or wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0016] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, other electronic components are not limited to these and may include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0018] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0019] Figure 2 This is a perspective view showing an example of an electronic device.

[0020] Reference Figure 2For example, the electronic device may be a smartphone 1100. A motherboard 1110 may be housed in the smartphone 1100, and various components 1120 may be physically and / or electrically connected to the motherboard 1110. Furthermore, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the motherboard 1110 or not physically and / or electrically connected to the motherboard 1110 may be housed in the smartphone 1100. A portion of the components 1120 may be chip-related components, such as a component package 1121, but its exemplary embodiments are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components (including active and / or passive components) are surface-mounted. Alternatively, the component package 1121 may be configured as a printed circuit board in which electronic components (including active and / or passive components) are embedded. The electronic device is not necessarily limited to the smartphone 1100 and may be other electronic devices as described above. Furthermore, the electronic device may be a server-related product requiring a large-area substrate.

[0021] Printed Circuit Board Figure 3 This is a cross-sectional view showing an example of a printed circuit board according to an example embodiment.

[0022] Reference Figure 3 The printed circuit board 100A according to the example may include: a glass layer 110; a first insulating layer 111 covering each of the upper and lower surfaces of the glass layer 110; a first conductor layer 121 disposed on the upper surface of the first insulating layer 111; a second conductor layer 122 disposed on the lower surface of the first insulating layer 111; and a via h penetrating the region located between the first conductor layer 121 and the second conductor layer 122 (e.g., the first insulating layer 111 and / or the glass layer 110), and a through-hole 130-1 including a via conductor 130 is disposed in the via h and connected to the first conductor layer 121 and the second conductor layer 122. The via h may together penetrate the first insulating layer 111 and the glass layer 110. For example, the via h may include: a first portion h1 penetrating the glass layer 110; a second portion h2 penetrating the region of the first insulating layer 111 covering the upper surface of the glass layer 110; and a third portion h3 penetrating the region of the first insulating layer 111 covering the lower surface of the glass layer 110. At least a portion of the via conductor 130 (e.g., a portion of the via conductor 130 disposed in the first portion h1) may contact the glass layer 110. At least another portion of the via conductor 130 (e.g., another portion of the via conductor 130 disposed in the second portion h2 and the third portion h3) may contact the first insulating layer 111.

[0023] Because the printed circuit board 100A includes the glass layer 110 as described above, warpage control can be easily implemented, and microcircuits can be easily realized. Furthermore, by covering the glass layer 110 with the first insulating layer 111, drilling through-holes h that penetrate the first insulating layer 111 and the glass layer 110 in a single pass, and forming the first conductor layer 121 and the second conductor layer 122, as well as the through-hole 130-1 (including the via conductor 130 connecting the first conductor layer 121 and the second conductor layer 122) through a plating process, the number of processes can be reduced, and costs can be lowered. Moreover, the reliability of the through-hole 130-1 is superior to that of stacked vias. Furthermore, the minimum spacing of the through-hole 130-1 can be easily achieved.

[0024] The glass layer 110 can be embedded in the first insulating layer 111. For example, the first insulating layer 111 can cover the upper and lower surfaces of the glass layer 110, and can also cover the side surfaces of the glass layer 110. Therefore, the glass layer 110 can be used as a core layer. Thus, the above-mentioned technical effects can be easily achieved. In addition, the breakage of the glass layer 110 can be effectively prevented.

[0025] If desired, the printed circuit board 100A may further include a frame 118 having a through-hole H. At least a portion of the glass layer 110 may be disposed in the through-hole H. A first insulating layer 111 may also cover the upper and lower surfaces of the frame 118 and may fill at least a portion of the through-hole H. For example, the first insulating layer 111 may fill at least a portion between the side surface of the frame 118 and the side surface of the glass layer 110. The frame 118 may be embedded in at least a portion of the first insulating layer 111. Warp control can be easily performed through the frame 118, and the process can be made easier. Furthermore, multiple through-holes H may be formed in the frame 118 having a large area, so multiple printed circuit boards 100A can be manufactured simultaneously using the same process, and multiple printed circuit boards 100A can be divided and manufactured by a cutting process, thereby improving productivity.

[0026] If needed, the printed circuit board 100A may further include: a second insulating layer 112 disposed on the upper surface of the first insulating layer 111 and covering at least a portion of the first conductor layer 121; a third insulating layer 113 disposed on the lower surface of the first insulating layer 111 and covering at least a portion of the second conductor layer 122; a third conductor layer 123 disposed on the upper surface of the second insulating layer 112; a fourth conductor layer 124 disposed on the lower surface of the third insulating layer 113; a first connection via 131 penetrating at least a portion of the second insulating layer 112 and connecting at least a portion of the first conductor layer 121 and at least a portion of the third conductor layer 123; and a second connection via 132 penetrating at least a portion of the third insulating layer 113 and connecting at least a portion of the second conductor layer 122 and at least a portion of the fourth conductor layer 124. Furthermore, the printed circuit board 100A may also include: a first passivation layer (or a first resist layer) 114 disposed on the upper surface of the second insulating layer 112 and having a plurality of first openings o1, each first opening o1 exposing at least a portion of the third conductor layer 123; and / or a second passivation layer (or a second resist layer) 115 disposed on the lower surface of the third insulating layer 113 and having a plurality of second openings o2, each second opening o2 exposing at least a portion of the fourth conductor layer 124. For example, the printed circuit board 100A may have a multilayer structure and can therefore be used as a flip chip board (FCB), a ball grid array (BGA) package, an interposer substrate, a package substrate, etc. However, its embodiments are not limited thereto, and embodiments can be applied to various other types of substrates.

[0027] The components of the printed circuit board 100A according to the example will be described in more detail below with reference to the accompanying drawings.

[0028] Glass layer 110 may comprise glass (an amorphous solid). The glass may include, for example, pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, embodiments are not limited thereto, and alternative glass materials (e.g., fluoride glass, phosphate glass, chalcogenide glass, etc.) may also be used as materials for glass layer 110. Furthermore, other additives may be included to form a glass with specific physical properties. Such additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates (such as calcium carbonate (e.g., limestone) and sodium carbonate (e.g., soda ash)) and / or oxides of these elements and other elements. Glass layer 110 may be distinguished from organic insulating material layers (such as copper-clad laminates (CCL), prepreg (PPG), etc.) that include glass fibers (e.g., glass fabrics, such as glass cloth). For example, glass layer 110 may comprise a glass panel (such as a glass plate) formed over a relatively large area.

[0029] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113, as well as the first resist layer 114 and the second resist layer 115, may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler, an organic filler, and / or glass fiber (e.g., a glass fabric, such as glass cloth) in a resin. For example, the organic insulating material may be a prepreg (PPG), an ajinomoto film (ABF), a photosensitive dielectric (PID), a solder resist (SR), etc., but embodiments are not limited thereto. If desired, each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113, as well as the first resist layer 114 and the second resist layer 115, may include multiple layers. The first resist layer 114 and the second resist layer 115 may each have a first opening o1 and a second opening o2, and multiple first openings o1 and multiple second openings o2 may be provided. The pad pattern of the third conductor layer 123 exposed through the first opening o1 and the pad pattern of the fourth conductor layer 124 exposed through the second opening o2 can be in the form of solder mask defined (SMD) and / or non-solder mask defined (NSMD).

[0030] Frame 118 may comprise various materials. For example, frame 118 may comprise an organic insulating material such as copper-clad laminate (CCL), or an inorganic insulating material such as silicon or ceramic, or a metal plate containing copper (Cu), etc. However, embodiments thereof are not limited thereto. Frame 118 may have a through-portion H. Through-portion H may penetrate the area between the upper and lower surfaces of frame 118. Through-portion H may have a shape that substantially corresponds to glass layer 110. Through-portion H may continuously surround the side surface of glass layer 110. For example, through-portion H may have a substantially rectangular shape in a plane. If desired, frame 118 may comprise a plurality of through-portions H spaced apart from each other, and the number of through-portions H is not limited to any particular example.

[0031] Each of the first conductor layer 121, the second conductor layer 122, the third conductor layer 123, and the fourth conductor layer 124 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments thereof are not limited thereto. Each of the first conductor layer 121, the second conductor layer 122, the third conductor layer 123, and the fourth conductor layer 124 may perform various functions according to design. For example, the first conductor layer 121, the second conductor layer 122, the third conductor layer 123, and the fourth conductor layer 124 may include signal patterns, power patterns, and ground patterns. These patterns may have various shapes, such as lines, planes, and pads, respectively. Each of the first conductor layer 121, the second conductor layer 122, the third conductor layer 123, and the fourth conductor layer 124 may include a seed layer and a plating layer. The seed layer may be formed by an electroless plating process (e.g., electroless copper plating) or, if desired, by a sputtering process. Alternatively, both electroless plating and sputtering processes can be used. The plating can be formed by an electrolytic plating process (e.g., electrolytic copper plating). Each of the first conductor layer 121, the second conductor layer 122, the third conductor layer 123, and the fourth conductor layer 124 can be formed from multiple layers and can be formed on or within the corresponding layers of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. Each of the first conductor layer 121, the second conductor layer 122, the third conductor layer 123, and the fourth conductor layer 124 can protrude from or be embedded within the corresponding layers of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0032] The through-hole 130-1 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may include copper (Cu), but embodiments thereof are not limited thereto. The through-hole 130-1 may include a via conductor 130 filling at least a portion of the through-hole h. The via conductor 130 may perform various functions depending on the design. For example, the via conductor 130 may include a signal via, a power via, a ground via, etc. The via conductor 130 may be connected to each of the first conductor layer 121 and the second conductor layer 122. The cross-section of the through-hole h and the via conductor 130 filling the through-hole h may have an hourglass shape such that, on the cross-section of the through-hole h cut in the thickness direction (e.g., vertical or stacking direction), the width at the upper end connected to the first conductor layer 121 and the width at the lower end connected to the second conductor layer 122 are greater than the width at the central portion in the thickness direction. The central portion of the via h can be disposed between the upper and lower surfaces of the glass layer 110. The via conductor 130 may include a seed layer and a plating layer. The seed layer can be formed by an electroless plating process (e.g., electroless copper plating) or, if desired, by a sputtering process. Optionally, both electroless plating and sputtering processes can be used. The plating layer can be formed by an electrolytic plating process (e.g., electrolytic copper plating). When multiple vias h are provided, multiple via conductors 130 can also be provided.

[0033] Each of the first connection via 131 and the second connection via 132 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments thereof are not limited thereto. Each of the first connection via 131 and the second connection via 132 may perform various functions according to design. For example, the first connection via 131 and the second connection via 132 may include signal vias, power vias, grounding vias, etc. If desired, each of the first connection via 131 and the second connection via 132 may include a filled via formed by filling the via with metal, or may include a conformal via formed by distributing metal along the wall surface of the via. Each of the first connection via 131 and the second connection via 132 may have a tapered shape in cross-section. For example, in cross-section, the upper width of the first connecting via 131 may be greater than the lower width, and in cross-section, the upper width of the second connecting via 132 may be less than the lower width. The first connecting via 131 may include the same seed layer and plating as those included in the third conductor layer 123, and the second connecting via 132 may include the same seed layer and plating as those included in the fourth conductor layer 124. Multiple first connecting vias 131 and multiple second connecting vias 132 may be provided.

[0034] Figures 4A to 4H It is shown Figure 3 The enlarged cross-sectional view shows various examples of the formation of a printed circuit board in region A vias.

[0035] Reference Figures 4A to 4D The wall surface of the through hole h may have at least one offset region S. In this illustration, the side surface penetrating the through hole 130-1 may have at least one offset region S. For example, as... Figures 4A to 4D As shown, in the cross-section of the through-hole h cut along the thickness direction, the wall surface of the through-hole h may have at least one offset region S, which is located at substantially the same height relative to the central portion of the through-hole h in the thickness direction. Specifically, the through-hole 130-1 may include at least two through-hole portions having tapered shapes in opposite directions and connected to each other. Figure 4A In this configuration, the lower via portion (e.g., the via portion located below the central portion of the through hole h) of at least two via portions may be offset to the right relative to the upper via portion (e.g., the via portion located above the central portion of the through hole h) of at least two via portions, such that the lower end of the upper via portion and the upper end of the lower via portion are misaligned with each other at at least one offset region S. The width at the lower end of the upper via portion may be substantially the same as the width at the upper end of the lower via portion. Figure 4B In this configuration, the lower via portion of at least two via portions may be offset to the left relative to the upper via portion of at least two via portions, such that the lower end of the upper via portion and the upper end of the lower via portion are misaligned at at least one offset region S. The width at the lower end of the upper via portion may be substantially the same as the width at the upper end of the lower via portion. Figure 4C In this configuration, the upper left and right edges of the lower through-hole portion can be offset towards the interior of the lower through-hole portion relative to the lower left and right edges of the upper through-hole portion, respectively. This allows the width at the lower end of the upper through-hole portion to be greater than the width at the upper end of the lower through-hole portion. Figure 4D In this configuration, the left and right edges of the upper end of the lower through-hole portion can be offset outwards relative to the left and right edges of the lower end of the upper through-hole portion, respectively. This allows the width at the lower end of the upper through-hole portion to be smaller than the width at the upper end of the lower through-hole portion.

[0036] like Figures 4E to 4H As shown, in the cross-section of the through-hole h cut along the thickness direction, the wall surface of the through-hole h may have at least one offset region S, each offset region S being located at substantially the same height relative to the thickness direction at the boundary between the upper surface of the glass layer 110 and the first insulating layer 111 or the boundary between the lower surface of the glass layer 110 and the first insulating layer 111. Figures 4E to 4HAs shown, in a cross-section cut along the thickness direction of the through-hole h, the wall surface of the through-hole h can have multiple inner walls with different slopes. For example, the wall surface of the first portion h1 of the through-hole h can have four inner walls with different slopes. In this case, the inflection points between the two inner walls on the left and between the two inner walls on the right can be set at different heights relative to the thickness direction. Therefore, multiple inner walls can exist in more different forms. The slope can be based on the following angle: an acute angle formed by the inner wall and the upper or lower surface of the first insulating layer 111, or an acute angle formed by the inner wall and the upper or lower surface of the glass layer 110, in a cross-section cut along the thickness direction of the through-hole h. For example, the slope can represent the degree of inclination of the inner wall relative to the upper or lower surface of the glass layer 110 or relative to the upper or lower surface of the first insulating layer 111. The slope can refer to the slope of the portion of the inner wall located near the offset region S.

[0037] When the wall surface of the via h has at least one offset region S as described above, thermal and mechanical stresses can be easily dispersed. For example, stresses arising from the difference in thermal expansion coefficients between glass and metal can be mitigated, preventing cracks or damage. Furthermore, the characteristics of high-frequency signals can be improved by diversifying the electrical signal path, and electromagnetic interference (EMI) can be reduced. Therefore, signal integrity can be easily maintained. Additionally, by diffusing heat over a wide area rather than concentrating it in one location, heating problems can be mitigated, which improves reliability at high temperatures. Furthermore, the electrical contact area can be increased, thereby reducing electrical contact resistance and achieving improved current transmission, which can be an important factor, especially in applications requiring high current. Moreover, flexibility is provided for compensating for alignment errors during the manufacturing process (e.g., alignment errors between the upper and lower via portions), thus improving joinability (e.g., joinability between the upper and lower via portions) and manufacturing reliability. These technical effects enable the through-hole 130-1 to be effectively used in electronic devices requiring high performance and high reliability, and can also be important factors in providing performance enhancement and mechanical stability in high-frequency or high-current applications.

[0038] Furthermore, the increased contact area between the through-hole 130-1 and the glass layer 110, as well as the increased contact area between the through-hole 130-1 and the first insulating layer 111, improves the reliability of the through-hole 130-1. When the wall surface of the through-hole h has multiple inner walls with different slopes, defects in the glass layer 110 (such as breakage of the glass layer 110 during processing or microcracks in the glass layer 110) can be prevented. Therefore, process stability can be ensured.

[0039] Other descriptions are substantially the same as those for the printed circuit board 100A, therefore, no duplicate descriptions will be provided.

[0040] Figure 5 This is a cross-sectional view showing another example of a printed circuit board according to an example embodiment.

[0041] Reference Figure 5 Compared to the printed circuit board 100A according to the example above, the printed circuit board 100B according to another example may further include a via hole v formed in the glass layer 110. The via hole v can penetrate the region between the upper and lower surfaces of the glass layer 110. A first insulating layer 111 can fill a portion of the via hole v. A via hole h can be formed in the region where the via hole v is formed. For example, the via hole h may include: a first portion h1, a region that penetrates the first insulating layer 111 and fills a portion of the via hole v; a second portion h2, a region that penetrates the first insulating layer 111 and is disposed on the upper side of the via hole v; and a third portion h3, a region that penetrates the first insulating layer 111 and is disposed on the lower side of the via hole v. Therefore, the via conductor 130 can contact the first insulating layer 111 and can be spaced apart from the glass layer 110. The via hole v may have a shape that substantially corresponds to the via hole h, but embodiments thereof are not limited thereto, and the via hole v and the via hole h may have different shapes if desired. Printed circuit board 100B can also have substantially the same technical effects as those described with respect to printed circuit board 100A. Furthermore, since the via conductor 130 is formed in the through-hole h penetrating the first insulating layer 111, adhesion is improved and plating processes can be easily performed. Therefore, the reliability of the through-hole 130-2 is improved.

[0042] Other descriptions are substantially the same as those for the printed circuit board 100A, therefore, no duplicate descriptions will be provided.

[0043] Figures 6A to 6H It is shown Figure 5 The enlarged cross-sectional view shows various examples of the formation of the printed circuit board in region B through the vias.

[0044] Reference Figures 6A to 6H The wall surface of the through hole h may have at least one offset region S. In this illustration, the side surface of the through hole 130-2 may have at least one offset region S. Furthermore, if desired, the inner wall of the through hole v may also have at least one offset region. For example, as... Figures 6A to 6D As shown, in a cross-section cut along the thickness direction of the through hole h, each of the wall surfaces of the through hole h and the via hole v may have at least one offset region S, which is located at substantially the same height relative to the central portion of the through hole h in the thickness direction. Furthermore, as... Figures 6E to 6HAs shown, in the cross-section where the through-hole h is cut along the thickness direction, the wall surface of the through-hole h may also have at least one offset region S, each offset region S being located at substantially the same height relative to the thickness direction at the boundary between the upper surface of the glass layer 110 and the first insulating layer 111 or the boundary between the lower surface of the glass layer 110 and the first insulating layer 111. Figures 6E to 6H As shown, in the cross-section of the through-hole h cut along the thickness direction, the wall surface of the through-hole h can have multiple inner walls with different slopes. For example, the wall surface of the first part h1 of the through-hole h can have four inner walls with different slopes. In this case, the inflection point between the two inner walls on the left and the inflection point between the two inner walls on the right can be set at different heights relative to the thickness direction. Therefore, multiple inner walls can exist in more different forms. The slope can be based on the following angles: in the cross-section of the through-hole h cut along the thickness direction, the acute angle formed by the inner wall and the upper or lower surface of the first insulating layer 111, or the acute angle formed by the inner wall and the upper or lower surface of the glass layer 110.

[0045] In this manner, when the wall surface of the through-hole h has at least one offset region S, thermal and mechanical stresses can be easily dispersed. For example, stresses arising from the difference in thermal expansion coefficients between glass and metal can be mitigated, preventing cracks or damage. Furthermore, the characteristics of high-frequency signals can be improved by diversifying the electrical signal path, and electromagnetic interference (EMI) can be reduced. Therefore, signal integrity can be easily maintained. Additionally, by diffusing heat over a wide area rather than concentrating it in one location, heating problems can be mitigated, which improves reliability at high temperatures. Moreover, the electrical contact area can be increased, thereby reducing electrical contact resistance and achieving improved current transmission, which can be an important factor, especially in applications requiring high current. Furthermore, flexibility is provided for compensating for alignment errors during the manufacturing process, thus improving mating capability and manufacturing reliability. These technical effects enable the through-hole 130-2 to be effectively used in electronic devices requiring high performance and high reliability, and can also be important factors in providing performance enhancement and mechanical stability in high-frequency or high-current applications.

[0046] Furthermore, the increased contact area between the through-hole 130-2 and the glass layer 110, as well as the increased contact area between the through-hole 130-2 and the first insulating layer 111, improves the reliability of the through-hole 130-2. When the wall surface of the through-hole h has multiple inner walls with different slopes, defects in the glass layer 110 (such as breakage of the glass layer 110 during processing or microcracks in the glass layer 110) can be prevented. Therefore, process stability can be ensured.

[0047] Other descriptions are substantially the same as those for printed circuit boards 100A and 100B, therefore, no duplicate descriptions will be provided.

[0048] According to the foregoing example embodiments, a printed circuit board that facilitates warpage control and allows for easy implementation of microcircuits therein can be provided.

[0049] In addition, a printed circuit board that reduces the number of processes and lowers costs can be provided.

[0050] In addition, a printed circuit board can be provided that ensures process stability and in which through-holes can have improved reliability.

[0051] In this disclosure, the term "cover" can include complete coverage and partial coverage, and can also include direct coverage and indirect coverage. Furthermore, the term "fill" can include complete filling and substantial filling, and can include, for example, the presence of gaps or voids. Furthermore, the term "surround" can include not only complete surrounding, but also partial surrounding and substantial surrounding. Furthermore, the term "expose" can include complete exposure and partial exposure, and the term "expose" can indicate that a component is exposed from another component in which it is embedded. For example, the statement "an opening in the resist layer exposes the pads" can mean that an opening in the resist layer exposes the pads from the resist layer, and a surface treatment layer can be applied to the exposed pads.

[0052] In this disclosure, the phrase "disposed in a through portion or through hole" can include a configuration in which an object is completely disposed in a through portion or through hole, or a configuration in which an object partially protrudes to the upper or lower side in cross-section. For example, it can be interpreted more broadly when the component is disposed in a through portion or through hole in a plane.

[0053] In this disclosure, the term "substantially identical" can include process errors, positional deviations, and measurement errors that occur in the manufacturing process. For example, the concept of substantially identical linewidths, distances, thicknesses, and heights can include situations where elements are numerically identical, or situations where elements may have similar values. In one or more aspects, the terms "substantially," "approximately," and "roughly" can provide industry-accepted tolerances for their respective items and / or the correlation between items, such as tolerances of ±1%, ±5%, or ±10% of the stated actual values, and other suitable tolerances. Furthermore, the concept of "substantially having a predetermined shape" can include situations where the shape is exactly the same as the predetermined shape, or situations where the shape is similar to the predetermined shape.

[0054] In this disclosure, "the same insulating material" can mean that the materials are exactly the same insulating material, or it can mean that the materials are the same type of insulating material. Therefore, the composition of the insulating materials can be substantially the same, but their specific composition ratios can be slightly different.

[0055] For ease of description, the terms "lower side," "lower part," and "lower surface," etc., can be used to refer to a side, part, or surface formed in the downward direction relative to the cross-section in the drawings, respectively; the terms "upper side," "upper part," and "upper surface," etc., can be used to refer to a side, part, or surface formed in the upward direction, respectively; and the terms "side part" and "side surface," etc., can be used to refer to a part or surface formed in the direction perpendicular to the upper and lower surfaces, respectively. However, these terms are defined for ease of description, and the scope of the exemplary embodiments is not specifically limited by the above terms.

[0056] In the example embodiments, the term "connection" can include not only "direct connection" but also "indirect connection" via adhesive layers, etc. Furthermore, the term "electrical connection" can include both cases where elements are "physically connected" and cases where elements are "not physically connected." Additionally, the terms "first" and "second," etc., can be used to distinguish one element from another and are not limited to the order and / or importance associated with the elements. In some cases, without departing from the scope of the example embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0057] In example embodiments, thickness, width, length, spacing, depth, etc., can be measured using a scanning electron microscope or optical microscope based on a polished or cut cross-section of the printed circuit board. The cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the desired cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section taken along the central axis of the via. In this case, when the value is not constant, it can be determined as the average of the values ​​measured at any five points.

[0058] In the example embodiments, the term "example embodiment" may not refer to the same example embodiment and may be provided to describe and highlight the distinct features of each example embodiment. The example embodiments presented above do not preclude the possibility of combining features with those of other example embodiments. For example, unless otherwise stated, even if a feature described in one example embodiment is not described in other example embodiments, the description may be understood to be relevant to other example embodiments.

[0059] Unless the singular form of an expression has a distinctly different meaning in the context, the singular form of an expression covers the plural form.

[0060] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Glass layer; A first insulating layer covers each of the upper and lower surfaces of the glass layer; A first conductor layer is disposed on the upper surface of the first insulating layer; A second conductor layer is disposed on the lower surface of the first insulating layer; as well as A via, penetrating the region between the first conductor layer and the second conductor layer, wherein a through-hole including a via conductor is provided in the via, and the through-hole connects the first conductor layer and the second conductor layer. The wall surface of the through hole has at least one offset region.

2. The printed circuit board according to claim 1, in, In a cross-section cut along the thickness direction, the width of the through-hole at the upper end connected to the first conductor layer and the width at the lower end connected to the second conductor layer are greater than the width of the through-hole at its central portion in the thickness direction. The central portion of the through hole is located between the upper surface and the lower surface of the glass layer.

3. The printed circuit board according to claim 2, wherein, The at least one offset region is located at substantially the same height relative to the thickness direction as the central portion of the through hole.

4. The printed circuit board according to claim 2, wherein, Each offset zone is located at substantially the same height relative to the thickness direction at the boundary between the upper surface of the glass layer and the first insulating layer or the boundary between the lower surface of the glass layer and the first insulating layer.

5. The printed circuit board according to claim 2, wherein, The wall surface of the through hole has multiple inner walls with different slopes.

6. The printed circuit board according to claim 5, in, On the cross-section of the through-hole cut along the thickness direction, a portion of the wall surface of the through-hole has four inner walls with different slopes, and the portion of the through-hole penetrates the region between the upper surface and the lower surface of the glass layer. The inflection points between the two inner walls on the left side of the cross-section and between the two inner walls on the right side of the cross-section are located at different heights relative to the thickness direction.

7. The printed circuit board according to claim 1, wherein, The first insulating layer also covers the side surface of the glass layer.

8. The printed circuit board according to claim 7, further comprising: The frame has a through section. The glass layer is disposed in at least a portion of the through portion. The first insulating layer also covers the upper and lower surfaces of the frame, and The first insulating layer is disposed in at least a portion of the through portion.

9. The printed circuit board according to claim 1, in, The through-hole includes: a first portion that penetrates the glass layer; a second portion that penetrates the area of ​​the first insulating layer covering the upper surface of the glass layer; and a third portion that penetrates the area of ​​the first insulating layer covering the lower surface of the glass layer.

10. The printed circuit board according to claim 9, in, At least a portion of the via conductor is in contact with the glass layer, and At least another portion of the via conductor is in contact with the first insulating layer.

11. The printed circuit board according to claim 1, in, The glass layer has a through-hole that allows penetration through the glass layer. Wherein, the first insulating layer fills a portion of the via hole, and The through hole includes: a first portion, a region that penetrates the first insulating layer and fills a portion of the passage hole; a second portion, a region that penetrates the first insulating layer and is disposed on the upper side of the passage hole; and a third portion, a region that penetrates the first insulating layer and is disposed on the lower side of the passage hole.

12. The printed circuit board according to claim 11, wherein, The via conductor is in contact with the first insulating layer and spaced apart from the glass layer.

13. The printed circuit board according to claim 1, further comprising: A second insulating layer is disposed on the upper surface of the first insulating layer and covers at least a portion of the first conductor layer; A third insulating layer is disposed on the lower surface of the first insulating layer and covers at least a portion of the second conductor layer; A third conductor layer is disposed on the upper surface of the second insulating layer; A fourth conductor layer is disposed on the lower surface of the third insulating layer; A first connection via penetrates at least a portion of the second insulating layer and connects at least a portion of the first conductor layer and at least a portion of the third conductor layer to each other; as well as The second connection via penetrates at least a portion of the third insulating layer and connects at least a portion of the second conductor layer and at least a portion of the fourth conductor layer to each other.

14. The printed circuit board of claim 13, further comprising: A first passivation layer is disposed on the upper surface of the second insulating layer and has a plurality of first openings, each first opening exposing at least a portion of the third conductor layer; as well as A second passivation layer is disposed on the lower surface of the third insulating layer and has a plurality of second openings, each second opening exposing at least a portion of the fourth conductor layer.

15. A printed circuit board, comprising: Insulating layer; A glass layer is embedded in the insulating layer; A first conductor layer is disposed on the upper surface of the insulating layer; A second conductor layer is disposed on the lower surface of the insulating layer; as well as The through-hole penetrates the insulating layer and the glass layer located between the first conductor layer and the second conductor layer, and connects the first conductor layer and the second conductor layer to each other. The side surface of the through hole has at least one offset region.

16. The printed circuit board of claim 15, further comprising: A frame having at least a portion embedded in the insulating layer and including a through portion in which at least a portion of the glass layer is disposed. The insulating layer is disposed in at least a portion between the frame and the glass layer.

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