Signal trace with discontinuity mitigation of width modulation

Abstract

The invention relates to a signal trace with discontinuity mitigation of width modulation. A signal conductor having one or more length-tuned wiring tortuosity is selectively widened within the tortuosity region to reduce impedance discontinuities caused by trace pitch differences.

Description

Attached Figure Description

[0001] Various embodiments disclosed herein are illustrated by way of example and not limitation in the accompanying drawings, wherein the same reference numerals denote similar elements, and wherein:

[0002] Figure 1 An exemplary implementation of a width-modulated tortuous signal trace in / on one or more layers of a printed circuit board (PCB) is shown;

[0003] Figure 2 An exemplary sequence of operations is shown for manufacturing a PCB with one or more width modulations; and

[0004] Figure 3 Exemplary operations performed within a design automation tool (e.g., software for design automation executed on one or more computing devices) are illustrated as design steps within manufacturing / process to generate a digital representation of a tortuous signal trace with one or more width modulations. Detailed Implementation

[0005] In various embodiments described herein, signal traces with one or more length-tuned wiring zigzags are selectively widened within the zigzag regions to reduce impedance discontinuities caused by differences in trace spacing. In several embodiments, width-modulated trace zigzags are implemented within one of the two paired signal conductors of a differential signal line—that is, zigzag wiring within the signal conductor (true or complementary (positive or negative)) to equalize the originally slightly different wiring distances (different lengths) traversed by that conductor relative to its paired conductor in their respective spans between the two endpoints. Because only one of the two signal conductors is zigzag (i.e., zigzag wiring, serpentine wiring, or other wiring bends that increase distance), the spacing between the paired conductors increases and the mutual impedance decreases (i.e., mutual capacitance and / or mutual inductance decreases) as the zigzag conductor turns away from the non-zigzag conductor, resulting in undesirable impedance discontinuities—discontinuities that become increasingly detrimental as signal rates push deeper into the gigahertz range (e.g., to 26 GHz, 50 GHz, 100 GHz and above). By modulating the trace width of one or two conductors in the region of increased spacing within the bend, the impedance discontinuity is significantly reduced (e.g., by 100%, 200%, 300% or more; in some embodiments, for example, from about 3-4 ohms to less than 1 ohm).

[0006] Figure 1An exemplary embodiment is shown of a width-modulated, zigzag signal trace 101 in / on one or more layers of a printed circuit board 103 (PCB), the signal trace forming a set of differential signal lines extending from electrical contacts of an integrated circuit component (IC or chip) to a terminal 107, which is used, for example, to electrically couple to an electrical connector, enabling the PCB 103 to be removably (electrically) coupled to another circuit board (e.g., motherboard, backplane blade, etc.), signal cable, etc. In one embodiment, the PCB 103 is a paddle card deployed in two or more instances at respective ends of a smart cable, wherein each (or any one or more) instance of the PCB 103 has a host-side connector coupled to the terminal 107 (and thus via the width-modulated signal trace 101 to an IC 105, such as a retimer IC) and a cable-side connector coupled via signal trace 109 (where any one or more or all of the signal traces may include width-modulated zigzags), which is used to engage with signal conductors extending between mating instances of the PCB 103.

[0007] An unfolded view of the differential pair of signal traces (one of the multiple conductor pairs comprising signal trace 101) is shown at 120. In the depicted example, the two paired traces 121 of the differential pair... P and 121 N (For example, defined by a ground conductor) bends towards the upper left of PCB103, causing the outer conductor (121) to bend. P The slightly longer path length on the inner conductor, as shown at 125, is compensated for by a wiring bend that extends the length of the originally shorter inner conductor (relative to the bend radius on the inside) through length tuning or matching. In bends in the opposite direction (e.g., oriented towards the upper right of PCB 103 as shown), conductor 121... P (Its relative to a right turn becomes the inner / inner conductor) can be implemented using zigzag wiring to compensate for its original size compared to conductor 121. N Slightly shorter length.

[0008] Referring to the detailed view 135 of the tortuous region 125, for the purpose of length matching, on signal trace 121 N The out-and-back turns (zigzag, undulating, serpentine wiring, etc.) implemented in the differential signal trace (121) N ,121 P A spatially varying (non-uniform) spacing was created between them, and more specifically, before zigzing back to the nominal trace spacing / distance p1, trace 121 N It deviates from the path and then runs parallel to the paired trace 121 PThe increased spacing (center-to-center distance) p2 between two traces during routing, i.e., in Figure 1 The example repeats a single "leave-return" zigzag twice, but depending on the length matching requirements, it can be implemented in a single instance or more than two instances (i.e., any number of leave-return zigzags). Furthermore, although in Figure 1 The example shows a uniform leave-return zigzag (e.g., both zigzags extend the trace spacing to p2), and the zigzags can be implemented using different spacing extensions (i.e., conductor 121). N One or more bends within the conductor turn away from the conductor than one or more other bends. P (Further). Additionally, although differential conductor pairs are shown, bends within a single-ended signal trace can similarly create uneven spacing between adjacent ground conductors and / or signal traces.

[0009] Referring to the time-domain reflectometer plot at 150, the non-uniform trace spacing caused by wiring bends (in this example, p2 = 15.5 mils, thus 5 mils wider than the nominal trace spacing p1 of 10 mils; "mil" refers to one-thousandth of an inch) results in an increased impedance 151 relative to the impedance 153 along the nominal spacing segment of the trace pair (i.e., at least due to 121 at each leave-return bend). N / 121 P The variation in mutual capacitance / mutual inductance between trace pairs, and therefore the impedance discontinuity, though slight (e.g., 3-4 ohms), becomes increasingly limiting / disruptive at higher signal rates, reducing time and voltage signal margins to limit the upper limit of the signal rate.

[0010] exist Figure 1 In the embodiment, conductor 121 N and 121 P The trace width is widened in the tortuous wiring segments (as shown in detailed view 170) to offset the increased impedance originally caused by the higher trace spacing in those areas, and thus alleviate (reduce, make negligible, or eliminate) the impedance discontinuity along the signal propagation path formed by the differential conductor pairs. In the depicted example, trace 121 is added in the tortuous regions. N and 121 PThe trace width, ranging from 4.75 mils to 5.75 mils (increasing by 1 mil), equalizes the impedance within the tortuous and non-tortuous sections (regions, portions) of the signal trace to within one ohm, as shown in the TDR diagram at 175. Trace width modulation (selectively increasing the trace width or otherwise altering the size of the trace cross-section in high-pitch tortuous regions) substantially reduces impedance discontinuities within the differential conductor pair, in this case reducing 3-4 ohms of impedance discontinuities to 1 ohm or less by a factor of 3 to 4 times or higher. In alternative embodiments, trace width modulation (i.e., increasing the trace width relative to the nominal trace width) can be implemented using traces with single-ended tortuosities relative to the differential signal trace pair or individual component traces, and / or can be implemented with a factor of more than... Figure 1 The example demonstrates implementation at higher or lower amplitudes (e.g., relative to). Figure 1 The 1 mil difference shown increases or decreases the difference between w2 and w1. Similarly, Figure 1 The specific trace spacing / trace width and differential impedance / common-mode impedance (the latter shown within the TDR plot) illustrated are presented for illustrative purposes only, and in alternative implementations, each, any, or all may be different. Furthermore, while traces on a printed circuit board illustrate conductor width modulation for discontinuity mitigation, trace width modulation can be implemented within integrated circuit dies and / or multi-die packages, for example, to mitigate impedance discontinuities on differential or single-ended metal layer wiring, differential or single-ended polysilicon wiring, and / or any other conductive signal paths on or outside the die that may exhibit undesirable impedance discontinuities. In all such cases, one or more zigzag layout units 177—that is, which can be instantiated a variable / specified number of times to define a desired number of out-back zigzags, and thus achieve a desired / specific length adjustment (equalization distance) of zigzags with width-modulated impedance discontinuity mitigation—can be provided as a deliverable product data representation of width-modulated zigzags and applied within a product layout tool / manufacturing process to define / generate a photomask (or other mask or feature definition structure), which can then be used to manufacture a printed circuit board with trace zigzags of specified width modulation.

[0011] Figure 2An exemplary sequence of operations is shown for fabricating a printed circuit board (PCB) with one or more width-modulated zigzags. At 191, a PCB substrate (e.g., a glass-reinforced epoxy laminate such as FR-4, or any feasible PCB substrate) is plated with a conductive material (e.g., copper, aluminum, other metals or metal alloys, or, where appropriate, a non-metallic conductive material). Photoresist or other etch mask material is deposited over the plated substrate (193), and then patterned (195) using one or more photomasks defining at least one length-matched zigzag trace with width modulation (and, in some cases, two paired traces with width modulation in the zigzag region), for example, by exposing the photoresist or other etch mask material to ultraviolet light so that the exposed areas of the photoresist can be washed away, revealing the plated layer according to the pattern. At 197, the plated layer is etched according to the patterned photoresist layer, such that the remaining conductive material forms at least one conductive trace with a length-matched zigzag of width modulation. In the case of differential pairing conductors, patterned photoresist and etching operations can simultaneously achieve both length-matched zigzag traces with width modulation and paired traces with one or more width-modulated segments adjacent to the length-matched zigzags with width modulation.

[0012] Figure 3Exemplary operations performed within a design automation tool (e.g., software for design automation executed on one or more computing devices) are illustrated as design steps within manufacturing / processing to generate a digital representation of a tortuous signal trace with one or more width modulations. As shown, the design automation tool receives printed circuit board design input at 204, such as a Gerber-formatted printed circuit board design specification (i.e., a "Gerber file," including extended Gerber or X-Gerber or X2-Gerber according to RS-274X or RS-274X2) or any other feasible design input data, which describes, for example, but not limited to, one or more printed circuit board images, copper layers, solder mask, legends, drill / via data, etc. When the design input specifies single-ended or differential traces with unoptimized trace length matching (i.e., no zigzag / serpentine routing at 206 and therefore a negative determination at 206) for one or more layers, masks, images, etc., the design tool defines the trace routing at 208 according to the pre-established geometry based on the design input (e.g., Gerber trace geometry). In contrast, when the design input specifies automatic routing of paired traces with optimized length matching differential signal lines (a positive determination at 206), as shown at 210, the design tool either (i) prompts the user / operator of the design tool to provide parameter information that at least specifies the corresponding endpoints of the paired traces and the nominal trace width, or (ii) obtains the parameter information from the design (e.g., from an extension of the design input file). At 212, based at least in part on the parameter information, an automated design tool determines the corresponding wiring for the mating traces and the difference between the lengths of these wirings (212), modifies the shorter of the mating wirings to include one or more width-modulated zigzag patterns (214), which both nominally balance the lengths of the mating wirings and produce estimated, simulated, and / or actual impedance discontinuities within predetermined tolerances (e.g., less than a target maximum value, which may be specified by the user, for example, as part of the parameter information). In one embodiment, as shown at 215, the automated design tool achieves an impedance discontinuity target (i.e., impedance discontinuity less than a target) by determining, based on the parameter information provided by the user, the impedance discontinuity to be caused by each of the one or more zigzags, and an increase in trace width (relative to the nominal trace width, which, when applied within one or more segments (or the whole) adjacent to the zigzags of the mating conductors, will reduce the impedance discontinuity to at least below the target maximum value).For example, in several implementations, parameter information may specify both the nominal trace width and the maximum trace width (and the extended spacing at bends), where design automation tools extend the trace width of one or more segments of the mating conductors (up to the user-specified maximum width) as needed (in bends) to achieve impedance discontinuities within the expected / estimated tolerances. For example, in some applications, design automation tools may determine longer or shorter traces for the widened trace regions as needed (and widen the trace width along all or part of these traces, exceeding the nominal width up to the specified maximum) to achieve simulated impedance discontinuities below the target maximum value. Furthermore, while the routing of a pair of mating traces is explained, design tools can automatically (or assist in determining) the layout for multiple such trace pairs (and / or single-ended traces, etc.) in a unified set of calculations / operations, taking into account, for example, the number of traces and the available board area (including multilayer area) for such routing.

[0013] After determining the layout of the zigzags for width modulation (commonly in operations 210, 212, 214), the automated design tool outputs a digital representation of the paired traces (i.e., zigzags with one or more width modulations) for use in generating one or more photomasks and / or other physical representations corresponding to the paired traces (216), which can then be used to manufacture a printed circuit board having the paired traces (zigzags with one or more width modulations) disposed on one or more of its layers.

[0014] In the foregoing description and figures, specific terms and symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some cases, terms and symbols may imply specific details not required for the practice of those embodiments. For example, various trace spacings, trace dimensions, impedances, wiring layouts, circuit implementations, etc., are provided for illustrative purposes only and are any feasible alternatives that can be implemented in all cases. Regardless of whether they are shown or described, signals and signal lines may be single-ended or differential. The term “coupled” is used herein to refer to direct connections as well as connections via one or more intermediate circuits or structures. The terms “exemplary” and “implementation” are used to express examples and not preferences or requirements. Furthermore, the terms “may” and “may” are used interchangeably to indicate optional (permitted) topics. The omission of any term should not be construed as implying a requirement for a given feature or technique.

[0015] Various modifications and changes may be made to the embodiments presented herein without departing from the broader spirit and scope of this disclosure. For example, a feature or aspect of any embodiment may be applied in combination with or in place of its paired feature or aspect in any other embodiment. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

Claims

1. An electrical device, the electrical device comprising: First signal conductor; A second signal conductor, which is wired along the first signal conductor at a nominal spacing, and has the following characteristics: Nominal cross-sectional dimensions; as well as One or more bends, in which the second signal conductor (i) is wired away from the first signal conductor and then returns toward the first signal conductor, such that a corresponding spacing different from the nominal spacing is achieved in each of the bends in one or more bends, and (ii) has a cross-sectional dimension that is changed relative to the nominal cross-sectional dimension to mitigate impedance discontinuities caused by the corresponding spacing different from the nominal spacing.

2. The electrical device according to claim 1, further comprising a printed circuit board, wherein the first signal conductor and the second signal conductor comprise a first signal trace and a second signal trace disposed on one or more substrate layers of the printed circuit board.

3. The electrical device of claim 2, further comprising an integrated circuit device disposed on the printed circuit board and having one or more integrated circuit dies, wherein the first signal trace and the second signal trace are electrically coupled to corresponding electrical contacts of the one or more integrated circuit dies.

4. The electrical device according to claim 1, wherein the first signal conductor and the second signal conductor are sandwiched between a grounding conductor.

5. The electrical device according to claim 1, wherein, The first signal conductor and the second signal conductor are wired between corresponding first and second pairs of endpoints such that, except for the one or more bends in the second signal conductor, the wiring of the first signal conductor between the first pairs of endpoints will be longer than the wiring of the second signal conductor between the second pairs of endpoints.

6. The electrical device according to claim 1, wherein, The one or more bends in the second signal conductor nominally make the originally different wiring lengths of the first and second signal conductors equal.

7. The electrical device of claim 1, wherein at least one of the one or more bend regions comprises wiring of the second signal conductor that departs from the first signal conductor at a first distance, is nominally parallel to the first signal conductor at the first distance, and then returns toward the first signal conductor, and wherein the sum of the first distance and the nominal spacing constitutes a corresponding spacing different from the first spacing.

8. The electrical device of claim 1, wherein the first signal conductor and the second signal conductor comprise a first signal trace and a second signal trace, and wherein the cross-sectional dimension varying relative to the nominal cross-sectional dimension includes the trace width.

9. The electrical device according to claim 1, wherein, The cross-sectional dimension that is changed relative to the nominal cross-sectional dimension to mitigate impedance discontinuities caused by a corresponding spacing that differs from the nominal spacing includes a cross-sectional dimension that is sufficiently changed relative to the nominal cross-sectional dimension to reduce the impedance discontinuities by at least two times.

10. The electrical device according to claim 1, wherein, The cross-sectional dimension that is changed relative to the nominal cross-sectional dimension to mitigate impedance discontinuities caused by a corresponding spacing that differs from the nominal spacing includes a cross-sectional dimension that is sufficiently changed relative to the nominal cross-sectional dimension to reduce the impedance discontinuities to less than 1 ohm.

11. A method for generating a digital representation of the physical layout of signal traces on a printed circuit board, performed within a computing device, the method comprising: The computing device receives information on a specified printed circuit board layout, the information including parameter information of the corresponding endpoints of a pair of first and second signal traces of a specified differential signal line; The corresponding wiring for the first signal trace and the second signal trace, and the non-zero difference between the lengths of the first signal trace and the second signal trace when arranged along the corresponding wiring, are determined at least in part based on the parameter information. as well as ； The routing of the first signal trace is adjusted to include one or more bends, in which the first signal trace (i) turns away from the second signal conductor and then returns toward the second signal conductor, such that in each of the bends, a corresponding spacing different from the nominal spacing between the first and second signal traces is achieved, and (ii) a cross-sectional dimension that is changed relative to the nominal cross-sectional dimension of the first signal trace, to mitigate impedance discontinuities caused by the corresponding spacing different from the nominal spacing.

12. The method of claim 11, wherein receiving information specifying the printed circuit board layout includes receiving an electronic document specifying the printed circuit board layout.

13. The method of claim 11, wherein receiving the electronic file includes receiving a Gerber file.

14. The method according to claim 11, wherein, Receiving the information specifying the printed circuit board layout, including the parameter information, includes: receiving (i) an electronic Gerber file specifying at least a portion of the printed circuit board layout, and (ii) user input including the parameter information specifying the corresponding endpoints of the paired first signal trace and the second signal trace.

15. The method of claim 11, wherein determining the corresponding wiring for the first signal trace and the second signal trace comprises determining the corresponding wiring for the first signal trace and the second signal trace along one or more substrate layers of the printed circuit board.

16. The method of claim 15, wherein determining the corresponding wiring for the first signal trace and the second signal trace along one or more substrate layers of the printed circuit board comprises determining the corresponding wiring for the first signal trace and the second signal trace extending from corresponding electrical contacts of an integrated circuit assembly to be mounted to the printed circuit board.

17. The method of claim 11, wherein determining the corresponding wiring for the first signal trace and the second signal trace comprises determining the corresponding wiring for the first signal trace and the second signal trace for routing between ground conductors.

18. The method according to claim 11, wherein, Determining the routing for the first signal trace and the second signal trace includes determining the routing for the first signal trace and the second signal trace to be routed between respective first pair of endpoints and second pair of endpoints, such that, except for the one or more tortuous regions in the first signal trace, the routing of the first signal trace between the first pair of endpoints will be shorter than the routing of the second signal trace between the second pair of endpoints.

19. The method according to claim 11, wherein, The cross-sectional dimension that is changed relative to the nominal cross-sectional dimension to mitigate impedance discontinuities caused by a corresponding spacing that differs from the nominal spacing includes a cross-sectional dimension that is sufficiently changed relative to the nominal cross-sectional dimension to reduce the impedance discontinuities by at least two times.

20. The method according to claim 11, wherein, The cross-sectional dimension that is changed relative to the nominal cross-sectional dimension to mitigate impedance discontinuities caused by a corresponding spacing that differs from the nominal spacing includes a cross-sectional dimension that is sufficiently changed relative to the nominal cross-sectional dimension to reduce the impedance discontinuities to less than 1 ohm.

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