Method of forming memory device

Abstract

Some embodiments of the present disclosure provide a method of forming a memory device, including forming a photoresist on a dielectric structure, forming a trench in the dielectric structure through the photoresist to expose a gate electrode embedded in the dielectric structure, removing the photoresist by an ashing gas, and removing the gate electrode through the photoresist. Wherein the ashing gas has an oxidizing ability to oxidize the surface of the silicon wafer into a thinner oxide layer. The method further includes forming a first spacer nitride as a liner of the trench and covering the gate electrode, and forming a metal layer filling the trench. The oxidizing ability of the ashing gas may reduce the likelihood that the gate electrode forms an oxide, and thus contact resistance between the gate structure and the contact may be reduced, thereby improving performance of the memory device.

Description

Technical Field

[0001] This disclosure relates to a method for forming a memory device. Background Technology

[0002] For example, memory cells in dynamic random access memory (DRAM) devices are continuously being shrunk in size to integrate more memory cells in a given area. Such size reduction processes can present challenges during memory cell formation. For instance, as critical size shrinks, titanium nitride (TiN) exhibits lower line resistance than tungsten / titanium nitride (W / TiN) stacks, making TiN suitable for word lines in memory cells. However, TiN is prone to oxidation, leading to high contact resistance between word lines and metal contacts. Summary of the Invention

[0003] Embodiments of this disclosure provide a method for forming a memory device to effectively solve the aforementioned problems.

[0004] According to one embodiment of the present disclosure, a method of forming a memory device includes forming a photoresist on a dielectric structure, forming a trench in the dielectric structure through the photoresist to expose a gate electrode embedded in the dielectric structure, and removing the photoresist by means of an ashing gas, wherein the ashing gas has the function of oxidizing the surface of a silicon wafer to a thickness less than [a certain value]. The method also includes forming a first spacer nitride as a liner for the trench and covering the gate electrode, and forming a metal layer to fill the trench.

[0005] In some embodiments, the ashing gas comprises a first proportion of hydrogen and a second proportion of nitrogen, wherein the second proportion is greater than or equal to the first proportion.

[0006] In some embodiments, the ashing gas comprises 4% to 50% hydrogen and 50% to 96% nitrogen.

[0007] In some embodiments, the ashing gas comprises a first proportion of ammonia and a second proportion of oxygen, wherein the second proportion is less than or equal to 60%.

[0008] In some embodiments, the ashing gas comprises 40% to 50% ammonia and 50% to 60% oxygen.

[0009] In some embodiments, the gate electrode is formed of a metal nitride material, and the oxidizing power of the ashing gas is weaker than that of the oxidizable metal nitride material.

[0010] In some embodiments, the top surface of the gate electrode is exposed after the trench is formed, and the first spacer nitride is in direct contact with the top surface of the gate electrode after the first spacer nitride is formed.

[0011] In some embodiments, the method further includes etching the first spacer nitride to expose the gate electrode after forming the first spacer nitride, and forming a second spacer nitride along the first spacer nitride and covering the gate electrode before forming the metal layer.

[0012] In some embodiments, the dielectric structure includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and the first dielectric layer and the second dielectric layer comprise different materials.

[0013] In some embodiments, the second spacer nitride separates the metal layer from the first spacer nitride.

[0014] In some embodiments, the second spacer nitride and the gate electrode comprise the same material.

[0015] According to one embodiment of this disclosure, a method of forming a memory device includes providing a gate structure embedded in a dielectric structure, wherein the gate structure includes a gate electrode and a gate dielectric surrounding the gate electrode. The method further includes forming a photoresist on the dielectric structure and etching trenches through the photoresist in the dielectric structure to expose a top surface of the gate electrode, wherein at least a portion of the top surface of the gate electrode is oxidized into an oxide portion. The method further includes removing the photoresist with an ashing gas, wherein the ashing gas reduces the oxide portion of the gate electrode. The method further includes forming contacts in the trenches that contact the gate structure.

[0016] In some implementations, the oxygen content of the ashing gas is less than or equal to 60%.

[0017] In some implementations, the ashing gas is oxygen-free.

[0018] In some implementations, the composition of the ashing gas differs from that of the etching gas used in the etching trenches.

[0019] In some implementations, after the photoresist is removed, the top surface of the gate electrode is free of oxide portions, allowing the contacts to directly contact the top surface of the gate electrode.

[0020] In some implementations, after etching the trench, the top surface of the gate electrode is fully exposed.

[0021] In some implementations, the critical size of the gate structure is less than or equal to 18 nanometers.

[0022] In some implementations, the gate electrode is substantially composed of titanium nitride.

[0023] In some implementations, the gate structure serves as a buried word line.

[0024] According to the above, in some embodiments of the method for forming a memory device disclosed herein, the photoresist used to form trenches on the gate structure is removed by an ashing gas, wherein the ashing gas can prevent oxidation of the gate electrode and even reduce the oxide portion of the gate electrode. Therefore, the contact resistance between the gate structure and the contacts can be reduced, thereby improving the performance of the memory device. Attached Figure Description

[0025] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0026] Figure 1 A flowchart illustrating a method for forming a memory device according to some embodiments of the present disclosure is provided.

[0027] Figure 2 , Figure 3 , Figure 4A , Figure 4B and Figure 5 A cross-sectional view illustrating an intermediate stage in forming a memory device according to some embodiments of the present disclosure is provided.

[0028] Figures 6A to 6C A cross-sectional view illustrating an intermediate stage in forming a memory device according to one embodiment of the present disclosure is shown.

[0029] Figures 7A to 7E A cross-sectional view illustrating an intermediate stage in forming a memory device according to another embodiment of the present disclosure is shown. Detailed Implementation

[0030] To achieve the different features of the mentioned subject matter, the following disclosure provides many different implementations or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or above a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0031] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0032] This disclosure provides a method for forming a memory device, comprising removing photoresist that forms trenches on a gate structure using an ashing gas. The ashing gas has the effect of oxidizing the surface of a silicon wafer to a thickness less than [missing information]. The oxidizing power of the oxide layer allows the ashing gas to avoid oxidizing the gate electrode of the gate structure, and even reduce the oxide portion of the gate electrode. Therefore, the contact resistance between the gate structure and the contacts can be reduced, thereby improving the performance of the memory device.

[0033] According to some embodiments of this disclosure Figure 1 A flowchart illustrating the method S100 for forming a memory device is provided. Figure 1 As shown, method S100 includes steps S110 to S150. Figures 2 to 7E To illustrate the cross-sectional view of the intermediate stages in forming the memory device, details of method S100 will be combined. Figures 2 to 7E Further description.

[0034] It should be noted that when Figures 2 to 7E When illustrating or depicting a series of steps in an implementation, the order of these steps should not be limited unless otherwise specified. For example, some steps may be performed in a different order than those described in the implementation, some steps may be performed simultaneously, some steps may be omitted, and / or some steps may be repeated. Additionally, extra steps may be performed before, during, or after the illustrated steps to complete the memory device.

[0035] refer to Figure 1 and Figure 2 In step S110 of method S100, a gate structure 110 is provided in dielectric structure 120. Dielectric structure 120 can serve as a substrate layer of a memory device, wherein the gate structure 110 is disposed in the active region of the memory device. Specifically, gate structure 110 includes a gate electrode 112 and a gate dielectric 114 surrounding the gate electrode 112. The dielectric material of dielectric structure 120 covers and surrounds the gate electrode 112 and the gate dielectric 114, such that gate structure 110 is embedded in dielectric structure 120. In some embodiments, gate structure 110 can serve as a buried word line of the memory device.

[0036] In some embodiments, as the critical size of the gate structure 110 shrinks to the nanoscale, the gate electrode 112 can be formed of a metal nitride material to reduce line resistance. For example, when the critical size is less than 18 nanometers, all-titanium nitride (TiN) material exhibits lower line resistance than tungsten / titanium nitride (W / TiN) stacks, making TiN more suitable for buried gate electrode 112. In some preferred embodiments, when the critical size of the gate structure 110 is less than or equal to 18 nanometers, the gate electrode 112 can be substantially composed of TiN.

[0037] In some embodiments, the dielectric structure 120 may be formed of multiple dielectric materials. For example... Figure 2 As shown, the dielectric structure 120 may include a first dielectric layer 122 and a second dielectric layer 124 on the first dielectric layer 122, wherein the first dielectric layer 122 and the second dielectric layer 124 comprise different materials. For example, the first dielectric layer 122 may be formed of an oxide, such as silicon oxide, while the second dielectric layer 124 may be formed of a nitride, such as silicon nitride.

[0038] refer to Figure 1 and Figure 3 In step S120 of method S100, a photoresist 130 with an opening 132 is formed on the dielectric structure 120. Specifically, the photoresist 130 can first be formed above the top surface of the dielectric structure 120 using a spin-coating technique. Next, the photoresist 130 can be patterned using an acceptable photolithography technique to form an opening 132 exposing the top surface of the dielectric structure 120. The location of the opening 132 corresponds to a trench subsequently formed to expose the gate structure 110, for example... Figure 4A The trench 140 in the middle. In other words, the projection of the opening 132 in the Z-axis direction at least partially overlaps with the gate structure 110.

[0039] refer to Figure 1 and Figure 4A In step S130 of method S100, a trench 140 is formed in the dielectric structure 120 to expose the gate structure 110. Specifically, an etching process, such as dry etching, can be performed through the opening 132 of the photoresist 130, and the etching process is performed into the dielectric structure 120 to form the trench 140. The etching process can stop at the top surface of the gate structure 110, such that the gate structure 110 remains substantially unetched. After the etching process, the trench 140 exposes at least the gate electrode 112 of the gate structure 110. In some embodiments where the gate electrode 112 is a major part of the top surface of the gate structure 110, such as Figure 4AAs shown, trench 140 can fully expose the top surface of gate electrode 112. Trench 140 can also expose the gate dielectric 114 surrounding gate electrode 112.

[0040] refer to Figure 1 and Figure 5 In step S140 of method S100, the photoresist 130 is removed by ashing gas 150. Since the trench 140 exposed during photoresist removal exposes the gate electrode 112, the ashing gas 150 may also contact the gate electrode 112. As described above, the gate electrode 112 can be formed of a low-line-resistance material, such as TiN or other metal nitride materials, to reduce the resistance of the gate structure 110. However, the gate electrode 112 formed of a metal nitride material may be easily oxidized when exposed to the external environment. If the gate electrode 112 undergoes undesirable oxidation, the contact resistance between the gate electrode 112 and subsequently formed elements (e.g., contacts) may increase. Therefore, the composition of the ashing gas 150 needs careful consideration.

[0041] In some embodiments, the composition of the ashing gas 150 may differ from that of the etching gas in the etching trench 140 to prevent oxidation of the gate electrode 112. For example, the ashing gas 150 may have a weak oxidizing ability to prevent oxidation of the gate electrode 112. Specifically, the ashing gas 150 may have the ability to oxidize the surface of the silicon wafer to a thickness less than [a certain value]. The oxidation capability of the oxide layer. If the ashing gas 150 can oxidize the surface of the silicon wafer to a thickness equal to or greater than... The ashing gas 150 may significantly oxidize the metal nitride material of the gate electrode 112. In other words, the ashing gas 150 will not oxidize the silicon wafer surface to a thickness equal to or greater than [a certain value]. When the oxide layer is formed, the oxidation ability of the ashing gas 150 can be weaker than that of the oxide gate electrode 112.

[0042] In some embodiments, the ashing gas 150 may have reducing capabilities to reduce the proportion of oxides in the gate electrode 112, thus ensuring that the top surface of the gate electrode 112 is free of oxides. For example... Figure 4B As shown, once the trench 140 exposes the gate electrode 112, the gate electrode 112 may be subject to undesirable oxidation. For example, before the photoresist 130 is ashed, a portion of the top surface of the gate electrode 112 may be oxidized into an oxide portion 116. Because the ashing gas 150 has reducing capabilities, the ashing gas 150 contacting the gate electrode 112 during the ashing process can reduce the oxide portion 116 of the gate electrode 112. Therefore, after the photoresist 130 is removed, the top surface of the gate electrode 112 may not have an oxide portion 116, as... Figure 5 As shown in the image.

[0043] In some embodiments where the ashing gas includes oxygen, the oxygen content of the ashing gas 150 may be less than or equal to 60% to reduce the oxidizing capacity of the ashing gas 150 and increase its reducing capacity. If the oxygen content of the ashing gas 150 is greater than 60%, the metal nitride material of the gate electrode 112 may be easily oxidized. For example, the ashing gas 150 may include a first proportion of ammonia (NH3) and a second proportion of oxygen (O2). The sum of the first and second proportions is equal to 100%, wherein the second proportion is less than or equal to 60%. In some embodiments, the ashing gas 150 may include 40% to 50% NH3 and 50% to 60% O2, such as 40% NH3 and 60% O2, 45% NH3 and 55% O2, or 50% NH3 and 50% O2.

[0044] In some other embodiments, the ashing gas 150 may be oxygen-free to reduce its oxidizing capacity and increase its reducing capacity. For example, the ashing gas 150 may include a first proportion of hydrogen (H2) and a second proportion of nitrogen (N2), wherein the sum of the first and second proportions is equal to 100%. The second proportion may be higher than or equal to the first proportion, thus facilitating control of the photoresist ashing rate and reducing the risk of oxidation of the gate material. In some embodiments, the ashing gas 150 may include 4% to 50% H2 and 50% to 96% N2, for example, 50% H2 and 50% N2, 40% H2 and 60% N2, 30% H2 and 70% N2, 20% H2 and 80% N2, 10% H2 and 90% N2, or 5% H2 and 95% N2.

[0045] Figures 6A to 6C To illustrate according to one embodiment Figure 1 A cross-sectional view of step S150 of method S100, wherein a contact 180 is formed in a trench 140 to contact the gate structure 110. (See reference...) Figure 6A A first spacer nitride 160 is formed to serve as a liner for the trench 140 and to cover the gate electrode 112. Specifically, the first spacer nitride 160 can be conformally formed on the sidewalls of the trench 140, the bottom surface of the trench 140, and the top surface of the dielectric structure 120 by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). After the first spacer nitride 160 is formed, a portion of the trench 140 remains above the first spacer nitride 160, and the first spacer nitride 160 directly contacts the top surface of the gate electrode 112.

[0046] refer to Figure 6B A metal layer 170 is formed to fill the trench 140. Specifically, the metal layer 170 can be formed in the trench 140 and above the dielectric structure 120 using deposition, electroplating, or other suitable techniques. The metal layer 170 is in direct contact with the first spacer nitride 160 and is separated from the gate structure 110 and the dielectric structure 120. As the first spacer nitride 160 improves the gap-filling capability of the metal layer 170, the trench 140 can be filled by the metal layer 170. In some embodiments, the metal layer 170 can be formed of tungsten (W).

[0047] refer to Figure 6C The first spacer nitride 160 and the metal layer 170 are planarized to form the contact 180 of the memory device 100a. Specifically, a planarization process is performed on the first spacer nitride 160 and the metal layer 170 to expose the top surface of the dielectric structure 120. After the planarization process, the top surfaces of the dielectric structure 120, the first spacer nitride 160, and the metal layer 170 can be substantially flush with each other. The remaining portions of the first spacer nitride 160 and the metal layer 170 form the contact 180 electrically connected to the gate structure 110, such that the contact 180 serves as the gate contact of the memory device 100a. In some embodiments, the contact 180 can directly contact the gate structure 110, particularly the gate electrode 112.

[0048] Figures 7A to 7E To illustrate according to another embodiment Figure 1 A cross-sectional view at step S150 of method S100. (Refer to...) Figure 7A A first spacer nitride 160 is formed to serve as a liner for the trench 140 and to cover the gate electrode 112. Specifically, the first spacer nitride 160 may be conformally formed on the sidewalls of the trench 140, the bottom surface of the trench 140, and the top surface of the dielectric structure 120. After the first spacer nitride 160 is formed, a portion of the trench 140 remains above the first spacer nitride 160, and the first spacer nitride 160 directly contacts the top surface of the gate electrode 112.

[0049] refer to Figure 7B The first spacer nitride 160 is etched to expose the gate electrode 112. Specifically, an etching process, such as a dry etching process, removes the horizontal portion of the first spacer nitride 160 to expose the top surface of the gate electrode 112. After the etching process is complete, the vertical portion of the first spacer nitride 160 may remain on the sidewalls of the trench 140. In some embodiments, the first spacer nitride 160 on the top surface of the dielectric structure 120 may also be removed after the etching process is complete.

[0050] refer to Figure 7CA second spacer nitride 162 is formed along the first spacer nitride 160 and covering the gate electrode 112. Specifically, the second spacer nitride 162 can be conformally formed on the sidewalls of the first spacer nitride 160, the top surface of the first spacer nitride 160, the top surface of the gate electrode 112, and the top surface of the dielectric structure 120 by, for example, chemical vapor deposition or atomic layer deposition. After the second spacer nitride 162 is formed, a portion of the trench 140 remains above the second spacer nitride 162, and the second spacer nitride 162 directly contacts the top surface of the gate electrode 112.

[0051] In some embodiments, the second spacer nitride 162 and the gate electrode 112 may comprise the same metal nitride material, while the metal nitride material of the second spacer nitride 162 may be different from the nitride material of the first spacer nitride 160. For example, the first spacer nitride 160 may be formed of a dielectric nitride material such as SiN, while the second spacer nitride 162 may be formed of a conductive metal nitride material such as TiN.

[0052] refer to Figure 7D A metal layer 170 is formed to fill the trench 140. Specifically, the metal layer 170 can be formed in the trench 140 and above the dielectric structure 120 using deposition, electroplating, or other suitable techniques. The metal layer 170 is in direct contact with the second spacer nitride 162 and is separated from the gate structure 110, the first spacer nitride 160, and the dielectric structure 120. As the first spacer nitride 160 and the second spacer nitride 162 improve the gap-filling capability and adhesion of the metal layer 170 during its formation, the trench 140 can be filled by the metal layer 170.

[0053] refer to Figure 7E The second spacer nitride 162 and the metal layer 170 are planarized to form the contact 180 of the memory device 100b. Specifically, a planarization process is performed on the second spacer nitride 162 and the metal layer 170 to expose the top surface of the dielectric structure 120. After the planarization process, the top surfaces of the dielectric structure 120, the first spacer nitride 160, the second spacer nitride 162, and the metal layer 170 can be substantially flush with each other. The remaining portions of the first spacer nitride 160, the second spacer nitride 162, and the metal layer 170 form the contact 180 electrically connected to the gate structure 110, thus the contact 180 serves as the gate contact of the memory device 100b. In some embodiments, the contact 180 can directly contact the gate structure 110, particularly the gate electrode 112.

[0054] In the following sections, various measurements and evaluations will be performed on the memory device of this disclosure to specifically describe the advantages of this disclosure. First, according to Figure 1 Method S100 and Figures 2 to 5 , Figures 7A to 7E The steps described above form the memory devices of the comparative examples and embodiments. The gate electrodes of each memory device are substantially composed of TiN. The ashing gas compositions of the comparative examples and embodiments are shown in Table 1. Other materials and parameters remain the same between the comparative examples and embodiments, as described above.

[0055] Next, the contact resistance between the gate electrode and the contact of the memory devices in each comparative example and embodiment was measured using a four-point probe wafer acceptance test (WAT). The oxide distribution between the gate electrode and the contact was measured using an energy dispersive X-ray (EDX) spectrometer. A higher EDX oxide signal indicates more oxide present between the gate electrode and the contact. The results for each comparative example and embodiment are shown in Table 1.

[0056] Table 1

[0057] Ashing gas Contact resistance (Ω) EDX oxide signal Comparative example <![CDATA[90%O2 + 10%N2H2]]> 900 high Example 1 <![CDATA[40%NH3 + 60%O2]]> 91.61 Low Example 2 <![CDATA[50%H2 + 50%N2]]> 65.47 Low Example 3 <![CDATA[4%H2 + 96%N2]]> 74.37 Low

[0058] As shown in Table 1, the contact resistance of all embodiments is lower than that of the comparative example. Furthermore, the EDX oxide signal of all embodiments is lower than that of the comparative example. These results indicate that the ashing gas composition of the embodiments can reduce the oxide formed between the gate electrode and the contact, thus reducing the contact resistance between the gate electrode and the contact.

[0059] According to the above embodiments, the method for forming a memory device disclosed herein includes removing photoresist by means of an ashing gas, wherein the ashing gas contacts the gate structure during the removal process. Because the ashing gas has the effect of oxidizing the surface of the silicon wafer to a thickness less than... The ashing gas has limited oxidation capacity, thus preventing the gate electrode of the gate structure from oxidizing, thereby reducing the likelihood of oxide portions forming on the gate electrode. The ashing gas also reduces the undesirable formation of oxide portions on the gate electrode. Therefore, the contact resistance between the gate structure and the contacts can be reduced, thereby improving the performance of the memory device.

[0060] The foregoing outlines some features of the embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0061] [Symbol Explanation]

[0062] 100a, 100b: Memory devices

[0063] 110: Gate structure

[0064] 112: Gate electrode

[0065] 114: Gate Dielectric

[0066] 116: Oxide section

[0067] 120: Dielectric structure

[0068] 122: First dielectric layer

[0069] 124: Second dielectric layer

[0070] 130: Optical Obscuration

[0071] 132: Opening

[0072] 140: Trench

[0073] 150: Ashing gas

[0074] 160: First spacer nitride

[0075] 162: Second spacer nitride

[0076] 170: Metal layer

[0077] 180: Contact element

[0078] S100: Method

[0079] S110, S120, S130, S140, S150: Steps

[0080] X, Y, Z: Axes.

Claims

1. A method for forming a memory device, characterized in that, include: Photoresist is formed on a dielectric structure; Trenches are formed in the dielectric structure through the photoresist to expose the gate electrode embedded in the dielectric structure; The photoresist is removed by an ashing gas, wherein the ashing gas has the function of oxidizing the surface of the silicon wafer to a thickness less than [a certain value]. The oxidation capacity of the oxide layer; A first spacer nitride is formed as a liner for the trench and covers the gate electrode; as well as A metal layer is formed to fill the trench.

2. The method according to claim 1, wherein the ashing gas comprises a first proportion of hydrogen and a second proportion of nitrogen, and the second proportion is higher than or equal to the first proportion.

3. The method according to claim 1, wherein the ashing gas comprises 4% to 50% hydrogen and 50% to 96% nitrogen.

4. The method of claim 1, wherein the ashing gas comprises a first proportion of ammonia and a second proportion of oxygen, and the second proportion is less than or equal to 60%.

5. The method of claim 1, wherein the ashing gas comprises 40% to 50% ammonia and 50% to 60% oxygen.

6. The method of claim 1, wherein the gate electrode is formed of a metal nitride material, and wherein the oxidizing power of the ashing gas is weaker than the oxidizing power capable of oxidizing the metal nitride material.

7. The method of claim 1, wherein the top surface of the gate electrode is exposed after the trench is formed, and wherein the first spacer nitride is in direct contact with the top surface of the gate electrode after the first spacer nitride is formed.

8. The method according to claim 1, wherein, Further includes: After forming the first spacer nitride, the first spacer nitride is etched to expose the gate electrode; and Before forming the metal layer, a second spacer nitride is formed along the first spacer nitride and covering the gate electrode.

9. The method of claim 8, wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer on the first dielectric layer, and the first dielectric layer and the second dielectric layer comprise different materials.

10. The method of claim 8, wherein the second spacer nitride separates the metal layer from the first spacer nitride.

11. The method of claim 8, wherein the second spacer nitride and the gate electrode comprise the same material.

12. A method for forming a memory device, characterized in that, include: A gate structure embedded in a dielectric structure is provided, wherein the gate structure includes a gate electrode and a gate dielectric surrounding the gate electrode; Photoresist is formed on this dielectric structure; The top surface of the gate electrode is exposed by etching trenches through the photoresist in the dielectric structure, wherein at least a portion of the top surface of the gate electrode is oxidized into an oxide portion. The photoresist is removed by an ashing gas, wherein the ashing gas reduces the oxide portion of the gate electrode; and Contacts that contact the gate structure are formed in the trench.

13. The method of claim 12, wherein the oxygen content of the ashing gas is less than or equal to 60%.

14. The method of claim 12, wherein the ashing gas is oxygen-free.

15. The method of claim 12, wherein the composition of the ashing gas is different from the composition of the etching gas used to etch the trench.

16. The method of claim 12, wherein after the photoresist is removed, the top surface of the gate electrode is free of the oxide portion, such that the contact directly contacts the top surface of the gate electrode.

17. The method of claim 12, wherein after etching the trench, the trench fully exposes the top surface of the gate electrode.

18. The method of claim 12, wherein the critical dimension of the gate structure is less than or equal to 18 nanometers.

19. The method of claim 12, wherein the gate electrode is substantially composed of titanium nitride.

20. The method of claim 12, wherein the gate structure serves as a buried word line.

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