Semiconductor memory device

Abstract

The embodiment of the invention provides a semiconductor memory device capable of properly operating. A semiconductor memory device according to an embodiment includes: a plurality of conductive layers (110) stacked in a stacking direction (Z) and extending in a first direction (X); a first semiconductor pillar (120) facing the plurality of conductive layers; a second semiconductor pillar (120) opposite to the plurality of conductive layers, the position of the second semiconductor pillar being different from that of the first semiconductor pillar in the second direction (Y); contact electrodes (Ch) respectively connected to end regions (124) of the first semiconductor pillar and the second semiconductor pillar in the lamination direction; and an insulating member (SHE) that is provided between the first semiconductor pillar and the second semiconductor pillar so as to overlap with a portion of the first semiconductor pillar and a portion of the second semiconductor pillar when viewed from the lamination direction, and that breaks a portion of the conductive layer in the second direction. The width (YR1) of the insulating member in the second direction at a position corresponding to the lamination direction of the first conductive layer (110 (SGD)) is larger than the width (YR2) of the insulating member in the second direction at a position corresponding to the lamination direction of the end regions of the first and second semiconductor pillars.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Technology

[0002] A known semiconductor memory device includes a plurality of conductive layers stacked in a stacking direction, semiconductor pillars extending in the stacking direction and facing the plurality of conductive layers, and a gate insulating film disposed between the plurality of conductive layers and the semiconductor pillars. The gate insulating film includes, for example, a charge accumulation film such as silicon nitride (SiN). Summary of the Invention

[0003] The problem to be solved by the present invention is to provide a semiconductor memory device that can operate properly.

[0004] A semiconductor memory device according to one embodiment includes: a plurality of conductive layers deposited in a stacking direction and extending in a first direction intersecting the stacking direction; a first semiconductor pillar extending in the stacking direction and facing the plurality of conductive layers, with a first end region on one side of the stacking direction containing impurities; a first gate insulating film disposed between the plurality of conductive layers and the first semiconductor pillar; a first contact electrode connected to the first end region; a second semiconductor pillar positioned differently from the first semiconductor pillar in a second direction intersecting the stacking direction and the first direction, extending in the stacking direction and facing the plurality of conductive layers, with a second end region on one side of the stacking direction containing impurities; a second gate insulating film disposed between the plurality of conductive layers and the second semiconductor pillar; a second contact electrode connected to the second end region; and an insulating member, which, when viewed from the stacking direction, is disposed between the first semiconductor pillar and the second semiconductor pillar in such a manner that it overlaps with a portion of the first semiconductor pillar and a portion of the second semiconductor pillar, and extends in the first direction, separating a portion of the conductive layers disposed on the side of the first contact electrode and the second contact electrode in the stacking direction in the second direction. The first width in the second direction of the insulating member at the position corresponding to the stacking direction of the first conductive layer in the portion of the conductive layer is larger than the second width in the second direction of the insulating member at the position corresponding to the first end region and the second end region, and relative to the position of the first contact electrode and the second contact electrode in the stacking direction on the side of the plurality of conductive layers. Attached Figure Description

[0005] Figure 1 This is a schematic circuit diagram showing the configuration of the semiconductor memory device according to Embodiment 1.

[0006] Figure 2 This is a schematic top view showing the configuration of a portion of the semiconductor memory device.

[0007] Figure 3 This is a schematic top view showing the configuration of a portion of the semiconductor memory device.

[0008] Figure 4 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0009] Figure 5 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0010] Figure 6 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0011] Figure 7 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0012] Figure 8 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0013] Figure 9 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0014] Figure 10 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0015] Figure 11 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0016] Figure 12 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0017] Figure 13 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0018] Figure 14 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0019] Figure 15 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 16 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 17 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 18 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0023] Figure 19This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 20 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 22 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 23 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 24 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 25 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 26 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 27 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 28 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 29 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 30 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0035] Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 33 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0038] Figure 34 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0039] Figure 35This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0040] Figure 36 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment.

[0041] Figure 37 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0042] Figure 38 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fourth embodiment.

[0043] Figure 39 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device.

[0044] Figure 40 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0045] Figure 41 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0046] Figure 42 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0047] Figure 43 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fifth embodiment. Detailed Implementation

[0048] Next, with reference to the accompanying drawings, the semiconductor memory device according to embodiments will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention.

[0049] Furthermore, the following figures are schematic diagrams, and for ease of explanation, some components may be omitted. Also, for multiple embodiments, common parts may be labeled with the same symbols, and descriptions may be omitted.

[0050] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to a memory die, and sometimes to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Also, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer.

[0051] Furthermore, when this specification mentions that the first component is "electrically connected" to the second component, the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0052] Furthermore, when this specification mentions that the first component is "connected between the second and third components", it is intended to mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0053] Furthermore, in this specification, the direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0054] Furthermore, in this specification, the direction intersecting the surface of the substrate is sometimes referred to as the stacking direction. Additionally, sometimes the direction along a predetermined surface intersecting the stacking direction is referred to as the first direction, and the direction along said surface intersecting the first direction is referred to as the second direction. The stacking direction may or may not be the same as the Z-direction. Furthermore, the first and second directions may or may not correspond to either the X-direction or the Y-direction.

[0055] Furthermore, in this specification, terms such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a component as a lower surface or lower end, it sometimes means the surface or end on the substrate side of that component; when referring to an upper surface or upper end, it sometimes means the surface or end on the opposite side of the substrate from that component. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0056] Furthermore, in this specification, when referring to components, parts, etc., the terms "width," "length," or "thickness" in a specified direction are used, they sometimes mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0057] [First Implementation Form]

[0058] [constitute]

[0059] Figure 1This is a schematic circuit diagram illustrating the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment includes a memory cell array.

[0060] The memory cell array comprises multiple memory blocks BLK. Each memory block BLK comprises multiple string cells SU. Each string cell SU comprises multiple memory strings MS. One end of each memory string MS is connected to an external circuit (not shown) via a bit line BL. Furthermore, the other end of each memory string MS is connected to an external circuit (not shown) via a common source line SL.

[0061] The memory string MS includes drain-side selection transistors STDT and STD, one or more drain-side pseudo-memory cells DMD, multiple memory cells MC (memory cell transistors), one or more source-side pseudo-memory cells DMS, and source-side selection transistors STS and STSB. The drain-side selection transistors STDT and STD, the drain-side pseudo-memory cells DMD, the multiple memory cells MC, the source-side pseudo-memory cells DMS, and the source-side selection transistors STS and STSB are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistors STDT and STD, and the source-side selection transistors STS and STSB will be simply referred to as selection transistors (STDT, STD, STS, STSB). Furthermore, the drain-side pseudo-memory cells DMD and the source-side pseudo-memory cells DMS will be simply referred to as pseudo-memory cells (DMD, DMS).

[0062] A memory cell MC is a field-effect transistor. A memory cell MC includes a portion of a semiconductor pillar, a gate insulating film, and a gate electrode. The portion of the semiconductor pillar functions as a channel region. The gate insulating film contains a charge accumulation film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. A memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to a memory string MS. These word lines WL are collectively connected to all memory strings MS in a memory block BLK.

[0063] Pseudo-memory cells (DMD, DMS) are field-effect transistors. They are constructed in the same way as memory cells (MC). However, pseudo-memory cells (DMD, DMS) are not used for data storage. The drain-side pseudo-memory cell (DMD) is positioned between the memory cell (MC) and the drain-side select transistor (STD). The source-side pseudo-memory cell (DMS) is positioned between the memory cell (MC) and the drain-side select transistor (STS). During read, write, and erase operations, the pseudo-memory cell (DMD, DMS) smooths the potential gradient between the memory cell (MC) and the select transistor (STD, STS). The gate electrode of one or more drain-side pseudo-memory cells (DMD) corresponding to a memory string (MS) is connected to a drain-side pseudo-word line (DWD). The gate electrode of one or more source-side pseudo-memory cells (DMS) corresponding to a memory string (MS) is connected to a source-side pseudo-word line (DWS). The drain-side pseudo-word line (DWD) and the source-side pseudo-word line (DWS) are all connected to all memory strings (MS) in a memory block (BLK).

[0064] Select transistors (STDT, STD, STS, STSB) are field-effect transistors. Each select transistor (STDT, STD, STS, STSB) has a portion of a semiconductor pillar, a gate insulating film, and a gate electrode. The portion of the semiconductor pillar functions as a channel region. Select gate lines (SGDT, SGD, SGS, SGSB) are connected to the gate electrodes of the select transistors (STDT, STD, STS, STSB). One drain-side select gate line SGDT is commonly connected to all memory strings MS in a memory block BLK. One drain-side select gate line SGD is commonly connected to all memory strings MS in a string cell SU. In the illustrated example, the gate electrodes of all drain-side select transistors STD in a memory string MS are connected to a common drain-side select gate line SGD. The drain-side select gate line SGD is electrically independent for each string cell SU. One source-side select gate line SGS is commonly connected to all memory strings MS in a memory block BLK. One source-side selected gate line (SGSB) is commonly connected to all memory strings (MS) in one memory block (BLK).

[0065] in addition, Figure 1 Each wiring in the illustrated memory cell array is electrically connected to peripheral circuitry (not shown). This peripheral circuitry includes, for example, a voltage generation circuit that generates an operating voltage, a voltage transmission circuit that transmits the generated operating voltage to selected bit lines BL, word lines WL, pseudo-word lines DWL, source lines SL, select gate lines (SGDT, SGD, SGS, SGSB), etc., a sense amplifier module connected to the bit line BL, and a sequencer that controls these.

[0066] Next, refer to Figures 2-7Here, an example of the configuration of the semiconductor memory device according to the first embodiment will be described. Figure 2 This is a schematic top view showing the configuration of a portion of the semiconductor memory device. Figure 3 This is a schematic top view showing the configuration of a portion of the semiconductor memory device, and... Figure 2 The portion shown as A is enlarged and represented in the image. Additionally, Figure 3 A portion of the image shows an XY cross-section corresponding to the height position of the conductive layer 110 (WL), described later. Furthermore, Figure 3 A portion of the image shows an XY cross-section corresponding to the height position of the conductive layer 110 (SGD), described later. Furthermore, Figure 3 In one part, the insulating layers 104 and 105, which will be described later, are omitted, and the bit line BL and the contact electrode Ch and contact electrode Vy, which will be described later, are recorded. Figure 4 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and showing a cut along line B-B'. Figure 3 The structure shown is a cross-section viewed along the direction of the arrow. Figure 5 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and... Figure 4 The portion indicated by C is enlarged and shown in the image. Additionally, Figure 5 The YZ section is shown, but when observing sections other than the YZ section along the central axis of the semiconductor pillar 120 (e.g., the XZ section), a similar pattern is also observed. Figure 5 Same construction. Figure 6 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and showing a cut along line D-D'. Figure 4 The structure shown is a cross-section viewed along the direction of the arrow. Figure 6 The XY cross-section shows the height position corresponding to the conductive layer 110 (SGD) described later. Figure 7 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and showing a cut along line E-E'. Figure 4 The structure shown is an XY cross-section viewed along the direction of the arrow. Figure 7 The XY cross-section shows the end region 124 corresponding to the semiconductor pillar 120 described later, and the height position relative to the contact electrode Ch on the conductive layer 110 side (below side).

[0067] like Figure 2 As shown, the semiconductor memory device of this embodiment includes a semiconductor substrate Sub. In the illustrated example, an array region R of four memory cells arranged in the X and Y directions is provided on the semiconductor substrate Sub. MCA .

[0068] Storage cell array region R MCAIt has multiple finger-like structures FS arranged in the Y direction. Examples of finger-like structures FS are as follows: Figure 3 As shown, the device comprises five string units SU arranged in the Y direction. An inter-finger structure ST is provided between two adjacent finger structures FS in the Y direction. Furthermore, an inter-string unit insulation member SHE is provided between two adjacent string units SU in the Y direction.

[0069] In this embodiment, a finger-like structure FS is used as a reference. Figure 1 The memory block BLK described above functions as such. However, multiple finger-structured FS can also function as memory blocks BLK. Furthermore, the finger-structured FS can have 2 to 4 serial units SU, or even more than 6 serial units SU.

[0070] like Figure 4 As shown, an insulating layer 100, such as silicon oxide (SiO2), and a conductive layer 112 are disposed above the semiconductor substrate Sub. Furthermore, above the conductive layer 112, a plurality of finger-like structures FS and a plurality of inter-finger structures ST arranged alternately in the Y direction are disposed. Moreover, above the plurality of finger-like structures FS and the plurality of inter-finger structures ST, an insulating layer 104, such as silicon nitride (SiN), and an insulating layer 105, such as silicon oxide (SiO2), are disposed.

[0071] The finger-structure FS includes a plurality of conductive layers 110 and insulating layers 101 such as silicon oxide (SiO2) arranged alternately in the Z direction, an insulating layer 102 such as silicon oxide (SiO2) disposed above them, and a plurality of semiconductor pillars 120 extending in the Z direction through a portion of the insulating layer 102, the plurality of conductive layers 110 and the plurality of insulating layers 101, and a portion of the conductive layers 112. Furthermore, gate insulating films 130 are disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0072] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 is, for example, as shown in... Figure 5 As shown, the conductive layer 110 may also include a stacked film containing a barrier conductive film 113 such as titanium nitride (TiN) and a metal film 114 such as tungsten (W). Furthermore, the conductive layer 110 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Additionally, a high-dielectric-constant insulating film 103 may be provided on the upper and lower surfaces of the conductive layer 110 and on the surface opposite to the semiconductor pillar 120. The high-dielectric-constant insulating film 103 may, for example, be a metal oxide film such as aluminum oxide (AlO), hafnium oxide (HfO), or zirconium oxide (ZrO).

[0073] Multiple conductive layers 110 as references Figure 1The word line WL and the gate electrodes of the multiple memory cells MC connected thereto function as described. In the following description, this conductive layer 110 will be referred to as conductive layer 110(WL). The multiple conductive layers 110(WL) are electrically independent according to each finger structure FS. The positive and negative sides of the conductive layer 110(WL) in the Y direction are electrically insulated from the other finger structures FS via the inter-finger structure ST.

[0074] One or more conductive layers 110 located below the plurality of conductive layers 110 (WL) are used as a reference. Figure 1 The source-side pseudo-word line DWS and the gate electrodes of the multiple source-side pseudo-memory cells DMS connected thereto function as described. In the following description, this conductive layer 110 will be referred to as conductive layer 110 (DWS). Conductive layer 110 (DWS) is constructed in the same manner as conductive layer 110 (WL).

[0075] One or more conductive layers 110 located below the plurality of conductive layers 110 (DWS) are used as a reference. Figure 1 The source-side selected gate line SGS and the gate electrodes of the plurality of source-side selected transistors STS connected thereto function as described. In the following description, this conductive layer 110 is referred to as conductive layer 110 (SGS). Conductive layer 110 (SGS) is constructed in the same manner as conductive layer 110 (WL).

[0076] One or more conductive layers 110 located below the plurality of conductive layers 110 (SGS) are used as a reference. Figure 1 The source-side selected gate line SGSB and the gate electrodes of the plurality of source-side selected transistors STSB connected thereto function as described. In the following description, this conductive layer 110 is referred to as conductive layer 110 (SGSB). Conductive layer 110 (SGSB) is constructed in the same manner as conductive layer 110 (WL).

[0077] One or more conductive layers 110 located above the plurality of conductive layers 110 (WL) serve as a reference. Figure 1 The gate electrodes of the drain-side pseudo-word line (DWD) and the multiple drain-side pseudo-memory cells (DMDs) connected thereto function as described. In the following description, this conductive layer 110 will sometimes be referred to as conductive layer 110 (DWD). A portion of the conductive layer 110 (DWD) may be constructed in the same manner as conductive layer 110 (WL). Another portion of the conductive layer 110 (DWD), disposed above the aforementioned portion, is constructed substantially in the same manner as conductive layer 110 (SGD) described later. However, the five portions of the conductive layer 110 (DWD) that are divided in the Y direction within a finger-like structure FS are electrically connected to each other.

[0078] One or more conductive layers 110 located above the plurality of conductive layers 110 (DWD) are used as a reference. Figure 1 The gate electrodes of the drain-side selected gate line SGD and the plurality of drain-side selected transistors STD connected thereto function as described. In the following description, this conductive layer 110 is sometimes referred to as conductive layer 110 (SGD).

[0079] like Figure 3 As shown, the conductive layer 110 (SGD) comprises five sections segmented in the Y direction via inter-cell insulation members (SHE). The width Y in the Y direction of the five sections is... SGD The width Y in the Y direction of the conductive layer 110 (WL) is smaller than the width Y of the conductive layer 110 (WL). WL The five parts are electrically independent according to each string unit SU. In each finger structure FS, the parts corresponding to the 1st and 5th string units SU counting from one side of the Y direction (e.g., the negative side of the Y direction) are electrically insulated from the parts in other finger structures FS via the inter-finger structure ST provided between the finger structures FS. Furthermore, in each finger structure FS, two adjacent parts in the Y direction are electrically insulated from each other via the inter-string unit insulation member SHE.

[0080] One or more conductive layers 110 located above one or more conductive layers 110 (SGD) are used as a reference. Figure 1 The gate electrodes of the drain-side selected gate line SGDT and the plurality of drain-side selected transistors STDT connected thereto function. In the following description, this conductive layer 110 is sometimes referred to as conductive layer 110 (SGDT). Conductive layer 110 (SGDT) is essentially constructed in the same way as conductive layer 110 (SGD). However, the five portions of conductive layer 110 (SGDT) that are divided in the Y direction within a finger-like structure FS are electrically connected to each other via contact electrodes (not shown).

[0081] Conductive layer 112 ( Figure 4 For example, it may contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, a conductive layer such as tungsten (W), tungsten silicide, or other conductive layers may be provided on the lower surface of the conductive layer 112. An insulating layer 101, such as silicon oxide (SiO2), is provided between the conductive layer 112 and the conductive layer 110.

[0082] Conductive layer 112 as a reference Figure 1 The source line SL, as described, functions. Conductive layer 112, for example, is applied to the memory cell array region R. MCA ( Figure 2 All finger structures contained in FS share common settings.

[0083] Semiconductor pillar 120, for example Figure 3As shown, they are arranged in a prescribed pattern in the X and Y directions. For example, the finger structure FS has 20 semiconductor pillars SC arranged from one side of the Y direction to the other side of the Y direction. Each of the 20 semiconductor pillars SC has a plurality of semiconductor pillars 120 arranged in the X direction.

[0084] Hereinafter, the semiconductor pillar 120 corresponding to the 4n (n is an integer between 1 and 4)th and 4n+1th semiconductor pillar columns SC counting from one side in the Y direction will be referred to as semiconductor pillar 120. O Furthermore, the semiconductor pillar 120 corresponding to the 1st, 2nd, 3rd, 4n+2nd, 4n+3rd, and 20th semiconductor pillar columns SC counting from one side in the Y direction is referred to as semiconductor pillar 120. I .

[0085] Semiconductor pillar 120 may contain, for example, polycrystalline silicon (Si). Semiconductor pillar 120 may contain, for example, polycrystalline silicon (Si). Figure 4 As shown, it has a roughly cylindrical shape, with an insulating layer 127 such as silicon oxide (SiO2) disposed in the central part.

[0086] The semiconductor pillar 120 includes a region 121 disposed below the lower surface of the bottom conductive layer 110, a region 122 disposed above the region 121 and below the lower end of the inter-string unit insulating member SHE, a region 123 disposed above the region 122 and below the upper end of the insulating pillar 127, and an end region 124 disposed above the region 123.

[0087] Region 121 is the region containing the lower end of semiconductor pillar 120. Region 121 contains N-type impurities such as phosphorus (P). Region 121 has a generally cylindrical shape. Region 121 is connected to conductive layer 112.

[0088] Region 122 is aligned with a portion of conductive layers 110 (SGSB), 110 (SGS), 110 (DWS), 110 (WL), and conductive layer 110 (DWD). Region 122 serves as a reference. Figure 1 The described memory cell MC, pseudo memory cells (DMD, DMS), and the channel regions of the source-side selection transistors STSB and STS function. Region 122 may also be free of N-type impurities such as phosphorus (P). Region 122 has a generally cylindrical shape.

[0089] Region 123 is aligned with a portion of conductive layer 110 (DWD) and conductive layers 110 (SGD) and 110 (SGDT). Region 123 serves as a reference. Figure 1 The drain-side pseudo-memory cell DMD and the channel regions of the drain-side selection transistors STD and STDT are explained to function. Region 123 may also not contain N-type impurities such as phosphorus (P).

[0090] Semiconductor pillar 120 I Region 123 has a generally cylindrical shape. On the other hand, semiconductor pillar 120... O Region 123, for example, Figure 6 As shown, it has a shape like a part missing from a cylinder (an arc shape in the XY cross section).

[0091] End region 124 ( Figure 4 The end region 124 is the region containing the upper end of the semiconductor pillar 120, disposed above the uppermost conductive layer 110. The end region 124 contains N-type impurities such as phosphorus (P). The end region 124 is connected via contact electrodes Ch and Vy extending in the Z direction. Figure 3 The contact electrode Ch and contact electrode Vy may be, for example, composite films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). The contact line BL may also be, for example, composite films of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0092] Semiconductor pillar 120 I The end region 124 has a generally cylindrical shape. On the other hand, the semiconductor pillar 120... O The end region 124, for example, Figure 7 As shown, it has a shape similar to a cylinder with a portion missing.

[0093] Gate insulating film 130, for example, Figure 5 As shown, a tunnel insulating film 131, a charge accumulation film 132, and a barrier insulating film 133 are deposited between a semiconductor pillar 120 and a conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 may contain, for example, silicon oxide (SiO2). The charge accumulation film 132 may be, for example, a film capable of accumulating charge on silicon nitride (SiN).

[0094] The portion of the gate insulating film 130 disposed at a position corresponding to region 121 of semiconductor 120, for example, Figure 4 As shown, it has a generally cylindrical shape with a bottom and extends in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the semiconductor pillar 120 and the conductive layer 112.

[0095] The portion of the gate insulating film 130 disposed at a position corresponding to region 122 of semiconductor 120 has a generally cylindrical shape and extends in the Z direction along the outer peripheral surface of semiconductor pillar 120.

[0096] The gate insulating film 130 is disposed in a manner corresponding to the semiconductor pillar 120 IThe portion of region 123 and end region 124 has a generally cylindrical shape, along the semiconductor pillar 120. I The outer peripheral surface extends in the Z direction.

[0097] The gate insulating film 130 is disposed in the corresponding semiconductor 120 O For example, the location of region 123 and end region 124 is as follows Figure 6 and Figure 7 As shown, it has a shape like a part missing from a cylinder (an arc shape in the XY cross section).

[0098] For example, interdigital structures ST Figure 3 and Figure 4 The device includes inter-finger electrodes 141 extending in the X and Z directions, and inter-finger insulating members 142 such as silicon oxide (SiO2) disposed on the side of the inter-finger electrodes 141 in the Y direction. The lower end of the inter-finger electrodes 141 is connected to the conductive layer 112. Furthermore, the upper end of the inter-finger electrodes 141 is almost aligned with the upper surface of the insulating layer 102. The inter-finger electrodes 141 may, for example, comprise a multilayer film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the inter-finger electrodes 141 may, for example, comprise polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The inter-finger electrodes 141 are used as a reference, for example. Figure 1 The source line SL described above functions as a part of the line. Alternatively, the interdigital electrode 141 can be provided without the interdigital structure ST.

[0099] Inter-cell insulation components (SHE) may contain, for example, silicon dioxide (SiO2). Inter-cell insulation components (SHE) may contain, for example, silicon dioxide (SiO2). Figure 3 As shown, they are respectively set between the 4nth semiconductor column SC and the 4n+1th semiconductor column SC counting from one side in the Y direction, and extend in the X direction.

[0100] In the illustrated example, the inter-cell insulation component SHE, when viewed from the Z direction, is located at the junction with the semiconductor pillar 120. O A portion of the tunnel insulating film 131, charge accumulation film 132 and barrier insulating film 133 that constitute the gate insulating film 130 overlap with a portion of the tunnel insulating film 131, charge accumulation film 132 and barrier insulating film 133.

[0101] Inter-unit insulation components SHE such as Figure 4As shown, regions R1 and R2 are included. Region R1 extends in the Z direction within the height range corresponding to the plurality of conductive layers 110 (SGDT), 110 (SGD), a portion of the conductive layers 110 (DWD), and the insulating layer 101 disposed on the upper and lower surfaces of these conductive layers 110, and interrupts the configuration in the Y direction. In the illustrated example, the lower end of region R1 is disposed along the upper surface of one of the plurality of conductive layers 110 (DWD). Region R2 extends in the Z direction within the height range corresponding to the insulating layer 102, and interrupts the insulating layer 102 in the Y direction.

[0102] The width Y in the Y direction of region R1 R1 It can be roughly fixed, or it can gradually decrease from top to bottom. In the example shown, the width Y in the Y direction of the region R1 corresponding to the height position of multiple conductive layers 110 (SGDT), 110 (SGD) and a portion of conductive layer 110 (DWD) is... R1 The width Y in the Y direction of the region R1 corresponding to the height position of the insulating layer 101 disposed on the upper and lower surfaces of these conductive layers 110. R1 Almost identical. The width Y in the Y direction of region R2 R2 It can be roughly fixed, or it can gradually decrease from top to bottom. The width Y in the Y direction of region R1... R1 The width Y in the Y direction of region R2 is greater than R2 .

[0103] The width Y in the Y direction of region R1 R1 For example, Figure 6 As shown, it can also be the distance in the Y direction between two parts of the insulating layer 101 disposed on the upper and lower surfaces of these conductive layers 110 (SGDT), 110 (SGD), a portion of the conductive layer 110 (DWD), or the distance in the Y direction between two parts of the insulating layer 101 disposed on the upper and lower surfaces of these conductive layers 110, which is divided in the Y direction by the inter-string unit insulating member SHE.

[0104] Additionally, within the height range corresponding to region R1, such as Figure 6 As illustrated, the distance and width Y in the Y direction of two adjacent semiconductor pillars SC separated by an inter-cell insulating member SHE are as follows: from the end of the inter-cell insulating member SHE side of one of the plurality of semiconductor pillars 120 to the end of the inter-cell insulating member SHE side of the other of the plurality of semiconductor pillars 120. R1 Almost identical, and larger than width Y R2 .

[0105] Similarly, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE, from the end of the inter-cell insulating member SHE side of the plurality of gate insulating films 130 of the plurality of semiconductor pillars 120 contained in one, to the end of the inter-cell insulating member SHE side of the plurality of gate insulating films 130 of the plurality of semiconductor pillars 120 contained in the other. R1 Almost identical, and larger than width Y R2 .

[0106] For example, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulation member SHE, from the end of the inter-cell insulation member SHE side of the plurality of charge accumulation films 132 of the plurality of semiconductor pillars 120 contained in one, to the end of the inter-cell insulation member SHE side of the plurality of charge accumulation films 132 of the plurality of semiconductor pillars 120 contained in the other. R1 Almost identical, and larger than width Y R2 .

[0107] Furthermore, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC, separated by the inter-cell insulation component SHE, are as follows: from the end of the high-dielectric-constant insulating film 103 corresponding to the plurality of semiconductor pillars 120 contained in one of them, to the end of the inter-cell insulation component SHE corresponding to the plurality of semiconductor pillars 120 contained in the other. R1 Almost identical, and larger than width Y R2 .

[0108] The width Y in the Y direction of region R2 R2 For example, Figure 7 As shown, it can also be the distance in the Y direction between the end region 124 of the plurality of semiconductor pillars 120 contained in one of the adjacent semiconductor pillars SC in the Y direction, separated by the inter-cell insulation component SHE, and the end region 124 of the plurality of semiconductor pillars 120 contained in the other.

[0109] Additionally, within the height range corresponding to region R2, such as Figure 7 As illustrated, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by inter-cell insulating members SHE are as follows: from the end of the inter-cell insulating member SHE side of the plurality of gate insulating films 130 of the plurality of semiconductor pillars 120 contained in one, to the end of the inter-cell insulating member SHE side of the plurality of gate insulating films 130 of the plurality of semiconductor pillars 120 contained in the other. R2 Almost identical, and smaller than width YR1 .

[0110] Within region R1, a void V is formed. Figure 4 In this example, the gap V extends in the Z direction within the height range corresponding to the plurality of conductive layers 110 (SGDT), 110 (SGD) and a portion of conductive layers 110 (DWD), and the insulating layer 101 disposed on the upper and lower surfaces of these conductive layers 110. Alternatively, the inter-string unit insulating member SHE may not include the gap V within the region R1.

[0111] [Manufacturing Method]

[0112] Next, refer to Figures 8 to 32 The manufacturing method of the semiconductor memory device according to the first embodiment will be described. Figures 8 to 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 ,and Figures 28-32 This is a schematic cross-sectional view used to illustrate the manufacturing method, and it shows the corresponding... Figure 4 The cross-section. Figure 18 , Figure 20 This is a schematic cross-sectional view used to illustrate the manufacturing method, and the indicated area corresponds to... Figure 7 The cross-section. Figure 22 , Figure 24 , Figure 26 and Figure 27 This is a schematic cross-sectional view used to illustrate the manufacturing method, and it shows the corresponding... Figure 6 The cross-section.

[0113] When manufacturing the semiconductor memory device of this embodiment, for example, Figure 8 As shown, an insulating layer 100 is formed above a semiconductor substrate (not shown). Next, a semiconductor layer 112A (such as silicon), a sacrificial layer 112B (such as silicon oxide), a sacrificial layer 112C (such as silicon), a sacrificial layer 112D (such as silicon oxide), and a semiconductor layer 112E (such as silicon) are formed on the insulating layer 100. Furthermore, multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed. Additionally, a portion of an insulating layer 102 is formed. These steps are performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0114] Next, for example, Figure 9As shown, a memory hole MH is formed at the position corresponding to semiconductor pillar 120. The memory hole MH extends in the Z direction, penetrating insulating layer 102, insulating layer 101, sacrificial layer 110A, semiconductor layer 112E, sacrificial layer 112D, sacrificial layer 112C, and sacrificial layer 112B, exposing the upper surface of semiconductor layer 112A. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0115] Next, for example, Figure 10 As shown, a gate insulating film 130, a semiconductor pillar 120, and an insulating pillar 127 are formed inside the memory hole MH. This step is performed, for example, by a method such as CVD.

[0116] Next, for example, Figure 11 As shown, a portion of the insulating layer 102 is formed using methods such as CVD. Furthermore, a trench STA is formed at positions corresponding to the interdigital structure ST. The trench STA extends in the Z and X directions, separating the insulating layer 102, insulating layer 101, sacrificial layer 110A, semiconductor layer 112E, and sacrificial layer 112D in the Y direction, exposing the upper surface of the sacrificial layer 112C. This step is performed, for example, by methods such as RIE.

[0117] Next, for example, Figure 12 As shown, a portion of sacrificial layers 112B, sacrificial layers 112C and 112D, and the gate insulating film 130 are removed to form a conductive layer 112. The removal of sacrificial layers 112B, 112C, 112D, and a portion of the gate insulating film 130 is performed, for example, by wet etching. The formation of the conductive layer 112 is performed, for example, by epitaxial growth.

[0118] Next, for example, Figure 13 As shown, the sacrificial layer 110A is removed via trench STA, forming a plurality of voids 110B arranged in the Z direction. This creates a hollow structure containing a plurality of insulating layers 101 and 102 arranged in the Z direction, and the structure within the memory via MH supporting them (semiconductor pillar 120, gate insulating film 130, and insulating pillar 127). This step is performed, for example, by a method such as wet etching.

[0119] Next, for example, Figure 14 As shown, a conductive layer 110 is formed in the void 110B. This step is performed, for example, by a method such as CVD.

[0120] Next, for example, Figure 15 As shown, finger-like interdigital structures ST are formed within the trench STA. This step is performed, for example, by methods such as CVD and RIE.

[0121] Next, for example, Figure 16 As shown, an insulating layer 104A, such as silicon nitride (SiN), and an insulating layer 105A, such as silicon oxide (SiO2), are formed on the upper surface of the insulating layer 102 and the finger-like interfacial structure ST. This step is performed, for example, by a method such as CVD.

[0122] Next, for example, Figure 17 and Figure 18 As shown, a trench SHEA is formed at the location corresponding to the inter-cell insulating component SHE. The trench SHEA extends in the Z and X directions, dividing the insulating layer 102 in the Y direction, exposing the upper surface of the uppermost conductive layer 110, as well as a portion of the semiconductor pillar 120, the gate insulating film 130, and the insulating pillar 127. This step is performed, for example, by a method such as RIE.

[0123] in addition, Figure 17 and Figure 18 In the example, at the height position corresponding to the end region 124 of the semiconductor pillar 120, the width of the trench SHEA in the Y direction is the same as the reference. Figure 4 and Figure 7 The width Y of the description R2 Almost identical.

[0124] Next, for example, Figure 19 and Figure 20 As shown, a protective film SHEB is formed on the bottom surface and inner wall surface of the trench SHEA, and on the upper surface of the insulating layer 105A. The protective film SHEB contains, for example, carbon (C). The step is performed, for example, by a method such as CVD. Furthermore, the protective film SHEB is formed relatively thinly so as not to be embedded in the trench SHEA.

[0125] Next, for example, Figure 21 and Figure 22 As shown, the portion of the protective film SHEB formed on the bottom surface of the trench SHEA is removed to further form a trench SHEC. The trench SHEC extends in the Z and X directions, and a plurality of conductive layers 110 (SGDT), 110 (SGD), a portion of conductive layer 110 (DWD), and an insulating layer 101 disposed therebetween are separated in the Y direction. This step is performed, for example, by a method such as RIE.

[0126] Next, for example, Figure 23 and Figure 24 As shown, a portion of the conductive layer 110 is removed via trench SHEC, and the width of the trench SHEC in the Y direction is increased at a position corresponding to the height of a portion of the conductive layer 110. This step is performed, for example, by a method such as wet etching. Furthermore, Figure 24 In this example, in addition to the conductive layer 110, a portion of the high dielectric constant insulating film 103 is also removed.

[0127] In the aforementioned step, the width of the trench SHEC in the Y direction corresponding to the height positions of the plurality of conductive layers 110 (SGDT), 110 (SGD), and a portion of the conductive layers 110 (DWD) is larger than the width of the trench SHEC in the Y direction corresponding to the height positions of the insulating layers 101 disposed on the upper and lower surfaces of these conductive layers 110. For example, at the height position corresponding to the conductive layer 110 (SGD), the width of the trench SHEC in the Y direction is larger than the reference width. Figure 4 and Figure 6 The width Y of the description R1 Almost identical.

[0128] Next, for example, Figure 25 and Figure 26 As shown, a portion of the insulating layer 101 is removed, and the width of the trench SHEC in the Y direction is increased at a position corresponding to the height of the insulating layer 101. This step is performed, for example, by a method such as wet etching. Furthermore, in this embodiment, the insulating layer 101, the insulating pillar 127, the tunnel insulating film 131, and the barrier insulating film 133 are made of silicon oxide (SiO2). Therefore, when a portion of the insulating layer 101 is removed, as... Figure 26 As illustrated, a portion of the insulating post 127, a portion of the tunnel insulating film 131, and a portion of the barrier insulating film 133 are also removed.

[0129] In the aforementioned steps, the width of the trench SHEC in the Y direction corresponding to the height positions of the plurality of conductive layers 110 (SGDT), 110 (SGD), and a portion of the conductive layers 110 (DWD) is almost identical to the width of the trench SHEC in the Y direction corresponding to the height positions of the insulating layers 101 disposed on the upper and lower surfaces of these conductive layers 110. For example, at the height positions corresponding to the insulating layers 101 disposed on the upper and lower surfaces of the conductive layers 110 (SGD), the width of the trench SHEC in the Y direction is almost identical to the width of the reference layer 101. Figure 4 and Figure 6 The width Y of the description R1 Almost identical.

[0130] Next, for example, Figure 27 As shown, a portion of the semiconductor pillar 120 and charge accumulation film 132 are removed via trench SHEC. This step is performed, for example, by a method such as wet etching.

[0131] Next, for example, Figure 28 As shown, the protective film SHEB is removed. This step is performed, for example, by methods such as ashing.

[0132] Next, for example, Figure 29As shown, insulating components SHED are formed inside the trenches SHEA and SHEC, and on the upper surface of the insulating layer 105A. The portion of the insulating component SHED formed inside the trench SHEC becomes region R1 of the inter-cell insulating component SHE. The portion of the insulating component SHED formed inside the trench SHEA becomes region R2 of the inter-cell insulating component SHE. This step is performed, for example, by CVD.

[0133] Next, for example, Figure 30 As shown, insulating layers 104A and 105A, and a portion of the insulating component SHED, are removed to expose the upper surface of insulating layer 102 and the finger-like inter-unit structure ST, forming the inter-unit insulating component SHE. This step is performed, for example, by methods such as CMP (Chemical Mechanical Polishing).

[0134] Next, for example, Figure 31 As shown, insulating layers 104 and 105 are formed on the upper surface of insulating layer 102. This step is performed, for example, by CVD.

[0135] Next, for example, Figure 32 As shown, a contact hole ChA is formed at the position corresponding to the contact electrode Ch. The contact hole ChA extends in the Z direction and penetrates a portion of insulating layers 105, 104, and 102, exposing the upper end of the semiconductor pillar 120. This step is performed, for example, by a method such as RIE.

[0136] Subsequently, contact electrode Ch is formed, thereby forming as shown in the reference. Figure 4 Explain that kind of construction.

[0137] [Effect]

[0138] For reference Figure 3 As explained above, in the semiconductor memory device of the first embodiment, the conductive layer 110 (SGD) is divided into multiple parts by the inter-cell insulation member SHE. Here, in the semiconductor memory device of the first embodiment, the inter-cell insulation member SHE is provided between the 4nth semiconductor column SC and the 4n+1th semiconductor column SC counting from one side in the Y direction.

[0139] With this configuration, all semiconductor pillars 120 in the semiconductor pillar array SC can be used as memory cells MC, etc. Therefore, by setting a portion of the semiconductor pillars 120 located at positions overlapping with the inter-cell insulation component SHE as pseudo-semiconductor pillars, a higher level of integration of the semiconductor memory device can be achieved compared to a configuration in which they are not used as memory cells MC, etc.

[0140] Here, in the first embodiment, the semiconductor pillar 120 is substantially surrounded by a conductive layer 110 covering its entire circumference. On the other hand, as... Figure 6 As shown, semiconductor pillar 120 O Region 123 is not completely surrounded by conductive layer 110, and its end in the Y direction is separated from other conductive layers 110 by inter-cell insulating member SHE. In this configuration, semiconductor pillar 120 is disposed on one side in the Y direction opposite to the inter-cell insulating member SHE. O It is affected by the electric field from the conductive layer 110 (SGD) disposed on the other side of the string unit insulation component SHE in the Y direction.

[0141] For example, when selecting a string cell SU located on the opposite side of the Y-direction relative to the inter-cell insulation component SHE, a voltage lower than the threshold voltage of the drain-side selection transistor STD is supplied to the conductive layer 110 (SGD) located on the Y-direction side. This creates a region in the semiconductor pillar 120 where the inversion layer (channel) is not formed, electrically disconnecting the bit line BL from the memory cell MC. Alternatively, a voltage higher than the threshold voltage of the drain-side selection transistor STD is supplied to the conductive layer 110 (SGD) located on the opposite side of the Y-direction, forming an inversion layer (channel) in the semiconductor pillar 120, thus connecting the bit line BL to the memory cell MC. In this operation, the electric field from the conductive layer 110 (SGD) located on the opposite side of the Y-direction creates an inversion layer (channel) in the semiconductor pillar 120 located on the Y-direction side. O A reversal layer (channel) is formed at the Y-direction end of region 123, causing the drain-side selection transistor STD, which should be in the off state, to become in the ON state.

[0142] To suppress this phenomenon, one could consider increasing the width of the inter-cell insulation component SHE in the Y direction. However, when increasing the width of the inter-cell insulation component SHE in the Y direction, at reference... Figure 32 In the described steps, it is difficult to position the contact hole ChA and the end region 124 of the semiconductor pillar 120. For example, if the end region 124 is not exposed inside the contact hole ChA, an open circuit defect may occur, resulting in the contact electrode Ch not being in contact with the semiconductor pillar 120. Furthermore, for example, if the conductive layer 110 is exposed inside the contact hole ChA, a short circuit defect may occur, resulting in the contact electrode Ch not contacting the conductive layer 110. Therefore, increasing the width of the inter-cell insulation component SHE in the Y direction leads to a decrease in yield.

[0143] Therefore, in this embodiment, as referenced Figure 23 and Figure 24As described above, a portion of the conductive layer 110 (SGD) is removed while protecting the end region 124 of the semiconductor pillar 120, and the width of the trench SHEC in the Y direction is increased at a position corresponding to the height of the conductive layer 110 (SGD). This method does not lead to a decrease in yield and provides a semiconductor memory device that operates properly.

[0144] Furthermore, in this embodiment, in reference Figure 25 and Figure 26 In the described steps, a portion of the insulating layer 101 is removed via a trench SHEC, and the width of the trench SHEC in the Y direction is increased at a position corresponding to the height of the insulating layer 101. According to this method, the inner wall surface of the trench SHEC can be made relatively flat, in reference... Figure 29 The steps described can properly form the insulating component SHED.

[0145] Furthermore, in this embodiment, in reference Figure 27 In the described steps, a portion of the semiconductor pillar 120 is removed via trench SHEC. According to this method, the semiconductor pillar 120 is positioned on one side in the Y direction relative to the inter-cell insulation member SHE. O The distance between the conductive layer 110 (SGD) and the inter-cell insulating component SHE disposed on the other side in the Y direction is further increased, thus providing a semiconductor memory device that operates more properly.

[0146] Furthermore, the charge accumulation film 132 and the high dielectric constant insulating film 103 are preferably covered by the conductive layer 110 in the XY cross-section corresponding to either conductive layer 110. This is because if the charge accumulation film 132 and the high dielectric constant insulating film 103 have portions that are separated from the conductive layer 110, charge accumulates in these portions, making it potentially difficult to adjust the threshold voltage of the drain-side selection transistor STD, etc.

[0147] Therefore, in this embodiment, when referring to Figure 24 In the described steps, a portion of the high-dielectric-constant insulating film 103 is removed via trench SHEC. Furthermore, in the reference... Figure 27 In the described steps, a portion of the charge accumulation film 132 is removed via trench SHEC. According to this method, the accumulation of charge as described above can be suppressed, providing a semiconductor memory device with more appropriate operation.

[0148] In addition, in reference Figure 24 Explanation of steps and references Figure 27 In the described steps, a portion of the semiconductor pillar 120, a portion of the charge accumulation film 132, and a portion of the high dielectric constant insulating film 103 are removed via trench SHEC, thereby setting the inner wall surface of the trench SHEC to a relatively flat state. Therefore, in reference... Figure 29 The steps described can properly form the insulating component SHED.

[0149] Alternatively, in the first embodiment, the step of removing a portion of the high dielectric constant insulating film 103 via trench SHEC may be omitted. Figure 24 ), the step of removing a portion of the semiconductor pillar 120 via trench SHEC ( Figure 27 The steps of removing a portion of the charge accumulation film 132 via trench SHEC and ( Figure 27 At least one of them. This can also reduce the number of manufacturing steps.

[0150] [Second Implementation]

[0151] In the manufacturing method of the semiconductor memory device according to the first embodiment, referring to Figure 25 and Figure 26 In the described steps, a portion of the insulating layer 101 is removed. However, this step can also be omitted. Hereinafter, a configuration manufactured without this step will be illustrated as a semiconductor memory device according to the second embodiment.

[0152] Figure 33 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the second embodiment. Figure 34 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and showing a cut along line E-E'. Figure 33 The structure shown is an XY cross-section viewed along the direction of the arrow. Figure 34 The XY cross-section is shown, corresponding to the height position of the conductive layer 110 (SGD). Figure 35 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and showing a cut along line F-F'. Figure 33 The structure shown is an XY cross-section viewed along the direction of the arrow. Figure 35 The XY cross-section is shown, corresponding to the height position of the insulating layer 101.

[0153] The semiconductor memory device of the second embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment replaces the inter-cell insulation member SHE2 with an inter-cell insulation member SHE2.

[0154] The inter-unit insulation component SHE2 is basically constructed in the same way as the inter-unit insulation component SHE. However, the inter-unit insulation component SHE2 replaces region R1 and has region R3.

[0155] Region R3 is constructed in essentially the same way as region R1. However, in region R3, the width Y in the Y direction corresponding to the height positions of the multiple conductive layers 110 (SGDT), 110 (SGD), and a portion of the conductive layer 110 (DWD) is different. R1 ( Figure 34 The width Y in the Y direction corresponding to the height position of the insulating layer 101 disposed on the upper and lower surfaces of these conductive layers 110 is greater than the width Y in the Y direction. R3 ( Figure 35 Large. Additionally, in reference... Figure 21 and Figure 22 In the described steps, the width of the trench SHEC in the Y direction is only reduced by the amount of protective film SHEB disposed on the inner wall surface of the trench SHEA in the Y direction, compared to the width of the trench SHEA in the Y direction. Therefore, the width Y... R3 Less than width Y R2 .

[0156] Furthermore, region R3 does not include, as referenced Figure 4 The gap V is as described above. However, the inter-cell insulation component SHE2 may also contain a gap V within region R3.

[0157] Additionally, in region R3, such as Figure 34 and Figure 35 As illustrated, the distance and width Y in the Y direction of two adjacent semiconductor pillars SC separated by inter-cell insulation members SHE2 are as follows: from the end of the inter-cell insulation member SHE2 side of one of the plurality of semiconductor pillars 120 to the end of the inter-cell insulation member SHE2 side of the other of the plurality of semiconductor pillars 120. R1 Almost identical, and larger than width Y R2 Y R3 .

[0158] Similarly, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE2 are as follows: from the end of the inter-cell insulating member SHE2 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in one to the end of the inter-cell insulating member SHE2 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in the other. R1 Almost identical, and larger than width Y R2 Y R3 .

[0159] Furthermore, at the height position corresponding to the multiple conductive layers 110 (SGDT), 110 (SGD) and a portion of the conductive layer 110 (DWD) in region R3, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE2 are as follows: from the end of the high-dielectric-constant insulating film 103 containing the multiple semiconductor pillars 120 of one to the end of the high-dielectric-constant insulating film 103 containing the multiple semiconductor pillars 120 of the other. R1 Almost identical, and larger than width Y R2 Y R3 .

[0160] According to the second embodiment, similar to the first embodiment, it does not lead to a decrease in yield and provides a semiconductor memory device that operates appropriately. Furthermore, in reference... Figure 24 Explanation of steps and references Figure 27 In the described steps, a portion of the semiconductor pillar 120, a portion of the charge accumulation film 132, and a portion of the high dielectric constant insulating film 103 are removed via trench SHEC, thereby providing a semiconductor memory device that operates more properly.

[0161] Furthermore, according to the second embodiment, compared with the first embodiment, the number of manufacturing steps can be reduced.

[0162] [Third Implementation]

[0163] As described above, in the first embodiment, the step of removing a portion of the high dielectric constant insulating film 103 via trench SHEC can also be omitted. Figure 24 ), the step of removing a portion of the semiconductor pillar 120 via trench SHEC ( Figure 27 The steps of removing a portion of the charge accumulation film 132 via trench SHEC and ( Figure 27 At least one of the steps described above. The same applies to the second embodiment. Hereinafter, a semiconductor memory device of the third embodiment will be illustrated by omitting all the steps described above in the manufacturing method of the second embodiment.

[0164] Figure 36 and Figure 37 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment. Figure 36 Indicate the corresponding Figure 34 A cross-section of the location. Figure 37 Indicate the corresponding Figure 35 A cross-section of the location.

[0165] The semiconductor memory device of the third embodiment is configured in the same way as the semiconductor memory device of the second embodiment.

[0166] but, Figure 36 and Figure 37 In the example, the distance and width Y in the Y direction of two adjacent semiconductor pillars SC in the Y direction via the inter-cell insulation member SHE2 are: from the end of the inter-cell insulation member SHE2 side of one of the plurality of semiconductor pillars 120 to the end of the inter-cell insulation member SHE2 side of the other of the plurality of semiconductor pillars 120. R3 Almost identical, and smaller than width Y R1 Y R2 .

[0167] Similarly, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE2 are as follows: from the end of the inter-cell insulating member SHE2 side of the plurality of gate insulating films 130 of the plurality of semiconductor pillars 120 contained in one to the end of the inter-cell insulating member SHE2 side of the plurality of gate insulating films 130 of the plurality of semiconductor pillars 120 contained in the other. R3 Almost identical, and smaller than width Y R1 Y R2 .

[0168] For example, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE2, from the end of the inter-cell insulating member SHE2 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in one to the end of the inter-cell insulating member SHE2 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in the other. R3 Almost identical, and smaller than width Y R1 Y R2 .

[0169] Furthermore, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE2 are as follows: from the end of the high-dielectric-constant insulating film 103 corresponding to the plurality of semiconductor pillars 120 contained in one to the end of the inter-cell insulating film 103 corresponding to the plurality of semiconductor pillars 120 contained in the other. R3 Almost identical, and smaller than width Y R1 Y R2 .

[0170] The semiconductor memory device according to the third embodiment, like the one in the first embodiment, does not lead to a decrease in yield and can provide a semiconductor memory device that operates properly.

[0171] Furthermore, according to the third embodiment, compared with the second embodiment, the number of manufacturing steps can be further reduced.

[0172] [Fourth Implementation]

[0173] [constitute]

[0174] Figure 38 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fourth embodiment. Figure 39 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and showing a cut along line G-G'. Figure 38 The structure shown is an XY cross-section viewed along the direction of the arrow. Figure 39 The XY cross-section is shown, corresponding to the height position of conductive layer 110 (SGDT).

[0175] The semiconductor memory device of the fourth embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the fourth embodiment replaces the inter-cell insulation member SHE with an inter-cell insulation member SHE3.

[0176] The inter-unit insulation component SHE3 is basically constructed in the same way as the inter-unit insulation component SHE. However, the inter-unit insulation component SHE3 replaces regions R1 and R2, and has regions R4 and R5.

[0177] Region R4 is constructed in essentially the same way as region R1. However, unlike region R1, region R4 is not located at a height corresponding to one or more conductive layers 110 (SGDT). That is, region R4 extends in the Z direction within the height range corresponding to the multiple conductive layers 110 (SGD) and a portion of the conductive layers 110 (DWD), as well as the insulating layers 101 disposed on the upper and lower surfaces of these conductive layers 110, thus dividing the configuration in the Y direction. Furthermore, it is also possible that the interior of region R4 does not contain elements as described in the reference... Figure 4 The gap V is as described above.

[0178] Region R5 is constructed in essentially the same way as region R2. However, unlike region R2, region R5 is not located at a height corresponding to one or more conductive layers 110 (SGDT). That is, region R5 extends in the Z direction within the height range corresponding to the insulating layer 102, the plurality of conductive layers 110 (SGDT), and the insulating layer 101 disposed on their upper and lower surfaces, thus dividing the configuration in the Y direction.

[0179] Additionally, within the height range corresponding to region R5, such as Figure 39As illustrated, the distance and width Y in the Y direction of two adjacent semiconductor pillars SC separated by inter-cell insulating members SHE3 are as follows: from the end of the inter-cell insulating member SHE3 side of one of the plurality of semiconductor pillars 120 to the end of the inter-cell insulating member SHE3 side of the plurality of semiconductor pillars 120 in the other. R2 Almost identical, and smaller than width Y R1 .

[0180] Similarly, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by inter-cell insulating members SHE3 are as follows: from the end of the inter-cell insulating member SHE3 side of the plurality of gate insulating films 130 corresponding to the plurality of semiconductor pillars 120 contained in one to the end of the inter-cell insulating member SHE3 side of the plurality of gate insulating films 130 contained in the other. R2 Almost identical, and smaller than width Y R1 .

[0181] For example, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by inter-cell insulating members SHE3, from the end of the inter-cell insulating member SHE3 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in one to the end of the inter-cell insulating member SHE3 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in the other. R2 Almost identical, and smaller than width Y R1 .

[0182] Furthermore, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE3 are as follows: from the end of the high-dielectric-constant insulating film 103 corresponding to the multiple semiconductor pillars 120 contained in one to the end of the high-dielectric-constant insulating film 103 corresponding to the multiple semiconductor pillars 120 contained in the other. R2 Almost identical, and smaller than width Y R1 .

[0183] [Manufacturing Method]

[0184] Next, refer to Figures 40-42 The manufacturing method of the semiconductor memory device according to the fourth embodiment will be described. Figures 40-42 This is a schematic cross-sectional view used to illustrate the manufacturing method, and it shows the corresponding... Figure 38 The cross-section.

[0185] The semiconductor memory device of the fourth embodiment can be manufactured in essentially the same way as the semiconductor memory device of the first embodiment.

[0186] However, when manufacturing the semiconductor memory device of the fourth embodiment, in reference Figure 17 and Figure 18 In the steps described, such as Figure 40 As shown, a trench SHEE is formed instead of a trench SHEA. The trench SHEE extends in the Z and X directions, and divides the insulating layer 102, the plurality of conductive layers 110 (SGDT), and the insulating layer 101 disposed on their upper and lower surfaces in the Y direction, exposing the upper surface of the uppermost conductive layer 110 (SGD), as well as a portion of the semiconductor pillar 120, the gate insulating film 130, and the insulating pillar 127.

[0187] In addition, in reference Figure 21 and Figure 22 In the steps described, such as Figure 41 As shown, a trench SHEF is formed instead of a trench SHEC. The trench SHEF extends in the Z and X directions, and segments multiple conductive layers 110 (SGD), a portion of conductive layer 110 (DWD), and an insulating layer 101 disposed between them in the Y direction.

[0188] In addition, in reference Figure 23 and Figure 24 In the steps described, such as Figure 42 As shown, with multiple conductive layers 110 (SGDT) protected by a protective film SHEB, the width of the trench SHEF in the Y direction is increased at a height position corresponding to a portion of the multiple conductive layers 110 (SGD) and conductive layers 110 (DWD).

[0189] [Effect]

[0190] For reference Figure 1 As explained, the drain-side select gate line SGD is electrically independent for each string cell SU. This is because, as mentioned above, the drain-side select gate line SGD is used to select the string cell SU. On the other hand, the drain-side select gate line SGDT is electrically common to all string cells SU within the memory block BLK. This is because the drain-side select gate line SGDT is not used to select the string cell SU, but is used to generate GIDL (Gate Induced Drain Leakage) during the erase operation.

[0191] In other words, during the erasure operation, a positive erasure voltage is supplied to the semiconductor pillar 120, and the voltage of the conductive layer 110 (WL) is set to approximately the ground voltage, leading the charge accumulated in the charge accumulation film 132 to the electron conductive layer 110 (WL). Here, when the voltage of the semiconductor pillar 120 is greater than the voltage of the conductive layer 110 (WL), and the voltage difference is greater than a predetermined value, a hole channel (inversion layer) is formed on the outer peripheral surface of the semiconductor pillar 120. On the other hand, because the semiconductor pillar 120 is connected to the source line SL via the region 121 containing N-type impurities, holes cannot be directly supplied from the source line SL to the semiconductor pillar 120. Furthermore, because the semiconductor pillar 120 is connected to the bit line BL via the end region 124 containing N-type impurities, holes cannot be directly supplied from the bit line BL to the semiconductor pillar 120.

[0192] Therefore, during the erasure operation, with the voltage of the conductive layer 110 (WL) set to approximately the level of ground, in order to supply an erasure voltage to the semiconductor pillar 120, a reverse bias is supplied, for example, between the source line SL and the conductive layer 110 (SGSB), and between the bit line BL and the conductive layer 110 (SGDT). This provides a hole to the outer peripheral surface of the semiconductor pillar 120 by creating interband tunnels (GIDL) in region 121 and end region 124.

[0193] Here, the erase operation is performed primarily on a memory block (BLK) basis. Therefore, for example, during an erase operation, even the semiconductor pillar 120, which is located on one side of the Y-direction relative to the inter-cell insulation component (SHE), is erased. O The operation is not hindered by the electric field from the conductive layer 110 (SGDT) located on the opposite side of the inter-cell insulation member SHE in the Y direction. In other words, there is no need to increase the width of the inter-cell insulation member SHE in the Y direction at the height position corresponding to the conductive layer 110 (SGDT).

[0194] Furthermore, from the viewpoint of generating holes via GIDL, it is desirable to have a larger area of ​​the opposing surface between the semiconductor pillar 120 and the conductive layer 110 (SGDT). This is because the amount of holes generated per unit time via GIDL is proportional to the area of ​​this opposing surface. Therefore, at the height position corresponding to the conductive layer 110 (SGDT), the width of the inter-cell insulation component SHE in the Y direction is not increased, but the erasure operation can still be performed appropriately.

[0195] Therefore, in this embodiment, as referenced Figure 42As explained, with multiple conductive layers 110 (SGDT) protected by a protective film SHEB, the width of the trench SHEF in the Y direction is increased at a height position corresponding to a portion of the multiple conductive layers 110 (SGD) and conductive layers 110 (DWD). This method does not lead to a decrease in yield and provides a semiconductor memory device that can accommodate the selection of serial cells SU within the memory block BLK and appropriately perform the erase operation of the memory block BLK units.

[0196] Furthermore, in the fourth embodiment, the step of removing a portion of the high dielectric constant insulating film 103 via the trench SHEF is performed, similar to the first embodiment (see reference). Figure 24 ), the step of removing a portion of the semiconductor pillar 120 via the trench SHEF (see reference) Figure 27 The steps of removing a portion of the charge accumulation film 132 via trench SHEF (see reference) Figure 27 This allows for the provision of semiconductor memory devices that operate more appropriately. Furthermore, by setting the inner wall surface of the trench SHEF to a relatively flat state, insulating components SHED can be appropriately formed.

[0197] In addition, in the fourth embodiment, similar to the first embodiment, the step of removing a portion of the high dielectric constant insulating film 103 via the trench SHEF can be omitted (see reference). Figure 24 ), the step of removing a portion of the semiconductor pillar 120 via the trench SHEF (see reference) Figure 27 The steps of removing a portion of the charge accumulation film 132 via trench SHEF (see reference) Figure 27 At least one of them. This can also reduce the number of manufacturing steps.

[0198] [Fifth Implementation]

[0199] In the fourth embodiment, similar to the second embodiment, references may also be omitted. Figure 25 and Figure 26 The steps described herein will be explained. Hereinafter, a semiconductor memory device manufactured with the steps omitted will be illustrated as an example of the fifth embodiment.

[0200] Figure 43 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fifth embodiment.

[0201] The semiconductor memory device of the fifth embodiment is basically constructed in the same way as the semiconductor memory device of the fourth embodiment. However, the semiconductor memory device of the fifth embodiment replaces the inter-cell insulation member SHE3 with an inter-cell insulation member SHE4.

[0202] The inter-unit insulation component SHE4 is basically constructed in the same way as the inter-unit insulation component SHE3. However, instead of region R4, the inter-unit insulation component SHE4 has region R6.

[0203] Region R6 is constructed in essentially the same manner as region R4. However, in region R6, the width in the Y direction corresponding to the height positions of the plurality of conductive layers 110 (SGD) and a portion of the conductive layers 110 (DWD) is larger than the width in the Y direction corresponding to the height positions of the insulating layers 101 disposed on the upper and lower surfaces of these conductive layers 110. Furthermore, the width in the Y direction of region R6 corresponding to the height positions of these insulating layers 101 is smaller than the width in the Y direction. R2 .

[0204] Furthermore, region R6 does not include Figure 38 The gap V is as shown. However, the inter-cell insulation component SHE4 may also contain a gap V inside region R6.

[0205] Additionally, in region R6, as referenced... Figure 34 and Figure 35 As explained, the distance and width Y in the Y direction of two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE4 are as follows: from the end of the inter-cell insulating member SHE4 side of one of the plurality of semiconductor pillars 120 to the end of the inter-cell insulating member SHE4 side of the plurality of semiconductor pillars 120 in the other. R1 Almost identical, and larger than width Y R2 Y R3 .

[0206] Similarly, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE4 are as follows: from the end of the inter-cell insulating member SHE4 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in one to the end of the inter-cell insulating member SHE4 side of the multiple charge accumulation films 132 of the multiple semiconductor pillars 120 contained in the other. R1 Almost identical, and larger than width Y R2 Y R3 .

[0207] Furthermore, at the height position corresponding to the multiple conductive layers 110 (SGD) and a portion of the conductive layers 110 (DWD) in region R6, the distance and width Y in the Y direction between two adjacent semiconductor pillars SC separated by the inter-cell insulating member SHE4 are as follows: from the end of the high-dielectric-constant insulating film 103 corresponding to the multiple semiconductor pillars 120 contained in one to the end of the high-dielectric-constant insulating film 103 corresponding to the multiple semiconductor pillars 120 contained in the other. R1 Almost identical, and larger than width Y R2 , YR3 .

[0208] According to the fifth embodiment, similarly to the fourth embodiment, it does not lead to a decrease in yield and provides a semiconductor memory device that can accommodate the selection of serial cells SU within the memory block BLK and appropriately perform the erase operation of the memory block BLK units. Furthermore, the step of removing a portion of the high-dielectric-constant insulating film 103 via the trench SHEF is performed (see reference). Figure 24 ), the step of removing a portion of the semiconductor pillar 120 via the trench SHEF (see reference) Figure 27 The steps of removing a portion of the charge accumulation film 132 via trench SHEF (see reference) Figure 27 This allows for the provision of semiconductor memory devices that operate more appropriately.

[0209] Furthermore, according to the fifth embodiment, compared with the fourth embodiment, the number of manufacturing steps can be reduced.

[0210] In addition, in the fifth embodiment, similar to the fourth embodiment, the step of removing a portion of the high dielectric constant insulating film 103 via the trench SHEF can be omitted (see reference). Figure 24 ), the step of removing a portion of the semiconductor pillar 120 via the trench SHEF (see reference) Figure 27 The steps of removing a portion of the charge accumulation film 132 via trench SHEF (see reference) Figure 27 At least one of them. This can also reduce the number of manufacturing steps.

[0211] [Other Implementation Methods]

[0212] In both the first and fourth embodiments, the step of removing a portion of the conductive layer 110 can be performed in reverse order. Figure 23 , Figure 24 ), and the step of removing a portion of the insulating layer 101 ( Figure 25 , Figure 26In this case, the lower ends of regions R1 and R4 are disposed along the upper surface of any insulating layer 101, which is disposed between the lowermost conductive layer 110 (SGD) and the uppermost conductive layer (WL).

[0213] Furthermore, in both the first and fourth embodiments, the steps of removing a portion of the conductive layer 110 and removing a portion of the insulating layer 101 can be performed simultaneously. For example, a liquid or gas capable of removing both the conductive layer 110 and the insulating layer 101 can be used.

[0214] [other]

[0215] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, and are encompassed by the invention as described in the claims and their equivalents.

[0216] [Symbol Explanation]

[0217] 100, 101, 102, 104, 105 Insulation Layers

[0218] 110 conductive layer

[0219] 120 Semiconductor Pillar

[0220] 124 Region (End)

[0221] 127 Insulating Post

[0222] 130 gate insulating film

[0223] Ch contact electrode

[0224] SHE inter-unit insulation components

[0225] V-shaped gap.

Claims

1. A semiconductor memory device comprising: Multiple conductive layers are stacked in a stacking direction and extend in a first direction that intersects the stacking direction; The first semiconductor pillar extends in the stacking direction and faces the plurality of conductive layers, and contains impurities in a first end region on one side of the stacking direction; A first gate insulating film is disposed between the plurality of conductive layers and the first semiconductor pillar; The first contact electrode is connected to the first end region; The second semiconductor pillar, whose position in the second direction intersecting the stacking direction and the first direction is different from that of the first semiconductor pillar, extends in the stacking direction and faces the plurality of conductive layers, and contains impurities in the second end region on one side of the stacking direction; A second gate insulating film is disposed between the plurality of conductive layers and the second semiconductor pillar; The second contact electrode is connected to the second end region; and An insulating component, when viewed from the stacking direction, is disposed between the first semiconductor pillar and the second semiconductor pillar in a manner coinciding with a portion of the first semiconductor pillar and a portion of the second semiconductor pillar, and extends in the first direction, interrupting a portion of the conductive layer disposed on the side of the first contact electrode and the second contact electrode in the stacking direction in the second direction; and The first width in the second direction of the insulating member at the position corresponding to the stacking direction of the first conductive layer in the portion of the conductive layer is greater than the second width in the second direction of the insulating member at the position corresponding to the first end region and the second end region, and relative to the positions of the first contact electrode and the second contact electrode on the stacking direction of the plurality of conductive layers.

2. The semiconductor memory device according to claim 1, wherein The first width is the distance in the second direction between the two portions of the first conductive layer that are divided by the insulating component in the second direction; The second width is the distance in the second direction from the surface of the insulating component side of the first end region to the surface of the insulating component side of the second end region.

3. The semiconductor memory device according to claim 1, wherein The portion of the conductive layer further includes: a second conductive layer adjacent to the first conductive layer in the stacking direction, and the semiconductor memory device further comprises: A first insulating layer is disposed between the first conductive layer and the second conductive layer, and together with a portion of the conductive layer, is separated by the insulating component in the second direction; and The width of the insulating member in the second direction at the position corresponding to the stacking direction of the first insulating layer is greater than the second width.

4. The semiconductor memory device according to claim 3, wherein The width of the insulating member in the second direction at the position corresponding to the stacking direction of the first insulating layer is the distance in the second direction between the two portions of the first insulating layer that are divided by the insulating member in the second direction.

5. The semiconductor memory device according to claim 3, further comprising: A second insulating layer is disposed on the side of the first contact electrode and the second contact electrode in the stacking direction, relative to the plurality of conductive layers; The insulating component includes: A first region extends in the stacking direction within a range corresponding to the stacking direction of the first conductive layer, the second conductive layer, and the first insulating layer, thereby dividing the first conductive layer, the second conductive layer, and the first insulating layer in the second direction; and The second region extends in the stacking direction within a range corresponding to the stacking direction of the second insulating layer, thus severing the second insulating layer in the second direction; and The width of the first region in the second direction is greater than the width of the second region in the second direction.

6. The semiconductor memory device according to claim 1, wherein The portion of the conductive layer further includes: a second conductive layer adjacent to the first conductive layer in the stacking direction, and the semiconductor memory device further comprises: A first insulating layer is disposed between the first conductive layer and the second conductive layer, and together with a portion of the conductive layer, is separated by the insulating component in the second direction; and The width of the insulating member in the second direction at the position corresponding to the stacking direction of the first insulating layer is smaller than the first width.

7. The semiconductor memory device according to claim 6, wherein The width of the insulating member in the second direction at the position corresponding to the stacking direction of the first insulating layer is the distance in the second direction between the two portions of the first insulating layer that are divided by the insulating member in the second direction.

8. The semiconductor memory device according to claim 6, further comprising: A second insulating layer is disposed on the side of the first contact electrode and the second contact electrode in the stacking direction, relative to the plurality of conductive layers; The insulating component includes: A first region extends in the stacking direction within a range corresponding to the stacking direction of the first conductive layer, the second conductive layer, and the first insulating layer, thereby dividing the first conductive layer, the second conductive layer, and the first insulating layer in the second direction; and The second region extends in the stacking direction within a range corresponding to the stacking direction of the second insulating layer, thus severing the second insulating layer in the second direction; and The width of the first region in the second direction corresponding to the stacking direction of the first conductive layer and the second conductive layer is greater than the width of the second region in the second direction; The width of the first region in the second direction corresponding to the stacking direction of the first insulating layer is smaller than the width of the second region in the second direction.

9. The semiconductor memory device according to claim 1, wherein The distance in the second direction from the end of the first semiconductor pillar on the insulating member side in the second direction to the end of the second semiconductor pillar on the insulating member side in the second direction at the position corresponding to the stacking direction of the first conductive layer is greater than the second width.

10. The semiconductor memory device according to claim 1, wherein The distance in the second direction from the end of the first gate insulating film on the insulating member side in the second direction to the end of the second gate insulating film on the insulating member side in the second direction at the position corresponding to the stacking direction of the first conductive layer is greater than the second width.

11. The semiconductor memory device according to claim 1, wherein The conductive layer further includes: a third conductive layer disposed relative to the first conductive layer on the side of the first contact electrode and the second contact electrode, and The third width of the insulating component in the second direction at the position corresponding to the stacking direction of the third conductive layer is smaller than the first width.

12. The semiconductor memory device of claim 11, wherein... The third width is the distance in the second direction between the two portions of the third conductive layer that are divided by the insulating component in the second direction.

13. The semiconductor memory device according to claim 11, wherein The two portions of the first conductive layer that are separated by the insulating component in the second direction are electrically insulated from each other; The two portions of the third conductive layer, which are separated by the insulating component in the second direction, are electrically connected to each other.

14. The semiconductor memory device according to claim 3, wherein The conductive layer further includes a third conductive layer disposed on the side of the first contact electrode and the second contact electrode relative to the first conductive layer and the second conductive layer. The third width of the insulating member in the second direction at the position corresponding to the stacking direction of the third conductive layer is smaller than the first width; The width of the insulating member in the second direction at the position corresponding to the stacking direction of the first insulating layer is greater than the third width.

15. The semiconductor memory device according to claim 3, wherein The conductive layer further includes a third conductive layer disposed on the side of the first contact electrode and the second contact electrode relative to the first conductive layer and the second conductive layer, and the semiconductor memory device further comprises: A second insulating layer is disposed on the side of the first contact electrode and the second contact electrode in the stacking direction, relative to the plurality of conductive layers; The insulating component includes: A first region extends in the stacking direction within a range corresponding to the stacking direction of the first conductive layer, the second conductive layer, and the first insulating layer, thereby dividing the first conductive layer, the second conductive layer, and the first insulating layer in the second direction; and The second region extends in the stacking direction within a range corresponding to the stacking direction of the third conductive layer and the second insulating layer, thus separating the third conductive layer and the second insulating layer in the second direction; and The width of the first region in the second direction is greater than the width of the second region in the second direction.

16. The semiconductor memory device according to claim 6, wherein The conductive layer further includes a third conductive layer disposed on the side of the first contact electrode and the second contact electrode relative to the first conductive layer and the second conductive layer. The third width of the insulating member in the second direction at the position corresponding to the stacking direction of the third conductive layer is smaller than the first width; The width of the insulating member in the second direction at the position corresponding to the lamination direction of the first insulating layer is smaller than the third width.

17. The semiconductor memory device according to claim 6, wherein The conductive layer further includes a third conductive layer disposed on the side of the first contact electrode and the second contact electrode relative to the first conductive layer and the second conductive layer, and the semiconductor memory device further comprises: A second insulating layer is disposed on the side of the first contact electrode and the second contact electrode in the stacking direction, relative to the plurality of conductive layers; The insulating component includes: A first region extends in the stacking direction within a range corresponding to the stacking direction of the first conductive layer, the second conductive layer, and the first insulating layer, thereby dividing the first conductive layer, the second conductive layer, and the first insulating layer in the second direction; and The second region extends in the stacking direction within a range corresponding to the stacking direction of the third conductive layer and the second insulating layer, thus separating the third conductive layer and the second insulating layer in the second direction; and The width of the first region in the second direction corresponding to the stacking direction of the first conductive layer and the second conductive layer is greater than the width of the second region in the second direction; The width of the first region in the second direction corresponding to the stacking direction of the first insulating layer is smaller than the width of the second region in the second direction.

18. The semiconductor memory device of claim 11, wherein... The distance in the second direction from the end of the first semiconductor pillar on the insulating member side in the second direction to the end of the second semiconductor pillar on the insulating member side in the second direction at the position corresponding to the stacking direction of the third conductive layer is less than the first width.

19. The semiconductor memory device of claim 11, wherein The distance in the second direction from the end of the first gate insulating film in the second direction to the end of the second gate insulating film in the second direction of the insulating component side at the position corresponding to the stacking direction of the third conductive layer is less than the first width.

20. The semiconductor memory device according to claim 1, wherein The insulating component does not break the remaining portion of the conductive layer other than the portion of the conductive layer in the second direction.

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