Power semiconductor device and manufacturing method thereof
By employing a double-layer P-type capping layer structure and a diffusion barrier layer design in gallium nitride high electron mobility transistors, the problems of low gate leakage current and low breakdown voltage caused by high doping concentration of traditional P-type capping layers are solved, achieving higher device reliability and efficiency.
Patent Information
- Application Number
- CN202411126056.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2026-03-03
AI Technical Summary
The high doping concentration of traditional P-type capping layers in gallium nitride high electron mobility transistors leads to high gate leakage current and low breakdown voltage, affecting device performance and reliability.
A double-layer P-type capping structure is adopted. The first P-type capping layer has a high doping concentration, while the doping concentration of the second P-type capping layer decreases along the vertical and horizontal directions. The diffusion of dopants is controlled by a diffusion barrier layer to form a deep depletion region to reduce the peak electric field.
This reduces gate leakage current, improves breakdown voltage, and enhances device reliability.
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Figure CN121604477A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to power semiconductor devices, particularly power gallium nitride devices and methods for manufacturing the same. Background Technology
[0002] Compared to silicon, gallium nitride (GaN) exhibits a larger band gap, higher electron mobility, higher saturation electron velocity, and a higher breakdown electric field. GaN high electron mobility transistors are common power devices and are widely used in high-frequency applications such as radio frequency (RF) and microwave.
[0003] An existing gallium nitride high electron mobility transistor structure is as follows: Figure 1 As shown, the device includes a buffer layer above a substrate, a channel layer above the buffer layer, a barrier layer above the channel layer, a conventional P-type capping layer 104 above the barrier layer, and a gate metal layer 107 above the conventional P-type capping layer 104. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer below the heterojunction. A primary function of the conventional P-type capping layer 104 is to form a Schottky contact with the gate metal layer 107 above it, reducing the gate current when the gate is forward-biased. Another primary function of the conventional P-type capping layer 104 is to deplete the 2DEG located below it, forming an enhancement-mode device. To reduce the chance of the enhancement-mode device being falsely turned on, the threshold voltage needs to be sufficiently high. To achieve a high threshold voltage, the conventional P-type capping layer 104 generally requires a high doping concentration to enhance its ability to deplete the 2DEG located below it. However, when the gate is forward-biased, the depletion region of the conventional P-type capping layer 104 with a higher doping concentration is shallower. A spike electric field will be formed at the corner position 110 of the conventional P-type capping layer 104, resulting in higher gate leakage current and lower breakdown voltage, which affects the performance and reliability of the device. Summary of the Invention
[0004] To address the aforementioned problems, this invention provides a power semiconductor device comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, and a first P-type capping layer above the barrier layer. Above the first P-type capping layer, a diffusion barrier layer is located at an edge portion, and a second P-type capping layer is located in the middle portion. The second P-type capping layer includes a second P-type intermediate capping layer above the first P-type capping layer and second P-type side capping layers extending to both sides and covering the diffusion barrier layer. Above the second P-type capping layer, a gate metal layer is provided, along with a source metal layer on one side of the gate metal layer and a drain metal layer on the other side. The second P-type capping layer forms a Schottky contact with the gate metal layer. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction. The doping concentration of the first P-type capping layer is in the range of 1 x 10⁻⁶. 16 –1x10 21 cm -3 The second P-type capping layer is formed by diffusion of the doped material through the first P-type capping layer. The doping concentration decreases vertically from bottom to top and horizontally from the middle to the two edges.
[0005] Furthermore, by increasing the width of the diffusion barrier layer, an undoped region is formed above the diffusion barrier layer and outside the second P-type capping layers on both sides.
[0006] Furthermore, the peak electric field formed at the first and second surface corner positions when the gate is positively pressed can be adjusted by adjusting the width of the diffusion barrier layer on one side of the source metal layer and the width of the diffusion barrier layer on the other side of the drain metal layer.
[0007] Furthermore, the width of the diffusion barrier layer located on one side of the source metal layer is greater than the width of the diffusion barrier layer located on the other side of the drain metal layer.
[0008] The present invention also provides a method for manufacturing the above-mentioned power semiconductor device, the method comprising the following steps:
[0009] The first step is to form a buffer layer on the substrate, then form a channel layer on the buffer layer, and finally form a barrier layer on the channel layer.
[0010] In the first step, the substrate material is silicon, gallium nitride, silicon carbide, or sapphire; or
[0011] The buffer layer is one or more of aluminum gallium nitride, aluminum nitride, and gallium nitride, and also contains carbon (C) and iron (Fe) doping elements; or
[0012] The channel layer is often made of gallium nitride, and its band gap is smaller than that of the barrier layer above it; or
[0013] The barrier layer is made of aluminum gallium nitride, and its band gap is larger than that of the channel layer material located below it.
[0014] The second step is to form a preliminary first P-type capping layer above the barrier layer, and then form a preliminary diffusion barrier layer above the preliminary first P-type capping layer.
[0015] In the second step, the initial P-type capping layer is made of doped gallium nitride or doped aluminum gallium nitride, with the doping material containing magnesium or other suitable P-type doping elements; or
[0016] The materials used in the initial diffusion barrier layer include one or more of boron nitride, aluminum boron nitride, gallium boron nitride, and indium boron nitride.
[0017] The third step is to form a patterned second-step diffusion barrier layer on the surface of the initial diffusion barrier layer;
[0018] The fourth step is to form a preliminary second P-type capping layer on the surface of the two-step diffusion barrier layer 285. The preliminary second P-type capping layer is an unintentionally doped layer. Its doping material is formed by the diffusion of the doping material of the preliminary first P-type capping layer during the formation of the preliminary second P-type capping layer. Since the two-step diffusion barrier layer prevents the doping material of the preliminary first P-type capping layer from diffusing directly from bottom to top in the vertical direction to both sides of the preliminary second P-type capping layer, the doping material of the preliminary first P-type capping layer needs to first diffuse from bottom to top in the vertical direction to the middle part of the second P-type capping layer, and then diffuse from the middle to the left and right in the horizontal direction to both sides of the preliminary second P-type capping layer.
[0019] Fifth step, a preliminary gate metal layer is formed on the surface of the preliminary second P-type capping layer, and the preliminary gate metal layer forms a Schottky contact with the preliminary second P-type capping layer located below it;
[0020] Step 6: Etch the preliminary gate metal layer, the two sides of the preliminary second P-type capping layer, the preliminary first P-type capping layer and the two-step diffusion barrier layer to form patterned gate metal layer, patterned two sides of the second P-type capping layer, patterned diffusion barrier layer and patterned first P-type capping layer respectively.
[0021] The middle part of the second P-type cap layer and the two sides of the second P-type cap layer constitute the second P-type cap layer;
[0022] Step 7: A source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side. The source metal layer and the drain metal layer form an ohmic contact with the channel layer located below them.
[0023] In the seventh step, the source metal layer and the drain metal layer are composed of one or more metals, namely titanium, nickel, tungsten, aluminum, copper, platinum, and gold.
[0024] The P-type capping layer of this invention comprises upper and lower layers. The high doping concentration of the lower first P-type capping layer ensures that the threshold voltage of the device can reach a high value, reducing the chance of the enhancement-mode device being falsely turned on. The doping concentration of the upper second P-type capping layer decreases vertically from bottom to top and horizontally from the center to the left and right edges. Therefore, the doping concentration at the surface corners of the upper second P-type capping layer is lower. When the gate is forward-biased, the depletion region at the surface corners of the upper second P-type capping layer is deeper, resulting in a lower peak electric field. This design reduces gate leakage current and improves gate breakdown voltage and reliability. Attached Figure Description
[0025] Figure 1 This is a schematic cross-sectional view of an existing high electron mobility transistor structure.
[0026] Figures 2-3 This is a cross-sectional schematic diagram of the device structure according to an embodiment of the present invention.
[0027] Figure 4 This is a cross-sectional schematic diagram of the device structure according to another embodiment of the present invention.
[0028] Figures 5-6 This is a cross-sectional schematic diagram of the device structure according to another embodiment of the present invention.
[0029] Figures 7-13 This is an embodiment of a method for manufacturing the device structure of the present invention. Detailed Implementation
[0030] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the positional terms used in this document, such as "upper," "lower," "left," "right," "front," "back," "vertical," "horizontal," and "vertical," correspond to the relative positions shown in the reference drawings. A fixed orientation is not limited in specific implementations. The devices in the drawings are not necessarily drawn to scale. The straight lines representing the boundaries of doped regions and trenches in the drawings, as well as the sharp angles formed by these boundaries, are generally not straight lines or precise angles in practical applications.
[0031] Reference Figure 2 This is a cross-sectional schematic diagram of the device structure according to the first embodiment of the present invention, the structure including:
[0032] The substrate layer 200 is located at the bottom;
[0033] Buffer layer 201 located above substrate layer 200;
[0034] Channel layer 202 located above buffer layer 201;
[0035] Barrier layer 203 located above channel layer 202;
[0036] The first P-type capping layer 204 is located above the barrier layer 203;
[0037] A diffusion barrier layer 205 and a second P-type capping layer 206 located above the first P-type capping layer 204;
[0038] The second P-type capping layer 206 includes a middle portion 206a of the second P-type capping layer located only above the first P-type capping layer 204 and two side portions 206b of the second P-type capping layer located above the diffusion barrier layer 205. The second P-type capping layer 206 is formed by combining the middle portion 206a of the second P-type capping layer and the two side portions 206b of the second P-type capping layer.
[0039] Gate metal layer 107 located above the second P-type capping layer 206;
[0040] The source metal layer 208 is located to the left of the gate metal layer 107 and the drain metal layer 209 is located to the right of the gate metal layer 107;
[0041] In the above structure, the channel layer 202 and the barrier layer 203 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer 202 located below the heterojunction, forming a current channel between the source metal layer 208 and the drain metal layer 209 when the device is turned on.
[0042] In the above structure, the first P-type capping layer 204 depletes the two-dimensional electron gas on the surface of the channel layer 202 located below it when the device is turned off, forming an enhancement-type device.
[0043] In the above structure, the second P-type capping layer 206 forms a Schottky contact with the gate metal layer 107 located above it, which reduces the gate current when the gate is positively pressured.
[0044] In the above structure, the doping material of the first P-type capping layer 204 includes magnesium (Mg) or other suitable P-type doping elements, with a doping concentration ranging from 1 x 10⁻⁶. 16 –1x10 21 cm -3 The second P-type capping layer 206 is an unintentionally doped layer, and its doping material is formed by diffusion through the doping material of the first P-type capping layer 204. Therefore, the doping concentration of the second P-type capping layer 206 is lower than that of the first P-type capping layer 204.
[0045] In the above structure, the diffusion barrier layer 205 prevents the doped material of the first P-type capping layer 204 from directly diffusing from bottom to top along the vertical direction (y) to the two side portions 206b of the second P-type capping layer. The doped material of the first P-type capping layer 204 needs to first diffuse from bottom to top along the vertical direction (y) to the middle portion 206a of the second P-type capping layer, and then diffuse from the middle to the left and right along the horizontal direction (x) to the two side portions 206b of the second P-type capping layer. The material of the diffusion barrier layer 205 may include one or a combination of boron nitride (BN), aluminum boron nitride (AlBN), gallium boron nitride (GaBN), indium boron nitride (InBN), or other suitable materials.
[0046] In the above structure, the doping concentration of the second P-type capping layer decreases from bottom to top along the vertical direction (y) and from the center to the left and right edges along the horizontal direction (x). Therefore, as Figure 3 As shown, the surface corner position 110 of the second P-type capping layer is the position with the lowest doping concentration in the entire second P-type capping layer. When the gate is positively pressed, the depletion region of the surface corner position 110 of the second P-type capping layer will be deeper, and the resulting peak electric field will also be lower.
[0047] In the above structure, the sidewalls of the first P-type capping layer 204 and the second P-type capping layer 206 are formed by etching, and there are many defects on the surface of the wall. The peak electric field at the corner position 110 of the surface of the second P-type capping layer is low, which reduces the gate leakage current and improves the gate breakdown voltage and reliability.
[0048] Example 2
[0049] A variation of the device embodiment of the present invention is as follows: Figure 4 As shown, and Figure 3 The difference in this embodiment is that the diffusion barrier layer 205 has a larger width, and the second P-type capping layer 206 is composed of a middle portion 206a, two side portions 206b, and outer two side portions. The outer two side portions of the second P-type capping layer are undoped regions 206c.
[0050] In the above structure, the increased width of the diffusion barrier layer 205 can prevent the doped material of the first P-type capping layer 204 from diffusing horizontally from the middle to the left and right to the sidewall of the second P-type capping layer, thereby forming the undoped region on both sides of the second P-type capping layer 206c, further reducing the peak electric field formed at the corner of the surface of the second P-type capping layer when the gate is positively pressed.
[0051] Example 3
[0052] A variation of the device embodiment of the present invention is as follows: Figure 4 As shown, and Figure 3The difference in this embodiment is that the width (x1) of the diffusion barrier layer 205 near the source metal layer 208 is not the same as the width (x2) of the diffusion barrier layer 205 near the drain metal layer 209 (x1≠x2), as shown below. Figure 5 As shown.
[0053] In the above structure, different widths (x1) of the diffusion barrier layer 205 near the source metal layer 208 and (x2) of the diffusion barrier layer 205 near the drain metal layer 209 can be used to adjust the spike electric fields formed at the first surface corner position 211 near the source metal layer 208 and the second surface corner position 212 near the drain metal layer 209 when the gate is forward-biased, respectively. Figure 6 As shown.
[0054] In the above structure, the width (x2) of the diffusion barrier layer 205 near the drain metal layer 209 can be greater than the width (x1) of the diffusion barrier layer 205 near the source metal layer 208. This results in a lower doping concentration at the surface corner position 212 of the second P-type capping layer near the drain metal layer 209 compared to the doping concentration at the surface corner position 211 of the second P-type capping layer near the source metal layer 208. When the gate is forward biased, the depletion region at the surface corner position 212 of the second P-type capping layer near the drain metal layer 209 will be deeper, resulting in a lower peak electric field and fewer gate defects. Therefore, the drain-gate leakage current of the device is reduced, improving the reliability performance of the device under high temperature reverse bias (HTRB).
[0055] Those skilled in the art should know that the structural features mentioned in the various embodiments of the present invention above can be combined with each other to form more device structures of the present invention embodiments.
[0056] Example 4
[0057] Based on the structural features of the above-described embodiments of the present invention, and combined with existing gallium nitride high electron mobility transistor manufacturing processes, various methods for forming embodiments of the present invention can be obtained. An exemplary method for forming an embodiment of the present invention is as follows: Figure 7 -- Figure 13 As shown:
[0058] The first step involves forming a buffer layer 201 on the substrate layer 200, then forming a channel layer 202 on the buffer layer 201, and finally forming a barrier layer 203 on the channel layer 202. Figure 7 As shown.
[0059] The substrate 200 is typically made of silicon (Si), but may also be made of other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), or sapphire.
[0060] The buffer layer 201 may contain one or a combination of materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), and gallium nitride (GaN). This combination of materials may contain doping elements such as carbon (C) and iron (Fe), which helps to reduce crystal layer dislocations and leakage current.
[0061] The channel layer 202 is typically made of gallium nitride (GaN), but may also be made of other materials. Its band gap is smaller than that of the barrier layer 203 located above it.
[0062] The barrier layer 203 is typically made of aluminum gallium nitride (AlGaN), but may also be made of other materials. Its band gap is larger than that of the material of the channel layer 202 located below it.
[0063] The above-mentioned structures can be formed through processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth.
[0064] The second step involves forming a preliminary first P-type capping layer 294 above the barrier layer 203, followed by forming a preliminary diffusion barrier layer 295 above the preliminary first P-type capping layer 294, as follows: Figure 8 As shown.
[0065] The material of the initial first P-type capping layer 294 is typically doped gallium nitride (GaN), or possibly doped aluminum gallium nitride (AlGaN) or other materials, which contain magnesium (Mg) or other suitable P-type doping elements.
[0066] The material of the initial diffusion barrier layer 295 may include one or a combination of boron nitride (BN), aluminum boron nitride (AlBN), gallium boron nitride (GaBN), indium boron nitride (InBN), or other suitable materials.
[0067] The above-mentioned structures can be formed through processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth.
[0068] The third step involves performing photolithography, dry etching, and wet etching processes on the surface of the initial diffusion barrier layer 295 to form a patterned two-step diffusion barrier layer 285, such as... Figure 9 As shown.
[0069] The fourth step involves forming a preliminary second P-type capping layer 296 on the surface of the two-step diffusion barrier layer 285, such as... Figure 10As shown. The preliminary second P-type capping layer 296 is an unintentionally doped layer, and its dopant material is formed by the diffusion of the dopant material of the preliminary first P-type capping layer 294 during the formation of the preliminary second P-type capping layer 296. Because the two-step diffusion barrier layer 285 prevents the dopant material of the preliminary first P-type capping layer 294 from diffusing directly from bottom to top vertically to the two sides 296b of the preliminary second P-type capping layer, the dopant material of the preliminary first P-type capping layer 294 needs to first diffuse vertically from bottom to top to the middle part 206a of the second P-type capping layer, and then diffuse horizontally from the middle to the left and right sides 296b of the preliminary second P-type capping layer. The outer two sides 296c of the preliminary second P-type capping layer are undoped regions.
[0070] Alternatively, the width of the two-step diffusion barrier layer 285 can be increased, the width of the middle portion 206a of the second P-type capping layer can be reduced, and the width of the undoped regions on both sides of the initial second P-type capping layer 296c can be increased.
[0071] The above-mentioned structures can be formed through processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth.
[0072] Fifth step, forming a preliminary gate metal layer 197 on the surface of the preliminary second P-type capping layer 296, such as... Figure 11 As shown.
[0073] The initial gate metal layer 197 may be formed by processes such as vapor deposition and sputtering, and its constituent materials may include, but are not limited to, metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), and gold (Au), their alloys, their compounds, or other suitable materials.
[0074] Typically, the initial gate metal layer 197 forms a Schottky contact with the initial second P-type capping layer 296 located below it.
[0075] Step 6 involves photolithography, dry etching, and wet etching processes on the preliminary gate metal layer 197, the two side portions 296b of the preliminary second P-type capping layer, the preliminary first P-type capping layer 294, and the two-step diffusion barrier layer 285 to form patterned gate metal layer 107, patterned two side portions 206b of the second P-type capping layer, patterned diffusion barrier layer 205, and patterned first P-type capping layer 204, respectively. Figure 12 As shown.
[0076] The second P-type capping layer 206 is composed of the middle part 206a of the second P-type capping layer and the two side parts 206b of the second P-type capping layer.
[0077] Step 7: A source metal layer 208 is formed to the left of the gate metal layer 107 and a drain metal layer 209 is formed to the right of the gate metal layer 107, as follows: Figure 13 As shown.
[0078] The source metal layer 208 and the drain metal layer 209 may be formed by processes such as vapor deposition and sputtering, and their constituent materials may include, but are not limited to, metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), and gold (Au), their alloys, their compounds, or other suitable materials.
[0079] The methods for forming the patterned source metal layer 208 and drain metal layer 209 may include photolithography, dry etching, wet etching and other process steps.
[0080] Typically, the source metal layer 208 and the drain metal layer 209 form an ohmic contact with the channel layer 202 located below them.
[0081] Those skilled in the art will understand that the above manufacturing steps only list the key steps and do not show the complete process for forming the device. Specific, detailed manufacturing steps can be derived from common manufacturing processes and general knowledge, and can be appropriately added to, subtracted from, or modified.
Claims
1. A power semiconductor device, the device comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, and a first P-type capping layer above the barrier layer; characterized in that, Above the first P-type capping layer, there is a diffusion barrier layer located at the edge and a second P-type capping layer located in the middle. The second P-type capping layer includes a second P-type intermediate capping layer above the first P-type capping layer and second P-type side capping layers extending to both sides and covering the diffusion barrier layer. Above the second P-type capping layer, there is a gate metal layer, a source metal layer on one side of the gate metal layer, and a drain metal layer on the other side. The second P-type capping layer forms a Schottky contact with the gate metal layer. The channel layer and the barrier layer form a heterojunction, and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction. The doping concentration of the first P-type capping layer is in the range of 1x10⁻¹⁰. 16 –1x10 21 cm -3 The second P-type capping layer is formed by diffusion of the doped material through the first P-type capping layer. The doping concentration decreases vertically from bottom to top and horizontally from the middle to the two edges.
2. The power semiconductor device as described in claim 1, characterized in that, The width of the diffusion barrier layer is increased to form an undoped region above the diffusion barrier layer and outside the second P-type capping layers on both sides.
3. The power semiconductor device as described in claim 1, characterized in that, The spike electric field formed at the first and second surface corner positions when the gate is positively pressed is adjusted by adjusting the width of the diffusion barrier layer on one side of the source metal layer and the width of the diffusion barrier layer on the other side of the drain metal layer.
4. The power semiconductor device as described in claim 3, characterized in that, The width of the diffusion barrier layer located on one side of the source metal layer is greater than the width of the diffusion barrier layer located on the other side of the drain metal layer.
5. The method for manufacturing the power semiconductor device according to any one of claims 1-4, characterized in that, The manufacturing method includes the following steps: The first step is to form a buffer layer on the substrate, then form a channel layer on the buffer layer, and finally form a barrier layer on the channel layer. The second step is to form a preliminary first P-type capping layer above the barrier layer, and then form a preliminary diffusion barrier layer above the preliminary first P-type capping layer. The third step is to form a patterned second-step diffusion barrier layer on the surface of the initial diffusion barrier layer; The fourth step is to form a preliminary second P-type capping layer on the surface of the two-step diffusion barrier layer. The preliminary second P-type capping layer is an unintentionally doped layer. Its doping material is formed by the diffusion of the doping material of the preliminary first P-type capping layer during the formation of the preliminary second P-type capping layer. Since the two-step diffusion barrier layer prevents the doping material of the preliminary first P-type capping layer from diffusing directly from bottom to top in the vertical direction to both sides of the preliminary second P-type capping layer, the doping material of the preliminary first P-type capping layer needs to first diffuse from bottom to top in the vertical direction to the middle part of the second P-type capping layer, and then diffuse from the middle to the left and right in the horizontal direction to both sides of the preliminary second P-type capping layer. Fifth step, a preliminary gate metal layer is formed on the surface of the preliminary second P-type capping layer, and the preliminary gate metal layer forms a Schottky contact with the preliminary second P-type capping layer located below it; The sixth step involves etching the preliminary gate metal layer, the two sides of the preliminary second P-type capping layer, the preliminary first P-type capping layer, and the two-step diffusion barrier layer to form patterned gate metal layer, patterned two sides of the second P-type capping layer, patterned diffusion barrier layer, and patterned first P-type capping layer, respectively. The middle part of the second P-type cap layer and the two sides of the second P-type cap layer constitute the second P-type cap layer; Step 7: A source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side. The source metal layer and the drain metal layer form an ohmic contact with the channel layer located below them.
6. The method for manufacturing a power semiconductor device as described in claim 5, characterized in that, In the first step, the substrate material is silicon, gallium nitride, silicon carbide, or sapphire; or The buffer layer is one or more of aluminum gallium nitride, aluminum nitride, and gallium nitride, and also contains carbon (C) and iron (Fe) doping elements; or The channel layer is often made of gallium nitride, and its band gap is smaller than that of the barrier layer above it; or The barrier layer is made of aluminum gallium nitride, and its band gap is larger than that of the channel layer material located below it.
7. The method for manufacturing a power semiconductor device as described in claim 5, characterized in that, In the second step, the material of the initial first P-type capping layer is doped gallium nitride or doped aluminum gallium nitride, and the doping material includes magnesium or other suitable P-type doping elements. or The materials used in the initial diffusion barrier layer include one or more of boron nitride, aluminum boron nitride, gallium boron nitride, and indium boron nitride.
8. The method for manufacturing a power semiconductor device as described in claim 5, characterized in that, In the seventh step, the source metal layer and the drain metal layer are composed of one or more metals, namely titanium, nickel, tungsten, aluminum, copper, platinum, and gold.