Integrated circuit device and method of forming integrated circuit device

Abstract

Integrated circuit devices and methods of forming integrated circuit devices are provided. The integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first transistor and the second transistor includes a plurality of channel patterns extending between the source / drain regions in the first direction and alternately stacked with the gate patterns in the second direction. Respective lengths of the channel pattern, the gate pattern, and / or the inner spacer at opposite ends of the gate pattern differ along the first direction for at least one of the first transistor and the second transistor. Related devices and methods of manufacture are also discussed.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 683,002, filed August 14, 2024, entitled “Stacked Transistors Having Independently Adjustable Gate Lengths, Channel Lengths, and Inner Spacer Lengths and the Methods of Manufacturing the Same,” and U.S. Patent Application No. 19 / 049,440, filed February 10, 2025, with the U.S. Patent and Trademark Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to integrated circuit devices. Background Technology

[0003] Integrated circuit devices can utilize stacked transistors to increase density and improve performance. In some cases, the stacked transistors can be complementary to each other (e.g., complementary metal-oxide-semiconductor (CMOS) transistors). For example, a complementary field-effect transistor (FET) (CFET) layout may include multiple vertically stacked pairs of fully all-around gate field-effect transistors (GAAFETs) having a P-type GAAFET at one height, an N-type GAAFET at another height (i.e., above or below), and a shared gate, wherein each shared gate extends between and wraps around the channel pattern of the N-type and P-type GAAFETs in the stacked pair. In such a structure, the source / drain region of the lower GAAFET is electrically isolated from the source / drain region of the upper GAAFET by a dielectric layer. The gate, channel pattern, and isolation structure (including the spacer between the gate and the source / drain region) may be dimensionally similar between the upper and lower devices of the stacked transistors. Summary of the Invention

[0004] According to some embodiments, an integrated circuit device includes: a substrate; and a stacked transistor structure on the substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes one or more channel patterns that extend between source / drain regions in a first direction and are alternately stacked with one or more gate patterns in a second direction. For at least one of the first and second transistors, the respective lengths of the plurality of channel patterns and the plurality of gate patterns are different along the first direction.

[0005] In some embodiments, at least one of the first transistor and the second transistor is the second transistor, and the respective lengths of the plurality of channel patterns of the second transistor are shorter than the respective lengths of the plurality of channel patterns of the first transistor.

[0006] In some embodiments, for the at least one of the first transistor and the second transistor, the corresponding length of at least one of the plurality of channel patterns is shorter than the corresponding length of the channel patterns above and below the at least one channel pattern in the second direction of the plurality of channel patterns.

[0007] In some embodiments, at least one of the first and second transistors includes a plurality of inner spacers located in a first direction between opposite ends of the plurality of gate patterns of the at least one of the first and second transistors and the source / drain regions. The respective lengths of the plurality of inner spacers differ along the first direction for the at least one of the first and second transistors.

[0008] In some embodiments, at least one of the first transistor and the second transistor is the second transistor, and the respective lengths of the plurality of inner spacers of the second transistor are shorter than the respective lengths of the plurality of inner spacers of the first transistor.

[0009] In some embodiments, for the at least one of the first transistor and the second transistor, the corresponding length of at least one of the plurality of inner spacers is shorter than the corresponding length of the inner spacers above and below the at least one inner spacer in a second direction.

[0010] In some embodiments, for at least one of the first and second transistors, the respective lengths of the plurality of channel patterns and the plurality of gate patterns are different along a first direction.

[0011] In some embodiments, at least one of the first transistor and the second transistor is the second transistor, and the respective lengths of the plurality of gate patterns of the second transistor are shorter than the respective lengths of the plurality of gate patterns of the first transistor.

[0012] In some embodiments, for the at least one of the first transistor and the second transistor, the corresponding length of at least one of the plurality of gate patterns is shorter than the corresponding lengths of the gate patterns above and below the at least one gate pattern in a second direction.

[0013] In some embodiments, the plurality of channel patterns, the plurality of gate patterns, and the source / drain regions are the lower nanosheet, lower gate pattern, and lower source / drain region of a first transistor, and the upper nanosheet, upper gate pattern, and upper source / drain region of a second transistor.

[0014] In some embodiments, the lower source / drain region has a first conductivity type, and the upper source / drain region has a second conductivity type opposite to the first conductivity type.

[0015] According to some embodiments, a method of forming an integrated circuit device includes forming a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes one or more channel patterns extending between source / drain regions in a first direction and alternately stacked with one or more gate patterns in a second direction. For at least one of the first and second transistors, the respective lengths of the plurality of channel patterns and the plurality of gate patterns are different along the first direction.

[0016] In some embodiments, the step of forming a stacked transistor structure includes: forming a plurality of stacked channel layers on a substrate; and performing at least one etching process on the plurality of channel layers to form the plurality of channel patterns of the at least one transistor of a first transistor and a second transistor, the plurality of channel patterns having corresponding lengths different along a first direction.

[0017] In some embodiments, the step of performing the at least one etching process includes performing a tapered etching process on the plurality of channel layers such that the corresponding length of at least one channel pattern of the plurality of channel patterns of the second transistor is 10% or more shorter than the corresponding length of at least one channel pattern of the plurality of channel patterns of the first transistor.

[0018] In some embodiments, the step of performing the at least one etching process includes: performing a first etching process on the plurality of channel layers; and performing a bowl-shaped etching process on the plurality of channel patterns of the at least one transistor in the first transistor and the second transistor, such that the corresponding length of at least one channel pattern in the plurality of channel patterns is shorter than the corresponding length of the channel patterns in the plurality of channel patterns above and below the at least one channel pattern in a second direction.

[0019] In some embodiments, at least one of the first transistor and the second transistor is the second transistor, and the method further includes: epitaxially growing source / drain regions of the first transistor at opposite ends of the plurality of channel patterns of the first transistor after performing a first etching process; forming an etch stop layer on the source / drain regions of the first transistor before performing a bowl-shaped etching process on the plurality of channel patterns of the second transistor; and epitaxially growing source / drain regions of the second transistor at opposite ends of the plurality of channel patterns of the second transistor after performing the bowl-shaped etching process.

[0020] In some embodiments, the plurality of gate patterns of the second transistor include a plurality of sacrificial gate patterns having a plurality of inner spacers at opposite ends of the plurality of sacrificial gate patterns, and wherein, in response to a bowl-shaped etching process, a corresponding length of at least one of the plurality of inner spacers is shorter than the corresponding lengths of the inner spacers above and below the at least one inner spacer in a second direction.

[0021] In some embodiments, the plurality of gate patterns of the second transistor include a plurality of sacrificial gate patterns without inner spacers at opposite ends of the plurality of sacrificial gate patterns, and wherein, in response to a bowl-shaped etching process, the corresponding length of at least one of the plurality of sacrificial gate patterns is shorter than the corresponding lengths of the sacrificial gate patterns above and below the at least one sacrificial gate pattern in a second direction.

[0022] In some embodiments, the plurality of channel patterns, the plurality of gate patterns, and the source / drain regions include a lower nanosheet, a lower gate pattern, and a lower source / drain region of a first transistor, and an upper nanosheet, an upper gate pattern, and an upper source / drain region of a second transistor, wherein the lower source / drain region has a first conductivity type, and the upper source / drain region has a second conductivity type opposite to the first conductivity type.

[0023] According to some embodiments, a method of forming an integrated circuit device includes: forming a plurality of alternately stacked channel layers and sacrificial layers on a substrate; performing a first etching process on the plurality of channel layers and sacrificial layers to form a plurality of channel patterns and a plurality of sacrificial gate patterns, the plurality of channel patterns extending in a first direction and the plurality of sacrificial gate patterns being alternately stacked with each other in a second direction; and performing a second etching process on at least one subset of a first subset of the plurality of channel patterns corresponding to a first transistor and a second subset of the plurality of channel patterns corresponding to a second transistor stacked on the first transistor. In response to the second etching process, the respective lengths of the plurality of channel patterns in the first subset and the at least one subset of the second subset are different along the first direction.

[0024] In some embodiments, the at least one subset of the first subset and the second subset is the second subset, and the method further includes: epitaxially growing source / drain regions of a first transistor at opposite ends of the plurality of channel patterns in the first subset after performing a first etching process; forming an etch stop layer on the source / drain regions of the first transistor before performing a second etching process on the plurality of channel patterns in the second subset; and epitaxially growing source / drain regions of a second transistor at opposite ends of the plurality of channel patterns in the second subset after performing the second etching process. In response to the second etching process, a corresponding length of at least one channel pattern in the plurality of channel patterns of the second subset is shorter than the corresponding lengths of channel patterns in the plurality of channel patterns of the second subset above and below the at least one channel pattern in a second direction.

[0025] In some embodiments, the plurality of sacrificial gate patterns between the plurality of channel patterns of the second subset include a plurality of inner spacers at opposite ends of the plurality of sacrificial gate patterns, and in response to a second etching process, a corresponding length of at least one of the plurality of inner spacers is shorter than the corresponding lengths of the inner spacers above and below the at least one inner spacer in a second direction.

[0026] In some embodiments, the plurality of sacrificial gate patterns between the plurality of channel patterns of the second subset have no inner spacers at the opposite ends of the plurality of sacrificial gate patterns, and in response to the second etching process, the corresponding length of at least one of the plurality of sacrificial gate patterns is shorter than the corresponding length of the sacrificial gate patterns above and below the at least one sacrificial gate pattern in the second direction.

[0027] After reviewing the accompanying drawings and detailed description, other apparatuses, devices, and / or methods according to some embodiments will become apparent to those skilled in the art. All such additional embodiments, in addition to any and all combinations of the embodiments described above, are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Attached Figure Description

[0028] Figure 1A and Figure 1B This is a schematic cross-sectional view illustrating various configurations of a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0029] Figure 2A , Figure 2B and Figure 2C This is a schematic cross-sectional view illustrating various configurations of a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0030] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H and Figure 3I This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0031] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor integrated circuit apparatus according to a further embodiment of the present disclosure.

[0032] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E1 , Figure 5E2 , Figure 5F1 and Figure 5F2 This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor integrated circuit apparatus according to a further embodiment of the present disclosure.

[0033] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0034] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor integrated circuit device according to a further embodiment of the present disclosure.

[0035] Figure 8A and Figure 8B This is a schematic cross-sectional view showing a semiconductor integrated circuit device according to a comparative example. Detailed Implementation

[0036] In the embodiments described herein, the stacked transistor structure may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor), and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other (e.g., CMOS transistors), and in some embodiments, the stacked transistor may be a stack of CMOS transistors or may include a stack of CMOS transistors. The first and second transistors may be stacked in any order (e.g., the first transistor on top of the second transistor, or the second transistor on top of the first transistor) to produce a stack including a top device (also referred to herein as an upper device or upper transistor relative to the underlying substrate) and a bottom device (also referred to herein as a lower device or lower transistor relative to the underlying substrate). The gate, channel, source / drain regions, and inner spacers of the upper and lower devices may also be referred to by the terms "upper" and "lower" (e.g., upper gate / lower gate, upper channel / lower channel, upper source / drain region / lower source / drain region, and upper inner spacer / lower inner spacer).

[0037] Some embodiments of this disclosure may be derived from the understanding that the gate, source / drain (S / D) regions, and inner spacers (between the gate and S / D regions) of both the upper and lower devices of some stacked transistors can typically be formed simultaneously using the same process. That is, the upper gate and lower gate can be formed simultaneously using the same process; the upper channel region and lower channel region can be formed simultaneously using the same process; and the upper inner spacer and lower inner spacer can be formed simultaneously using the same process.

[0038] As a result, the lengths of the gate, channel, and inner spacers of the upper and lower devices (measured along the extension direction of the channel between the source / drain (S / D) regions) may not be independently (e.g., individually) adjustable. For example, the gate, channel, and inner spacers of some upper and lower devices (including the uppermost, lowermost, and middle gate, channel, and inner spacers of each device) may each have substantially the same length. As a more specific example and referring to... Figures 8A to 8B The semiconductor device 800 shown (wherein) Figure 8B yes Figure 8A(Enlarged view of region 8B in the diagram), the length of each of the gate patterns 802 in the first direction D1 can be T1, the length of each of the channels 804 in the first direction D1 can be T2, and the length of each of the inner spacers 806 in the first direction D1 can be T3. Furthermore, the lengths of the channels and / or the thicknesses of the inner spacers on the substrate (upper) of the upper and lower devices can be substantially the same. Here, the length of the channel can represent the extension distance of the channel between the S / D regions at opposite ends of the channel (i.e., the separation distance between the S / D regions); the length of the gate can represent the extension distance of the gate electrode along the channel; and the length of the inner spacer can represent the extension distance of the inner spacer along the extension direction of the channel between the corresponding gate electrode and the corresponding S / D region. Depending on the orientation of the device or sublayer of the device, the length can also be referred to as the width or thickness.

[0039] Embodiments of this disclosure provide integrated circuit devices having a stacked transistor structure, such as a 3D stacked FET (3DSFET) constructed in CMOS, the stacked transistor structure having gates, channels, and / or inner spacers that are asymmetrical (e.g., have different lengths or thicknesses) between upper and lower devices and / or between components of the upper and lower devices. For example, the lower gate may be formed longer than the upper gate (or vice versa); the lower channel may be formed longer than the upper channel (or vice versa); and / or the lower inner spacer may be formed longer than the upper inner spacer (or vice versa).

[0040] For example, by forming a profile of stacked transistors (e.g., 3DSFETs) with a tapered shape (e.g., formed by a tapered or isotropic etching process), some embodiments can provide upper and lower devices of stacked transistors with independently controllable gate / channel / inner spacer lengths. For example, the profile may have a trapezoidal shape in cross-sectional view. In some examples, the uppermost lower gate among the lower gates may be longer than the lowermost upper gate among the upper gates; the uppermost lower channel among the lower channels may be longer than the lowermost upper channel among the upper channels; and / or the uppermost lower inner spacer among the lower inner spacers may be longer than the lowermost upper inner spacer among the upper inner spacers. That is, each of the upper gates and each of the lower gates may have different lengths; each of the upper channels and each of the lower channels may have different lengths; and / or each of the upper inner spacers and each of the lower inner spacers may have different lengths.

[0041] For example, by forming the upper and / or lower S / D regions using a bowl etching process (using plasma), followed by epitaxial growth of the S / D regions, some embodiments can provide upper and lower devices of stacked transistors with independently controllable gate / channel / inner spacer lengths. In some embodiments, due to the characteristics of the bowl etching process, the S / D regions (e.g., the upper and / or lower S / D regions) may protrude toward the channels and inner spacers. As a result, the intermediate gate may include the shortest gate, the intermediate channel may include the shortest channel, and the intermediate inner spacer may include the shortest inner spacer. For example, the middle upper gate in the upper gate may include the shortest upper gate; the middle lower gate in the lower gate may include the shortest lower gate; the middle upper channel in the upper channel may include the shortest upper channel; the middle lower channel in the lower channel may include the shortest lower channel; the middle upper inner spacer in the upper inner spacer may include the shortest upper inner spacer; and / or the middle lower inner spacer in the lower inner spacer may include the shortest lower inner spacer. When the cup-shaped etching process is applied to the upper device, the upper inner spacer, upper gate, and / or upper channel may be shorter than the lower inner spacer, lower gate, and / or lower channel, respectively. When the cup-shaped etching process is applied to the lower device, the lower inner spacer, lower gate, and / or lower channel may be shorter than the upper inner spacer, upper gate, and / or upper channel, respectively.

[0042] Therefore, (depending on whether the bowl-shaped etching is applied to the upper or lower device, and the amount or duration of the bowl-shaped etching) the gate length, channel length, and inner spacer length (or thickness) of the upper device may be shorter or longer than the gate length, channel length, and inner spacer length of the lower device. In some embodiments, some of the inner spacers may be omitted or completely replaced by S / D regions. Even without inner spacers, the shortest upper channel may be included in the middle of the upper channel, and the shortest lower channel may be included in the middle of the lower channel.

[0043] In other words, embodiments of this disclosure can provide an integrated circuit device with a stacked transistor structure, in which, with or without internal spacers, the gate length of the upper device is shorter than the gate length of the lower device (and may vary within each device stack). In embodiments with internal spacers, the gate length (along the channel length direction) of the upper device and / or the length of the internal spacers may be shorter than or longer than the gate length and / or the length of the internal spacers of the lower device (and / or may vary within each device stack); the length of the internal spacers (along the channel length direction) in the upper or lower device may be thinnest (or narrowest) at the midpoint of each device stack; and / or the channel length of the upper or lower device may be shortest at the midpoint of each device stack. In embodiments where at least one of the upper and lower devices lacks or omits internal spacers (or is replaced by source / drain regions), the gate length and / or channel length of the upper or lower device may be shortest at the midpoint of each device stack.

[0044] Figure 1A and Figure 1B This is a cross-sectional view illustrating an example configuration of a semiconductor integrated circuit device 100 according to some embodiments of the present disclosure. Figures 1A to 1B (in Figure 1B yes Figure 1A As shown in the enlarged view of region 1B in the figure, the integrated circuit device includes a stacked transistor structure 101 comprising a first transistor 102 and a second transistor 104 vertically stacked on a substrate 106 (e.g., the upper surface 106U of the substrate 106). The first transistor 102 includes at least one first channel pattern 108 (e.g., at least one lower nanosheet or a first subset of channel patterns corresponding to the first transistor 102) between gate patterns (e.g., conductive gate patterns) 107. The second transistor 104 includes at least one second channel pattern 110 (e.g., at least one upper nanosheet or a second subset of channel patterns corresponding to the second transistor 104) between conductive gate patterns 107. Figures 1A to 1B In the example, multiple second channel patterns 110 are stacked on multiple first channel patterns 108, and gate patterns 107 are alternately stacked between channel patterns 108 and 110 (e.g., lower gate patterns are alternately stacked between first channel patterns 108, and upper gate patterns are alternately stacked between second channel patterns 110), but embodiments of this disclosure may include fewer or more channel patterns 108 and 110 than shown. Channel patterns 108 and 110 may be provided of a semiconductor material, such as silicon (Si). Gate contact structures may be electrically connected to gate pattern 107.

[0045] The stacked transistor structure 101 may further include inner spacers 112 and additional semiconductor (e.g., Si) layers and insulating (e.g., SiN, SiO) layers stacked on channel patterns 108 and 110, the inner spacers 112 being between adjacent first channel patterns 108 and / or second channel patterns 110 (e.g., formed of insulating or dielectric materials (e.g., SiOCN or other low-k dielectric materials)). It should be understood that in some embodiments, the inner spacers 112 may be omitted from the first transistor 102 and / or second transistor 104. As an example, the inner spacers 112 may be between adjacent first channel patterns 108 in the first channel pattern 108, and the second channel pattern 110 may be without inner spacers 112 therebetween. As another example, the inner spacers 112 may be between adjacent second channel patterns 110 in the second channel pattern 110, and the first channel pattern 108 may be without inner spacers 112 therebetween.

[0046] A first (or lower) source / drain region 114 of the first transistor 102 having a first conductivity type (e.g., n-type) is disposed on the opposite side (also referred to herein as the opposite end) of the first channel pattern 108, and a second (or upper) source / drain region 116 of the second transistor 104 having a second conductivity type opposite to the first conductivity type (e.g., p-type) is disposed on the opposite side or end of the second channel pattern 110. In some embodiments, the first source / drain region 114 may comprise the same material or material composition as the first channel pattern 108 and the substrate 106. For example, the first channel pattern 108 and the first source / drain region 114 may be implemented as a silicon layer. In some embodiments, the second source / drain region 116 may comprise a different material or material composition than the first source / drain region 114. For example, the second channel pattern 110 may be implemented as a silicon-germanium (SiGe) layer. In some embodiments, refer to the following... Figures 3A to 3I As described in further detail, the first source / drain region 114 and the second source / drain region 116 have a trapezoidal shape in cross-sectional view and are formed by a tapered or isotropic etching process. In some embodiments, see below. Figure 2C In further detail, the first source / drain region 114 and the second source / drain region 116 may extend between portions of the conductive gate pattern 107 and directly contact the first channel pattern 108 and the second channel pattern 110 when the inner spacer 112 is omitted. The first channel pattern 108 and the second channel pattern 110 may extend in a first direction D1 and are respectively between the source / drain regions 114 and 116.

[0047] The source / drain contact structure may be disposed on the first source / drain region 114 and the second source / drain region 116, and electrically connected to the first source / drain region 114 and the second source / drain region 116. The source / drain contact structures may be electrically isolated from each other and electrically isolated from the gate contact structure.

[0048] exist Figures 1A to 1B In the example, the first (or lower) transistor 102 and the second (or upper) transistor 104 have complementary conductivity types (e.g., to configure a CMOS device). Specifically, the first transistor 102 may have a first conductivity type (e.g., n-type), while the second transistor 104 may have a second conductivity type opposite to the first conductivity type (e.g., p-type), or vice versa. That is, the stacked transistor structure 101 according to embodiments of the present disclosure is not limited to the specific orientation of transistors with different conductivity types. Furthermore, in some embodiments, the first transistor 102 and the second transistor 104 may have the same conductivity type (e.g., both the first transistor 102 and the second transistor 104 may be n-type, or both the first transistor 102 and the second transistor 104 may be p-type). Moreover, although described with reference to the first transistor 102 and the second transistor 104, it will be understood that the stacked transistor structure 101 according to embodiments of the present disclosure is not limited to a dual-transistor arrangement and may include additional transistors (e.g., a third transistor, a fourth transistor, etc.) vertically stacked on the substrate 106.

[0049] Still refer to Figures 1A to 1B The first isolation pattern 120 may include an insulating (e.g., oxidized) material and may be disposed between the first channel pattern 108 and the second channel pattern 110. The second isolation pattern 122 may be disposed on the upper surface of the first source / drain region 114 and the lower surface of the second source / drain region 116. The first isolation pattern 120 between the first channel pattern 108 and the second channel pattern 110 and the second isolation pattern 122 between the second source / drain region 116 and the first source / drain region 114 together define a device isolation pattern 124, which provides electrical isolation between the first transistor 102 and the second transistor 104. Even when the contact polysilicon pitch (CPP) is reduced and / or the aspect ratio (A / R) is increased, the device isolation pattern 124, including the first isolation pattern 120 and the second isolation pattern 122, as described herein, can efficiently provide electrical isolation between the first transistor 102 and the second transistor 104. Although not shown, it should be understood that an additional isolation pattern may be provided on the upper surface of the second source / drain region 116.

[0050] For example Figures 1A to 1BAs shown, an insulating region 126 (e.g., a leakage protection region) is disposed on the substrate 106 adjacent to the opposite side of the first channel pattern, such that the first source / drain region 114 is located between the second source / drain region 116 and the insulating region 126. The insulating region 126 may be implemented by forming one or more insulating patterns in or on the substrate 106. For example, as shown below... Figures 3A to 3F , Figures 4A to 4F and Figures 5A to 5F2 In some embodiments described in more detail, the substrate 106 may include a recessed surface adjacent to the opposite side of the first channel pattern 108, and an insulating pattern may at least partially fill the recessed surface to provide the insulating region 126. In some embodiments, the insulating pattern may be an oxide-based pattern (e.g., silicon oxide) or a nitride-based pattern (e.g., silicon nitride). Other insulating materials (e.g., SiO2, SiON, SiOCN, SiBCN, SiCN, etc.) may also be used as the insulating pattern, such that the insulating region 126 may be the same material as the first isolation pattern 120 and / or the second isolation pattern 122 or a different material. The insulating region 126 is thus disposed between the first source / drain region 114 and the substrate 106.

[0051] In some embodiments, the inner spacer 112, the first channel pattern 108 and the second channel pattern 110, and the conductive gate pattern 107 extend in a first direction D1 parallel to the lower surface 106L of the substrate 106. For at least one of the first transistor 102 and the second transistor 104, the respective lengths of the channel pattern 108 or 110, the gate pattern 107, and / or the inner spacer 112 at opposite ends of the gate pattern 107 differ along the first direction D1.

[0052] In some embodiments, the length of each of the first channel patterns 108 in the first direction D1 may be different. As an example, the first channel pattern 108 may include a lower first channel pattern 108-L1, an upper first channel pattern 108-U1, and an intermediate first channel pattern 108-M1 between the lower first channel pattern 108-L1 and the upper first channel pattern 108-U1. Each of the lower first channel pattern 108-L1, the intermediate first channel pattern 108-M1, and the upper first channel pattern 108-U1 may have a different length in the first direction D1. Figure 1B As shown, the lower first channel pattern 108-L1 has a length L in the first direction D1. 108-L1 The first channel pattern 108-M1 in the middle has a length L in the first direction D1. 108-M1 Length L 108-M1 Shorter than or less than the length L of the first channel pattern 108-L1 108-L1Furthermore, the first channel pattern 108-U1 has a length L in the first direction D1. 108-U1 Length L 108-U1 Shorter than or less than the length L of the first channel pattern 108-M1 in the middle 108-M1 In other words, as by Figure 1A As indicated by the first dashed line L1, the length of the first channel pattern 108 in the first direction D1 may be further away from the lower surface 106L of the substrate 106 in the third direction D3 (e.g., the third direction D3 is perpendicular to the first direction D1 and the second direction D2) or decrease with distance from the lower surface 106L of the substrate 106 (e.g., L...). 108-L1 >L 108-M1 >L 108-U1 Therefore, the edges of the first channel pattern 108 can collectively define an inclined plane relative to the first direction D1.

[0053] In some embodiments, the length of each of the second channel patterns 110 in the first direction D1 may be different. As an example, the second channel pattern 110 may include a lower second channel pattern 110-L2, an upper second channel pattern 110-U2, and an intermediate second channel pattern 110-M2 between the lower second channel pattern 110-L2 and the upper second channel pattern 110-U2. Each of the lower second channel pattern 110-L2, the intermediate second channel pattern 110-M2, and the upper second channel pattern 110-U2 may have a different length in the first direction D1. Figure 1B As shown, the lower second channel pattern 110-L2 has a length L in the first direction D1. 110-L2 The second channel pattern 110-M2 in the middle has a length L in the first direction D1. 110-M2 Length L 110-M2 Shorter than or less than length L 110-L2 Furthermore, the second channel pattern 110-U2 has a length L in the first direction D1. 110-U2 Length L 110-U2 Shorter than or less than length L 110-M2 In other words, as by Figure 1A As indicated by the first dashed line L1, the length of the second channel pattern 110 in the first direction D1 may decrease in the third direction D3, either away from the lower surface 106L of the substrate 106 or with increasing distance from the lower surface 106L of the substrate 106 (e.g., L...). 110-L2 >L 110-M2 >L 110-U2 Therefore, the edges of the second channel pattern 110 can collectively define an inclined plane relative to the first direction D1.

[0054] In some embodiments, at least one of the lengths of the first channel pattern 108 in the first direction D1 and at least one of the lengths of the second channel pattern 110 in the first direction D1 are different from each other. As an example, the length L of the second channel pattern in the first direction D1 is... 110-L2 L 110-M2 L 110-U2 At least one of them is longer than the length L of the first channel pattern in the first direction D1. 108-L1 L 108-M1 L 108-U1 At least one of them is shorter or smaller by at least 10% (e.g., about 20% to 30%). As a more specific example, the length L of each of the second channel patterns 110 is... 110-L2 L 110-M2 L 110-U2 The length L of each of the first channel patterns 108 108-L1 L 108-M1 L 108-U1 Shorter or smaller by about 20% to 30%. In some embodiments, the length of the uppermost first channel pattern (e.g., upper first channel pattern 108-U1) in the first channel pattern 108 may be longer than or greater than the length of the lowermost second channel pattern (e.g., lower second channel pattern 110-L2) in the second channel pattern 110.

[0055] In some embodiments, the lengths of each of the inner spacers 112 at opposite ends of the conductive gate patterns 107 of the first transistor 102 and / or the second transistor 104 in the first direction D1 may be the same (or substantially the same).

[0056] In some embodiments, the lengths in the first direction D1 between the outer edges of the inner spacers 112 disposed at each end of the conductive gate pattern 107 of the first transistor 102 and / or the second transistor 104 (e.g., the total length in the first direction D1 of the gate pattern 107 and the inner spacers 112 at each opposite end) may be different. As an example, the inner spacers 112 between the first channel patterns 108 of the first transistor 102 may include a lower first inner spacer 112-L1, an upper first inner spacer 112-U1, and an intermediate first inner spacer 112-M1 between the lower first inner spacer 112-L1 and the upper first inner spacer 112-U1, and the inner spacers 112 between the second channel patterns 110 of the second transistor 104 may include a lower second inner spacer 112-L2, an upper second inner spacer 112-U2, and an intermediate second inner spacer 112-M2 between the lower second inner spacer 112-L2 and the upper second inner spacer 112-U2.

[0057] Each of the lower inner spacers 112-L1, 112-M1, and 112-U1 may have different lengths in the first direction D1 (L1, L2, M1, and U1 are respectively L1, L2, M1, and U1). 112-L1 L 112-M1 L 112-U1 ), and / or each of the upper inner spacers 112-L2, 112-M2, 112-U2 may have different lengths in the first direction D1 (L respectively) 112-L2 L 112-M2 L 112-U2 The length of each of the upper inner spacers 112-L2, 112-M2, and 112-U2 may be less than or shorter than the length of each of the lower inner spacers 112-L1, 112-M1, and 112-U1. In some embodiments, the length of the inner spacer 112 in the first direction D1 may be reduced in the third direction D3 away from the lower surface 106L of the substrate 106 or decreases with distance from the lower surface 106L of the substrate 106 (e.g., L...). 112-L1 >L 112-M1 >L 112-U1 >L 112-L2 >L 112-M2 >L 112-U2 In some embodiments, the length of the uppermost lower inner spacer (e.g., lower inner spacer 112-U1) may be longer than or greater than the length of the lowermost upper inner spacer (e.g., upper inner spacer 112-L2).

[0058] In some embodiments, the lengths of the conductive gate patterns 107 of the first transistor 102 and / or the second transistor 104 in the first direction D1 may be different. As an example, the conductive gate pattern 107 of the first transistor 102 may include a lower first gate pattern 107-L1, an upper first gate pattern 107-U1, and an intermediate first gate pattern 107-M1 between the lower first gate pattern 107-L1 and the upper first gate pattern 107-U1. The gate pattern 107 of the second transistor 104 may include a lower second gate pattern 107-L2, an upper second gate pattern 107-U2, and an intermediate second gate pattern 107-M2 between the lower second gate pattern 107-L2 and the upper second gate pattern 107-U2.

[0059] Each of the lower gate patterns 107-L1, 107-M1, and 107-U1 may have different lengths in the first direction D1 (L1, L2, M1, and M1 are respectively L2, M1, M1, and M1). 107-L1 L 107-M1 L 107-U1 ), and / or each of the upper gate patterns 107-L2, 107-M2, 107-U2 may have different lengths in the first direction D1 (L, respectively). 107-L2 L 107-M2 L107-U2 In some embodiments, the length of each of the upper gate patterns 107-L2, 107-M2, and 107-U2 is less than or shorter than the length of each of the lower gate patterns 107-L1, 107-M1, and 107-U1. In some embodiments, as... Figure 1A As indicated by the second dashed line L2, the length of the gate pattern 107 in the first direction D1 may decrease in the third direction D3, either away from the lower surface 106L of the substrate 106 or with increasing distance from the lower surface 106L of the substrate 106 (e.g., L...). 107-L1 >L 107-M1 >L 107-U1 >L 107-L2 >L 107-M2 >L 107-U2 In some embodiments, the length of the uppermost lower gate pattern (e.g., lower gate pattern 107-U1) may be longer than or greater than the length of the lowermost upper gate pattern (e.g., upper gate pattern 107-L2).

[0060] Reference Figures 2A to 2B (in Figure 2B yes Figure 2A The enlarged view of region 2B in the diagram shows a cross-sectional view illustrating an example configuration of a semiconductor integrated circuit device 200 according to some embodiments of the present disclosure. The semiconductor integrated circuit device 200 is similar to [other devices] except that it includes a second transistor 204 instead of a second transistor 104. Figures 1A to 1B The semiconductor integrated circuit device 100 shown herein. Specifically, the second transistor 204 includes a second source / drain region 216 having a curved or non-linear profile (e.g., circular and / or elliptical shape) protruding toward the second channel pattern 210 and the inner spacers 212, such that the width of the second source / drain region 216 (in the first direction D1) varies within the second channel pattern 210 in the direction in which the second channel patterns 210 are stacked. In some embodiments, the second channel pattern 210 may include a lower second channel pattern 210-L2, an intermediate second channel pattern 210-M2, and an upper second channel pattern 210-U2, and the inner spacers 212 may include a lower second inner spacer 212-L2, an intermediate second inner spacer 212-M2, and an upper second inner spacer 212-U2. Although three second channel patterns 210 and pairs of inner spacers 212 are shown, it should be understood that any number of second channel patterns 210 and pairs of inner spacers 212 may be included, and the examples described herein are not limited to. Furthermore, it should be understood that in other embodiments, the characteristics described with reference to the second transistor 204 may be optionally or additionally applied to the first transistor 102. For example, although in Figures 2A to 2BThe description refers to an upper transistor 204 having a second source / drain region 216 having curved or non-linear side surfaces, an inner spacer 212, and a channel pattern 210. However, it will be understood that in some embodiments, these characteristics may be additionally or optionally applied to the source / drain region 114, the inner spacer 112, and the channel pattern 108 of the lower transistor 102.

[0061] In some embodiments, such as Figure 2B As shown, the lower second channel pattern 210-L2 has a length L in the first direction D1. 210-L2 The second channel pattern 210-M2 in the middle has a length L in the first direction D1. 210-M2 Length L 210-M2 Less than or shorter than the length L of the second channel pattern 210-L2 210-L2 Furthermore, the second channel pattern 210-U2 has a length L in the first direction D1. 210-U2 Length L 210-U2 Greater than or longer than length L 210-M2 (For example, the length L of the second channel pattern in the middle) 210-M2 Less than or shorter than the length of each of the second groove patterns above and below the intermediate second groove pattern on the third-direction D3.

[0062] In some embodiments, the length L of the intermediate second inner spacer 212-M2 212-M2 It may be less than or shorter than the length L of the lower second inner spacer 212-L2 212-L2 The length L of the second inner spacer 212-U2 212-U2 And the length L of the second inner spacer 212-M2 in the middle 212-M2 It may be less than the length of each of the inner spacers 112 of the first transistor 102 (e.g., the length L of the middle second inner spacer 212-M2). 212-M2 Shorter than or less than the length of each of the second inner spacers 212 above and below the intermediate second inner spacers 212-M2 on the third-direction D3, and shorter than or less than the length of each of the first inner spacers 112 of the first transistor 102. That is, the length L of the intermediate second inner spacer 212-M2 212-M2 It can be the shortest among the corresponding lengths of the other second inner spacers 212-L2, 212-U2 and inner spacer 112. Figure 2B In the embodiment, the corresponding lengths of the lower gate pattern 107-L2, the middle gate pattern 107-M2 and the upper gate pattern 107-U2 of the second transistor 204 can be substantially the same among the lower second inner spacer 212-L2, the middle second inner spacer 212-M2 and the upper second inner spacer 212-U2, respectively.

[0063] In some embodiments, such as Figure 2C (that is) Figure 2A As shown in the alternative enlarged view of region 2B in the figure, the second inner spacers 212-L2, 212-M2, 212-U2 of the second transistor 204 (and / or the inner spacer 112 of the first transistor 102) can be omitted. Therefore, referring to Figure 2C The conductive gate pattern 107 of the second transistor 204 can be replaced by a conductive gate pattern 207 that directly contacts the second source / drain region 216. The conductive gate pattern 207 may include a lower second gate pattern 207-L2, an intermediate second gate pattern 207-M2, and an upper second gate pattern 207-U2. The lower second gate pattern 207-L2 has a length L in the first direction D1. 207-L2 The intermediate second gate pattern 207-M2 has a length L in the first direction D1. 207-M2 The length L 207-M2 Shorter than or less than the length L of the lower second gate pattern 207-L2 207-L2 The second gate pattern 207-U2 has a length L in the first direction D1. 207-U2 Length L 207-U2 Greater than or longer than the length L of the intermediate second gate pattern 207-M2 207-M2 The length L of the second gate pattern 207-L2 in the first direction D1 207-L2 The length L of the second gate pattern 207-U2 in the first direction D1 207-U2 It may be greater than or longer than the length L of the intermediate second gate pattern 207-M2 in the first direction D1. 207-M2 .

[0064] As shown, in other embodiments, the characteristics described with reference to the second transistor 204 may be optionally or additionally applied to the first transistor 102. That is, although in Figure 2CThe description refers to an upper transistor 204 having a second source / drain region 216, a second channel pattern 210, and a second gate pattern 207 having curved or nonlinear side surfaces. However, it will be understood that in some embodiments, these characteristics may be additionally or optionally applied to the first source / drain region 114, the first channel pattern 108, and the gate pattern 107 of the lower transistor 102. For example, when the channel patterns 108 and 210 are implemented as nanosheets, the inner spacer 112 may be between adjacent lower nanosheets 108 in the lower nanosheet 108, and the upper nanosheet 210 may not have an inner spacer therebetween; or the inner spacer 212 may be between adjacent upper nanosheets 210 in the upper nanosheet 210, and the lower nanosheet 108 may not have an inner spacer therebetween; or both the upper nanosheet 210 and the lower nanosheet 108 may not have an inner spacer therebetween.

[0065] The following reference Figures 3A to 3F Description of formation Figures 1A to 1B The method of the semiconductor integrated circuit device 100 shown, Figures 3A to 3F A schematic cross-sectional view depicting an intermediate process for forming a semiconductor integrated circuit device 100 is shown. It should be understood that in various embodiments, certain steps may not be performed, and the order of steps for forming the semiconductor integrated circuit device 100 is not limited to the examples shown and described herein.

[0066] Reference Figure 3A A method for forming a semiconductor integrated circuit device 100 may include forming a plurality of alternately stacked channel layers 302 and sacrificial layers 304 on a substrate 106. In some embodiments, the method may further include forming an intermediate sacrificial layer 306 between a pair of sacrificial layers 304 (which may correspond to a first transistor 102 and a second transistor 104). In some embodiments, the intermediate sacrificial layer 306 may have a greater thickness than the sacrificial layers 304. The plurality of channel layers 302 may include a semiconductor material (such as silicon (Si)), and the sacrificial layers 304 and 306 may include a material (such as silicon germanium (SiGe)) that is etch-selective for the material of the channel layers 302.

[0067] Reference Figures 3B to 3D The method of forming the semiconductor integrated circuit device 100 may include forming channel patterns (e.g., first channel pattern 108 and second channel pattern 110) of a first transistor 102 and / or a second transistor 104, the channel patterns having different corresponding lengths (e.g., at least one of the channel patterns of the second transistor 104 is about 10% or more shorter than at least one of the channel patterns of the first transistor 102), and the sacrificial gate pattern 308 (or inner spacer 112) of the first transistor 102 and / or the second transistor 104 having different corresponding lengths.

[0068] To form the channel patterns 108 and 110 and the sacrificial gate pattern 308, for example, and referring to Figure 3B The method may include performing a tapered etching process on a portion of the channel layer 302, sacrificial layer 304, intermediate sacrificial layer 306, and substrate 106 to form a groove 310 extending into at least a portion of the substrate 106 at opposite sides of the channel layer 302, sacrificial layer 304, and intermediate sacrificial layer 306. The tapered etching process may include a wet etching process and / or a dry etching process (such as plasma-enhanced etching) and utilize one or more mask patterns such that the resulting edges of the channel layer 302, sacrificial layer 304, and intermediate sacrificial layer 306 are inclined relative to a third direction D3 (e.g., a vertical direction). The tapered etching process may involve gases (including, but not limited to, HBr, Cl2, O2, SF6, and N2). In some embodiments, the tapered etching process includes performing a dry etching process and controlling its parameters (e.g., controlling mass flow rate, pressure, power, ion density, and etchant ratio) to form a desired inclination. In some embodiments, the tapered etching process includes performing a wet etching process and controlling its parameters (e.g., controlling the type of etchant) to form a desired inclination. In some embodiments, the tapered etching process includes using a mask pattern having sloping edges to form the sloping surface of the contact groove 310 using a dry or wet etching process.

[0069] Reference Figure 3C The method of forming a semiconductor integrated circuit device 100 may further include forming mask structures 130 and 132 (mask structures 130 and 132 may include one or more cover patterns or other protective patterns) and spacer structures 134 in the recess 310 and on a portion of the remaining alternating stacked members. Figure 3D In this method, the method may include using mask structures 130 and 132 and spacer structure 134 as etch masks to perform a tapered etching process to form a recess 314 defining a first channel pattern 108 and a second channel pattern 110 from the channel layer 302 and a sacrificial gate pattern 308 from the sacrificial layer 304.

[0070] Reference Figure 3E A selective etching process is performed to remove the intermediate sacrificial layer 306. For example... Figure 3FAs shown, an isolation pattern 120 (also referred to as intermediate dielectric isolation (MDI)) is formed by filling the area from which the intermediate sacrificial layer 306 is removed using an insulating material (such as, but not limited to, SiN, SiOx, SiBCN, SiCN, SiON, SiOCN, or other insulating materials). For example, the area from which the intermediate sacrificial layer 306 is removed and the groove 314 can be filled with MDI insulating material, and the MDI insulating material can be substantially removed from the area from which the intermediate sacrificial layer 306 is removed to form the isolation pattern 120. A portion of the insulating material may remain at the bottom of the groove 314 to form a preliminary insulating region 126'.

[0071] Reference Figure 3G The edges of the sacrificial gate pattern 308 are selectively recessed, and inner spacers 112 are formed at opposite ends of the sacrificial gate pattern 308. The inner spacers 112 may be formed of a low-k material (e.g., oxides or nitrides (such as, but not limited to, SiN, SiOx, SiBCN, SiCN, SiON, SiOCN)) or other insulating materials. For example, a selective etching process can be used to recess the edges or side surfaces of the sacrificial gate pattern 308 exposed by the groove 314, and an oxide or nitride layer can be formed on the recessed ends of the sacrificial gate pattern 308 to form the inner spacers 112. In some embodiments, the selective etching process can recess the edges or side surfaces of the sacrificial gate pattern 308 by substantially similar amounts, such that two or more of the inner spacers 112 may have substantially similar lengths in the first direction D1 (e.g., such that...). Figure 1B L in 112-L1 L 112-M1 L 112-U1 L 112-L2 L 112-M2 and / or L 112-U2 (substantially equal). In other embodiments, the selective etching process may cause the edges or side surfaces of the sacrificial gate pattern 308 to be recessed by different amounts, such that two or more of the inner spacers 112 may have different lengths in the first direction D1 (e.g., such that L... 112-L1 >L 112-M1 >L 112-U1 , and / or L 112-L2 >L 112-M2 >L 112-U2 The recessed sacrificial gate pattern 308 may have different lengths in the first direction D1 in response to a selective etching process used to form the inner spacer 112.

[0072] The groove 314 may extend into a portion of the substrate 106, such that the substrate 106 may include a recessed surface adjacent to the opposite side of the first channel pattern 108. For example... Figure 3HAs shown, one or more insulating patterns may be formed in or on a portion of the substrate 106 to at least partially fill the recessed surface, forming an insulating region 126. In some embodiments, the insulating region 126 may be an oxide-based (e.g., silicon oxide) pattern or a nitride-based (e.g., silicon nitride) pattern, and the insulating region 126 may be formed by filling the groove 314 with an oxide- or nitride-based material and etching the material.

[0073] Reference Figure 3I A method of forming a semiconductor integrated circuit device 100 may include forming a first source / drain region 114 at opposite ends of a first channel pattern 108 and in a recess 314. For example, the first source / drain region 114 may be formed by selective epitaxial growth at opposite sides of the first channel pattern 108. In some embodiments, the first source / drain region 114 may comprise a first semiconductor material that is the same as the first semiconductor material of the first channel pattern 108. For example, the first channel pattern 108 and the first source / drain region 114 may be silicon (Si). After growing the first source / drain region 114, the method includes forming a second isolation pattern 122 on the first source / drain region 114. For example, an oxidation process (e.g., plasma oxidation or thermal oxidation) may be performed to oxidize the upper surface of the first source / drain region 114 to form the second isolation pattern 122. The method further includes forming a second source / drain region 116 at opposite ends of the second channel pattern 110 and on the second isolation pattern 122, such that the second isolation pattern 122 electrically isolates the second source / drain region 116 from the first source / drain region 114. For example, the second source / drain region 116 can be formed by selective epitaxial growth on opposite sides of the second channel pattern 110. In some embodiments, the second source / drain region 116 may comprise a second semiconductor material different from the first semiconductor material of the second channel pattern 110. For example, the second channel pattern 110 may be silicon (Si), while the second source / drain region 116 may be silicon-germanium (SiGe). It will be understood that the first source / drain region 114 and the second source / drain region 116 can be formed in any order and are not limited to the order described above.

[0074] Additionally, still refer to Figure 3I The method may further include replacing the sacrificial gate pattern 308 with a conductive gate pattern 107 between the first source / drain regions 114 and between the second source / drain regions 116 (or between the inner spacers 112), thereby forming Figures 1A to 1B The semiconductor integrated circuit device 100 shown has a first transistor 102 and a second transistor 104.

[0075] like Figure 1B As shown, due to the reference above Figure 3B and / or Figure 3D The described (one or more) tapered etching processes, the second (upper) channel pattern 110, each length L 110-L2 L 110-M2 L 110-U2 Each length L less than or shorter than the first (lower) channel pattern 108 108-L1 L 108-M1 L 108-U1 This allows the second (upper) source / drain region 116 formed at the opposite ends of the second channel pattern 110 to be wider (in the first direction D1) than the first (lower) source / drain region 114 formed at the opposite ends of the first channel pattern 108. For example, in some embodiments, the second source / drain region 116 may be at least 10% wider than the first source / drain region 114 (e.g., about 20% to 30%).

[0076] In addition, although Figures 1A to 1B and Figures 3A to 3F The reference above is shown in the middle. Figure 3B and Figure 3D The described tapered etching process forms both the first transistor 102 and the second transistor 104 of the semiconductor integrated circuit device 100, but it will be understood that embodiments of this disclosure are not so limited. For example, in some embodiments, a tapered etching process may be used to form the first transistor 102 (such that the respective lengths of the channel pattern 108, gate pattern 107, and / or inner spacer 112 of the first transistor 102 are different along the first direction D1), while the respective lengths of the channel pattern 110, gate pattern 107, and / or inner spacer 112 of the second transistor 104 are substantially equal (e.g., formed using an anisotropic etching process as described in further embodiments below), or vice versa. More generally, it may be modified... Figures 3A to 3F The operation shown is to independently control the respective lengths of the channel patterns 108 and / or 110, gate patterns 107 and / or inner spacers 112 of the first transistor 102 and / or the second transistor 104 in various combinations.

[0077] The following reference Figures 4A to 4F Description of formation Figures 2A to 2C The method of the semiconductor integrated circuit device 200 shown, Figures 4A to 4F A schematic cross-sectional view depicting an intermediate process for forming a semiconductor integrated circuit device 200 is shown. It should be understood that certain steps may not be performed in various embodiments, and the order of steps for forming the semiconductor integrated circuit device 200 is not limited to the examples shown and described herein.

[0078] Reference Figure 4AThe method of forming a semiconductor integrated circuit device 200 may include forming a plurality of alternately stacked channel layers 402 and sacrificial layers 404, and an intermediate sacrificial layer 406 on a substrate 106, the intermediate sacrificial layer 406 being formed with reference to the above. Figure 3A The channel layer 302, sacrificial layer 304 and intermediate sacrificial layer 306 are arranged in a similar manner between a pair of sacrificial layers 404.

[0079] Continue to refer to Figure 4A The method may include etching (e.g., wet or dry etching) a portion of the channel layer 402, sacrificial layer 404, intermediate sacrificial layer 406, and substrate 106 to form a groove 410 extending into at least a portion of the substrate 106 at opposite sides of the channel layer 402, sacrificial layer 404, and intermediate sacrificial layer 406. In some embodiments, (e.g., on a third direction D3) the channel layers 402, which are vertically stacked to each other, may have substantially the same length in a first direction D1 (different from...). Figure 3B (as shown in the embodiment), and the sacrificial layers 404 stacked vertically to each other may have substantially the same length in the first direction D1 (unlike the embodiment shown). Figure 3B The embodiment shown). That is, Figure 4B The etching of the channel layer 402, sacrificial layer 404, and intermediate sacrificial layer 406 shown can be anisotropic and may not form the reference layer above. Figure 3B The described conical inclination.

[0080] Reference Figure 4B The method may include forming mask structures 130 and 132 (mask structures 130 and 132 may include one or more cover patterns or other protective patterns) and spacer structure 134 in the recess 410 and on a portion of the remaining alternating stack, and performing an etching process (e.g., similar to the one described above). Figure 4A The described anisotropic etching process forms a first channel pattern 108 and a second channel pattern 210 from channel layer 402, a sacrificial gate pattern 408 from sacrificial layer 404, and a recess 414. In some embodiments, in response to the etching process, channel patterns 108 and 210, the first isolation pattern 120, and the sacrificial gate pattern 408 may have substantially the same length in a first direction D1. The recess 414 may extend into a portion of the substrate 106 to provide a recessed surface adjacent to the opposite sides of the channel patterns 108 and 210 and the sacrificial gate pattern 408. (Refer to above) Figure 3E and Figure 3F Similarly, as described, the isolation pattern 120 (or MDI) is formed by selectively removing the intermediate sacrificial layer 406 and filling the areas from which the intermediate sacrificial layer 406 has been removed with an insulating material.

[0081] Reference Figure 4CIn some embodiments, the edges of the sacrificial gate pattern 408 are selectively recessed, and inner spacers 212 are formed at opposite ends of the sacrificial gate pattern 408. For example, a selective etching process can be used to recess the edges or side surfaces of the sacrificial gate pattern 408 exposed by the groove 414, and an oxide layer or nitride layer (such as, but not limited to, SiN, SiOx, SiBCN, SiCN, SiON, SiOCN) can be formed on the recessed ends of the sacrificial gate pattern 408 to form the inner spacers 212. In some embodiments, the selective etching process can recess the edges or side surfaces of the sacrificial gate pattern 308 by substantially similar amounts, such that two or more of the inner spacers 212 can have substantially similar lengths in the first direction D1 (e.g., such that...). Figure 2B L in 212-L2 L 212-M2 and / or L 212-U2 (Substantially equal). In other embodiments, the selective recessing process and the formation of the inner spacer 212 may be omitted (e.g., as... Figure 2C As shown in the figure.

[0082] Reference Figure 4D One or more insulating patterns may be formed in or on a portion of the substrate 106 to at least partially fill the recessed surface, forming an insulating region 126 (as shown above). Figure 3H Similarly, and a first source / drain region 114 can be formed at the opposite ends of the first channel pattern 108, thereby forming Figure 2A The first transistor 102. The insulating region 126, the first source / drain region 114, and the second isolation pattern 122 can be referenced above. Figure 3F Formed in a similar manner as described. For example, in some embodiments using the same semiconductor material (e.g., Si) as the first channel pattern 108, the first source / drain region 114 can be formed by selective epitaxial growth at opposite sides of the first channel pattern 108. After growing the first source / drain region 114, the method includes forming a second isolation pattern 122 on the first source / drain region 114 (e.g., by plasma oxidation or thermal oxidation of the upper surface of the first source / drain region 114).

[0083] Reference Figure 4EThe method includes performing one or more bowl-shaped etching processes 418 such that the side surfaces of the channel pattern 210, the sacrificial gate pattern 408, and / or the inner spacer 212 exposed by the groove 414 have a curved or non-linear profile convex toward the second channel pattern 210. The bowl-shaped etching process 418 (e.g., a dry or wet etching process) is configured to remove a portion of the channel pattern 210 and the sacrificial gate pattern 408 (and / or the inner spacer 212) located in the middle of the stack to a greater extent than the corresponding layers / patterns (e.g., corresponding layers and patterns) above and below the channel pattern 210 and the sacrificial gate pattern 408 (and / or the inner spacer 212) in the stack (i.e., making the middle pattern shorter). The bowl-shaped etching process 418 may involve gases (including, but not limited to, HBr, Cl2, O2, SF6, and N2). In some embodiments, the bowl-shaped etching process 418 may include performing a dry etching process (such as plasma-enhanced etching) and controlling its parameters (e.g., controlling mass flow rate, pressure, power, ion density, and etchant ratio) to form a curved or non-linear profile. In some embodiments, the bowl-shaped etching process 418 may include performing a wet etching process and controlling its parameters (e.g., controlling the type of etchant) to form a curved or non-linear profile. The second isolation pattern 122 and the first isolation pattern 120 may together serve as an etch stop layer to protect the underlying first source / drain region 114, channel pattern 108, sacrificial gate pattern 408, and / or inner spacer 112 from being etched by the bowl-shaped etching process 418.

[0084] Reference Figure 4F ,like Figure 2A As shown, the method includes forming a second source / drain region 216 of the second transistor 204 at opposite ends of the second channel pattern 210. The second source / drain region 216 can be configured similarly to the one described above. Figure 3F Formed in a similar manner as described. For example, in some embodiments of a semiconductor material (e.g., SiGe) different from the semiconductor material (e.g., Si) of the second channel pattern 210, the second source / drain region 116 may be formed by selective epitaxial growth at the opposite side of the second channel pattern 210.

[0085] Additionally, and refer to Figure 4F The method may further include replacing the sacrificial gate pattern 408 with a conductive gate pattern 107 or 207 between the first source / drain regions 114 and between the second source / drain regions 216 (or between the inner spacers 112 and 212), thereby forming Figures 2A to 2C The first transistor 102 and the second transistor 204 of the semiconductor integrated circuit device 200. For example... Figure 2B As shown, due to the reference above Figure 4E The described bowl-shaped etching process 418, the corresponding length L of the intermediate channel pattern 210_M2 and the inner spacer 212_M2 in the first direction D1 210-M2 and L 212-M2 It can be less than or shorter than the corresponding length L of the channel patterns 210_L2 and 210_U2 below the intermediate channel pattern 210_M2 and the inner spacer 212_M2, and above the intermediate channel pattern 210_M2 and the inner spacer 212_M2, respectively. 210-L2 and L 210-U2 And the corresponding length L of the inner spacers 212_L2 and 212_U2 212-L2 and L 212-U2 Optionally, in cases such as Figure 2C In the embodiment shown where the inner spacer 212 is omitted, due to the above reference... Figure 4E The described bowl-shaped etching process 418, with corresponding lengths L of the intermediate channel pattern 210_M2 and the gate pattern 207_M2. 210-M2 and L 207-M2 It can be less than or shorter than the corresponding lengths L of the channel patterns 210_L2 and 210_U2 below the intermediate channel pattern 210_M2 and the gate pattern 207_M2, and above the intermediate channel pattern 210_M2 and the gate pattern 207_M2, respectively. 210-L2 and L 210-U2 and the corresponding length L of gate patterns 207_L2 and 207_U2 207-L2 and L 207-U2 More typically, this will be understood as changeable. Figures 4A to 4F The operation shown is to independently control the respective lengths of the channel patterns 108 and / or 210, gate patterns 107 and / or 207, and / or inner spacers 112 of the first transistor 102 and / or the second transistor 204 in various combinations.

[0086] The following reference Figures 5A to 5D , Figure 5E1 / Figure 5E2 (For example, Figure 5E1 or Figure 5E2 )and Figure 5F1 / Figure 5F2 (For example, Figure 5F1 or Figure 5F2 This describes another method for forming semiconductor integrated circuit devices. Figures 5A to 5D , Figure 5E1 / Figure 5E2 and Figure 5F1 / Figure 5F2A schematic cross-sectional view depicting an intermediate process for forming semiconductor integrated circuit devices 500 and 500' is shown. It should be understood that certain steps may not be performed in various embodiments, and the order of steps for forming the semiconductor integrated circuit devices is not limited to the examples shown and described herein.

[0087] In addition to performing a bowl-shaped etching process before forming the second isolation pattern 122 (e.g., an etch stop layer) and the second source / drain region, Figures 5A to 5D , Figure 5E1 and Figure 5F1 The method for forming the integrated circuit device 500 shown is similar to Figures 4A to 4F The method shown includes performing a first bowl-shaped etching process 518-1 before forming the first (or lower) source / drain region 514 and the second isolation pattern 122, and performing a second bowl-shaped etching process 518-2 after forming the second isolation pattern 122 and before forming the second (or upper) source / drain region 516. Figures 5A to 5D , Figure 5E2 and Figure 5F2 The method for forming the integrated circuit device 500' shown in the figure is similar to Figures 4A to 4F as well as Figures 5A to 5D 5E1 and Figure 5F1 The method shown in the figure.

[0088] Reference Figure 5A The method of forming semiconductor integrated circuit devices 500 and 500' may include forming a plurality of alternately stacked channel layers 501 and sacrificial layers 404 and intermediate sacrificial layers 506 on a substrate 106, the intermediate sacrificial layers 506 being aligned with the above-mentioned reference. Figure 3A and Figure 4A The same manner described for forming channel layers 302 / 402 (e.g., channel layers 302 and 402), sacrificial layers 304 / 404 (e.g., sacrificial layers 304 and 404), and intermediate sacrificial layers 306 / 406 (e.g., intermediate sacrificial layers 306 and 406) is placed between a pair of sacrificial layers 404.

[0089] Continue to refer to Figure 5A The method may include etching (e.g., wet or dry etching) a portion of the channel layer 501, sacrificial layer 404, intermediate sacrificial layer 506, and substrate 106 to form a groove 530 extending into at least a portion of the substrate 106 at opposite sides of the channel layer 501, sacrificial layer 404, and intermediate sacrificial layer 506. In some embodiments, (e.g., on a third direction D3) the vertically stacked channel layers 501 may have substantially the same length in a first direction D1, and the vertically stacked sacrificial layers 404 may have substantially the same length in the first direction D1.

[0090] Reference Figure 5BThe method may include forming mask structures 130 and 132 (mask structures 130 and 132 may include one or more cover patterns or other protective patterns) and spacer structure 134 in the recess 410 and on a portion of the remaining alternating stack, and performing an etching process (e.g., similar to the one described above). Figure 4B The described anisotropic etching process forms a first channel pattern 508 and a second channel pattern 510 from channel layer 501, a sacrificial gate pattern 408 from sacrificial layer 404, a first isolation pattern 120 from intermediate sacrificial layer 506, and a recess 414. In some embodiments, the channel patterns 508 and 510, the first isolation pattern 120, and the sacrificial gate pattern 408 have substantially the same length in a first direction D1. The recess 414 may extend into a portion of the substrate 106 to provide recessed surfaces adjacent to opposite sides of the channel patterns 508 and 510 and the sacrificial gate pattern 408. (Refer to above) Figure 3E and Figure 3F Similarly, as described, the isolation pattern 120 (or MDI) is formed by selectively removing the intermediate sacrificial layer 506 and filling the areas from which the intermediate sacrificial layer 506 has been removed with an insulating material.

[0091] Reference Figure 5C In some embodiments, the edges of the sacrificial gate pattern 408 are selectively recessed and formed in accordance with the above reference. Figure 4C The inner spacer 212 is formed at opposite ends of the sacrificial gate pattern 408 in a manner similar to that described in the previous example. In other embodiments, a selective recess process and the formation of the inner spacer 512 may be performed in subsequent operations.

[0092] Reference Figure 5D One or more insulating patterns may be formed in or on a portion of the substrate 106 to at least partially fill the recessed surface, thereby forming an insulating region 126 (as shown above). Figure 3H Similarly, a bowl-shaped etching process 518-1 can be performed such that the side surfaces of the channel pattern 508, the sacrificial gate pattern 408, and / or the inner spacer 512 exposed by the groove 414 have a curved or non-linear profile convex toward the first channel pattern 508. The bowl-shaped etching process 518-1 can be similar to that described in reference [reference]. Figure 4EThe described bowl-shaped etching process 418 causes the intermediate first channel pattern 508 and inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted) of the first / lower transistor (e.g., the first transistor or the lower transistor) 502 to be formed on the first direction D1 shorter than the channel pattern 508 and inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted) and the inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted) of the first / lower transistor 502 above and below the intermediate first channel pattern 508 and inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted).

[0093] Reference Figure 5E1 and Figure 5F1 The method may include forming a first source / drain region 514 of a first transistor 502 at opposite ends of a first channel pattern 508, forming a second isolation pattern 122 on the first source / drain region 514, and forming a second source / drain region 516 of a second transistor 504 on the second isolation pattern 122 and at opposite ends of the second channel pattern 510. The first source / drain region 514, the second isolation pattern 122, and the second source / drain region 516 may be aligned with a reference. Figure 4D and Figure 4F The first source / drain region 114, the second isolation pattern 122, and the second source / drain region 216 are formed in a similar manner. Because the bowl-shaped etching process 518-1 is performed such that the intermediate first channel pattern 508 and inner spacer 512 (or sacrificial gate pattern 408) of the first / lower transistor 502 are formed shorter in the first direction D1 than the channel patterns 508 and inner spacers 512 (or sacrificial gate patterns 408) above and below them, the width of the first source / drain region 514 (in the first direction D1) varies between the first channel patterns 508, while the width of the second source / drain region 516 can be substantially consistent between the second channel patterns 510.

[0094] Additionally, see reference Figure 5F1 The method may further include replacing the sacrificial gate pattern 408 with a conductive gate pattern 107 between the first source / drain regions 514 and between the second source / drain regions 516 (or between the inner spacers 512) to form the first transistor 502 and the second transistor 504.

[0095] In one variant, executable Figure 5E2 and Figure 5F2 The process shown is not Figure 5E1 and Figure 5F1 The process shown is used to form the first transistor 502 and the second transistor 504'. (Refer to...) Figure 5E2 After executing such Figure 5D Following the first bowl-shaped etching process 518-1 shown, in accordance with the reference... Figure 4D The formation of the first source / drain region 114 and the second isolation pattern 122 is described in a similar manner. The first source / drain region 514 is formed at opposite ends of the first channel pattern 508, and the second isolation pattern 122 is formed on the first source / drain region 514. After forming the second isolation pattern 122, a second bowl-shaped etching process 518-2 is performed, such that the second isolation pattern 122 and the first isolation pattern 120 serve as an etch stop layer protecting the lower layer of the first / lower transistor 502. The second bowl-shaped etching process 518-2 can be similar to that described in reference [reference missing]. Figure 4E The described bowl-shaped etching process 418 causes the intermediate second channel pattern 510 and inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted) of the second / upper transistor (e.g., the second transistor or the upper transistor) 504' to be formed on the first direction D1 shorter than the channel pattern 510 and inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted) and the inner spacer 512 (or sacrificial gate pattern 408, in embodiments where the inner spacer 512 is omitted) of the second / upper transistor 504'.

[0096] Reference Figure 5F2 The method includes forming a second source / drain region 516' at opposite ends of the second channel pattern 210. The second source / drain region 516' can be formed in accordance with the above reference. Figure 4F The second source / drain region 216 is formed in a similar manner to that described in the previous example. The method may also include replacing the sacrificial gate pattern 408 with a conductive gate pattern 107 between the first source / drain regions 514 and between the second source / drain regions 516' (or between the inner spacers 512) to form the first transistor 502 and the second transistor 504'.

[0097] Because the first bowl-shaped etching process 518-1 and the second bowl-shaped etching process 518-2 are performed sequentially, the intermediate first channel patterns 508 and 510 and the inner spacer 512 (or sacrificial gate pattern 408) in each of the first / lower transistors 502 and the second / upper transistors 504' are formed in the first direction D1 to be shorter than the channel patterns 508 and 510 and the inner spacer 512 (or sacrificial gate pattern 408) above and below the intermediate first channel patterns 508 and 510 and the inner spacer 512 (or sacrificial gate pattern 408). Thus, the widths (in the first direction D1) of the first source / drain region 514 and the second source / drain region 516' vary between the first channel pattern 508 and the second channel pattern 510, respectively. However, it will be understood that the widths can be changed... Figures 5A to 5F2 The operation shown is to independently control the respective lengths of the channel patterns 508 and / or 510, gate patterns 107 and / or inner spacers 512 of the first transistor 502 and / or the second transistor 504' in various combinations.

[0098] Figure 6 This is a flowchart 600 illustrating a method for forming an integrated circuit device according to some embodiments. The method shown in flowchart 600 may correspond to the intermediate process diagrams described above individually or in combination (such as, Figures 3A to 3F Intermediate process diagrams, or by Figures 3A to 3F , Figures 4A to 4F , Figures 5A to 5D , Figure 5E1 , Figure 5E2 , Figure 5F1 and / or Figure 5F2 (The combination of intermediate process diagrams shown). It should be understood that certain steps may not be performed in various embodiments, and the order of steps for forming a semiconductor integrated circuit device is not limited to the examples shown and described herein.

[0099] In step 602, the method may include forming a plurality of alternately stacked channel layers and sacrificial layers (e.g., ...) on a substrate. Figure 3A The intermediate process shown is illustrated. In step 604, the method may include performing one or more tapered etching processes to form channel patterns and sacrificial gate patterns of different corresponding lengths for the first transistor and / or the second transistor (e.g., lower transistor and / or upper transistor stacked on a substrate) (and optionally, inner spacers at opposite ends of the sacrificial gate patterns). Figures 3B to 3EThe intermediate process shown is illustrated. In optional step 606, the method may include performing one or more bowl-shaped etching processes such that the respective lengths of the intermediate channel pattern and intermediate sacrificial gate pattern (and optionally, intermediate inner spacer) of at least one of the first and second transistors are shorter than the respective lengths of the channel pattern and sacrificial gate pattern (or inner spacer) above and below the intermediate channel pattern and intermediate sacrificial gate pattern (and optionally, intermediate inner spacer) (e.g., Figure 4E , 5D Or the intermediate process shown in 5E2). In step 608, the method may include epitaxially growing source / drain regions at opposite ends of the channel patterns of the first transistor and / or the second transistor (e.g., Figure 3I , Figure 4D , Figure 4F , Figure 5E1 , Figure 5E2 , Figure 5F1 and / or Figure 5F2 (The intermediate process shown). In step 610, the method may include replacing the sacrificial gate pattern with a conductive gate pattern between the source / drain regions (or between the inner spacers). Figure 3I , Figure 4F , 5F1 Or the intermediate process shown in 5F2).

[0100] Figure 7 This is a flowchart 700 illustrating a method for forming an integrated circuit device according to some embodiments. The method shown in flowchart 700 may correspond to the intermediate process diagrams described above individually or in combination (such as those by...). Figures 4A to 4F , Figures 5A to 5D , Figure 5E1 , Figure 5E2 , Figure 5F1 and / or Figure 5F2 (The combination of intermediate process diagrams shown). It should be understood that certain steps may not be performed in various embodiments, and the order of steps for forming a semiconductor integrated circuit device is not limited to the examples shown and described herein.

[0101] In step 702, the method may include forming a plurality of alternately stacked channel layers and sacrificial layers (e.g., ...) on a substrate. Figure 4A or Figure 5A The intermediate process shown is illustrated. At step 704, the method may include performing a first etching process (e.g., one or more anisotropic etching processes) to form a channel pattern and a sacrificial gate pattern of substantially uniform length for the first transistor and / or the second transistor (e.g., a lower transistor and / or an upper transistor stacked on a substrate). (and optionally, inner spacers at opposite ends of the sacrificial gate pattern) Figures 4A to 4B or Figures 5A to 5B The intermediate process shown is illustrated. In step 706, the method may include performing a second etching process (e.g., one or more bowl-shaped etching processes) such that the respective lengths of the intermediate channel pattern and intermediate sacrificial gate pattern (and optionally, intermediate inner spacer) of at least one of the first and / or second transistors are shorter than the respective lengths of the channel pattern and sacrificial gate pattern (or inner spacer) above and below the intermediate channel pattern and intermediate sacrificial gate pattern (and optionally, intermediate inner spacer) (e.g., Figure 4E , Figure 5D Or the intermediate process shown in 5E2). In step 708, the method may include epitaxially growing source / drain regions at opposite ends of the channel patterns of the first transistor and / or the second transistor (e.g., Figure 3I , Figure 4D , Figure 4F , Figure 5E1 , Figure 5E2 , Figure 5F1 and / or Figure 5F2 The intermediate process shown is described. At step 710, the method may include replacing the sacrificial gate pattern with a conductive gate pattern between the source / drain regions (or between inner spacers). Figure 4F , 5F1 Or the intermediate process shown in 5F2).

[0102] Due to the tapered etching process and / or bowl-shaped etching process described herein, the channel length, gate length, and / or inner spacer thickness of the upper (and / or lower) device can be independently controlled and varied as needed to provide different characteristics for the upper and lower devices in the stacked transistor structure. Advantages of the structure, features, or operation formed by the upper and lower devices as described herein may include, for example, fabricating the upper and lower transistors in a stacked transistor structure such that the lengths of the gate, channel, and / or inner spacers can be independently adjusted, which can improve or optimize the performance of the stacked transistor (e.g., CMOS). For example, stacked transistors can have reduced leakage current and improved performance through the short-channel effect (SCE) of N-type FETs (NFETs). Furthermore, stacked transistors can have improved performance through P-type FET (PFET) junction optimization. However, embodiments of this disclosure are not limited thereto.

[0103] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, unless expressly defined herein, all terms shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0104] In the above description, each example embodiment has been described with reference to a region of a specific conductivity type. It will be understood that in each of the embodiments above, devices of opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers. Therefore, it will be understood that this disclosure covers both n-channel and p-channel devices for each different device structure.

[0105] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising” and / or “including” specify the presence of the said features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0106] It will be understood that although the terms “first,” “second,” etc., are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0107] It will be understood that when a component (such as a layer, region, or substrate) is referred to as being "on" another component or extending "to" another component, it may be directly on or directly extended to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" another component or "directly" extending "to" another component, there are no intermediate components. It will also be understood that when a component is referred to as being "connected" or "bonded" to another component, it may be directly connected or bonded to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly bonded" to another component, there are no intermediate components.

[0108] As illustrated in the accompanying drawings, spatially relative terms such as “below,” “above,” “upper,” “lower,” “top,” or “bottom” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region based on a reference frame (e.g., a substrate). It will be understood that these terms are intended to cover different orientations of the device in addition to those depicted in the accompanying drawings.

[0109] Example embodiments are described herein with reference to the accompanying drawings, which may include cross-sectional views as schematic illustrations of idealized embodiments (and intermediate structures). Many different forms and embodiments are possible without departing from the teachings of this disclosure. Therefore, the disclosure should not be construed as limited to the example embodiments set forth herein. Thus, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined herein. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Additionally, variations in the illustrated shapes are foreseeable due to, for example, manufacturing techniques and / or tolerances.

[0110] Embodiments of this disclosure are also described with reference to manufacturing operations and flowcharts. It will be understood that the steps shown in the manufacturing operations and flowcharts do not need to be performed in the order shown.

[0111] The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the scope of the disclosure. Therefore, to the fullest extent permitted by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. An integrated circuit device, comprising: Base; as well as A stacked transistor structure, on a substrate, includes a first transistor and a second transistor stacked on top of the first transistor. Each of the first and second transistors includes multiple channel patterns that extend between source / drain regions in a first direction and are alternately stacked with multiple gate patterns in a second direction. Wherein, for at least one of the first transistor and the second transistor, the corresponding lengths of the plurality of channel patterns and the plurality of gate patterns are different along a first direction.

2. The integrated circuit device according to claim 1, wherein, The first transistor and the second transistor are at least one of the second transistors, and the respective lengths of the plurality of channel patterns of the second transistor are shorter than the respective lengths of the plurality of channel patterns of the first transistor.

3. The integrated circuit device according to claim 1, wherein, For the at least one of the first transistor and the second transistor, the corresponding length of at least one of the plurality of channel patterns is shorter than the corresponding length of the channel patterns above and below the at least one channel pattern in the second direction of the plurality of channel patterns.

4. The integrated circuit device according to claim 1, wherein, The at least one of the first transistor and the second transistor includes a plurality of inner spacers, the plurality of inner spacers being located in a first direction between opposite ends of the plurality of gate patterns of the at least one transistor in the first transistor and the source / drain regions, and Wherein, for at least one of the first transistor and the second transistor, the corresponding lengths of the plurality of inner spacers are different along a first direction.

5. The integrated circuit device according to claim 4, wherein, The at least one of the first transistor and the second transistor is the first transistor and the second transistor, and the respective lengths of the plurality of inner spacers of the second transistor are shorter than the respective lengths of the plurality of inner spacers of the first transistor.

6. The integrated circuit device according to claim 4, wherein, For at least one of the first transistor and the second transistor, the corresponding length of at least one of the plurality of inner spacers is shorter than the corresponding lengths of the inner spacers above and below the at least one inner spacer in the second direction.

7. The integrated circuit device according to claim 1, wherein, The at least one of the first transistor and the second transistor includes the plurality of gate patterns extending between the source and drain regions in a first direction.

8. The integrated circuit device according to claim 7, wherein, The at least one of the first transistor and the second transistor is the first transistor and the second transistor, and the respective length of the plurality of gate patterns of the second transistor is shorter than the respective length of the plurality of gate patterns of the first transistor.

9. The integrated circuit device according to claim 7, wherein, For at least one of the first transistor and the second transistor, the corresponding length of at least one of the plurality of gate patterns is shorter than the corresponding lengths of the gate patterns above and below the at least one gate pattern in the second direction.

10. A method of forming an integrated circuit device, the method comprising: A stacked transistor structure is formed on a substrate, the stacked transistor structure including a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes multiple channel patterns that extend between source / drain regions in a first direction and are alternately stacked with multiple gate patterns in a second direction. Wherein, for at least one of the first transistor and the second transistor, the corresponding lengths of the plurality of channel patterns and the plurality of gate patterns are different along a first direction.

11. The method according to claim 10, wherein, The steps to form a stacked transistor structure include: Multiple channel layers are stacked on the substrate; and At least one etching process is performed on the plurality of channel layers to form the plurality of channel patterns of the at least one transistor of the first transistor and the second transistor, the plurality of channel patterns having corresponding lengths different along a first direction.

12. The method according to claim 11, wherein, The steps of performing the at least one etching process include: A tapered etching process is performed on the plurality of channel layers such that the corresponding length of at least one of the plurality of channel patterns of the second transistor is 10% or more shorter than the corresponding length of at least one of the plurality of channel patterns of the first transistor.

13. The method according to claim 11, wherein, The steps of performing the at least one etching process include: A first etching process is performed on the plurality of channel layers; and A bowl-shaped etching process is performed on the plurality of channel patterns of the first transistor and the second transistor such that the corresponding length of at least one of the plurality of channel patterns is shorter than the corresponding length of the channel patterns above and below the at least one channel pattern in a second direction.

14. The method according to claim 13, wherein, The first transistor and the second transistor are both second transistors, and the method further includes: After performing the first etching process, the source / drain regions of the first transistor are epitaxially grown at opposite ends of the plurality of channel patterns of the first transistor. Before performing a bowl-shaped etching process on the plurality of channel patterns of the second transistor, an etch stop layer is formed on the source / drain regions of the first transistor; and After performing the bowl-shaped etching process, the source / drain regions of the second transistor are epitaxially grown at opposite ends of the plurality of channel patterns of the second transistor.

15. The method according to claim 14, wherein, The plurality of gate patterns of the second transistor include a plurality of sacrificial gate patterns having a plurality of inner spacers at opposite ends of the plurality of sacrificial gate patterns, and wherein, in response to a bowl-shaped etching process, the corresponding length of at least one of the plurality of inner spacers is shorter than the corresponding lengths of the inner spacers above and below the at least one inner spacer in a second direction.

16. The method of claim 14, wherein, The plurality of gate patterns of the second transistor include a plurality of sacrificial gate patterns without inner spacers at opposite ends of the plurality of sacrificial gate patterns, and wherein, in response to a bowl-shaped etching process, the corresponding length of at least one of the plurality of sacrificial gate patterns is shorter than the corresponding lengths of the sacrificial gate patterns above and below the at least one sacrificial gate pattern in a second direction.

17. A method of forming an integrated circuit device, the method comprising: Multiple channel layers and multiple sacrificial layers are formed on the substrate in alternating stacks; A first etching process is performed on the plurality of channel layers and the plurality of sacrificial layers to form a plurality of channel patterns and a plurality of sacrificial gate patterns, the plurality of channel patterns extending in a first direction and being alternately stacked with the plurality of sacrificial gate patterns between the plurality of channel patterns in a second direction; as well as A second etching process is performed on at least one subset of a first subset of the plurality of channel patterns corresponding to the first transistor and a second subset of the plurality of channel patterns corresponding to the second transistors stacked on the first transistor. In response to the second etching process, the corresponding lengths of the plurality of channel patterns in at least one subset of the first subset and the second subset are different along the first direction.

18. The method according to claim 17, wherein, The first subset and the second subset are at least one subset of the second subset, and the method further includes: After performing the first etching process, the source / drain regions of the first transistor are epitaxially grown at opposite ends of the plurality of channel patterns in the first subset. Before performing a second etching process on the plurality of channel patterns of the second subset, an etch stop layer is formed on the source / drain region of the first transistor; and After performing the second etching process, the source / drain regions of the second transistor are epitaxially grown at the opposite ends of the plurality of channel patterns in the second subset. In response to the second etching process, the corresponding length of at least one channel pattern in the second subset of the plurality of channel patterns is shorter than the corresponding length of the channel patterns in the second subset above and below the at least one channel pattern in the second direction.

19. The method according to claim 18, wherein, The plurality of sacrificial gate patterns between the plurality of channel patterns in the second subset include a plurality of inner spacers at opposite ends of the plurality of sacrificial gate patterns, and in response to the second etching process, the corresponding length of at least one of the plurality of inner spacers is shorter than the corresponding length of the inner spacers above and below the at least one inner spacer in the second direction.

20. The method according to claim 18, wherein, The plurality of sacrificial gate patterns between the plurality of channel patterns in the second subset do not have inner spacers at the opposite ends of the plurality of sacrificial gate patterns, and in response to the second etching process, the corresponding length of at least one of the plurality of sacrificial gate patterns is shorter than the corresponding length of the sacrificial gate patterns above and below the at least one sacrificial gate pattern in the second direction.

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