Laminated tunneling process suitable for TOPCon battery and TOPCon battery structure

Abstract

The invention discloses a laminated tunneling process suitable for a TOPCon cell and a TOPCon cell structure, and relates to the field of solar cells, the process comprises the following steps: introducing laughing gas, controlling the pressure and temperature in a furnace to be within a set value range, carrying out glow discharge through a radio frequency power supply, and depositing a tunneling oxide layer; low-power tunneling and high-power tunneling are performed in sequence in the tunneling oxide layer deposition process; wherein the power of the low-power tunneling is lower than that of the high-power tunneling, and the time of the low-power tunneling is shorter than that of the high-power tunneling. According to the laminated tunneling technology, the damage is reduced and the passivation level is improved by reducing bombardment of plasma on a silicon substrate through low power, the in-chip uniformity of a tunneling layer is improved through outer layer high power, and in-chip bright and dark chips are improved, so that carrier transport is optimized, series resistance is reduced, surface recombination is reduced, and open-circuit voltage is improved; and finally, obvious advantages are shown in the aspects of cost optimization and efficiency improvement.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and more specifically to a stacked tunneling process and TOPCon cell structure adapted to TOPCon cells. Background Technology

[0002] Electricity is not merely one of many energy sources; it is the most fundamental and core energy form upon which modern society depends for survival and operation. It is a key indicator of a country's or region's modernization level and standard of living. A stable, reliable, clean, and affordable electricity supply is the fundamental guarantee for the sustainable development of modern civilization. Globally, thermal power generation is currently the primary form of electricity generation. However, the large-scale combustion of fossil fuels has not only led to energy depletion but also exacerbated environmental pollution. Research indicates that only by transforming current energy usage patterns, vigorously developing and popularizing clean energy, and fundamentally changing the energy structure dominated by fossil fuels can energy shortages and environmental pollution be alleviated at their root. Therefore, new energy sources have developed rapidly in recent years. Among them, photovoltaic solar energy utilizes renewable energy—sunlight—to generate electricity through the principle of photovoltaic power generation, thus broadening its applicability. However, with the continuous upgrading of the photovoltaic industry, highly efficient, stable, and low-cost photovoltaic cells are the core of market competition.

[0003] TOPCon is a tunnel oxide passivated contact solar cell technology based on the selective carrier principle. Its cell structure is an N-type silicon substrate cell. An ultrathin silicon oxide layer is prepared on the back of the cell, and then a doped silicon thin layer is deposited. The two together form a passivated contact structure, which effectively reduces surface recombination and metal contact recombination, and provides more room for further improvement of cell conversion efficiency.

[0004] Traditional processes typically employ a single-layer tunneling layer when fabricating the tunneling layer. However, this structure cannot effectively balance passivation and carrier flow in practical applications, resulting in limited yield and efficiency improvements. Summary of the Invention

[0005] (a) Technical problems to be solved To address the shortcomings of existing technologies, this invention provides a stacked tunneling process and TOPCon battery structure adapted to TOPCon batteries, solving at least one technical problem mentioned in the background art.

[0006] (II) Technical Solution The technical solution adopted in this invention provides a stacked tunneling process adapted to TOPCon cells and TOPCon battery structure; In a first aspect, a stacked tunneling process adapted to TOPCon batteries is provided, characterized in that the process includes: introducing nitrous oxide and controlling the pressure and temperature inside the furnace within a set range, performing glow discharge through a radio frequency power supply, and depositing a tunneling oxide layer; The deposition of the tunneling oxide layer involves sequential low-power tunneling and high-power tunneling. The power of low-power tunneling is lower than that of high-power tunneling, and the tunneling time of low-power tunneling is longer than that of high-power tunneling. The tunneling time is short.

[0007] Preferably, the power of the low-power tunneling is 500-8000W; and the tunneling time is 10-30 seconds.

[0008] Preferably, the power of the high-power tunneling is 12000-15000W; and the tunneling time is 60-90 seconds.

[0009] Preferably, the low-power tunneling forms at least two tunneling layers.

[0010] Preferably, the high-power tunneling forms at least two tunneling layers.

[0011] Preferably, during the process of forming at least two tunneling layers through low-power tunneling, the tunneling power increases sequentially.

[0012] Preferably, during the process of forming at least two tunneling layers in the low-power tunneling, the tunneling power increases sequentially, and the maximum power is less than 8000W.

[0013] Preferably, during the process of forming at least two tunneling layers through high-power tunneling, the tunneling power increases sequentially.

[0014] Preferably, during the process of forming at least two tunneling layers through high-power tunneling, the tunneling power increases sequentially, and the minimum power is not less than 12000W.

[0015] Secondly, a TOPCon battery structure is also provided, wherein the TOPCon battery structure adopts any of the above-described methods. Preparation using a multilayer tunneling process.

[0016] (III) Beneficial Effects This invention provides a stacked tunneling process and TOPCon cell structure adapted to TOPCon cells, which has the following advantages compared with the prior art: By using stacked tunneling technology, the plasma bombardment of the silicon substrate is reduced by low power to reduce damage and improve passivation level. The high power of the outer layer improves the uniformity of the tunneling layer and improves the brightness and darkness of the wafer, thereby optimizing carrier transport, reducing series resistance, reducing surface recombination, and increasing open-circuit voltage. Ultimately, it shows significant advantages in cost optimization and efficiency improvement. Attached Figure Description

[0017] Figure 1 Diagram of the single-layer tunnel structure of the TOPCon battery; Figure 2 Diagram of the double-layer tunnel structure of TOPCon batteries; Figure 3 This is a diagram of the multi-layer tunnel structure of the TOPCon battery. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. To address the technical problems raised in the background art, this invention proposes an improvement to the method for fabricating the back structure of a battery by forming a stacked tunneling layer on the back side to improve yield and efficiency. Furthermore, a stacked tunneling process suitable for TOPCon batteries is proposed, the process comprising: Laughing gas is introduced and the pressure and temperature inside the furnace are controlled within the set range. A glow discharge is performed by an RF power supply to deposit a tunneling oxide layer. The deposition of the tunneling oxide layer involves sequential low-power tunneling and high-power tunneling. The power of low-power tunneling is lower than that of high-power tunneling, and the time of low-power tunneling is shorter than that of high-power tunneling.

[0019] The above embodiments utilize stacked tunneling technology to adjust the power during the deposition tunneling oxidation process, forming a low-power tunneling layer and a high-power tunneling layer. The low-power tunneling layer reduces plasma bombardment of the silicon substrate, thereby reducing damage and improving passivation. The high power of the outer layer improves the on-chip uniformity of the tunneling layer and improves the on-chip bright and dark areas, thereby optimizing carrier transport, reducing series resistance, reducing surface recombination, and increasing open-circuit voltage. Ultimately, it demonstrates significant advantages in cost optimization and efficiency improvement.

[0020] Specifically, during the deposition of the tunneling oxide layer, the flow rate of nitrous oxide introduced is 10,000-12,000 sccm, and the furnace pressure is controlled at 2,000-2,200 mTorr and the temperature at 400-450℃.

[0021] In one embodiment, the power of the low-power tunneling is 500-8000W; and the tunneling time is 10-30 seconds.

[0022] The high-power tunneling has a power of 12,000 to 15,000 W and a tunneling time of 60 to 90 seconds.

[0023] Furthermore, in the embodiments of the present invention, the low-power tunneling forms at least two tunneling layers; the high-power tunneling forms at least two tunneling layers, with the tunneling power increasing sequentially; during the formation of at least two tunneling layers in the low-power tunneling, the tunneling power increases sequentially, and the maximum power is less than 8000W. During the formation of at least two tunneling layers in the high-power tunneling, the tunneling power increases sequentially, and the minimum power is not less than 12000W.

[0024] In one embodiment, a TOPCon battery structure is also provided, wherein the TOPCon battery structure is prepared by any of the above-described stacked tunneling processes, that is, the deposited tunneling oxide layer of the TOPCon battery structure includes a low-power tunneling oxide layer and a high-power tunneling oxide layer. The deposition power of low-power tunneling oxide layer is lower than that of high-power tunneling oxide layer, and the time of low-power tunneling oxide layer is shorter than that of high-power tunneling oxide layer.

[0025] The above embodiments will be described in detail below based on a complete method for preparing a passivation layer on the back of a TOPCon battery. A method for preparing a passivation layer on the back of a TOPCon battery includes: S1: Boat entry, using a conveyor slurry to send a graphite boat containing silicon wafers into the furnace tube, and closing the furnace door after the slurry rod exits the furnace tube; S2: Vacuuming, start vacuuming and auxiliary heating to preheat the furnace tubes, temperature set to 400-450℃; S3: Leak detection, check whether the furnace tube leakage rate is within the normal range; S4: Pre-deposited tunneling layer, nitrous oxide is introduced and the furnace pressure and temperature are controlled within the set range; the nitrous oxide flow rate is 10000-12000 sccm, and the furnace pressure is controlled at 2000-2200 mTorr and the temperature at 400-450℃.

[0026] S5: Tunneling layers a, b, ... The bottom layer reduces damage and improves passivation by reducing plasma bombardment of the silicon substrate through short-term (10-30 seconds) low-power (500-8000W) deposition; the bottom layer is formed by low-power tunneling, which can be one layer or multiple layers, i.e., tunneling layers a, b, ... At least two tunneling layers are formed through low-power short-term deposition; and when forming tunneling layers a, b, ..., the deposition power increases sequentially, but does not exceed 8000W; During implementation, the aforementioned bottom layer takes a short time (10-30 seconds) to form the deposition time of the entire bottom layer. For example, when the bottom layer is multi-layered, the total deposition time of the multi-layered low-power tunneling deposition is 10-30 seconds. The deposition time of each layer in the multi-layered low-power tunneling deposition is adjusted as needed during implementation. For example, when there are 2 layers, the bottom layer takes 5 seconds and the top layer takes 10 seconds, so the deposition time of the bottom layer of the entire 2-layer structure is 15 seconds.

[0027] S6: Tunneling layers 1, 2, ..., the outer layer improves the intra-film uniformity of the tunneling layers and improves the intra-film brightness and darkness through long-term (60-90 seconds) high-power (12000-15000W) tunneling; the outer layer is formed through high-power tunneling; the outer layer can be a single layer or multiple layers, i.e., tunneling layers 1, 2, ..., are formed by high-power long-term deposition, with at least two tunneling layers; when forming tunneling layers 1, 2, ..., the deposition power increases sequentially, not less than 12000W; Similarly, when at least two tunneling layers are formed, the total time for high-power tunneling is 60 to 90 seconds. The deposition time for each layer in the specific multi-layer high-power tunneling deposition is adjusted as needed during implementation. For example, when there are two layers, the inner layer is 30 seconds and the upper layer is 40 seconds, so the bottom layer deposition of the entire two-layer structure is 70 seconds.

[0028] S7: Vacuuming, removing any remaining gas from the furnace tubes; S8: Pre-deposit Poly-1 layer, introduce a mixed gas of silane 3000-3300 sccm, hydrogen 8000-10000 sccm, and phosphine 250-350 sccm, and control the furnace pressure and temperature within the set range of 2800-3100 mTorr and 400-450℃. S9: Poly-1 layer, through RF power supply (power setting 9000-12000W): performs glow discharge on the silicon wafer inside the furnace tube; S10: Vacuuming, removing any remaining gas from the furnace tubes; S11: Pre-deposited "molecular sieve" layer, nitrous oxide is introduced and the pressure and temperature inside the furnace are controlled within the set range. The nitrous oxide flow rate is 10000-12000 sccm, and the pressure inside the furnace is controlled at 2000-2200 mTorr and the temperature is controlled at 400-450℃. S12: Molecular sieve layer, utilizing the conductivity of the graphite boat to perform glow discharge on the silicon wafer inside the furnace tube through an RF power supply (power setting 12000-15000W); S13: Vacuuming, removing any remaining gas from the furnace tubes; S14: Pre-deposit a Poly-2 layer, introduce a mixed gas of silane (3000-3300 sccm), hydrogen (8000-10000 sccm), and phosphine (800-1000 sccm), and control the furnace pressure and temperature within the set range; the furnace pressure is 2800-3100 mTorr and the temperature is 400-450℃. S15: Poly-2 layer, glow discharge is performed on the silicon wafer inside the furnace tube by an RF power supply (power setting 10000-13000W); S16: Vacuuming, removing any remaining gas from the furnace tubes; Compared with existing technologies, the advantages of the embodiments of the present invention are as follows: like Figure 1 -like Figure 3 As shown, the embodiments of the present invention reduce damage and improve passivation level by using stacked tunneling technology to reduce the bombardment of silicon substrate by plasma with low power, while the high power of the outer layer improves the uniformity of the tunneling layer and improves the brightness and darkness of the wafer, thereby optimizing carrier transport, reducing series resistance, reducing surface recombination, and improving open-circuit voltage. Ultimately, it shows significant advantages in cost optimization and efficiency improvement.

[0029] Furthermore, among them Figure 2 The low-power tunneling layer and the high-power tunneling layer are both single layers, thus forming a double-layer tunneling structure. Figure 3 The low-power tunneling layer and the high-power tunneling outer layer both consist of two layers, forming a multi-layered tunneling structure. When both the low-power tunneling layer and the high-power tunneling outer layer are at least two layers, continuous gradient changes can be achieved by controlling the time and power, thus improving performance.

[0030] The following detailed explanation is provided with reference to specific embodiments: Comparative Example Preparation method: Steps S1-S4 are the same as described above, depositing a tunneling layer using high power (12000-15000W) for a process time of 88-100 seconds. Steps S7-S16 are the same as described above. (The film structure is as follows...) Figure 1(As shown).

[0031] Example 1 Preparation method: Steps S1-S4 are the same as described above. Two-layer tunneling is achieved through steps S5-S6. The first layer tunnels using a short time with low power, and the second layer tunnels using a long time with high power (time and power relative to the comparative example). Steps S7-S16 are the same as described above. (The membrane structure is as follows...) Figure 2 , 3 (As shown).

[0032] Based on the above embodiments, the performance of the batteries prepared in the comparative examples and Example 1 was tested (according to national standard GB / T 6495.1). Table 1 below shows the WCT-120 minority carrier lifetime test of the semi-finished batteries prepared in the comparative example and Example 1, and the electrical performance test of the batteries in the comparative example and Example 1 after screen printing and sintering. The WCT-120 minority carrier lifetime test involves texturing N-type single crystal silicon, boron expansion on the front side, oxidation, BSG removal and alkaline polishing, PECVD nitrous oxide ionization tunneling oxide deposition on the back side, poly silicon deposition, annealing, PSG-RCA removal, ALD on the front side, silicon nitride on the back side, sintering, and photoinjection. The minority carrier lifetime test includes the potential open-circuit voltage (1-sun_Implied Voc), the potential fill factor (Implied FF), and the reverse saturation current (Jo) under a standard solar intensity, and then the test results are compared.

[0033] Table 1: Table 2 below shows the electrical performance tests performed on the batteries prepared in the comparative example and Example 1 after screen printing and sintering. Electrical performance testing involves texturing N-type single crystal silicon, boron expansion on the front side, oxidation, BSG removal and alkaline polishing, PECVD nitrous oxide ionization tunneling deposition on the back side, polysilicon deposition, annealing, PSG-RCA removal, ALD and silicon nitride on the front side, silicon nitride on the back side, screen printing on both sides, sintering, photoinjection, and Halm testing.

[0034] Table 2: Tables 1 and 2 present the performance evaluation results of the novel TOPCon solar cells prepared using the methods described in the embodiments of the present invention and the conditions used in the comparative examples. According to the test data in Table 1, under a standard solar intensity, Example 1 has a higher potential open-circuit voltage, a higher potential fill factor, a lower reverse saturation current, and a higher minority carrier lifetime. The results show that the above process has significant advantages in the preparation of TOPCon solar cells.

[0035] According to the test data in Table 2, the photoelectric conversion efficiency (Eta), open circuit voltage (Uoc), short circuit current (Isc), fill factor (FF), series resistance (Rs), and parallel resistance (Rsh) of the Halm test results are generally higher than those of the control group, while the leakage current (IRev2) is lower than that of the control group. This indicates that the various indicators of the present invention have significant advantages in the preparation of TOPCon batteries.

[0036] In this invention, the thickness and uniformity of the thin film can be controlled by changing the power and time gradient of the radio frequency power supply in the steps of preparing tunneling layers a, b, ... and tunneling layers 1, 2, ... to achieve optimal passivation effect. Alternatively, as described in the invention, the tunneling layers can exist in different numbers of layers (e.g., ...). Figure 2 , Figure 3 The stacked tunneling process can be applied to other passivated contact batteries, such as HTBCs, TBCs, and related stacked batteries. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this invention should be included within the protection scope of this invention. Therefore, the protection scope of this invention should be determined by the scope of the claims.

Claims

1. A stacked tunneling process adapted to TOPCon cells, characterized in that, The process includes: Laughing gas is introduced and the pressure and temperature inside the furnace are controlled within the set range. A glow discharge is performed by an RF power supply to deposit a tunneling oxide layer. The deposition of the tunneling oxide layer involves sequential low-power tunneling and high-power tunneling. The power of low-power tunneling is lower than that of high-power tunneling, and the time of low-power tunneling is shorter than that of high-power tunneling.

2. The stacked tunneling process adapted to TOPCon cells according to claim 1, characterized in that, The power of the low-power tunneling is 500-8000W; and the tunneling time is 10-30 seconds.

3. The stacked tunneling process adapted to TOPCon cells according to claim 1, characterized in that, The high-power tunneling has a power of 12000-15000W and a tunneling time of 60-90 seconds.

4. The stacked tunneling process adapted to TOPCon cells according to claim 1, characterized in that, The low-power tunneling forms at least two tunneling layers.

5. The stacked tunneling process adapted to TOPCon cells according to claim 1, characterized in that, The high-power tunneling forms at least two tunneling layers.

6. The stacked tunneling process adapted to TOPCon cells according to claim 4, characterized in that, During the process of forming at least two tunneling layers through low-power tunneling, the power of the tunneling increases sequentially.

7. The stacked tunneling process adapted to TOPCon cells according to claim 4, characterized in that, During the process of forming at least two tunnel layers in the low-power tunneling, the tunneling power increases sequentially, and the maximum power is less than 8000W.

8. The stacked tunneling process adapted to TOPCon cells according to claim 5, characterized in that, During the process of forming at least two tunneling layers through high-power tunneling, the power of the tunneling increases sequentially.

9. The stacked tunneling process adapted to TOPCon cells according to claim 5, characterized in that, During the process of forming at least two tunnel layers in the high-power tunneling, the tunneling power increases sequentially, and the minimum power is not less than 12000W.

10. A TOPCon battery structure, characterized in that, The TOPCon battery structure is prepared using the stacked tunneling process described in any one of claims 1-9.

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