Display panel

Abstract

The display panel includes a base member, an active pattern, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source-drain electrode, a first via planarization layer, an ashing stop layer, a second via planarization layer, a third via planarization layer, a plurality of anode electrodes, and a plurality of light emitting layers. The second via planarization layer is defined with a plurality of planarization opening portions. Accordingly, in a third via planarization layer provided on the second via planarization layer, a portion partially overlapping the plurality of planarization openings is recessed in a concave shape. Accordingly, the plurality of anode electrodes and the plurality of light emitting layers also have a shape of a specific portion recessed by the concave shape according to a shape of the third via planarization layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0114417, filed on August 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display panel having a guaranteed viewing angle at one or more folding angles of the device, an electronic device including the display panel, and a method of manufacturing the display panel. Background Technology

[0004] It is desirable for display devices to have a method that ensures or provides a substantially constant viewing angle at one or more folding angles of the device. For example, the development of such a method has become more important with the development of foldable display devices, bendable display devices, and / or rollable display devices.

[0005] Display devices, such as foldable, bendable, and / or rollable display devices, having one or more shape factors, are repeatedly bent or unfolded to an angle convenient for the user to view the image. Furthermore, since the light-emitting layers of the red, green, and blue pixels of the display device are provided to emit light of different wavelengths, it is desirable for such display devices to have a structure for emitting light according to a specific wavelength range.

[0006] Applying a concave shape to the light-emitting unit of a display panel may be advantageous or beneficial in ensuring or providing a substantially constant viewing angle. Summary of the Invention

[0007] One or more aspects of embodiments of this disclosure relate to a display panel that can ensure or provide a substantially constant viewing angle at one or more folding angles of the device, an electronic device including the display panel, and a method of manufacturing the display panel (or a method of manufacturing the display panel).

[0008] One or more aspects of embodiments of this disclosure relate to a display panel that conforms to or satisfies customer optical characteristic requirements by adjusting the extension angle of the light-emitting unit, an electronic device including the display panel, and a method of manufacturing the display panel (or a method of manufacturing a display panel).

[0009] Further aspects of the embodiments will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0010] A display panel according to one or more embodiments of the present disclosure includes a substrate member, an active pattern, a gate insulating (e.g., electrically insulating) layer, a gate electrode, an interlayer insulating (e.g., electrically insulating) layer, source-drain electrodes, a first via planarization layer, an ablation stop layer, a second via planarization layer, a third via planarization layer, a plurality of anode electrodes, and a plurality of light-emitting layers. The active pattern may include a semiconductor material and is on the substrate member. The gate insulating (e.g., electrically insulating) layer may cover the active pattern. The gate electrode may be on the gate insulating (e.g., electrically insulating) layer and has at least a portion overlapping the active pattern. The interlayer insulating (e.g., electrically insulating) layer may be on the gate electrode. The source-drain electrodes may be on the interlayer insulating (e.g., electrically insulating) layer. The first via planarization layer may be on the source-drain electrodes. The ablation stop layer may include an inorganic material and is on the first via planarization layer. The second via planarization layer may be on the ablation stop layer and defines a plurality of planarization openings. The third via planarization layer may be on the second via planarization layer. Multiple anode electrodes may be located on a third via planarization layer, and at least one of the multiple anode electrodes may overlap with a corresponding planarization opening in the multiple planarization openings. Each of the multiple light-emitting layers may be located on a corresponding anode electrode among the multiple anode electrodes.

[0011] In one or more embodiments of this disclosure, the plurality of light-emitting layers may include a first light-emitting layer that overlaps with one of the plurality of planarized opening portions. The first light-emitting layer may include a first light-emitting unit extending in a selectable direction and a second light-emitting unit extending in a direction that intersects (e.g., intersects) the selectable direction.

[0012] In one or more embodiments of this disclosure, the angle between a plane parallel to (e.g., substantially parallel to) the first via planarization layer and the second light-emitting unit may be greater than approximately 15 degrees and less than approximately 25 degrees.

[0013] In one or more embodiments of this disclosure, the distance between the upper surface of the first via planarization layer and the first light-emitting unit may be less than the distance between the upper surface of the first via planarization layer and the second light-emitting unit.

[0014] In one or more embodiments of this disclosure, the distance between the portion of the upper surface of the third via planarization layer that overlaps with the planarization opening and the upper surface of the first via planarization layer can be a first distance. The distance between the portion of the upper surface of the third via planarization layer that does not overlap with the planarization opening and the upper surface of the first via planarization layer can be a second distance. The first distance can be less than the second distance.

[0015] In one or more embodiments of this disclosure, at least one of a plurality of anode electrodes may include a first anode unit extending in a selectable direction and a second anode unit extending in a direction intersecting (e.g., intersecting) the selectable direction.

[0016] In one or more embodiments of this disclosure, the plurality of light-emitting layers may further include a second light-emitting layer. The distance between the upper surface of the first via planarization layer and the bottom surface of the first light-emitting layer may be less than the distance between the upper surface of the first via planarization layer and the bottom surface of the second light-emitting layer.

[0017] In one or more embodiments of this disclosure, a first light-emitting layer may be provided to emit light having a first wavelength, and a second light-emitting layer may be provided to emit light having a second wavelength shorter than the first wavelength.

[0018] In one or more embodiments of this disclosure, the hard mask layer may include a metallic material. The hard mask layer may be defined with a plurality of metallic openings overlapping a plurality of planarization openings. The hard mask layer may be located between a second via planarization layer and a third via planarization layer.

[0019] In one or more embodiments of this disclosure, the angle between the inner surface of each of the plurality of planarized opening portions and the normal of the ashing stop layer may be an acute angle.

[0020] An electronic device according to one or more embodiments of the present disclosure may include a display panel. The display panel may include a substrate member, an active pattern, a gate insulating (e.g., electrically insulating) layer, a gate electrode, an interlayer insulating (e.g., electrically insulating) layer, source-drain electrodes, a first via planarization layer, an ablation stop layer, a second via planarization layer, a third via planarization layer, a plurality of anode electrodes, and a plurality of light-emitting layers. The active pattern may include a semiconductor material and is on the substrate member. The gate insulating (e.g., electrically insulating) layer may cover the active pattern. The gate electrode may be on the gate insulating (e.g., electrically insulating) layer and is configured to have at least a portion overlapping the active pattern. The interlayer insulating (e.g., electrically insulating) layer may be on the gate electrode. The source-drain electrodes may be on the interlayer insulating (e.g., electrically insulating) layer. The first via planarization layer may be on the source-drain electrodes. The ablation stop layer may include an inorganic material and is on the first via planarization layer. The second via planarization layer may be on the ablation stop layer and defines a plurality of planarization openings. The third via planarization layer may be on the second via planarization layer. Multiple anode electrodes may be located on a third via planarization layer, and at least one of the multiple anode electrodes may overlap with a corresponding planarization opening in the multiple planarization openings. Each of the multiple light-emitting layers may be located on a corresponding anode electrode among the multiple anode electrodes.

[0021] In one or more embodiments of this disclosure, the plurality of light-emitting layers may include a first light-emitting layer that overlaps with any one of the plurality of planarized opening portions. The first light-emitting layer may include a first light-emitting unit extending in a selectable direction and a second light-emitting unit extending in a direction that intersects (e.g., intersects) the selectable direction.

[0022] In one or more embodiments of this disclosure, the angle between a plane parallel to (e.g., substantially parallel to) the first via planarization layer and the second light-emitting unit may be greater than approximately 15 degrees and less than approximately 25 degrees.

[0023] In one or more embodiments of this disclosure, the distance between the upper surface of the first via planarization layer and the first light-emitting unit may be less than the distance between the upper surface of the first via planarization layer and the second light-emitting unit.

[0024] In one or more embodiments of this disclosure, the distance between the portion of the upper surface of the third via planarization layer that overlaps with the planarization opening and the upper surface of the first via planarization layer can be a first distance. The distance between the portion of the upper surface of the third via planarization layer that does not overlap with the planarization opening and the upper surface of the first via planarization layer can be a second distance. The first distance can be less than the second distance.

[0025] In one or more embodiments of this disclosure, at least one of a plurality of anode electrodes may include a first anode unit extending in a selectable direction and a second anode unit extending in a direction intersecting (e.g., intersecting) the selectable direction.

[0026] In one or more embodiments of this disclosure, the plurality of light-emitting layers may include a second light-emitting layer. The distance between the upper surface of the first via planarization layer and the bottom surface of the first light-emitting layer may be less than the distance between the upper surface of the first via planarization layer and the bottom surface of the second light-emitting layer.

[0027] In one or more embodiments of this disclosure, a first light-emitting layer may be provided to emit light having a first wavelength, and a second light-emitting layer may be provided to emit light having a second wavelength shorter than the first wavelength.

[0028] A method for manufacturing a display panel according to one or more embodiments of the present disclosure includes the steps of providing a first via planarization layer, providing an ablation stop layer, providing a second via planarization layer, providing a hard mask layer, providing a metal opening portion, providing a planarized opening portion, providing a third via planarization layer, providing an anode electrode, and providing a light-emitting layer. In the step of providing the first via planarization layer, a first via planarization layer covering an electrode pattern may be provided. After the step of providing the first via planarization layer, a step of providing an ablation stop layer comprising an inorganic material may be included. After the step of providing the ablation stop layer, a step of providing a second via planarization layer may be included. After the step of providing the second via planarization layer, a step of providing a hard mask layer comprising a metallic material may be included. After the step of providing the hard mask layer, a step of providing a metal opening portion may be included. After the step of providing the metal opening portion, a step of providing a planarized opening portion overlapping the metal opening portion may be included in the second via planarization layer. After the step of providing the planarized opening portion, a step of providing a third via planarization layer may be included on the second via planarization layer. After the step of providing the third via planarization layer, a step of providing an anode electrode overlapping the planarized opening portion may be included on the third via planarization layer. After the step of providing the anode electrode, a step of providing a light-emitting layer may be included on the anode electrode.

[0029] One or more embodiments of this disclosure provide a display panel having a guaranteed viewing angle at one or more folding angles of the device, an electronic device including the display panel, and a method of manufacturing the display panel.

[0030] One or more embodiments of this disclosure provide a display panel that conforms to or satisfies customer optical characteristic requirements by adjusting the extension angle of the light-emitting unit, an electronic device including the display panel, and a method of manufacturing the display panel. Attached Figure Description

[0031] The above and other aspects and features of specific embodiments of this disclosure will become more apparent and readily understood from the following description of one or more embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1A and Figure 1B This is a schematic diagram of an electronic device according to one or more embodiments of the present disclosure;

[0033] Figures 2A to 2D Each of these is a cross-sectional view of an electronic device according to one or more embodiments of the present disclosure;

[0034] Figure 3 This is an exemplary illustration of a portion of a cross-section of a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 4 Is it like this? Figure 3 An exemplary enlarged view of the area marked AA in the diagram;

[0036] Figure 5 According to one or more embodiments of this disclosure, such as Figure 3 Another exemplary enlarged view of the area marked AA in the diagram;

[0037] Figure 6 This is an exemplary illustration of a portion of a cross-section of a display panel according to one or more embodiments of the present disclosure;

[0038] Figure 7 This is an exemplary illustration of a portion of a cross-section of a display panel according to one or more embodiments of the present disclosure;

[0039] Figure 8 This is an exemplary illustration of a portion of a cross-section of a display panel according to one or more embodiments of the present disclosure;

[0040] Figure 9 This is an exemplary illustration of a portion of a cross-section of a display panel according to one or more embodiments of the present disclosure;

[0041] Figure 10 This is a flowchart of a method for manufacturing a display panel according to one or more embodiments of the present disclosure;

[0042] Figure 11A Is it like this? Figure 4 An exemplary illustration of the layout of the first via planarization layer shown in the figure;

[0043] Figure 11B Is towards Figure 11A An illustration of adding a grayscale stop layer;

[0044] Figure 11C Is towards Figure 11B Illustration of adding a second via planarization layer;

[0045] Figure 11D Is towards Figure 11C Illustration of adding a hard mask layer;

[0046] Figure 11E Is Figure 11D An exemplary illustration of the steps providing the first metal opening portion is provided;

[0047] Figure 11F Is Figure 11E An exemplary illustration of the steps for the first flattening opening portion is provided;

[0048] Figure 11G Is towards Figure 11F Illustration of the layout with a third via planarization layer added;

[0049] Figure 11H Is towards Figure 11G A diagram showing the layout with the first anode electrode added;

[0050] Figure 11I Is towards Figure 11H Illustration of the layout with added hole function layer and pixel confinement film;

[0051] Figure 11J Is towards Figure 11I A diagram illustrating the layout with the first light-emitting layer added;

[0052] Figure 12 This is an exemplary block diagram of an electronic device according to one or more embodiments; and

[0053] Figure 13 The figure shows a schematic diagram of an electronic device according to one or more embodiments. Detailed Implementation

[0054] Reference will be made in more detail to one or more embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals refer to the same elements throughout. In this respect, the subject matter of this disclosure may be embodied in different forms and arrangements, but this disclosure should in no way be construed as limited to the one or more embodiments set forth herein. Rather, this disclosure should be construed as encompassing all forms, arrangements, equivalents, and substitutions that fall within the spirit and scope of this disclosure. More precisely, these embodiments are provided as examples, with reference to the accompanying drawings, to illustrate aspects and features of this disclosure to those skilled in the art.

[0055] Similar or identical reference numerals refer to similar or identical elements. Furthermore, in the drawings, the thickness, ratios, and dimensions of elements may not be to exact scale and may have been exaggerated to effectively or appropriately illustrate the technical features of this disclosure associated with these elements. Therefore, this disclosure should not be limited to the thicknesses, ratios, and / or dimensions illustrated in the drawings.

[0056] Expressions such as “having,” “including,” or “comprising” are intended to specify a feature, number, step, operation, element, part, or combination thereof, and should not be construed as excluding any possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof.

[0057] In this disclosure, it will be understood that the terms “comprising,” “including,” or “having” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising,” “including,” “having,” or similar terms include or support the terms “consisting of,” and “substantially consisting of,” thereby indicating the presence of the stated features, integrals, steps, operations, elements, and / or components, without excluding or substantially excluding the presence of other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have substantially the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Any term defined in a dictionary, or which is generally available or commonly used, shall be interpreted as having substantially the same meaning as it has in the context of the relevant field, and shall not be interpreted as having an ideal or overly formalistic meaning unless otherwise expressly defined.

[0059] Figure 1A and Figure 1B This is a schematic diagram of an electronic device ED according to one or more embodiments of the present disclosure.

[0060] According to one or more embodiments of this disclosure, Figure 1A and Figure 1B A display device is illustrated as an electronic device ED, as exemplarily shown. For example, a foldable display device that is foldable along a folding axis FX is illustrated as an electronic device ED. However, embodiments of this disclosure are not limited to those illustrated in the figures and may include one or more suitable electronic devices. For example, the display device may be a device that displays images on a front surface, such as a monitor, television, smartphone, wearable device, navigation device, and / or tablet computer. The shape and / or function are not limited thereto. For example, the front surface may be one or more suitable shapes such as circular (e.g., a substantially circular shape) or polygonal (e.g., a substantially polygonal shape). In one or more embodiments, the display device may be a bendable display device and / or a rollable display device.

[0061] A first direction DR1, a second direction DR2, and a third direction DR3 can be defined. The first direction DR1 and the second direction DR2 can be, for example... Figure 1A and Figure 1B The directions defined on the plane of the electronic device ED in the diagram can intersect each other (e.g., cross each other). The third direction DR3 can be as follows: Figure 1A and Figure 1BThe thickness direction of the electronic device ED shown in the figure.

[0062] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a cross-sectional view of an electronic device ED according to one or more embodiments of the present disclosure. According to one or more embodiments of the present disclosure, a display device is exemplarily illustrated as an electronic device ED. Figure 2A , Figure 2B , Figure 2C and Figure 2D Simplified to describe the lamination relationship between the functional panels and / or functional components that constitute a display device.

[0063] like Figure 2A As illustrated, the electronic device ED may include a display panel DP, an input sensor circuit ISC, a reflection protection component RPP, and a window component WP. The input sensor circuit ISC may be directly on the display panel DP. If an element is "directly disposed" or "directly on" another element (e.g., when an element is "directly disposed" or "directly on" another element), it should be interpreted that there are no other adhesive layers / adhesive components between them.

[0064] In this disclosure, the display module DPM can be defined as including a display panel DP and an input sensor circuit ISC on the display panel DP. An optically transparent (e.g., substantially transparent) adhesive member OCA can be provided between the display module DPM and the reflective protective member RPP, and between the reflective protective member RPP and the window member WP.

[0065] The display panel DP can reproduce an image, and the input sensor circuit ISC can obtain coordinate information from external inputs (e.g., microcurrents and / or applied pressure). The display module DPM according to one or more embodiments of this disclosure may further include a protective plate beneath the display panel DP. The protective plate and the display panel DP can be joined by an adhesive member, as described below. Figure 2B , Figure 2C and Figure 2D The display device may further include protective components.

[0066] The display panel DP according to one or more embodiments of this disclosure may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, a quantum dot light-emitting display panel, or a micro light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. Inorganic light-emitting display panels made of inorganic materials may include quantum dot light-emitting display panels or micro light-emitting display panels. Hereinafter, the display panel DP will be described in more detail as an organic light-emitting display panel.

[0067] The display panel DP may be defined by a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image, and the non-display area NDA may be an area adjacent to the display area DA where no image is displayed. The non-display area NDA may be around the display area DA (e.g., surrounding the display area DA). However, this is an exemplary illustration, and the non-display area NDA may be adjacent to a portion of the edge of the display area DA and is not limited to the disclosed embodiments.

[0068] A reflective protective member RPP can reduce the reflectivity of external light incident from the upper side of a window member WP. According to one or more embodiments of this disclosure, the reflective protective member RPP may include a retarder and a polarizer.

[0069] The reflective protective member RPP according to one or more embodiments of the present disclosure may include a color filter.

[0070] A window member WP according to one or more embodiments of the present disclosure may include a base film WP-BS and a light-shielding pattern WP-BZ. The base film WP-BS may include glass and / or synthetic resin. The base film WP-BS is not limited to a single layer. The base film WP-BS may include two or more films joined by an adhesive member.

[0071] The light-shielding pattern WP-BZ may partially overlap with the base film WP-BS. The light-shielding pattern WP-BZ may be below the base film WP-BS to define the border area of ​​the display device, such as the non-display area NDA.

[0072] In the following text, the light-shielding pattern WP-BZ and the basement membrane WP-BS may not be mentioned. Figure 2B , Figure 2C and Figure 2D The diagram in the middle is shown.

[0073] like Figure 2B As illustrated in the diagram, the electronic device ED may include a display panel DP, a reflection protection component RPP, an input sensor circuit ISC, and a window component WP.

[0074] The display panel (DP) and the reflective protection component (RPP) can be connected via an optically transparent adhesive component (OCA). The reflective protection component (RPP) and the input sensor circuit (ISC) can be connected via an optically transparent adhesive component (OCA). The input sensor circuit (ISC) and the window component (WP) can be connected via an optically transparent adhesive component (OCA).

[0075] refer to Figure 2C ,and Figure 2B The difference is that the positions of the reflective protection component RPP and the input sensor circuit ISC can be interchanged.

[0076] like Figure 2D As illustrated, adhesive components may not be provided in the electronic device ED, and the display panel DP, input sensor circuit ISC, reflective protective component RPP, and window component WP can be laminated sequentially. In one or more embodiments of this disclosure, the lamination order of the input sensor circuit ISC and reflective protective component RPP can be interchanged.

[0077] Figure 3 This is an exemplary illustration of a portion of a cross-section of a display panel DP according to one or more embodiments of the present disclosure.

[0078] The display panel (DP) may include a substrate (BL), a circuit layer (CL), a light-emitting diode (EDL) layer, and a packaging layer (TFE).

[0079] The substrate component BL may include at least one selected from organic materials and inorganic materials such as glass.

[0080] The circuit layer CL may be located on the substrate component BL. The circuit layer CL may include a barrier layer BR, a buffer layer BF, an active pattern ACT, gate insulating layers GI1 and GI2, gate electrodes GAT1 and GAT2, an interlayer insulating layer ILD, source-drain electrodes SD1 and SD2, via planarization layers VIA1, VIA2 and VIA3, an ashing stop layer ASST, and a hard mask layer MHM. In one or more embodiments, the circuit layer CL may include a transistor. A portion of the active pattern ACT may constitute an active cell of the transistor, portions of the gate electrodes GAT1 and GAT2 may constitute the control electrodes of the transistor, and portions of the source-drain electrodes SD1 and SD2 may constitute the input and output electrodes of the transistor.

[0081] The light-emitting diode layer (EDL) can be on the circuit layer (CL). The EDL can include light-emitting diodes (LD1, LD2, and LD3) and a pixel-defining film (PDL).

[0082] A TFE encapsulation layer can be provided to seal the LED layer to protect it from external oxygen and / or moisture (or reduce the extent or frequency of exposure of the LED layer to external oxygen and / or moisture).

[0083] The encapsulation layer TFE may include a first inorganic layer CVD1, an organic layer MN, and a second inorganic layer CVD2. Figure 3 In the illustration, as an example, the encapsulation layer TFE is shown to include two inorganic layers and one organic layer; however, embodiments of this disclosure are not limited to this example. For instance, the encapsulation layer TFE may include three inorganic layers and two organic layers, and in one or more embodiments, the inorganic and organic layers may be laminated alternately.

[0084] Functional layers, such as barrier layers BR and / or buffer layers BF, may be present on one side of the substrate member BL. These functional layers may include barrier layers BR and / or buffer layers BF.

[0085] Functional layers such as barrier layers (BR) and / or buffer layers (BF) can be provided to prevent impurities present at the bottom from flowing into the pixel during the manufacturing process (or reduce the extent or rate of impurities present at the bottom flowing into the pixel during the manufacturing process). For example, functional layers such as barrier layers (BR) and / or buffer layers (BF) can be provided to prevent impurities from diffusing into the active pattern ACT constituting the pixel (or reduce the extent or rate of impurities diffusing into the active pattern ACT constituting the pixel).

[0086] The active pattern ACT constituting the transistor may be on the buffer layer BF. The active pattern ACT may include polycrystalline silicon and / or amorphous (e.g., non-crystalline) silicon. In one or more embodiments, the active pattern ACT may include polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, and / or metal-oxide-semiconductor.

[0087] An active pattern ACT may include a channel region that acts as a channel through which electrons or holes can move, and a first ion-doped region and a second ion-doped region, with the channel region between the first ion-doped region and the second ion-doped region.

[0088] The first gate insulating layer GI1 covering the active pattern ACT can be on the buffer layer BF. The first gate insulating layer GI1 may include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and / or an aluminum oxide layer. However, embodiments of this disclosure are not limited thereto.

[0089] The first gate electrode GAT1 may be on the first gate insulating layer GI1. The first gate electrode GAT1 may have a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys thereof.

[0090] A second gate insulating layer GI2 covering the first gate electrode GAT1 may be present on the first gate insulating layer GI1. The second gate insulating layer GI2 may comprise an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and / or an aluminum oxide layer. However, embodiments of this disclosure are not limited thereto.

[0091] The second gate electrode GAT2 can be on the second gate insulating layer GI2.

[0092] The second gate electrode GAT2 may have a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0093] Figure 3 The illustration exemplarily shows that the gate electrodes GAT1 and GAT2 of the transistor can serve as upper gates on the active pattern ACT, but the embodiments of this disclosure are not limited thereto. The gate electrodes GAT1 and GAT2 of the transistor can serve as lower gates below the active pattern ACT, or the gate electrodes GAT1 and GAT2 can serve as dual gates both above and below the active pattern ACT.

[0094] The interlayer insulating layer (ILD) covering the second gate electrode GAT2 can be on the second gate insulating layer GAT2. The interlayer insulating layer (ILD) can include organic films and / or inorganic films. The interlayer insulating layer (ILD) can include multiple inorganic films and / or multiple organic films. The multiple inorganic films can include silicon nitride layers and / or silicon oxide layers.

[0095] The first source-drain electrode SD1 can be on the interlayer insulating layer ILD. The first source-drain electrode SD1 can be connected to the active pattern ACT through contact holes that penetrate the gate insulating layers GI1 and GI2 and the interlayer insulating layer ILD.

[0096] The first via planarization layer VIA1 may be on the first source-drain electrode SD1. The first via planarization layer VIA1 may include an organic film and / or an inorganic film. For example, the first via planarization layer VIA1 may include an organic film of acrylic resin, epoxy resin, phenolic resin and / or polyimide resin. The first via planarization layer VIA1 may provide a flat surface (e.g., a substantially flat surface).

[0097] An ashing stop layer ASST may be provided on the first via planarization layer VIA1. The ashing stop layer ASST may comprise an inorganic material. The ashing stop layer ASST may be provided to prevent the first via planarization layer VIA1 from being etched during the ashing process (or to reduce the degree or frequency of etching of the first via planarization layer VIA1 during the ashing process). In one or more embodiments, the upper and lower thicknesses of the second via planarization layer VIA2 on the ashing stop layer ASST may be adjusted to a desired width. Here, the upper and lower thicknesses of the second via planarization layer VIA2 may refer to the height of the second via planarization layer VIA2 itself.

[0098] The second source-drain electrode SD2 can be located on the ashing stop layer ASST. The second source-drain electrode SD2 can be connected to the first source-drain electrode SD1 through a contact hole that penetrates the ashing stop layer ASST and the first via planarization layer VIA1.

[0099] The second via planarization layer VIA2 may be located on the second source-drain electrode SD2. The second via planarization layer VIA2 may comprise an organic film and / or an inorganic film. For example, the second via planarization layer VIA2 may comprise an organic film of acrylic resin, epoxy resin, phenolic resin, and / or polyimide resin. The second via planarization layer VIA2 may provide a flat surface (e.g., a substantially flat surface).

[0100] According to one or more embodiments of this disclosure, the second via planarization layer VIA2 may be defined with a first planarization opening portion F-OP1. In one or more embodiments, the second via planarization layer VIA2 may further be defined with a plurality of planarization opening portions in addition to the first planarization opening portion F-OP1.

[0101] A hard mask layer MHM may be present on the second via planarization layer VIA2. The hard mask layer MHM may comprise a metallic material. The hard mask layer MHM may be provided to prevent a portion of the second via planarization layer VIA2 from being etched during a photoresist process (or to reduce the extent or frequency of etching of a portion of the second via planarization layer VIA2 during a photoresist process). In one or more embodiments, the width of the first planarization opening portion F-OP1 defined in the second via planarization layer VIA2 from left to right may be adjusted to a desired width.

[0102] According to one or more embodiments of this disclosure, the hard mask layer MHM may be defined with a first metal opening portion M-OP1. In one or more embodiments, the hard mask layer MHM may be further defined with multiple metal opening portions in addition to the first metal opening portion M-OP1.

[0103] According to one or more embodiments of the present disclosure, the first metal opening portion M-OP1 may overlap with the first planarized opening portion F-OP1.

[0104] The third via planarization layer VIA3 can be on the hard mask layer MHM. The third via planarization layer VIA3 can include organic and / or inorganic films. For example, the third via planarization layer VIA3 can include organic films of acrylic resin, epoxy resin, phenolic resin, and / or polyimide resin. The third via planarization layer VIA3 can provide a flat surface (e.g., a substantially flat surface). The third via planarization layer VIA3 can be between the anode electrodes AE1, AE2, and AE3 and the hard mask layer MHM.

[0105] The pixel-limiting film PDL and / or light-emitting diodes LD1, LD2 and LD3 can be on the third via planarization layer VIA3.

[0106] The first light-emitting diode LD1 may include a first anode electrode AE1, a hole functional layer HL, a first light-emitting layer EML1, an electron functional layer EL, and a cathode electrode CE.

[0107] The second light-emitting diode LD2 may include a second anode electrode AE2, a hole functional layer HL, a second light-emitting layer EML2, an electron functional layer EL, and a cathode electrode CE.

[0108] The third light-emitting diode LD3 may include a third anode electrode AE3, a hole functional layer HL, a third light-emitting layer EML3, an electron functional layer EL, and a cathode electrode CE.

[0109] Anode electrodes AE1, AE2, and AE3 can be connected to the second source-drain electrode SD2 through contact holes penetrating the third via planarization layer VIA3, the hard mask layer MHM, and the second via planarization layer VIA2. Anode electrodes AE1, AE2, and AE3 can overlap with the first metal opening portion M-OP1 and the first planarization opening portion F-OP1.

[0110] The pixel opening portion P-OP defined in the pixel-limiting film PDL can expose the anode electrodes AE1, AE2 and AE3.

[0111] In this disclosure, the first light-emitting diode LD1, the second light-emitting diode LD2, and the third light-emitting diode LD3 are illustrated as parallel (e.g., substantially parallel). However, it should be understood that the first light-emitting diode LD1, the second light-emitting diode LD2, and the third light-emitting diode LD3 may not be on substantially the same plane and may not be electrically connected. This is consistent with... Figure 6 , Figure 7 and Figure 9 They are basically the same.

[0112] According to one or more embodiments of this disclosure, Figure 3 It can be divided into three regions: AR1 (first region), AR2 (second region), and AR3 (third region). In the following text, Figure 6 , Figure 7 , Figure 8 and Figure 9 It can also be divided into three regions: AR1 (first region), AR2 (second region), and AR3 (third region).

[0113] According to one or more embodiments of this disclosure, Figure 3The first region AR1 can be fitted with a concave structure (e.g., a substantially concave structure) to provide a first light-emitting layer EML1 with a concave shape (e.g., a substantially concave shape). The second region AR2 can be fitted with a non-concave structure to provide a second light-emitting layer EML2 with a flat shape (e.g., a substantially flat shape). The third region AR3 can be fitted with a non-concave structure to provide a third light-emitting layer EML3 with a flat shape (e.g., a substantially flat shape).

[0114] According to one or more embodiments of this disclosure, the distance between the upper surface of the first via planarization layer VIA1 and the bottom surface of the first light-emitting layer EML1 may be less than the distance between the upper surface of the first via planarization layer VIA1 and the bottom surface of the second light-emitting layer EML2.

[0115] A first emitting layer EML1, a second emitting layer EML2, and a third emitting layer EML3 can be provided to emit light with different wavelengths. The wavelength of light emitted from the second emitting layer EML2 can be shorter than the wavelength of light emitted from the first emitting layer EML1, and the wavelength of light emitted from the third emitting layer EML3 can be shorter than the wavelength of light emitted from the second emitting layer EML2. As an example, the first emitting layer EML1 can emit red light, the second emitting layer EML2 can emit green light, and the third emitting layer EML3 can emit blue light.

[0116] According to one or more embodiments of this disclosure, if the first light-emitting layer EML1 emitting red light is applied with a concave structure (e.g., a substantially concave structure) (e.g., when the first light-emitting layer EML1 emitting red light is applied with a concave structure (e.g., a substantially concave structure)), then ensuring or providing a substantially constant viewing angle at one or more folding angles of the device and reducing the phenomenon of the screen displaying blue may be effective or suitable. However, embodiments of this disclosure are not limited thereto, and the wavelengths of the light emitted from the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may be modified. According to one or more embodiments of this disclosure, the first light-emitting layer EML1 may overlap with the first metal opening portion M-OP1 and the first planarized opening portion F-OP1.

[0117] In the following text, see references Figure 4 The concave structure (e.g., substantially concave structure) of the first light-emitting layer EML1, which provides a concave shape (e.g., a substantially concave shape), is described in more detail.

[0118] Figure 4 yes Figure 3 An exemplary magnified view of the area marked AA in the image.

[0119] The third via planarization layer VIA3 can have a concave structure (e.g., a substantially concave structure) through the first planarization opening F-OP1 and the first metal opening M-OP1. For example, the distance between the portion of the upper surface of the third via planarization layer VIA3 that overlaps with the first planarization opening F-OP1 and the first metal opening M-OP1 and the upper surface of the first via planarization layer VIA1 can be a first distance D1. The distance between the portion of the upper surface of the third via planarization layer VIA3 that does not overlap with the first planarization opening F-OP1 and the first metal opening M-OP1 and the upper surface of the first via planarization layer VIA1 can be a second distance D2. In one or more embodiments, the first distance D1 can be less than the second distance D2.

[0120] According to one or more embodiments of the present disclosure, the first light-emitting layer EML1 may include a first light-emitting unit EML1-1 extending in a selectable direction and a second light-emitting unit EML1-2 extending in a direction that intersects (e.g., crosses) the selectable direction.

[0121] According to one or more embodiments of this disclosure, the angle CR between the plane parallel to (e.g., substantially parallel to) the first via planarization layer VIA1 and the second light-emitting unit EML1-2 can be greater than approximately 15 degrees and less than approximately 25 degrees.

[0122] If the first light-emitting layer EML1 is an organic light-emitting layer (e.g., when the first light-emitting layer EML1 is an organic light-emitting layer), a significant reduction in brightness may occur at viewing angles greater than approximately 20 degrees, depending on the material properties. In one or more embodiments, considering process dispersion, a reduction in brightness can be prevented if the angle CR between the plane parallel to (e.g., substantially parallel to) the first via planarization layer VIA1 and the second light-emitting unit EML1-2 is greater than approximately 15 degrees and less than approximately 25 degrees (e.g., when the angle CR between the plane parallel to (e.g., substantially parallel to) the first via planarization layer VIA1 and the second light-emitting unit EML1-2 is greater than approximately 15 degrees and less than approximately 25 degrees). However, this is an angle suggested as an example, and the angle may be modified as needed or required according to one or more embodiments.

[0123] According to one or more embodiments of this disclosure, the distance between the upper surface of the first via planarization layer VIA1 and the first light-emitting unit EML1-1 can be less than the distance between the upper surface of the first via planarization layer VIA1 and the second light-emitting unit EML1-2.

[0124] According to one or more embodiments of the present disclosure, the first anode electrode AE1 may include a first anode unit AE1-1 extending in a selectable direction and a second anode unit AE1-2 extending in a direction intersecting (e.g., intersecting) the selectable direction.

[0125] According to one or more embodiments of this disclosure, the angle between the plane parallel to (e.g., substantially parallel to) the first via planarization layer VIA1 and the second anode unit AE1-2 can be greater than approximately 15 degrees and less than approximately 25 degrees. However, this is an angle suggested as an example, and according to one or more embodiments, the angle may be modified as needed or required.

[0126] In one or more embodiments of this disclosure, the plane defining the first planarization opening portion F-OP1 of the second via planarization layer VIA2 may be orthogonal (e.g., substantially orthogonal) to the ashing stop layer ASST.

[0127] Figure 5 Is it like this? Figure 3 An enlarged view of another example, AA-1, of the area labeled AA shown in the diagram. (Compared to...) Figure 4 The difference is that, in Figure 5 In the process, the plane of the first planarization opening portion F-OP1 defined by the second through-hole planarization layer VIA2 may not be orthogonal to the ashing stop layer ASST.

[0128] For example, the angle between the normal (e.g., substantially perpendicular) direction of the ashing stop layer ASST and the inner plane surface defining the first planarization opening portion F-OP1 of the second via planarization layer VIA2 can be an acute angle. A more detailed description of another element can be provided below. Figure 3 and Figure 4 The detailed description of another element in the text is essentially the same, and therefore may not be provided.

[0129] Figure 6 This is an exemplary illustration of a portion of a cross-section of a display panel DP according to one or more embodiments of the present disclosure. Figure 3 The difference is that, in Figure 6 In the first region AR1 and the second region AR2, a concave structure (e.g., a substantially concave structure) can be applied to provide concave-shaped (e.g., substantially concave) light-emitting layers EML1 and EML2. A non-concave structure can be applied to the third region AR3 to provide a flat-shaped (e.g., substantially flat) third light-emitting layer EML3.

[0130] In addition, such as Figure 6As illustrated in the diagram, the second planarization opening portion F-OP2 can be defined within the second region AR2 and the second via planarization layer VIA2. In one or more embodiments, as... Figure 6 As shown in the diagram, the second metal opening portion M-OP2 can be confined within the second region AR2, within the hard mask layer MHM.

[0131] According to one or more embodiments of the present disclosure, the second metal opening portion M-OP2 may overlap with the second planarized opening portion F-OP2.

[0132] According to one or more embodiments of the present disclosure, the second light-emitting layer EML2 may overlap with the second metal opening portion M-OP2 and the second planarized opening portion F-OP2.

[0133] According to one or more embodiments of the present disclosure, the second anode electrode AE2 may overlap with the second metal opening portion M-OP2 and the second planarized opening portion F-OP2.

[0134] In the following text, the description of concave structures (e.g., substantially concave structures) can be compared with... Figure 3 and Figure 4 The description of concave structures (e.g., substantially concave structures) is essentially the same and therefore may not be provided.

[0135] Figure 7 This is an exemplary illustration of a cross-section of a display panel DP according to one or more embodiments of the present disclosure. Figure 6 The difference is that the concave structures (e.g., substantially concave structures) of the light-emitting layers EML1, EML2, and EML3 used to provide concave shapes (e.g., substantially concave shapes) can be applied to the first region AR1, the second region AR2, and the third region AR3.

[0136] exist Figure 7 In this context, the third region AR3 may be defined by a third planarization opening portion F-OP3 within the second via planarization layer VIA2. In one or more embodiments, in... Figure 7 In the middle, the third region AR3 can be defined by the third metal opening portion M-OP3 in the hard mask layer MHM.

[0137] According to one or more embodiments of the present disclosure, the third metal opening portion M-OP3 may overlap with the third planarized opening portion F-OP3.

[0138] According to one or more embodiments of the present disclosure, the third light-emitting layer EML3 may overlap with the third metal opening portion M-OP3 and the third planarization opening portion F-OP3.

[0139] According to one or more embodiments of the present disclosure, the third anode electrode AE3 may overlap with the third metal opening portion M-OP3 and the third planarized opening portion F-OP3.

[0140] In the following text, the description of concave structures (e.g., substantially concave structures) can be compared with... Figure 3 and Figure 4 The description of concave structures (e.g., substantially concave structures) is essentially the same and therefore may not be provided.

[0141] Figure 8 This is an exemplary illustration of a portion of a cross-section of a display panel DP according to one or more embodiments of the present disclosure. (As shown in the image) Figure 3 The difference in the laminated structure shown in the diagram is that, Figure 8 The diagram shows the laminated structure excluding the hard mask layer MHM on the second via planarization layer VIA2. In the following description, the concave structure (e.g., a substantially concave structure) can be compared with... Figure 3 and Figure 4 The description of concave structures (e.g., substantially concave structures) is essentially the same and therefore may not be provided. For example... Figure 8 The structure shown in the middle diagram can be provided by removing the hard mask layer MHM via a method such as wet etching before providing the third via planarization layer VIA3.

[0142] Figure 9 This is an exemplary illustration of a portion of a cross-section of a display panel DP according to one or more embodiments of the present disclosure. (As shown in the image) Figure 3 The difference in the laminated structure shown in the diagram is that, Figure 9 In this context, the ashing stop layer ASST can be placed on the second source-drain electrode SD2. In the following description, the concave structure (e.g., a substantially concave structure) can be compared with... Figure 3 and Figure 4 The description of concave structures (e.g., substantially concave structures) is essentially the same and therefore may not be provided.

[0143] Figure 10 This is a flowchart of a method S10 for manufacturing a display panel according to one or more embodiments of the present disclosure. Here, a repeated description of the display panel as described in one or more embodiments may be omitted from the description of the method S10 for manufacturing the display panel.

[0144] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H , Figure 11I and Figure 11J This is a cross-sectional view corresponding to a portion of the manufacturing process S10 of a display panel according to one or more embodiments of the present disclosure. In this disclosure, for convenience, the figures shown are as follows... Figure 3 The manufacturing method S10 is illustrated in the diagram for the area marked AA. In one or more embodiments, the manufacturing method S10 for the display panel can also be applied substantially the same way, except for... Figure 3 The area outside the region marked AA in the diagram.

[0145] refer to Figure 10 and Figure 11A The manufacturing method S10 of a display panel according to one or more embodiments of the present disclosure may include the step S100 of providing a first via planarization layer.

[0146] refer to Figure 10 and Figure 11B A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include step S110, following step S100 of providing a first via planarization layer, of providing an altrace stop layer ASST on the first via planarization layer VIA1. In one or more embodiments, the altrace stop layer ASST may comprise an inorganic material.

[0147] refer to Figure 10 and Figure 11C The manufacturing method S10 of a display panel according to one or more embodiments of the present disclosure may include step S120, after step S110 of providing a gray stop layer, providing a second via planarization layer VIA2 on the gray stop layer ASST to provide a second via planarization layer VIA2.

[0148] refer to Figure 10 and Figure 11D A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include step S130, following step S120 of providing a second via planarization layer, of providing a hard mask layer MHM on the second via planarization layer VIA2. In one or more embodiments, the hard mask layer MHM may comprise a metallic material.

[0149] refer to Figure 10 and Figure 11EA method S10 for manufacturing a display panel according to one or more embodiments of the present disclosure may include a step S140, following a step S130 of providing a hard mask layer, of providing a metal opening portion M-OP1 in the hard mask layer MHM to provide a metal opening portion M-OP1. In this disclosure, the step of providing the first metal opening portion M-OP1 may be performed by a photoresist process. The photoresist process may further include a step of providing a photoresist layer that completely overlaps with the upper surface of the hard mask layer MHM. Step S140 of providing the metal opening portion may further include an etching process following the photoresist process.

[0150] refer to Figure 10 and Figure 11F A method S10 for manufacturing a display panel according to one or more embodiments of the present disclosure may include a step S150, following a step S140 of providing a metal opening portion, of providing a first planarization opening portion F-OP1 in a second via planarization layer VIA2 to provide a planarization opening portion. The step of providing the first planarization opening portion F-OP1 may be performed by a photoresist process. The photoresist process may further include a step of providing a photoresist layer that completely overlaps with the upper surface of a hard mask layer MHM. Step S150 of providing the planarization opening portion may further include an etching process following the photoresist process. In step S150 of providing the planarization opening portion, the hard mask layer MHM may be used as a mask to provide planarization opening portions F-OP1, F-OP2, and F-OP3.

[0151] refer to Figure 10 and Figure 11G A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include step S160, following step S150 of providing a planarization opening portion, a third via planarization layer VIA3 is provided on a hard mask layer MHM to provide a third via planarization layer VIA3. According to one or more embodiments of the present disclosure, the third via planarization layer VIA3 may include a region overlapping with the first metal opening portion M-OP1 and the first planarization opening portion F-OP1. Since etching processes are performed in step S140 of providing the metal opening portion and step S150 of providing the planarization opening portion, the region of the third via planarization layer VIA3 that overlaps with the etched portion of the second via planarization layer VIA2 may have a concave shape (e.g., a substantially concave shape).

[0152] According to one or more embodiments of this disclosure, the step of removing the hard mask layer MHM by removing the hard mask layer MHM may be further included between step S150 of providing the planarized opening portion and step S160 of providing the third via planarization layer. In one or more embodiments, the hard mask layer MHM may be removed by a wet etching process. If the hard mask layer MHM is removed (e.g., when the hard mask layer MHM is removed), then in step S160 of providing the third via planarization layer, the third via planarization layer VIA3 may be provided on the second via planarization layer VIA2.

[0153] refer to Figure 10 and Figure 11H According to one or more embodiments of the present disclosure, the manufacturing method S10 of a display panel may include a step S170 of providing an anode electrode by providing a first anode electrode AE1 on the third via planarization layer VIA3 after step S160 of providing the third via planarization layer VIA3. Since no processes such as etching have been performed on the third via planarization layer VIA3, the upper surface of the third via planarization layer VIA3 may have a smooth surface (e.g., substantially smooth surface) without deviations (e.g., significant deviations). In one or more embodiments, the first anode electrode AE1 may be stably (e.g., substantially stably) provided on the third via planarization layer VIA3 without process deviations. In one or more embodiments, the first anode electrode AE1 may be provided with a concave structure (e.g., substantially concave structure) having relatively high quality and reliability.

[0154] According to one or more embodiments of the present disclosure, the first anode electrode AE1 may have portions overlapping with the first metal opening portion M-OP1 and the first planarization opening portion F-OP1.

[0155] Figure 11I Is towards Figure 11H A diagram illustrating the layout of adding a hole functional layer (HL) and a pixel-limiting film (PDL). Figure 11J Is towards Figure 11I An illustration of the layout for adding the first light-emitting layer EML1. In this disclosure, the steps of providing the hole-functional layer HL and the pixel-defining film PDL may not correspond to any feature aspect or characteristic of this disclosure, and therefore are not described separately in the description of the method of manufacturing the display panel S10.

[0156] refer to Figure 10 and Figure 11JThe manufacturing method S10 of a display panel according to one or more embodiments of the present disclosure may include a step S180, following the step of providing an anode electrode S170, of providing a light-emitting layer by providing a first light-emitting layer EML1 on a hole functional layer HL. As described in one or more embodiments, the first anode electrode AE1 may have relatively high quality and reliability, and therefore, the first light-emitting layer EML1 on the first anode electrode AE1 may also have relatively high quality and reliability.

[0157] According to one or more embodiments of the present disclosure, the first light-emitting layer EML1 may have a region overlapping with the first metal opening portion M-OP1 and the first planarization opening portion F-OP1.

[0158] Figure 12 This is an exemplary block diagram of an electronic device ED according to one or more embodiments.

[0159] refer to Figure 12 An electronic device ED according to one or more embodiments may include a display module DPM, a processor PCS, a memory MMR, and a power module PM.

[0160] The processor PCS may include at least one selected from the central processing unit (CPU), application processor (AP), graphics processing unit (GPU), communication processor (CP), image signal processor (ISP), and controller.

[0161] The memory MMR can be provided to store data information used to operate the processor PCS or the display module DPM. If the processor PCS runs an application stored in the memory MMR (e.g., when the processor PCS runs an application stored in the memory MMR), the display module DPM can be provided to receive image data signals and / or input control signals and process the received signals to provide image information output through the display screen.

[0162] The power module PM may include power modules such as power adapters and / or battery devices, as well as power conversion modules that convert the power supplied by the power module to generate power for operating electronic devices ED.

[0163] According to one or more embodiments, at least one of the elements of the electronic device ED as described in one or more embodiments may be included in the display device. In one or more embodiments, one or more individual modules that are functionally included in a single module may be included in the display device, and others may be provided separately from the display device. For example, the display module DPM may be included in the display device, and the processor PCS, memory MMR, and power module PM may be provided as another device within the electronic device ED besides the display device.

[0164] Figure 13 The figure shows a schematic diagram of an electronic device according to one or more embodiments.

[0165] refer to Figure 13 One or more suitable electronic devices having a display device according to one or more embodiments may include not only image display electronic devices such as smartphones ED-1a, tablet PCs ED-1b, laptops ED-1c, TVs ED-1d, and desktop monitors ED-1e, but also wearable electronic devices including display modules such as smart glasses ED-2a, head-mounted displays ED-2b, and / or smartwatches ED-2c, and / or vehicle electronic devices including display modules such as central information displays (CID) and / or interior mirror displays on the instrument panel, central dashboard, and / or dashboard of a car ED-3.

[0166] Although specific embodiments of this disclosure have been described and illustrated herein, those skilled in the art will understand that one or more suitable modifications and arrangements of this disclosure may exist without departing from the spirit and scope of this disclosure as defined in the claims and their equivalents. Furthermore, it should be understood that the disclosed embodiments are not intended to limit the aspects and features of this disclosure, and the technical ideas and aspects of this disclosure are to be interpreted as being included within the scope of the claims and their equivalents.

Claims

1. A display panel, comprising: Base components; An active pattern is provided on the substrate member and includes a semiconductor material; A gate insulating layer covers the active pattern; A gate electrode is provided on the gate insulating layer and has at least a portion overlapping the active pattern; An interlayer insulating layer is provided on the gate electrode; The source-drain electrodes are provided on the interlayer insulating layer; A first via planarization layer is provided on the source-drain electrodes; An ashing stop layer, comprising an inorganic material, is provided on the first via planarization layer; A second via planarization layer is provided on the ashing stop layer and is defined with a plurality of planarization opening portions; A third via planarization layer is provided on the second via planarization layer; Multiple anode electrodes are provided on the third via planarization layer, and at least one of the multiple anode electrodes overlaps with a corresponding planarization opening portion of the multiple planarization opening portions; as well as Multiple light-emitting layers are each provided on a corresponding anode electrode among the multiple anode electrodes.

2. The display panel according to claim 1, in, The plurality of light-emitting layers includes a first light-emitting layer that overlaps with any one of the plurality of planarized opening portions, and The first light-emitting layer includes a first light-emitting unit extending in a selectable direction and a second light-emitting unit extending in a direction intersecting the selectable direction.

3. The display panel according to claim 2, in, The angle between the plane parallel to the first through-hole planarization layer and the second light-emitting unit is more than 15 degrees and less than 25 degrees.

4. The display panel according to claim 2, in, The distance between the upper surface of the first through-hole planarization layer and the first light-emitting unit is less than the distance between the upper surface of the first through-hole planarization layer and the second light-emitting unit.

5. The display panel according to claim 2, in, The distance between the portion of the upper surface of the third through-hole planarization layer that overlaps with the planarization opening and the upper surface of the first through-hole planarization layer is a first distance. Wherein, the distance between the portion of the upper surface of the third through-hole planarization layer that does not overlap with the planarization opening and the upper surface of the first through-hole planarization layer is the second distance, and Wherein, the first distance is less than the second distance.

6. The display panel according to claim 2, in, At least one of the plurality of anode electrodes includes a first anode unit extending in the selectable direction and a second anode unit extending in the direction intersecting the selectable direction.

7. The display panel according to claim 2, in, The plurality of light-emitting layers further include a second light-emitting layer, and Wherein, the distance between the upper surface of the first through-hole planarization layer and the bottom surface of the first light-emitting layer is less than the distance between the upper surface of the first through-hole planarization layer and the bottom surface of the second light-emitting layer.

8. The display panel according to claim 7, in, The first light-emitting layer emits light with a first wavelength, and The second light-emitting layer emits light with a second wavelength that is shorter than the first wavelength.

9. The display panel according to claim 2, further comprising: A hard mask layer, comprising a metallic material and defined with a plurality of metallic openings overlapping the plurality of planarized openings, and The hard mask layer is located between the second via planarization layer and the third via planarization layer.

10. The display panel according to any one of claims 2-9, in, The angle between the inner surface of each of the plurality of planarized opening portions defined by the second through-hole planarization layer and the normal of the ashing stop layer is an acute angle.

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