Electronic device and method for manufacturing electronic device

Abstract

An electronic device and a method for manufacturing the electronic device are disclosed. An electronic device may include an electronic module and a display module including an aperture region overlapping the electronic module, in which the display module includes: a base layer having a module aperture defined in the base layer and corresponding to the aperture region; a circuit layer on the base layer; a display element layer provided on the circuit layer and including a light emitting element; and an encapsulation layer partially provided on the display element layer and including at least a first inorganic layer, in which the circuit layer includes: a plurality of insulating layers provided on the base layer and including a first intermediate insulating layer; a first dam portion spaced apart from the first intermediate insulating layer; and a protruding pattern provided on at least a portion of the first intermediate insulating layer and the first dam portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0110560, filed with the Korean Intellectual Property Office on August 19, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to electronic devices and methods for manufacturing electronic devices, and for example, to electronic devices having improved or enhanced reliability and methods for manufacturing electronic devices. Background Technology

[0004] Electronic devices such as televisions, mobile phones, computers (e.g., tablets), navigation systems, and / or game consoles, used to provide images to users, may include display panels for generating and displaying images. In addition to display panels, electronic devices may also consist of one or more suitable electronic components, such as electronic modules and / or input sensors for sensing external input. Electronic modules may include cameras, infrared sensors, and / or proximity sensors.

[0005] To provide users with a wider display area, the electronic module of the electronic device can be positioned or provided below the display panel, and holes can be provided in the display panel to expose the electronic module. Furthermore, more advanced technologies are desired or needed to protect one or more layers of the display panel exposed around the holes to ensure the reliability of the electronic device. Summary of the Invention

[0006] One or more aspects of embodiments of this disclosure relate to electronic devices that have improved or enhanced reliability due to low water vapor transmission rate.

[0007] One or more aspects of the embodiments of this disclosure also relate to methods for manufacturing electronic devices that can improve or enhance the reliability of electronic devices through simplified processes.

[0008] Additional aspects of the embodiments will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0009] One or more embodiments of this disclosure provide an electronic device including an electronic module and a display module. The display module includes a hole region defined to overlap with the electronic module. The display module further includes: a substrate layer having module holes defined in the substrate layer and corresponding to the hole region; a circuit layer disposed or provided on the substrate layer; a display element layer disposed or provided on the circuit layer and including a light-emitting element; and an encapsulation layer partially disposed or provided on the display element layer and including at least a first inorganic layer. The circuit layer includes: a plurality of insulating (e.g., electrically insulating) layers disposed or provided on the substrate layer and including a first intermediate insulating (e.g., electrically insulating) layer; and a first dam portion spaced apart from and / or separated from the first intermediate insulating layer (e.g., (separated or separated) and defining at least one groove between the first intermediate insulating layer and the first dam portion; and a protruding pattern, disposed or provided on at least a portion of the first intermediate insulating layer and the first dam portion, and including a pointed tip portion projecting inward in the at least one groove, wherein the first dam portion includes a first inclined surface disposed or provided below the protruding pattern, and the first inorganic layer includes a first portion disposed or provided on the upper surface of the pointed tip portion, a second portion disposed or provided on the lower surface of the pointed tip portion, and a third portion disposed or provided on the first inclined surface, wherein the thickness of the second portion is more than about 30% of the thickness of the first portion, and the thickness of the third portion is more than about 40% of the thickness of the first portion.

[0010] In one or more embodiments, at least one groove may include a first groove defined by a first inclined surface, the encapsulation layer may further include a second inorganic layer, and at least a portion of the first inorganic layer and at least a portion of the second inorganic layer may contact each other in an area overlapping with the first groove.

[0011] In one or more embodiments, the first inorganic layer may include: a first sublayer disposed or provided adjacent to the tip portion; a second sublayer disposed or provided on the first sublayer; and a third sublayer disposed or provided on the second sublayer. The density of the second sublayer may be lower than the density of each of the first and third sublayers.

[0012] In one or more embodiments, the thickness of the first sublayer may be from about 0.1% to about 10% of the thickness of the first inorganic layer.

[0013] In one or more embodiments, the density difference between the first sublayer and the second sublayer can be approximately 0.1 g / cm³. 3 above.

[0014] In one or more embodiments, the encapsulation layer may further include: a second inorganic layer disposed or provided on the first inorganic layer; and an organic layer disposed or provided between the first inorganic layer and the second inorganic layer. The organic layer may not overlap (or may not overlap with) at least a portion of the protruding pattern in a planar (e.g., in a planar view) layout.

[0015] In one or more embodiments, each of the first inorganic layer and the second inorganic layer may include silicon nitride.

[0016] In one or more embodiments, the first dam portion may include: a first dam layer disposed or provided on substantially the same layer as the first intermediate insulation layer and configured or arranged to provide a substrate surface on which a raised pattern is disposed or provided; and a second dam layer disposed or provided on the raised pattern. A first inclined surface may be provided to the first dam layer.

[0017] In one or more embodiments, the refractive index of the first inorganic layer may be from about 1.7 to about 2.0 at a wavelength of about 550 nm.

[0018] In one or more embodiments, the thickness of the first inorganic layer may be approximately up to approximately

[0019] In one or more embodiments, the water vapor permeability of the first inorganic layer may be 1.0 × 10⁻⁶. -4 g / (m 2 (Heaven) and below.

[0020] In one or more embodiments, the first inorganic layer may completely (e.g., substantially completely) cover the upper surface of the tip portion, the lower surface of the tip portion, and the side surface connecting the upper and lower surfaces to each other.

[0021] In one or more embodiments, the first inorganic layer may completely (e.g., substantially completely) cover the first inclined surface.

[0022] In one or more embodiments, the plurality of insulating layers may further include a first lower insulating (e.g., electrical insulating) layer disposed or provided beneath the first intermediate insulating layer. The upper surface of the first lower insulating layer may be exposed by at least one groove, and the first inorganic layer may contact the upper surface of the first lower insulating layer.

[0023] In one or more embodiments, at least one groove may be on a plane (e.g., in a plan view) around the module hole (e.g., around the module hole).

[0024] In one or more embodiments of this disclosure, the electronic device includes an electronic module and a display module, the display module including an aperture region defined to overlap with the electronic module. The display module further includes: a substrate layer having module apertures defined in the substrate layer and corresponding to the aperture region; a circuit layer disposed or provided on the substrate layer; a display element layer disposed or provided on the circuit layer and including a light-emitting element; and an encapsulation layer partially disposed or provided on the display element layer and including a first inorganic layer and a second inorganic layer. The circuit layer includes: a dam pattern disposed or provided in the aperture region and including a first dam portion and a second dam portion; and a protruding pattern disposed or provided on at least a portion of the dam pattern. A first groove is defined between the first dam portion and the second dam portion, the protruding pattern including a pointed tip portion projecting inwardly in the first groove, and each of the first dam portion and the second dam portion includes a first inclined surface disposed or provided below the protruding pattern and defining the first groove. The first inorganic layer includes a first portion disposed or provided on the upper surface of the tip portion, a second portion disposed or provided on the lower surface of the tip portion, and a third portion disposed or provided on the first inclined surface. The thickness of the second portion is more than 30% of the thickness of the first portion, and the thickness of the third portion is more than 40% of the thickness of the first portion.

[0025] In one or more embodiments of this disclosure, a method for manufacturing an electronic device includes: providing a substrate layer having module holes defined therein; forming or providing a circuit layer including a plurality of insulating (e.g., electrically insulating) layers on the substrate layer, a dam pattern spaced and / or separated (e.g., spaced apart or separated) from the plurality of insulating layers, and a protruding pattern; and forming or providing an encapsulation layer on the circuit layer. The dam pattern includes a first dam portion spaced and / or separated (e.g., spaced apart or separated) from the plurality of insulating layers and defining at least one recess between the plurality of insulating layers and the first dam portion. The protruding pattern is disposed or provided on at least a portion of the first dam portion. The first dam portion includes a first inclined surface disposed or provided below the protruding pattern, and the protruding pattern includes a tip portion projecting from the first inclined surface. Forming or providing the encapsulation layer includes forming or providing a first inorganic layer covering the tip portion and the first inclined surface. The first inorganic layer includes a first portion disposed or provided on an upper surface of the tip portion, a second portion disposed or provided on a lower surface of the tip portion, and a third portion disposed or provided on the first inclined surface. The thickness of the second part is approximately 30% or more of the thickness of the first part, and the thickness of the third part is approximately 40% or more of the thickness of the first part.

[0026] In one or more embodiments, the formation or provision of the first inorganic layer may include: applying a first deposition material by any of a plasma-enhanced atomic layer deposition (PEALD) method, a sputtering method, and an electron beam evaporator method to form or provide a preliminary first inorganic layer; and applying a second deposition material on the preliminary first inorganic layer by a plasma-enhanced chemical vapor deposition (PECVD) method.

[0027] In one or more embodiments, the thickness of the initial first inorganic layer may be from about 0.1% to about 10% of the total thickness of the first inorganic layer.

[0028] In one or more embodiments, the first inorganic layer may include a first sublayer formed or provided corresponding to the initial first inorganic layer, a second sublayer disposed or provided on the first sublayer, and a third sublayer disposed or provided on the second sublayer. The density of the second sublayer may be lower than the density of each of the first and third sublayers. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of embodiments of the subject matter of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the subject matter of this disclosure and, together with the description, serve to explain the principles of embodiments of the subject matter of this disclosure. In the drawings:

[0030] Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0031] Figure 2 This is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0032] Figure 3 This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0033] Figure 4 This is a schematic plan view illustrating a portion of a display module according to one or more embodiments of the present disclosure;

[0034] Figure 5 and Figure 6 Each of these is a cross-sectional view of a portion of a display module according to one or more embodiments of the present disclosure;

[0035] Figures 7 to 9 Each of these is an enlarged cross-sectional view of a portion of a display module according to one or more embodiments of the present disclosure;

[0036] Figures 10A to 10C Each of the figures schematically illustrates a step of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure;

[0037] Figure 11A and Figure 11B Each of these is an enlarged cross-sectional view of a portion of a display module in a step of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure; and

[0038] Figure 12 This is an enlarged cross-sectional view of a portion of a display module in a step of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure. Detailed Implementation

[0039] In the following description, the subject matter of this disclosure will be more fully described with reference to the accompanying drawings, in which embodiments of this disclosure are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in one or more suitable different ways without departing from the spirit and scope of this disclosure. The drawings and description are considered to be illustrative in nature and not restrictive. Throughout the drawings and written description, the same reference numerals denote the same elements, and repeated descriptions of the same elements may not be provided in the specification.

[0040] In this disclosure, it will be understood that if an element (or section, layer, and / or portion, etc.) is referred to as being “on,” “connected to,” or “linked to” another element (e.g., when an element (or section, layer, and / or portion, etc.) is referred to as being “on,” “connected to,” or “linked to” another element), then the element may be directly on, directly connected to, or directly linked to the other element, or an intermediary element may exist between the element and the other element. Conversely, if an element is referred to as being “directly” on, “directly connected to,” or “directly linked to” another element (e.g., when an element is referred to as being “directly” on, directly connected to, or directly linked to” another element), then an intermediary element may not exist between the element and the other element.

[0041] In this disclosure, the expression "directly disposed" or "directly provided" can mean that there is no additional layer, membrane, zone, and / or plate between one part of a layer, membrane, zone, and / or plate. For example, the expression "directly disposed" can mean disposed or provided between two layers or two components, without any additional components such as adhesive components between the two layers or the two components.

[0042] In one or more embodiments, the thickness, proportions, and dimensions of components may be exaggerated in the accompanying drawings for the purpose of effective description of technical features or content.

[0043] As used herein, the term “and / or” includes any and all combinations that the associated components may be defined in.

[0044] It will be understood that although terms such as “first” and / or “second” may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of this disclosure. Similarly, a second element may also be referred to as a first element. Unless otherwise specified, singular terms may include plural forms.

[0045] In one or more embodiments, for ease of description, terms such as “below,” “down,” “above,” and / or “up” are used herein to describe the relationship between one element and another(s) as illustrated in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0046] It will be understood that, if used in this disclosure (e.g., when used in this disclosure), the terms "comprising," "including," and / or "having" indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. For example, it should be understood that the terms "comprising," "including," or "having" indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms "comprising," "including," "having," or similar terms include or support the terms "consisting of" and "substantially consisting of," thereby indicating the presence of the stated features, integrals, steps, operations, elements, and / or components without or substantially without the presence of other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0047] As used herein, the terms “substantially,” “approximately,” or similar terms are used as approximations and not as terms of degree, and are intended to take into account the inherent biases in values ​​of measurements or calculations that would be recognized by one of ordinary skill in the art. Taking into account the measurements discussed and the errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), as used herein, “approximately” includes the stated value and refers to a range of acceptable deviations from the specific value as determined by one of ordinary skill in the art. For example, “approximately” may refer to one or more standard deviations, or to ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] In the context of this application and unless otherwise specified, the terms “use,” “in use,” and “being used” may be considered synonymous with the terms “utilization,” “being utilized,” and “being exploited,” respectively.

[0049] Any numerical ranges listed herein are intended to include all subranges of the same numerical precision falling within the listed range. For example, the range “1.0 to 10.0” is intended to include all subranges between the listed minimum value of 1.0 and the listed maximum value of 10.0 (and inclusive of both), such as all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits falling within it, and any minimum numerical limit listed in this disclosure is intended to include all higher numerical limits falling within it. Therefore, the applicant reserves the right to modify this disclosure (including the claims) to expressly list any subranges falling within the range expressly listed herein.

[0050] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) have substantially the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In one or more embodiments, it will be further understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] In the following, one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0052] Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure. Figure 2 This is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0053] An electronic device (ED) can be activated and display an image based on an electrical signal. The electronic device (ED) may include one or more suitable embodiments that provide images to a user, and for example, the electronic device (ED) may be a large device such as a television and / or an outdoor billboard, as well as a small to medium-sized device such as a monitor, mobile phone, computer (e.g., tablet computer), navigation system, and / or game console. One or more embodiments of the electronic device (ED) are exemplary and are not limited to any single embodiment, provided they do not depart from the concept or scope of this disclosure. Figure 1 In the illustration, a mobile phone is shown as an example of an electronic device (ED).

[0054] refer to Figure 1The electronic device ED may have a rectangular shape (e.g., a generally rectangular shape) in a plane (e.g., in a plan view), having a short side extending in a first direction DR1 and a long side extending in a second direction DR2. However, it is not limited thereto, and the electronic device ED may have one or more suitable shapes such as a circle (e.g., a generally circular shape) or other polygons (e.g., other generally polygonal shapes).

[0055] The electronic device ED can display an image IM on a third direction DR3 via a display surface IS that is parallel (e.g., substantially parallel) to the plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 can be substantially parallel to the normal direction of the display surface IS. The display surface IS of the electronic device ED can correspond to the front surface of the electronic device ED.

[0056] Images displayed on an electronic device (ED) can include moving images and still images. Figure 1 The illustration shows a clock window and several icons as an example of an image IM.

[0057] In one or more embodiments of this disclosure, the front (or upper) surface and rear (or lower) surface of each component or unit may be defined based on the orientation of the displayed image IM. The front and rear surfaces may be opposite to each other in a third direction DR3, and the normal direction of each of the front and rear surfaces may be substantially parallel to the third direction DR3. The separation distance defined between the front and rear surfaces along the third direction DR3 may correspond to the thickness of the component (or unit).

[0058] In this disclosure, the expression "in a plane" or "in a plan view" can be defined as a state viewed from a third party toward DR3. In this disclosure, the expression "in a cross section" can be defined as a state viewed from a first direction DR1 or a second direction DR2. In one or more embodiments, the directions indicated by the first direction DR1, the second direction DR2, and the third direction toward DR3 are relative concepts and can be converted to other directions.

[0059] Electronic devices (EDs) can be flexible devices. The statement "flexible" refers to the property of being bendable, and flexible structures can include everything from fully foldable structures to structures that can be bent to the nanometer level. For example, flexible electronic devices (EDs) can include bending or foldable devices. Not limited to this, electronic devices (EDs) can also be rigid devices.

[0060] Figure 1 An example of an electronic device ED with a flat display surface IS is illustrated. However, the shape of the display surface IS of the electronic device ED is not limited to this, and it can be curved or three-dimensional.

[0061] The display surface IS of the electronic device ED may include a display portion AA-DD and a non-display portion NAA-DD. The display portion AA-DD may be a portion within the front surface of the electronic device ED on which an image IM is displayed, and the user can view the image IM through the display portion AA-DD. This embodiment illustrates an example of a display portion AA-DD having a quadrilateral shape (e.g., substantially quadrilateral) on a plane (e.g., in a plan view), but the display portion AA-DD may have one or more suitable shapes depending on the design of the electronic device ED.

[0062] The non-display portion NAA-DD can be a portion within the front surface of the electronic device ED on which an image IM is not displayed. The non-display portion NAA-DD can have a set or predetermined color and is a portion that blocks light (or reduces the degree or occurrence of light). The non-display portion NAA-DD can be adjacent to the display portion AA-DD. For example, the non-display portion NAA-DD can be disposed or provided outside the display portion AA-DD and around the display portion AA-DD (e.g., surrounding the display portion AA-DD). However, this is illustrated by way of example, and the non-display portion NAA-DD can be adjacent only to one side of the display portion AA-DD or can be disposed or provided on a side surface other than the front surface of the electronic device ED. In one or more embodiments, not limited thereto, the non-display portion NAA-DD may not be provided.

[0063] The display portion AA-DD of the electronic device ED according to one or more embodiments of the present disclosure may include a sensing area SA-DD. The sensing area SA-DD may be connected to... Figure 2 The electronic module EM corresponds to its overlapping area. (See Electronic Module EM) Figure 2 It can receive external input transmitted through the sensing area SA-DD or output signals through the sensing area SA-DD. Figure 1 An exemplary illustration shows a sensing area SA-DD set or provided within the display portion AA-DD, but embodiments of this disclosure are not limited thereto, and multiple sensing areas SA-DD may be provided within the display portion AA-DD.

[0064] An electronic device ED according to one or more embodiments of the present disclosure can sense external input applied from the outside. The external input may have one or more suitable forms, such as pressure, temperature, and / or light provided from the outside. The external input may include not only input that is in contact with the electronic device ED (e.g., the touch of a user's hand and / or pen), but also input applied close to the electronic device ED (e.g., hovering).

[0065] refer to Figure 1 and Figure 2 An electronic device ED may include a window WP and a housing HU. The window WP and housing HU may be connected to each other to form or provide the appearance of the electronic device ED, while providing internal space to accommodate the components of the electronic device ED. The electronic device ED may include a display module DM, a light control component ARP, and an electronic module EM disposed or provided between the window WP and the housing HU.

[0066] An electronic module (EM) may be positioned or provided below a display module (DM). The electronic module (EM) may be positioned or provided overlapping the display module (DM). The electronic module (EM) may be an electronic component configured or provided to output or receive optical signals. For example, the electronic module (EM) may be a camera module for capturing external images. Not limited to this, the electronic module (EM) may be a sensor module such as a proximity sensor and / or an infrared emission sensor.

[0067] The display module DM can be mounted or provided on the electronic module EM. The display module DM may include the display panel DP described herein (see [link to documentation]). Figure 3 Display panel DP (see) Figure 3 An image can be generated based on an electrical signal. The display panel DP (see...) Figure 3 It can be a light-emitting display panel, but the embodiments disclosed herein are not limited thereto.

[0068] The display module DM may include an active area DM-AA and an adjacent peripheral area DM-NAA. The active area DM-AA can be activated according to an electrical signal. Multiple pixels PX can be set or provided in the active area DM-AA.

[0069] The peripheral area DM-NAA may be located around the active area DM-AA (e.g., surrounding the active area DM-AA). Drive circuitry or drive lines for driving pixels PX set or provided in the active area DM-AA and / or one or more suitable signal lines or pads for providing electrical signals to the components may be set or provided in the peripheral area DM-NAA.

[0070] The display module DM may include an aperture region HA placed or provided within the effective area DM-AA. The aperture region HA may correspond to the sensing areas SA-DD described in one or more embodiments. In one or more embodiments, the expression "area / part corresponds to another area / part" means "areas / parts overlap each other," and this expression is not limited to having substantially the same area and / or substantially the same shape. The aperture region HA may also be referred to as the first area HA.

[0071] The aperture region HA may overlap with the electronic module EM. A module aperture HH passing through the display module DM may be defined within the aperture region HA. The module aperture HH may overlap with the electronic module EM. In one or more embodiments of this disclosure, a portion of the electronic module EM may be inserted into the module aperture HH.

[0072] exist Figure 2 In the illustration, a module aperture HH having a circular shape (e.g., a generally circular shape) is shown as an example, but embodiments of this disclosure are not limited thereto. A plurality of module apertures HHs may be defined such that the number of module apertures HHs may correspond to the number of electronic modules EMs disposed or provided below the display module DM. In one or more embodiments, the shape of the module aperture HH in a plane (e.g., in a plan view) may be polygonal (e.g., substantially polygonal) and / or elliptical (e.g., substantially elliptical), etc., and the shape of the module aperture HH in a plane (e.g., in a plan view) may be provided in one or more suitable forms depending on the shape or arrangement of the electronic modules EMs.

[0073] The electronic device ED can receive external signals desired or required by the electronic module EM through the aperture region HA, or provide signals output from the electronic module EM to the outside. According to this disclosure, because the aperture region HA is provided within the effective area DM-AA, the area of ​​the non-display portion NAA-DD used to set or provide the electronic module EM can be reduced.

[0074] At least a portion of the aperture region HA may be surrounded by the display region AA. The display region AA may be referred to as the second region. The effective area DM-AA of the display module DM according to one or more embodiments of the present disclosure may include the aperture region HA and the display region AA. In one or more embodiments of the present disclosure, the aperture region HA may be completely (e.g., substantially completely) surrounded by the display region AA, but embodiments of the present disclosure are not limited thereto, and a portion of the aperture region HA may be surrounded by the display region AA and the remaining portion of the aperture region HA may contact the peripheral region DM-NAA.

[0075] An electronic device ED may include an ARP (Optical Reflection Component) disposed or provided between a display module DM and a window WP. The ARP may be a reflection reduction layer that reduces the reflection (or the degree or frequency of reflection) of external light incident from outside the electronic device ED. However, embodiments of this disclosure are not limited thereto, and the ARP may include one or more suitable types or kinds of light control layers for improving or enhancing the display quality of the electronic device ED. For example, the ARP according to one or more embodiments of this disclosure may include a polarization layer, a phase delayer, a destructive interference structure, or a plurality of color filters. In one or more embodiments, the ARP may not be provided in the electronic device ED according to one or more embodiments of this disclosure.

[0076] The portion of the light control component ARP that overlaps with the aperture region HA can have relatively high transmittance. For example, the light control component ARP may include a transmissive portion that overlaps with the aperture region HA, or, not limited thereto, the light control component ARP may also include an aperture defined to overlap with the aperture region HA and pass through the light control component ARP.

[0077] A window WP can be set or provided on the light control component ARP. The window WP can protect the display module DM and the light control component ARP that are set or provided below the window WP.

[0078] The window WP may include an optically transparent (e.g., substantially transparent) insulating (e.g., electrically insulating) material. For example, the window WP may include glass, sapphire, and / or plastic. The window WP may have a single-layer or multi-layer structure. The window WP may further include functional layers (such as anti-fingerprint layers, phase control layers, and hard coatings) disposed or provided on an optically transparent (e.g., substantially transparent) substrate.

[0079] The front surface FS of the window WP may correspond to the display surface IS of the electronic device ED described in one or more embodiments. The front surface FS of the window WP may include a transmissive area TA and a border area BZA.

[0080] The transmissive area TA of the window WP can be an optically transparent (e.g., substantially transparent) area. The transmissive area TA can correspond to the display portions AA-DD of the electronic device ED. The transmissive area TA can overlap with at least a portion of the effective area DM-AA of the display module DM. The window WP can transmit the image provided by the display module DM through the transmissive area TA, and the user can view the image.

[0081] The transmission area TA of the window WP may include the sensing area SA. The sensing area SA of the window WP may correspond to the sensing area SA-DD of the electronic device ED. The sensing area SA of the window WP may overlap with the aperture area HA and the electronic module EM. The sensing area SA of the window WP may have relatively high light transmittance. Accordingly, the electronic module EM can effectively or appropriately receive external input or output signals through the sensing area SA.

[0082] The border area BZA of the window WP can be provided by depositing, coating, and / or printing a material with a set or predetermined color on a transparent (e.g., substantially transparent) substrate. The border area BZA can correspond to the non-display portion NAA-DD of the electronic device ED. The border area BZA can overlap with at least a portion of the peripheral area DM-NAA of the display module DM. Because the border area BZA of the window WP covers the peripheral area DM-NAA of the display module DM, it is feasible to prevent the construction or arrangement of the display module DM within the peripheral area DM-NAA from being seen from the outside.

[0083] The housing HU can be disposed or provided below the display module DM. The housing HU protects the components housed within it. The housing HU prevents foreign objects and / or moisture from entering the display module DM (or reduces the extent or frequency of such entry) and the light control component ARP. The housing HU may comprise a material with relatively high rigidity and can absorb impacts applied from the outside. The housing HU may be provided in a configuration where multiple storage components are interconnected.

[0084] Figure 3 This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure. Figure 3 schematic diagram and Figure 2 The cross section corresponding to line I-I'.

[0085] refer to Figure 3 According to one or more embodiments, the display module DM may include a display panel DP and an input sensor ISL. The display panel DP may include a substrate layer BS, a circuit layer D-CL, a display element layer D-OL, and a package layer ECL.

[0086] The substrate layer BS can be a component on which the circuit layer D-CL is disposed or provided. The substrate layer BS can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. The substrate layer BS can be a glass substrate, a metal substrate, a silicon substrate, and / or a polymer substrate. However, the embodiments of this disclosure are not limited thereto, and the substrate layer BS can be an inorganic layer, an organic layer, or a composite material layer.

[0087] A circuit layer D-CL can be disposed or provided on a substrate layer BS. The circuit layer D-CL may include an insulating (e.g., electrically insulating) layer, semiconductor patterns, conductive (e.g., electrically conductive) patterns, and signal transmission areas. The insulating (e.g., electrically insulating) layer, semiconductor layer, and conductive (e.g., electrically conductive) layer can be formed or provided on the substrate layer BS by coating and / or deposition, and then the insulating (e.g., electrically insulating) layer, semiconductor layer, and conductive (e.g., electrically conductive) layer can be selectively patterned by multiple photolithography processes. Thereafter, the insulating (e.g., electrically insulating) layer, semiconductor patterns, conductive (e.g., electrically conductive) patterns, and signal transmission areas included in the circuit layer D-CL can be formed or provided.

[0088] The display element layer D-OL can be disposed or provided on the circuit layer D-CL. The display element layer D-OL may include light-emitting elements. For example, the display element layer D-OL may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micron LEDs and / or nano LEDs.

[0089] An encapsulation layer (ECL) can be disposed on or provided on the display element layer (D-OL). The ECL protects the display element layer (D-OL) from moisture, oxygen, and / or foreign matter such as dust particles. The ECL can be disposed directly on or provided on the display element layer (D-OL), or attached to the display element layer (D-OL) via a separate component.

[0090] In one or more embodiments of this disclosure, the encapsulation layer ECL may include multiple layers, and at least one layer selected from the multiple layers may include an inorganic layer. For example, the encapsulation layer ECL may include a first inorganic layer IOL1 (see...). Figure 5 ), organic layer OL (see Figure 5 ) and the second inorganic layer IOL2 (see Figure 5 ). Will be Figure 5 The description of the ECL encapsulation layer is more detailed.

[0091] In a display module DM according to one or more embodiments of the present disclosure, an input sensor ISL may be disposed on or provided on a package layer ECL. The input sensor ISL may be formed or provided on the package layer ECL via a continuous (e.g., substantially continuous) process. In one or more embodiments, the input sensor ISL may be represented as being directly disposed on the package layer ECL. Being directly disposed may mean that no third component is disposed or provided between the input sensor ISL and the package layer ECL. For example, no separate adhesive material may be disposed or provided between the input sensor ISL and the package layer ECL. In one or more embodiments, the input sensor ISL may be bonded to the package layer ECL via an adhesive member. The adhesive member may include generally available or generally known adhesives and / or glues.

[0092] Figure 4 This is a schematic plan view illustrating a portion of a display module according to one or more embodiments of the present disclosure. Figure 4 The diagram shows Figure 2 The area XX', and the area XX' can correspond to the part of the effective area DM-AA that includes the module hole HH.

[0093] refer to Figure 4 Multiple pixels (PX) can be set or provided in the display module DM (see [link]). Figure 2 The effective area DM-AA of the module hole area HA is used. In one or more embodiments of this disclosure, most of the plurality of pixels PX may be set or provided in a display area AA (or a second area) that is separated from and / or separated from the hole area HA (e.g., spaced apart or separated), and one or more pixels PX may be set or provided in the display area AA along the boundary between the hole area HA (or the first area) and the display area AA. Pixels PX adjacent to the boundary of the hole area HA may be set or provided as separated from and / or separated from the module hole HH (e.g., spaced apart or separated).

[0094] The module aperture HH can be defined within the aperture region HA. The module aperture HH can be defined within the effective region DM-AA. Accordingly, at least one of the pixels PX can be configured or provided adjacent to the module aperture HH, and in one or more embodiments, the pixels PX can be configured or provided spaced apart and / or separated from each other (e.g., spaced apart or separated) while the module aperture HH is between the pixels PX. Electronic module EM (see...) Figure 2 It can overlap with module hole HH.

[0095] The dam pattern DMP can be set or provided in the orifice region HA. In an electronic device ED according to one or more embodiments of this disclosure (see...) Figure 2In the module aperture HH, the dam pattern DMP can block the path of moisture and / or oxygen through which it flows from the module aperture HH to the pixel PX. The dam pattern DMP can be disposed or provided in the aperture region HA and includes at least one selected from dam portions DM1, DM2, and DM3. Each of the dam portions DM1, DM2, and DM3 can be around at least a portion of the module aperture HH (e.g., surrounding at least a portion of the module aperture HH). According to one or more embodiments of this disclosure, in a plane (e.g., in a plan view), each of the dam portions DM1, DM2, and DM3 can have a closed line shape around the module aperture HH (e.g., surrounding the module aperture HH). Dam portions DM1, DM2, and DM3 can be disposed or provided in substantially the same layer and with the insulating layers 10, 20, 30, 40, 50, and 60, which will be described in more detail herein (see [link to documentation]). Figure 6 At least one of them is formed or provided using substantially the same process.

[0096] Selected from grooves GV1, GV2, and GV3 (see...) Figure 6 At least one of them can be defined in the orifice region HA. Grooves GV1, GV2 and GV3 (see Figure 6 ) can be defined as being around the module hole HH (e.g., surrounding the module hole HH). Recesses GV1, GV2, and GV3 (see...) Figure 6 The recesses GV1, GV2, and GV3 may be defined between the dam portions DM1, DM2, and DM3, or between at least one of the dam portions DM1, DM2, and DM3 and the display area AA. In one or more embodiments of this disclosure, the recesses GV1, GV2, and GV3 (see...) Figure 6 It can be composed of dam sections DM1, DM2, and DM3 or raised pattern MTP (see...). Figure 6 )limited.

[0097] In one or more embodiments of this disclosure, a filler material may be further disposed or provided inside the module aperture HH. The filler material may include a polymeric resin. Because the filler material is disposed or provided inside the module aperture HH, the module aperture HH can provide a flat surface (e.g., a substantially flat surface) to the components disposed or provided on the module aperture HH. In one or more embodiments, a transparent (e.g., substantially transparent) material that does not have optical anisotropy can be used as the filler material. This is as long as it does not degrade the electronic module EM (see [link to documentation]). Figure 2 The sensing capability allows any suitable material to be used as a filler without limitation. In one or more embodiments, a filler material may not be provided.

[0098] A portion of each of the multiple signal lines SGL1 and SGL2 connected to pixel PX can be set or provided in the aperture region HA. Signal lines SGL1 and SGL2 are connected via the aperture region HA to pixels PX that are spaced apart and / or separated (e.g., spaced apart or separated) by module apertures HH. For ease of illustration, in Figure 4 The diagram illustrates two signal lines SGL1 and SGL2, which are among the multiple signal lines SGL1 and SGL2 connected to pixel PX, as an example.

[0099] A first signal line SGL1 extends along a first direction DR1. The first signal line SGL1 is connected to a pixel PX that is arranged or provided along the first direction DR1 and is substantially in the same row. The first signal line SGL1 is exemplarily described as corresponding to any scan line selected from the scan lines connected to the pixel PX.

[0100] One or more pixels PX connected to the first signal line SGL1 are positioned or provided on the left side centered on the module aperture HH, while other pixels PX are positioned or provided on the right side centered on the module aperture HH. Accordingly, even if no one or more pixels are provided around the module aperture HH, pixels PX connected to the first signal line SGL1 that are substantially in the same row can be turned on / off by substantially the same scan signal.

[0101] The second signal line SGL2 extends along the second direction DR2. The second signal line SGL2 is connected to a pixel PX that is disposed or provided along the second direction DR2 and is substantially in the same column. The second signal line SGL2 is exemplarily described as corresponding to any of the data lines selected from those connected to the pixel PX.

[0102] One or more pixels PX connected to the second signal line SGL2 are positioned or provided on the upper side centered on the module aperture HH, and other pixels PX are positioned or provided on the lower side centered on the module aperture HH. Accordingly, even if no one or more pixels PX are provided around the module aperture HH, pixels PX connected to the second signal line SGL2 in substantially the same column can receive data signals through substantially the same line.

[0103] At the point where the first signal line SGL1 and the second signal line SGL2 intersect each other, at least one of the first signal line SGL1 and the second signal line SGL2 may be disconnected within the aperture region HA, and may further include a connection pattern that is disposed or provided on a layer different from the layer of the disconnected signal line and connects the disconnected portion. However, the connection relationship of pixels PX that are spaced apart and / or separated (e.g., spaced apart or separated) between the module aperture HH is not limited to this.

[0104] Figure 5 and Figure 6 Each of these is a cross-sectional view of a portion of a display module according to one or more embodiments of the present disclosure. Figure 5 Can be illustrated with Figure 4 The part corresponding to line II-II', and Figure 6 Can be illustrated with Figure 4 The part corresponding to line III-III'. Figure 5 The diagram illustrates the display area AA (see...). Figure 4 Part of ) and Figure 6 The diagram illustrates the pore region HA (see...). Figure 4 Part of ).

[0105] refer to Figure 5 and Figure 6 The display module DM may include a display panel DP and an input sensor ISL, and the display panel DP may include a substrate layer BS, a circuit layer D-CL, a display element layer D-OL and a package layer ECL stacked in sequence.

[0106] Figure 5 An exemplary illustration shows the relationship with Figure 4 The pixel PX described in (see Figure 4 The corresponding part. Figure 5 An exemplary illustration shows the pixel PX (see Figure 4 It includes a transistor TR and a light-emitting element LD.

[0107] The circuit layer D-CL may include a buffer layer BFL, a shielding electrode BML, a transistor TR, a signal transmission region SCL, multiple insulating layers 10, 20, 30, 40, 50, and 60, an upper electrode pattern EE, and multiple connection electrodes CNE1 and CNE2. In one or more embodiments, the circuit layer D-CL may further include multiple conductive (e.g., electrically conductive) patterns. For example, in addition to the illustrated transistor TR, the circuit layer D-CL may further include additional conductive (e.g., electrically conductive) patterns constituting multiple transistors, capacitors, or connection electrodes. In one or more embodiments, as... Figure 5 The construction or arrangement of the circuit layer D-CL shown is exemplary, and the type or variety, quantity and arrangement of conductive (e.g., electrically conductive) patterns and the number of insulating (e.g., electrically insulating) layers can be changed.

[0108] A buffer layer BFL may be disposed or provided on the substrate layer BS. The buffer layer BFL can improve or enhance the bonding strength between the substrate layer BS and the semiconductor pattern or conductive (e.g., electrically conductive) pattern disposed or provided on the buffer layer BFL. In one or more embodiments, the buffer layer BFL can prevent metal atoms and / or impurities from diffusing from the substrate layer BS to the semiconductor pattern or conductive (e.g., electrically conductive) pattern (or reduce the degree or frequency of metal atom and / or impurity diffusion).

[0109] The buffer layer BFL can be an inorganic film. The buffer layer BFL may include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked. In one or more embodiments of this disclosure, the buffer layer BFL may not be provided.

[0110] A shielding electrode BML may be disposed or provided on a buffer layer BFL. The shielding electrode BML may overlap with a transistor TR. In one or more embodiments of this disclosure, the shielding electrode BML may also be disposed or provided below a signal transmission region SCL. The shielding electrode BML protects conductive (e.g., electrically conductive) patterns or semiconductor patterns such as those on the transistor TR and signal transmission region SCL by blocking light incident from the lower part of the display panel DP onto the transistor TR or signal transmission region SCL (or by reducing the degree or frequency of light incident). The shielding electrode BML may comprise a conductive (e.g., electrically conductive) material. If a voltage is applied to the shielding electrode BML (e.g., when a voltage is applied to the shielding electrode BML), the threshold voltage of the transistor TR disposed or provided on the shielding electrode BML can be maintained. Not limited thereto, the shielding electrode BML may be a floating electrode. In one or more embodiments of this disclosure, the shielding electrode BML may not be provided.

[0111] The circuit layer D-CL may include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 stacked in sequence. Insulating layers 10, 20, 30, 40, 50, and 60 may be disposed on or provided on the buffer layer BFL. Insulating layers 10, 20, 30, 40, 50, and 60 may be inorganic and / or organic layers. For example, in one or more embodiments of this disclosure, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may include inorganic films, and the fifth insulating layer 50 and the sixth insulating layer 60 may include organic films. However, embodiments of this disclosure are not limited thereto. In one or more embodiments, at least one of the insulating layers selected from the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50, and the sixth insulating layer 60 may not be provided in the circuit layer D-CL, or the circuit layer D-CL may further include additional insulating (e.g., electrically insulating) layers.

[0112] The first insulating layer 10 may be disposed or provided on the buffer layer BFL. The first insulating layer 10 may include an inorganic film. The first insulating layer 10 may also be referred to as a first inorganic film. For example, the first insulating layer 10 may be an inorganic film comprising at least one selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 10 may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may have a structure in which multiple inorganic films are stacked.

[0113] In one or more embodiments, in addition to the inorganic membrane, the first insulating layer 10 may further include an organic membrane. If the first insulating layer 10 includes a structure in which the inorganic and organic membranes are stacked (e.g., when the first insulating layer 10 includes a structure in which the inorganic and organic membranes are stacked), the first insulating layer 10 may further include a buffer inorganic membrane disposed or provided between adjacent inorganic and organic membranes.

[0114] In one or more embodiments, the description of the first insulating layer 10 can be applied substantially equivalently to the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 described herein. The second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may be referred to as the second inorganic film, the third inorganic film, and the fourth inorganic film, respectively. Each of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may have a single-layer structure or a multilayer structure. For example, each of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may independently include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0115] A semiconductor pattern may be formed or provided on the first insulating layer 10. The semiconductor pattern may include polycrystalline silicon. However, it is not limited thereto; the semiconductor pattern may include amorphous (e.g., amorphous) silicon and / or metal oxides. Depending on whether the semiconductor pattern is doped, it may have different electrical properties. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with a negative or negative-class dopant (e.g., N-type or N-class dopant) or a positive or positive-class dopant (e.g., P-type or P-class dopant). A P-type or P-class transistor may include a first region doped with a P-type or P-class dopant.

[0116] The first region may have higher conductivity (e.g., electrical conductivity) than the second region and is essentially used as an electrode or signal line. The second region may substantially correspond to the active region (or channel) of a transistor. For example, a portion of the semiconductor pattern may be the active region of a transistor, another portion of the semiconductor pattern may be the source or drain region of a transistor, and yet another portion of the semiconductor pattern may be a conductive (e.g., electrically conductive) region.

[0117] refer to Figure 5 In one or more embodiments of this disclosure, a transistor TR may be disposed or provided on a first insulating layer 10. In one or more embodiments, the transistor TR may be electrically connected to a light-emitting element LD. The source region SD, active region AD, and drain region DD of the transistor TR may be formed or provided by a semiconductor pattern. In one or more embodiments, Figure 5 The illustration shows a portion of a signal transmission region SCL formed or provided from a semiconductor pattern. In one or more embodiments, the signal transmission region SCL may be connected in a plane (e.g., in a planar view) to the drain region DD of a transistor TR.

[0118] The second insulating layer 20 may cover the signal transmission region SCL and the source region SD, active region AD, and drain region DD of the transistor TR, which are disposed or provided on the first insulating layer 10. The gate GD of the transistor TR may be disposed or provided on the second insulating layer 20. The third insulating layer 30 may be disposed or provided on the second insulating layer 20 to cover the gate GD. The upper electrode pattern EE may be disposed or provided on the third insulating layer 30. The fourth insulating layer 40 may be disposed or provided on the third insulating layer 30 to cover the upper electrode pattern EE.

[0119] A first connecting electrode CNE1 may be disposed or provided on a fourth insulating layer 40. The first connecting electrode CNE1 may be connected to the signal transmission area SCL via a contact hole CH1 passing through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. A fifth insulating layer 50 may be disposed or provided on the fourth insulating layer 40 to cover the first connecting electrode CNE1. The fifth insulating layer 50 may be an organic layer. In this disclosure, the fifth insulating layer 50 may be referred to as a "first intermediate insulating (e.g., electrical insulating) layer".

[0120] The second connecting electrode CNE2 may be disposed or provided on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CH2 passing through the fifth insulating layer 50. A sixth insulating layer 60 may be disposed or provided on the fifth insulating layer 50 to cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer. In this disclosure, the sixth insulating layer 60 may be referred to as a "second intermediate insulating (e.g., electrical insulating) layer".

[0121] Each of the fifth insulating layer 50 and the sixth insulating layer 60 may independently include at least one selected from acrylic resins, methacrylic resins, polyisoprene resins, ethylene resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins.

[0122] The display element layer D-OL can be disposed or provided on the circuit layer D-CL. The display element layer D-OL may include a light-emitting element LD and a pixel defining film PDL. The light-emitting element LD may include a first electrode AE, a second electrode CE opposite to the first electrode AE ​​(e.g., facing the first electrode AE), and a functional layer EL disposed or provided between the first electrode AE ​​and the second electrode CE.

[0123] The light-emitting opening OH, which exposes a portion of the upper surface of the first electrode AE, can be defined within the pixel-defining film PDL. The light-emitting region EA can be defined to correspond to the light-emitting opening OH.

[0124] The first electrode AE ​​may be disposed or provided on the circuit layer D-CL. In one or more embodiments of this disclosure, the first electrode AE ​​may be disposed or provided on the sixth insulating layer 60 of the circuit layer D-CL. The first electrode AE ​​can be connected to the second connection electrode CNE2 via the connection contact hole CH3 defined through the sixth insulating layer 60. Therefore, the first electrode AE ​​can be electrically connected to the signal transmission area SCL via the first connection electrode CNE1 and the second connection electrode CNE2, and can be electrically connected to the corresponding circuit element. The first electrode AE ​​may include a single-layer structure or a multi-layer structure.

[0125] The first electrode AE ​​can be an anode or a cathode. In one or more embodiments, the first electrode AE ​​can be a pixel electrode. The second electrode CE can be a cathode or an anode. The second electrode CE can be a common electrode. For example, if the first electrode AE ​​is an anode (e.g., when the first electrode AE ​​is an anode), then the second electrode CE can be a cathode, and if the first electrode AE ​​is a cathode (e.g., when the first electrode AE ​​is a cathode), then the second electrode CE can be an anode.

[0126] The first electrode AE ​​can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The first electrode AE ​​can include silver (Ag), magnesium (Mg), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or compounds (e.g., LiF) or mixtures (e.g., a mixture of Ag and Mg), or materials having a multilayer structure such as LiF / Ca or LiF / Al. In one or more embodiments, the first electrode AE ​​can have a multilayer structure including a reflective or semi-transmissive film of the materials described in one or more embodiments, and a transparent (e.g., substantially transparent) conductive (e.g., electrically conductive) film of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (e.g., ZnO), and / or indium tin zinc oxide (ITZO), etc. For example, the first electrode AE ​​can have a three-layer structure of ITO / Ag / ITO, but embodiments of this disclosure are not limited thereto. In one or more embodiments, the first electrode AE ​​may include the metallic material described in one or more embodiments, a combination of two or more metallic materials selected from the metallic materials described in one or more embodiments, and / or an oxide of the metallic material described in one or more embodiments, etc.

[0127] The second electrode CE can be a transmission electrode, a semi-transmission electrode, or a reflection electrode. If the second electrode CE is a transmission electrode (e.g., when the second electrode CE is a transmission electrode), then the second electrode CE can be composed of a transparent (e.g., substantially transparent) metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (e.g., ZnO), and indium tin zinc oxide (ITZO). In one or more embodiments, the second electrode CE can be formed or provided by a material comprising Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, or compounds thereof (e.g., LiF) or mixtures thereof (e.g., mixtures of Ag and Mg) or having a multilayer structure such as LiF / Ca or LiF / Al.

[0128] The functional layer EL may include a light-emitting layer. The light-emitting layer may include light-emitting materials such as organic materials and / or quantum dots. The functional layer EL including the light-emitting layer can be configured in each individual pixel PX (see [link to documentation]). Figure 4 It emits light selected from at least one color among blue, red, and green. In one or more embodiments, the functional layer EL can be located throughout the entire effective area DM-AA (see...). Figure 4 It provides blue light.

[0129] In addition to the light-emitting layer, the functional layer EL may further include a hole control layer and an electron control layer. The hole control layer may be disposed or provided between the first electrode AE and the light-emitting layer, and the electron control layer may be disposed or provided between the light-emitting layer and the second electrode CE.

[0130] The light-emitting layer of the functional layer EL may be patterned and then provided to correspond to the light-emitting region EA. In one or more embodiments, the hole control layer and the electron control layer of the functional layer EL may be formed or provided jointly for a plurality of pixels PX (see Figure 4 ). For example, the hole control layer and the electron control layer may be provided as a common layer for all pixels PX (see Figure 4 ). However, embodiments of the present disclosure are not limited thereto, and the hole control layer and the electron control layer may be patterned and then provided to correspond to the light-emitting region EA, or may be provided in a form in which the hole control layer and the electron control layer overlap with the pixel defining film PDL and a part of the hole control layer and the electron control layer is disconnected.

[0131] In one or more embodiments of the present disclosure, the pixel defining film PDL may have a single-layer structure or a multi-layer structure. The pixel defining film PDL may be a polymer resin. For example, the pixel defining film PDL may be formed or provided by including an acrylate resin and / or a polyimide resin. In one or more embodiments, in addition to the polymer resin, the pixel defining film PDL may be formed or provided by further including an inorganic material. In one or more embodiments, the pixel defining film PDL may be formed or provided by including a light-absorbing material and / or by including a black pigment and / or a black dye. The pixel defining film PDL formed or provided by including a black pigment and / or a black dye may achieve a black pixel defining film. When the pixel defining film PDL is formed or provided (for example, when the pixel defining film PDL is formed or provided), carbon black or the like may be used as the black pigment and / or the black dye, but embodiments of the present disclosure are not limited thereto.

[0132] In one or more embodiments, the pixel defining film PDL may be an inorganic material. For example, the pixel defining film PDL may be an inorganic material such as silicon nitride (for example, Si3N4 or SiN x , where 0 < X ≤ 2), silicon oxide (for example, SiO x , where 0 < X ≤ 2; for example, SiO2) and / or silicon oxynitride (for example, Si2N2O or SiO x N y , where 0 < X ≤ 2 and 0 < Y ≤ 2; for example, SiON).

[0133] An encapsulation layer ECL may be disposed on or provided on the second electrode CE of the light-emitting element LD. The encapsulation layer ECL may cover the light-emitting element LD. In one or more embodiments of this disclosure, the encapsulation layer ECL may be disposed on or provided in the aperture region HA of the display module DM (see [link to documentation]). Figure 4 The dam pattern in DMP (see) Figure 4 ) and grooves GV1, GV2 and GV3 (see Figure 6 )superior.

[0134] The encapsulation layer ECL may include multiple encapsulation films. The encapsulation layer ECL may include at least one inorganic film. In one or more embodiments, the encapsulation layer ECL may further include at least one organic film. In one or more embodiments of this disclosure, the encapsulation layer ECL may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 sequentially stacked on a third-direction DR3. However, embodiments of this disclosure are not limited thereto, and the number of stacked layers of the encapsulation layer ECL may vary. The first inorganic layer IOL1 and the second inorganic layer IOL2 may protect the display element layer D-OL from moisture and / or oxygen, and the organic layer OL may protect the display element layer D-OL from foreign matter such as dust particles.

[0135] The input sensor ISL can be disposed on or provided on the display panel DP. The input sensor ISL can be directly disposed on or provided on the encapsulation layer ECL. The input sensor ISL can be directly disposed on or provided on the second inorganic layer IOL2. The input sensor ISL may include a sensor substrate layer 210, a first sensor conductive layer 220, a sensor insulating layer 230, a second sensor conductive layer 240, and a sensor cover layer 250.

[0136] The sensor substrate 210 can be directly disposed on or provided on the display panel DP. The sensor substrate 210 can be an inorganic layer comprising at least one selected from silicon nitride, silicon oxynitride, and silicon oxide. In one or more embodiments, the sensor substrate 210 can be an organic layer comprising epoxy resin, acrylic resin, and / or imide resin. The sensor substrate 210 can have a monolayer structure or a multilayer structure in which the layers are stacked along the third direction DR3.

[0137] Each of the first sensor conductive layer 220 and the second sensor conductive layer 240 may have a single-layer structure or a multi-layer structure in which the layers are stacked along the third direction DR3.

[0138] A single-layer conductive (e.g., electrically conductive) layer may include a metal layer and / or a transparent (e.g., substantially transparent) conductive (e.g., electrically conductive) layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include transparent (e.g., substantially transparent) conductive (e.g., electrically conductive) oxides such as indium tin oxide, indium zinc oxide, zinc oxide, and / or indium zinc tin oxide. In one or more embodiments, the transparent conductive layer may include conductive (e.g., electrically conductive) polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, and / or graphene, etc.

[0139] Multilayer conductive (e.g., electrically conductive) layers may include metal layers. For example, the metal layers may have a titanium / aluminum / titanium three-layer structure. Multilayer conductive layers may include at least one metal layer and at least one transparent (e.g., substantially transparent) conductive (e.g., electrically conductive) layer.

[0140] A sensor insulating layer 230 may be disposed or provided between the first sensor conductive layer 220 and the second sensor conductive layer 240. A sensor cover layer 250 may be disposed or provided on the sensor insulating layer 230 and cover the second sensor conductive layer 240. The second sensor conductive layer 240 may include a conductive (e.g., electrically conductive) pattern. The sensor cover layer 250 may cover the conductive (e.g., electrically conductive) pattern and reduce or eliminate the possibility of damage to the conductive (e.g., electrically conductive) pattern in subsequent processes.

[0141] Each of the sensor insulating layer 230 and the sensor cover layer 250 may include an inorganic film. The inorganic film may include at least one selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0142] In one or more embodiments, each of the sensor insulating layer 230 and the sensor cover layer 250 may include an organic film. The organic film may include at least one selected from acrylic resins, methacrylic resins, polyisoprene resins, ethylene resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0143] refer to Figure 4 and Figure 6 A module aperture HH may be defined within a display module DM, and the display module DM may include an aperture region HA, which includes the module aperture HH formed or provided through the display module DM. The module aperture HH may be formed or provided through the display module DM and is defined by the exposed sidewall DM-HS of the display module DM.

[0144] The display module DM may include multiple dam portions DM1, DM2, and DM3 disposed or provided in the hole region HA. During the process of forming or providing the module hole HH, the dam portions DM1, DM2, and DM3 can protect the display element layer D-OL, etc. For example, the dam portions DM1, DM2, and DM3 can prevent physical impacts such as cracks that may occur if the module hole HH is formed or provided (e.g., when forming or providing the module hole HH) from being transmitted to the display region AA (or reduce the extent or frequency of such physical impacts such as cracks that may occur if the module hole HH is formed or provided (e.g., when forming or providing the module hole HH) is transmitted to the display region AA). In one or more embodiments, the dam portions DM1, DM2, and DM3 can prevent chemical materials used in the process of the display module DM (such as the formation of the module hole HH) from penetrating into the display region AA (or reduce the extent or frequency of such chemical materials used in the process of the display module DM (such as the formation of the module hole HH) penetrating into the display region AA). In one or more embodiments, if an excess of resin composition or the like is provided during the formation of the organic layer OL of the encapsulation layer ECL (e.g., when an excess of resin composition or the like is provided during the formation of the organic layer OL of the encapsulation layer ECL), the dam portions DM1, DM2, and DM3 may also be used to prevent the resin composition from flowing (or reduce the degree or frequency of resin composition flow).

[0145] In one or more embodiments, Figure 4 and Figure 6 In the illustration, three dam sections DM1, DM2, and DM3 are shown as being installed or provided, but the embodiments of this disclosure are not limited thereto. The number of dam sections can be between two and four.

[0146] Dam portions DM1, DM2, and DM3 may be disposed or provided on the base layer BS. In one or more embodiments of this disclosure, dam portions DM1, DM2, and DM3 may be disposed or provided on the lower insulating layer LIL. The lower insulating layer LIL may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, and a fourth insulating layer 40, such as Figure 5 As described in [the text]. In one or more embodiments, a fourth insulating layer 40 disposed or provided at the uppermost part of the lower insulating layer LIL can be described as a “first lower insulating (e.g., electrical insulating) layer”.

[0147] In one or more embodiments of this disclosure, a first dam portion DM1 may be configured or provided around (e.g., surrounding) the module aperture HH, and a second dam portion DM2 may be configured or provided around (e.g., surrounding) the first dam portion DM1. In one or more embodiments, the display module DM may further include a third dam portion DM3 around (e.g., surrounding) the second dam portion DM2 and adjacent to the display area AA.

[0148] Grooves GV1, GV2, and GV3 can be defined between dam sections DM1, DM2, and DM3. The first groove GV1 can be defined between the first dam section DM1 and the second dam section DM2, and the second groove GV2 can be defined between the second dam section DM2 and the third dam section DM3. In such a case... Figure 6 In the display module DM illustrated in the figure according to one or more embodiments of the present disclosure, the third recess GV3 may be defined between the third dam portion DM3 and a portion of the display panel DP at the boundary between the display area AA and the hole area HA.

[0149] Each of the dam sections DM1, DM2, and DM3 may include multiple dam layers stacked on a third direction DR3 in the thickness direction. Each of the first dam section DM1 and the second dam section DM2 may include first dam layers DM1-B and DM2-B and second dam layers DM1-T and DM2-T. The second dam layers DM1-T and DM2-T may be disposed on or provided on the first dam layers DM1-B and DM2-B.

[0150] The first dam layers DM1-B and DM2-B may be disposed or provided in substantially the same layer as the fifth insulating layer 50, and the second dam layers DM1-T and DM2-T may be disposed or provided in substantially the same layer as the sixth insulating layer 60. For example, the first dam layers DM1-B and DM2-B may be formed or provided in substantially the same process steps as the fifth insulating layer 50, and the second dam layers DM1-T and DM2-T may be formed or provided in substantially the same process steps as the sixth insulating layer 60. For example, in one or more embodiments of this disclosure, the first dam layers DM1-B and DM2-B may be organic layers of substantially the same material as the fifth insulating layer 50, and the second dam layers DM1-T and DM2-T may be organic layers of substantially the same material as the sixth insulating layer 60. However, embodiments of this disclosure are not limited thereto.

[0151] exist Figure 6In the figures, each of the first dam section DM1 and the second dam section DM2 is illustrated as including two dam layers, but the embodiments of this disclosure are not limited thereto, and at least one selected from the first dam section DM1 and the second dam section DM2 may include three dam layers or may include only one dam layer.

[0152] In one or more embodiments, the third dam portion DM3 may include a first dam layer DM3-B, a second dam layer DM3-T, and a third dam layer DM3-A stacked on the third-direction DR3. In the third dam portion DM3, the first dam layer DM3-B may be formed or provided with the fifth insulating layer 50 in substantially the same process steps, the second dam layer DM3-T may be formed or provided with the sixth insulating layer 60 in substantially the same process steps, and the third dam layer DM3-A may be formed or provided with the pixel defining film PDL in substantially the same process steps. However, embodiments of this disclosure are not limited thereto.

[0153] In one or more embodiments of this disclosure, each of the first dam layers DM1-B, DM2-B, and DM3-B, and the second dam layers DM1-T, DM2-T, and DM3-T, may have inclined side surfaces. However, embodiments of this disclosure are not limited thereto, and at least a portion of the first dam layers DM1-B, DM2-B, and DM3-B, and the second dam layers DM1-T, DM2-T, and DM3-T may be formed or provided to include side surfaces with curved shapes.

[0154] The circuit layer D-CL may further include a raised pattern MTP. The raised pattern MTP may be disposed or provided on at least one of the dam portions DM1, DM2, and DM3. The raised pattern MTP may be disposed or provided on the first dam layers DM1-B, DM2-B, and DM3-B. The raised pattern MTP may be disposed or provided between the first dam layers DM1-B, DM2-B, and DM3-B and the second dam layers DM1-T, DM2-T, and DM3-T. The raised pattern MTP may be disposed or provided on the first dam layers DM1-B, DM2-B, and DM3-B, and has a width in one direction greater than the width of the first dam layers DM1-B, DM2-B, and DM3-B by including a protruding portion.

[0155] The raised pattern MTP can be formed or provided in substantially the same process steps as any of the conductive (e.g., electrically conductive) patterns selected from the circuit layer D-CL that are disposed or provided in the display area AA. For example, the raised pattern MTP can be formed or provided in substantially the same process steps as the second connection electrode CNE2. For example, the raised pattern MTP can have substantially the same material as the second connection electrode CNE2. However, embodiments of this disclosure are not limited thereto.

[0156] The display module DM may further include an inorganic dam IOP that is set or provided in the borehole region HA. Figure 6 The illustration shows two inorganic dam IOPs disposed or provided adjacent to module hole HH, but the embodiments of this disclosure are not limited thereto, and at least one of the inorganic dam IOPs may not be provided, or more inorganic dams may be disposed or provided.

[0157] In one or more embodiments of this disclosure, each of the inorganic dam IOPs may include a first layer IL1 and a second layer IL2. The first layer IL1 may comprise substantially the same material as the first insulating layer 10 and be formed or provided by substantially the same process as the first insulating layer 10. The second layer IL2 may comprise substantially the same material as the second insulating layer 20 and be formed or provided by substantially the same process as the second insulating layer 20. However, this is merely an example, and the composition of the layers constituting each of the inorganic dam IOPs may be appropriately modified. The width of the first layer IL1 may be greater than the width of the second layer IL2. In one or more embodiments of this disclosure, each of the inorganic dam IOPs may have a stepped shape (e.g., a substantially stepped shape).

[0158] refer to Figure 5 and Figure 6 The encapsulation layer ECL can cover the components of the display element layer D-OL and the exposed circuit layer D-CL. In the display area AA, the encapsulation layer ECL can cover the light-emitting element LD and the pixel defining film PDL, and in the aperture area HA, the encapsulation layer ECL can cover the exposed portion of the circuit layer D-CL, dam portions DM1, DM2 and DM3, and the recesses GV1, GV2 and GV3 defined between the dam portions DM1, DM2 and DM3. The encapsulation layer ECL includes at least a first inorganic layer IOL1.

[0159] The first inorganic layer IOL1 may be disposed on or provided on the second electrode CE. The first inorganic layer IOL1 may be disposed on or provided on the dam portions DM1, DM2, and DM3, a portion of the raised pattern MTP, and the grooves GV1, GV2, and GV3. The first inorganic layer IOL1 may cover the exposed surfaces of the dam portions DM1, DM2, and DM3, a portion of the raised pattern MTP, and the grooves GV1, GV2, and GV3. The first inorganic layer IOL1 may protect the components of the display panel DP from the effects of external moisture and / or oxygen, etc.

[0160] The first inorganic layer IOL1 may include multiple sublayers. The first inorganic layer IOL1 can be formed or provided by two different methods and includes multiple sublayers distinguished by density. The first inorganic layer IOL1 may include silicon nitride. The first inorganic layer IOL1 can be formed or provided by sequentially performing a first method selected from plasma-enhanced atomic layer deposition (PEALD), sputtering, and electron beam evaporation, and a second method selected from plasma-enhanced chemical vapor deposition (PECVD). A description of the multiple sublayers included in the first inorganic layer IOL1 will be provided in more detail herein.

[0161] The encapsulation layer ECL may further include an organic layer OL disposed or provided on the first inorganic layer IOL1 and a second inorganic layer IOL2 disposed or provided on the organic layer OL.

[0162] An organic layer OL may be disposed or provided on a first inorganic layer IOL1 and overlap with at least one of a first groove GV1, a second groove GV2, and a third groove GV3. For example, the organic layer OL may overlap with the third groove GV3. The organic layer OL may not overlap with the first groove GV1 or the second groove GV2.

[0163] The second inorganic layer IOL2 can be disposed or provided on the organic layer OL and cover all (e.g., substantially all) of the first groove GV1, the second groove GV2, and the third groove GV3. In a portion of the aperture region HA, the second inorganic layer IOL2 can be directly disposed or provided on the first inorganic layer IOL1. In regions corresponding to the first groove GV1 and the second groove GV2 where the organic layer OL is not disposed, the second inorganic layer IOL2 can contact the upper surface of the first inorganic layer IOL1.

[0164] Figures 7 to 9 Each of these is an enlarged cross-sectional view of a portion of a display module according to one or more embodiments of the present disclosure. Figure 7 yes Figure 6 Enlarged cross-sectional view of region AA'. Figure 8 yes Figure 7 Enlarged cross-sectional view of area BB'.

[0165] Figure 9 It is a schematic diagram as shown below. Figure 6 and Figure 7 A more detailed cross-sectional view of the layer structure or arrangement of the first inorganic layer IOL1 shown in the figure.

[0166] refer to Figure 6 and Figure 7The circuit layer D-CL may include a protruding pattern MTP comprising a pointed portion TP projecting from dam portions DM1, DM2, and DM3. The pointed portion TP may project inward in the recesses GV1, GV2, and GV3. The protruding pattern MTP may completely (e.g., substantially completely) overlap with the second dam layers DM1-T, DM2-T, and DM3-T and has a width in one direction greater than the width of a surface of an adjacent dam layer. In one or more embodiments, the protruding pattern MTP may not completely overlap with the second dam layers DM1-T, DM2-T, and DM3-T and may be provided as two separate portions in cross-section, adjacent to the edges of the second dam layers DM1-T, DM2-T, and DM3-T adjacent to the recesses GV1, GV2, and GV3. In one or more embodiments, the shape of the raised pattern MTP may be provided in one or more suitable forms, depending on the shape of the provided dam portions DM1, DM2 and DM3, the patterning method of the dam portions DM1, DM2 and DM3, or the patterning process of the dam portions DM1, DM2 and DM3.

[0167] Because the raised pattern MTP is set or provided to protrude further inward into the groove GV1 than the upper surfaces of the first dam layers DM1-B and DM2-B and the lower surfaces of the second dam layers DM1-T and DM2-T, so as to have a pointed portion TP, the dam portions DM1 and DM2 may include undercut portions UCP.

[0168] The first groove GV1 and the second groove GV2 can be defined between two adjacent dam portions DM1, DM2, and DM3, and the first groove GV1 can include a first recessed portion GV-B defined by the first dam layers DM1-B and DM2-B, and a second recessed portion GV-T defined by the second dam layers DM1-T and DM2-T. The second recessed portion GV-T can overlap with the first recessed portion GV-B and is defined on the first recessed portion GV-B. The first groove GV1 can be defined between the first dam portion DM1 and the second dam portion DM2, and the second groove GV2 can be defined between the second dam portion DM2 and the third dam portion DM3. The third groove GV3 can be defined between the third dam portion DM3 and each of the fifth insulating layer 50 and the sixth insulating layer 60.

[0169] Each of the dam sections DM1, DM2, and DM3 may include inclined surfaces IS1 and IS2 defining grooves GV1, GV2, and GV3. Dam sections DM1, DM2, and DM3 may include a first inclined surface IS1 and a second inclined surface IS2. For example... Figure 7As illustrated in the figure, the first dam layers DM1-B and DM2-B may include a first inclined surface IS1 defining a first recessed portion GV-B, and the second dam layers DM1-T and DM2-T may include a second inclined surface IS2 defining a second recessed portion GV-T.

[0170] The first inorganic layer IOL1 may be configured or provided to cover the upper surface of the fourth insulating layer 40 exposed in the grooves GV1, GV2, and GV3, the first inclined surface IS1 which is the side surface of the first dam layers DM1-B and DM2-B, the tip portion TP of the protruding pattern MTP, the second inclined surface IS2 which is the side surface of the second dam layers DM1-T and DM2-T, and all (e.g., substantially all) of the upper surface of the second dam layers DM1-T and DM2-T. The first inorganic layer IOL1 may contact each of the upper surface of the fourth insulating layer 40, the first inclined surface IS1, the tip portion TP of the protruding pattern MTP, the second inclined surface IS2, and the upper surface of the second dam layers DM1-T and DM2-T.

[0171] Let's refer to each other. Figures 6 to 8 Due to the undercut portion UCP, the portion of the first inorganic layer IOL1 that is set or provided around the tip portion TP may not have a uniform (e.g., substantially uniform) thickness, and the thickness of this portion of the first inorganic layer IOL1 may be smaller than the thickness of other portions.

[0172] The first inorganic layer IOL1 may include a first portion IOL1-1 disposed or provided on the upper surface MTP-U of the tip portion TP of the protruding pattern MTP, a second portion IOL1-2 disposed or provided on the lower surface MTP-B of the tip portion TP, and a third portion IOL1-3 disposed or provided on the first inclined surface IS1. The first inorganic layer IOL1 may further include a fourth portion IOL1-4 disposed or provided on the side surface MTP-S of the tip portion TP. The first portions IOL1-1 to the fourth portions IOL1-4 may have a monolithic shape (e.g., substantially monolithic shape), but may have different thicknesses. Through the first portions IOL1-1 to the fourth portions IOL1-4, the first inorganic layer IOL1 may completely (e.g., substantially completely) cover each of the upper surface MTP-U, the lower surface MTP-B, and the side surface MTP-S of the tip portion TP, as well as each of the first inclined surface IS1 of the first dam layers DM1-B and DM2-B.

[0173] In the first inorganic layer IOL1 according to one or more embodiments of the present disclosure, the first portion IOL1-1 disposed or provided on the upper surface MTP-U of the tip portion TP may have a thickness T1 greater than the thickness of other portions. The thickness T2 of the second portion IOL1-2 disposed or provided on the lower surface MTP-B of the tip portion TP may be more than 30% of the thickness T1 of the first portion IOL1-1. The thickness T2 of the second portion IOL1-2 may be from about 30% to about 60% of the thickness T1 of the first portion IOL1-1. The thickness T3 of the third portion IOL1-3 disposed or provided on the first inclined surface IS1 may be more than 40% of the thickness T1 of the first portion IOL1-1. The thickness T3 of the third portion IOL1-3 may be from about 40% to about 70% of the thickness T1 of the first portion IOL1-1. The thickness T4 of the fourth portion IOL1-4, which is set or provided on the side surface MTP-S of the tip portion TP, may be more than 60% of the thickness T1 of the first portion IOL1-1. The thickness T4 of the fourth portion IOL1-4 may be from about 60% to about 90% of the thickness T1 of the first portion IOL1-1.

[0174] A display module DM according to one or more embodiments of the present disclosure may include dam portions DM1, DM2, and DM3 adjacent to module holes HH, and recesses GV1, GV2, and GV3, and may also include a raised pattern MTP comprising a tip portion TP protruding from the dam portions DM1, DM2, and DM3. Because the raised pattern MTP has the tip portion TP, the dam portions DM1, DM2, and DM3 may have an undercut portion UCP, and if the thickness of the first inorganic layer IOL1 in the undercut portion UCP becomes thinner (e.g., when the thickness of the first inorganic layer IOL1 in the undercut portion UCP becomes thinner), moisture and / or oxygen may relatively easily penetrate into this thin portion of the first inorganic layer IOL1. Accordingly, defects such as oxidation of components included in the circuit layer D-CL and display element layer D-OL of the display module DM may occur.

[0175] In a display module DM according to one or more embodiments of the present disclosure, the reliability of the display module DM can be improved or enhanced by providing the thickness of the first inorganic layer IOL1 in the undercut portion UCP to a set or predetermined thickness or greater. For example, in a display module DM according to one or more embodiments of the present disclosure, relative to a first portion IOL1-1 provided or provided on the upper surface MTP-U of the tip portion TP, a second portion IOL1-2 provided or provided on the lower surface MTP-B of the tip portion TP with a thickness of approximately 30% or more of the thickness of the first portion IOL1-1, and a third portion IOL1-3 provided or provided on the first inclined surface IS1 with a thickness of approximately 40% or more of the thickness of the first portion IOL1-1, can be provided to prevent moisture and / or oxygen from penetrating into the thin portion of the first inorganic layer IOL1 (or reduce the degree or frequency of moisture and / or oxygen penetrating into the thin portion of the first inorganic layer IOL1), thereby preventing defects (or reducing the degree or frequency of defects).

[0176] Figure 9 This is an enlarged cross-sectional view schematically illustrating a more detailed layer structure or arrangement of the first inorganic layer IOL1. For example... Figure 9 The first inorganic layer IOL1 shown in the diagram can be selected from... Figure 8 Any of the multiple portions of the first inorganic layer IOL1 illustrated in the diagram. For example, Figure 9 It can be selected from... Figure 8 Any one of the first part IOL1-1, the second part IOL1-2, the third part IOL1-3, and the fourth part IOL1-4 of the first inorganic layer IOL1 shown in the figure.

[0177] Let's refer to each other. Figure 8 and Figure 9 The bottom layer BSL can be a component providing the bottom surface BSF on which the first inorganic layer IOL1 is disposed or provided. In the first portion IOL1-1 of the first inorganic layer IOL1, the bottom surface BSF can be the upper surface MTP-U of the tip portion TP. In the second portion IOL1-2 of the first inorganic layer IOL1, the bottom surface BSF can be the lower surface MTP-B of the tip portion TP. In the third portion IOL1-3 of the first inorganic layer IOL1, the bottom surface BSF can be the first inclined surface IS1. In the fourth portion IOL1-4 of the first inorganic layer IOL1, the bottom surface BSF can be the side surface MTP-S of the tip portion TP.

[0178] In one or more embodiments of this disclosure, the first inorganic layer IOL1 may include a plurality of sublayers comprising substantially the same material but with different densities. The first inorganic layer IOL1 may include a first sublayer IL-S1 disposed or provided on the underlying BSL, a second sublayer IL-S2 disposed or provided on the first sublayer IL-S1, and a third sublayer IL-S3 disposed or provided on the second sublayer IL-S2. Because the first inorganic layer IOL1 has a structure comprising multiple sublayers, as described in one or more embodiments, the display module DM may provide the thickness of the first inorganic layer IOL1 in the undercut portion UCP to a set or predetermined thickness or greater.

[0179] The first sublayer IL-S1 can be directly disposed or provided on the bottom surface BSF. The first sublayer IL-S1 can have a relatively high density. The second sublayer IL-S2 can be directly disposed or provided on the first sublayer IL-S1 and has a relatively low density. The third sublayer IL-S3 can be directly disposed or provided on the second sublayer IL-S2 and has a relatively high density. In the first inorganic layer IOL1 according to one or more embodiments of the present disclosure, the second sublayer IL-S2 disposed or provided in the middle can have a lower density than the first sublayer IL-S1 and the third sublayer IL-S3 adjacent to the second sublayer IL-S2. The density difference between the second sublayer IL-S2 and the first sublayer IL-S1 can be approximately 0.1 g / cm³. 3 above.

[0180] Each of the first sublayer IL-S1, the second sublayer IL-S2, and the third sublayer IL-S3 may comprise silicon nitride. Each of the first sublayer IL-S1, the second sublayer IL-S2, and the third sublayer IL-S3 may be formed from or provided from substantially the same Si-N precursor.

[0181] In one or more embodiments of this disclosure, the density of a portion of the first inorganic layer IOL1 may increase in a direction away from the underlying layer BSL. In the second sublayer IL-S2 and the third sublayer IL-S3 of the first inorganic layer IOL1, the silicon nitride density may gradually increase in a direction away from the first sublayer IL-S1. In one or more embodiments, the silicon nitride density may be similar within a specific (e.g., defined or predetermined) thickness range, and the silicon nitride density outside a specific (e.g., defined or predetermined) thickness range may be gradually varied to be distinguishable from the density within the specific (e.g., defined or predetermined) thickness range.

[0182] The first sublayer IL-S1 may originate from a preliminary first inorganic layer PIL formed or provided by a first method as described in one or more embodiments (see [link]). Figure 11AThe second sublayer IL-S2 and the third sublayer IL-S3 may be formed or provided by a second method as described in one or more embodiments.

[0183] The thickness d2 of the first sublayer IL-S1 can be from about 0.1% to about 10% of the total thickness d1 of the first inorganic layer IOL1. For example, the thickness d2 of the first sublayer IL-S1 can be from about 0.1% to about 1% of the total thickness d1 of the first inorganic layer IOL1. The total thickness d1 of the first inorganic layer IOL1 can be approximately up to approximately

[0184] The first inorganic layer IOL1 can have a refractive index of approximately 1.7 to approximately 2.0 at a wavelength of approximately 550 nm. For example, the first inorganic layer IOL1 can have a refractive index of approximately 1.85 to approximately 1.9 at a wavelength of approximately 550 nm. Each of the first sublayer IL-S1, the second sublayer IL-S2, and the third sublayer IL-S3 included in the first inorganic layer IOL1 can have different refractive indices due to differences in density. For example, the refractive index of the second sublayer IL-S2, which has a low density, can be lower than the refractive index of each of the first sublayer IL-S1 and the third sublayer IL-S3, which have high densities.

[0185] Electronic devices including a first inorganic layer IOL1 according to one or more embodiments of this disclosure can exhibit excellent or suitable reliability characteristics. Due to the structure comprising two or more sublayers as described in one or more embodiments, the first inorganic layer IOL1 can have a low water vapor transmission rate (WVTR). The water vapor transmission rate of the first inorganic layer IOL1 can be approximately 1.0 × 10⁻⁶. -4 g / (m 2 (·days) or less. For example, the water vapor permeability of the first inorganic layer IOL1 can be approximately 5.0 × 10⁻⁶. -5 g / (m 2 (·days) or less. The first inorganic layer IOL1 may include a structure in which a first sublayer IL-S1, a second sublayer IL-S2 and a third sublayer IL-S3 as described in one or more embodiments are stacked, and the first sublayer IL-S1 adjacent to the bottom surface BSF may have a low water vapor transmission rate due to its high density.

[0186] Figures 10A to 10C Each of the figures schematically illustrates a step of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure. Figure 11A and Figure 11B Each of these is an enlarged cross-sectional view of a portion of a display module in a step of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure. Figure 12 This is an enlarged cross-sectional view of a portion of a display module in a step of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure. Figures 10A to 10C Each of them in relation to Figure 7 The corresponding cross-section schematically illustrates one step of the process used to manufacture the display module. Figure 11A and Figure 11B Each of them in relation to Figure 9 The corresponding cross-section schematically illustrates one step of the process used to manufacture the first inorganic layer. Figure 12 In Figure 8 The corresponding cross-section schematically illustrates one step of the process used to manufacture the first inorganic layer.

[0187] In the following text, reference will be made to Figures 10A to 12 A method for manufacturing an electronic device according to one or more embodiments of the present disclosure is described in more detail.

[0188] A method for manufacturing an electronic device according to one or more embodiments of the present disclosure may include providing a substrate layer, forming or providing a circuit layer, forming or providing a display element layer, and forming or providing an encapsulation layer. Forming or providing the encapsulation layer may include forming or providing a first inorganic layer. In the description of the method for manufacturing an electronic device according to one or more embodiments of the present disclosure, substantially the same description may be applied to references... Figures 1 to 9 The components of the described electronic device are essentially the same.

[0189] Figures 10A to 10C The sequential diagram illustrates the formation or provision of a first dam section DM1 and a second dam section DM2 on the lower insulation layers 30 and 40 (see...). Figure 6 ) and in the first groove GV1 (see Figure 7 The first inorganic layer IOL1 is formed or provided in a state provided between the first dam section DM1 and the second dam section DM2.

[0190] refer to Figures 10A to 10C Forming or providing a first inorganic layer IOL1 may include applying a first deposition material EM1 to form or provide a preliminary first inorganic layer PIL and applying a second deposition material EM2 on the preliminary first inorganic layer PIL to form or provide the first inorganic layer IOL1. In this disclosure, the first deposition material EM1 may be provided by a first method, and the second deposition material EM2 may be provided by a second method different from the first method.

[0191] The first deposited material EM1 can be provided by a first method selected from plasma-enhanced atomic layer deposition (PEALD), sputtering, and electron beam evaporation. For example, the first deposited material EM1 can be provided by plasma-enhanced atomic layer deposition (PEALD). The preliminary first inorganic layer PIL formed or provided by the first deposited material EM1 can be formed or provided as a first inclined surface IS1 covering the upper surface of the fourth insulating layer 40, being the side surfaces of the first dam layers DM1-B and DM2-B, and the tip portion TP of the protruding pattern MTP (see Figure 7 (i.e., substantially all) is the second inclined surface IS2 of the side surfaces of the second dam layers DM1-T and DM2-T and the entirety of the upper surfaces of the second dam layers DM1-T and DM2-T.

[0192] The second deposited material EM2 can be provided by a method different from the first method. The second deposited material EM2 can be provided by a second method, namely plasma-enhanced chemical vapor deposition (PECVD). When providing the second deposited material EM2, an additional stacked structure can be formed or provided on the previously formed or provided preliminary first inorganic layer PIL, thereby forming or providing the first inorganic layer IOL1. The first inorganic layer IOL1 can be formed or provided as a first inclined surface IS1 covering the upper surface of the fourth insulating layer 40, being the side surfaces of the first dam layers DM1-B and DM2-B, and the tip portion TP of the protruding pattern MTP (see...). Figure 7 (i.e., substantially all) is the second inclined surface IS2 of the side surfaces of the second dam layers DM1-T and DM2-T and the entirety of the upper surfaces of the second dam layers DM1-T and DM2-T.

[0193] refer to Figures 10A to 10C as well as Figure 11A and Figure 11BAfter a preliminary first inorganic layer PIL is formed or provided on the underlying BSL using a first deposition material EM1, a second deposition material EM2 can be provided on the preliminary first inorganic layer PIL to form or provide the first inorganic layer IOL1. Within the first inorganic layer IOL1, a first sublayer IL-S1 can correspond to the preliminary first inorganic layer PIL, and second sublayers IL-S2 and third sublayers IL-S3 can be formed or provided by providing the second deposition material EM2. For example, the first sublayer IL-S1 can be formed or provided by providing a portion of the second deposition material EM2 on the preliminary first inorganic layer PIL using a plasma-enhanced chemical vapor deposition (PECVD) method, and the remaining portion of the second deposition material EM2 can be provided on the first sublayer IL-S1 to form or provide sequentially stacked second sublayers IL-S2 and third sublayers IL-S3. In one or more embodiments, the underlying BSL can be a component providing the bottom surface BSF on which the first inorganic layer IOL1 is disposed or provided.

[0194] Because the first sublayer IL-S1 corresponds to the preliminary first inorganic layer PIL, the thickness d2 of the first sublayer IL-S1 can be substantially the same as the thickness dp of the preliminary first inorganic layer PIL. In one or more embodiments, "substantially the same" in terms of thickness can include not only cases where they are physically substantially the same, but also cases where, although the design is substantially the same, there are differences due to process variations. The thickness dp of the preliminary first inorganic layer PIL can be from about 0.1% to about 10% of the total thickness d1 of the first inorganic layer IOL1. For example, the thickness dp of the preliminary first inorganic layer PIL can be from about 0.1% to about 1% of the total thickness d1 of the first inorganic layer IOL1. The total thickness d1 of the first inorganic layer IOL1 can be approximately up to approximately

[0195] The first deposition material EM1 and the second deposition material EM2 may comprise substantially the same material as each other. Each of the first deposition material EM1 and the second deposition material EM2 may comprise a precursor material for forming or providing a silicon nitride film. Each of the first deposition material EM1 and the second deposition material EM2 may comprise an aminosilane material having a Si-N core structure. For example, each of the first deposition material EM1 and the second deposition material EM2 may comprise at least one selected from cyclosilazane, trisilamine, bis(diethylamino)silane, bis(tert-butylamino)silane, tri(dimethylamino)silane, tri(isopropylamino)silane, tetra(dimethylamino)silane, tri(isopropyl)cyclotrisilazane, and tetramethyldisilazane. However, this is not a limitation; each of the first deposition material EM1 and the second deposition material EM2 may include, but is not limited to, any suitable precursor material, as long as it is possible to form or provide a silicon nitride film.

[0196] The first deposition material EM1 and the second deposition material EM2 may comprise substantially the same material, but provided by different methods, and therefore, the first sublayer IL-S1 corresponding to the preliminary first inorganic layer PIL and the second sublayer IL-S2 formed or provided on the first sublayer IL-S1 may have different densities. The first sublayer IL-S1 may have a relatively high density. The second sublayer IL-S2 may be formed or provided directly on the first sublayer IL-S1 and may have a relatively low density. Because the first sublayer IL-S1 corresponds to the preliminary first inorganic layer PIL formed or provided by a method such as plasma-enhanced atomic layer deposition (PEALD), it can have a relatively high density. The second sublayer IL-S2 may be formed or provided by a plasma-enhanced chemical vapor deposition (PECVD) method and may be formed or provided as a low-density film in the early stages of film formation during the plasma-enhanced chemical vapor deposition process, and therefore, the second sublayer IL-S2 may have a relatively low density. The third sublayer IL-S3 may be formed or provided by a plasma-enhanced chemical vapor deposition method in substantially the same manner as the second sublayer IL-S2. However, because the film is formed or provided after an intermediate stage of the deposition process, the density of the third sublayer IL-S3 can be higher than that of the second sublayer IL-S2. The density difference between the second sublayer IL-S2 and the first sublayer IL-S1 can be approximately 0.1 g / cm³. 3 above.

[0197] Figure 12 The illustration shows a portion of a cross section of the initial first inorganic layer (PIL) formed or provided by a first deposited material during the step of manufacturing the first inorganic layer.

[0198] refer to Figure 12 Due to the undercut portion of UCP (see Figure 7 The initial first inorganic layer PIL surrounds the tip portion TP (see...). Figure 7 The portion that is set or provided may not have a consistent (e.g., substantially consistent) thickness, and the portion of the initial first inorganic layer PIL that is set or provided around the tip portion TP may have a smaller thickness than the other portions.

[0199] The preliminary first inorganic layer PIL may include a first preliminary portion PIL-1 disposed or provided on the upper surface MTP-U of the tip portion TP of the protruding pattern MTP, a second preliminary portion PIL-2 disposed or provided on the lower surface MTP-B of the tip portion TP, and a third preliminary portion PIL-3 disposed or provided on the first inclined surface IS1. The preliminary first inorganic layer PIL may further include a fourth preliminary portion PIL-4 disposed or provided on the side surface MTP-S of the tip portion TP. The first preliminary portions PIL-1 to the fourth preliminary portions PIL-4 may have a monolithic shape (e.g., substantially monolithic shape) or may have partially different thicknesses. Through the first preliminary portions PIL-1 to the fourth preliminary portions PIL-4, the preliminary first inorganic layer PIL may completely (e.g., substantially completely) cover each of the upper surface MTP-U, the lower surface MTP-B, and the side surface MTP-S of the tip portion TP, as well as each of the first inclined surface IS1 of the first dam layers DM1-B and DM2-B.

[0200] In the preliminary first inorganic layer PIL according to one or more embodiments of the present disclosure, the first preliminary portion PIL-1 disposed or provided on the upper surface MTP-U of the tip portion TP can have a thickness T greater than that of other portions. a The thickness T of the second preliminary portion PIL-2, which is set or provided on the lower surface MTP-B of the tip portion TP, is... b It can be the thickness T of the first preliminary part PIL-1 a Approximately 50% or more. The thickness T of the second preliminary part, PIL-2. b It can be the thickness T of the first preliminary part PIL-1 a Approximately 50% to approximately 80%. The thickness T of the third preliminary portion PIL-3, which is set or provided on the first inclined surface IS1, is... c It can be the thickness T of the first preliminary part PIL-1 a Approximately 80% or more. The thickness T of the third preliminary part, PIL-3. c It can be the thickness T of the first preliminary part PIL-1 a Approximately 80% to approximately 90%. The thickness T of the fourth preliminary portion PIL-4, which is set or provided on the side surface MTP-S of the tip portion TP, is [missing information]. d It can be the thickness T of the first preliminary part PIL-1 a Approximately 85% or more. The thickness T of the fourth preliminary part, PIL-4. d It can be the thickness T of the first preliminary part PIL-1 a Approximately 85% to approximately 95%.

[0201] In a method of manufacturing an electronic device according to one or more embodiments of the present disclosure, because the preliminary first inorganic layer PIL can be formed or provided by a first method as described in one or more embodiments, the thickness of the preliminary first inorganic layer PIL in the undercut portion UCP can be formed or provided to a set or predetermined thickness or greater. In one or more embodiments, if the first inorganic layer IOL1 is subsequently completed by a second method (e.g., when the first inorganic layer IOL1 is completed by a second method), the thickness of the first inorganic layer IOL1 in the undercut portion UCP can be formed or provided to a set or predetermined thickness or greater, thereby improving or enhancing the reliability of the display module DM. Because the method of manufacturing an electronic device according to one or more embodiments of the present disclosure includes a process of forming or providing the preliminary first inorganic layer PIL by a first method, the thickness of the first inorganic layer IOL1 in the undercut portion UCP (e.g., the second portion IOL1-2 (see...)) can be increased compared to a case where a process of forming or providing the preliminary first inorganic layer PIL is not included, as described in one or more embodiments. Figure 8 Part 3 IOL1-3 (see) Figure 8 ) and Part IV IOL1-4 (see Figure 8 The thickness of each of the layers can be formed or provided to be greater. Accordingly, it is feasible to reduce the water vapor transmission rate of the electronic device including the first inorganic layer IOL1 and to improve or enhance the reliability of the electronic device including the first inorganic layer IOL1.

[0202] Because the electronic device according to one or more embodiments of this disclosure includes an inorganic encapsulation layer comprising a plurality of sublayers with different densities, the thickness of the inorganic encapsulation layer in the undercut portion formed or provided by the dam structure and groove provided adjacent to the module aperture can be provided as a set or predetermined thickness or greater. Accordingly, due to the low water vapor permeability of the encapsulation layer, the display panel can be effectively or appropriately protected, and the electronic device can exhibit excellent or appropriate reliability characteristics.

[0203] Although one or more embodiments of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the present disclosure is not limited to these embodiments, but one or more suitable changes and modifications may be made within the spirit and scope of the claims and their equivalents, the detailed description of the present disclosure, and the drawings.

[0204] Accordingly, the scope of this disclosure should not be limited to one or more embodiments / examples, but should be determined by the claims and their equivalents.

Claims

1. An electronic device, comprising an electronic module and a display module, The display module includes: The aperture area is defined to overlap with the electronic module; A base layer having module holes defined in the base layer and corresponding to the hole region; Circuit layer, on the base layer; A display element layer is provided on the circuit layer and includes light-emitting elements; and An encapsulation layer, partially provided on the display element layer, includes at least a first inorganic layer. The circuit layer includes: Multiple insulating layers are provided on the substrate layer and include a first intermediate insulating layer; The first dam portion is spaced apart from the first intermediate insulating layer and defines at least one groove between the first intermediate insulating layer and the first dam portion; and A raised pattern is provided on at least a portion of the first intermediate insulating layer and the first dam portion, and includes a pointed tip portion projecting inward in the at least one groove. in: The first dam portion includes a first inclined surface beneath the protruding pattern; and The first inorganic layer includes a first portion on the upper surface of the tip portion, a second portion on the lower surface of the tip portion, and a third portion on the first inclined surface. in: The thickness of the second part is more than 30% of the thickness of the first part; and The thickness of the third part is more than 40% of the thickness of the first part.

2. The electronic device according to claim 1, wherein: The at least one groove includes a first groove defined by the first inclined surface. The encapsulation layer further includes a second inorganic layer, and At least a portion of the first inorganic layer and at least a portion of the second inorganic layer are in contact with each other in the region overlapping with the first groove.

3. The electronic device according to claim 2, wherein, The first inorganic layer includes: The first sublayer is adjacent to the tip portion; The second sub-layer, on top of the first sub-layer; and The third sub-layer, above the second sub-layer. The density of the second sublayer is lower than the density of each of the first and third sublayers.

4. The electronic device according to claim 3, wherein, The thickness of the first sublayer is 0.1% to 10% of the thickness of the first inorganic layer.

5. The electronic device according to claim 3, wherein, The density difference between the first sublayer and the second sublayer is 0.1 g / cm³. 3 above.

6. The electronic device according to any one of claims 1 to 5, wherein, The encapsulation layer further includes: A second inorganic layer, on top of the first inorganic layer; and An organic layer is located between the first inorganic layer and the second inorganic layer. In the planar view, the organic layer does not overlap with at least a portion of the protruding pattern.

7. The electronic device according to claim 1, wherein, In the plan view, the at least one groove is located around the module hole.

8. An electronic device, comprising an electronic module and a display module, The display module includes: The aperture area is defined to overlap with the electronic module; A base layer having module holes defined in the base layer and corresponding to the hole region; A circuit layer is provided on the substrate layer; A display element layer is provided on the circuit layer and includes light-emitting elements; and An encapsulation layer, partially provided on the display element layer, includes a first inorganic layer and a second inorganic layer. The circuit layer includes: A dam pattern is provided in the orifice area and includes a first dam section and a second dam section; and The raised pattern is on at least a portion of the dam pattern. in: A first groove is defined between the first dam section and the second dam section; The protruding pattern includes a pointed tip that protrudes inward in the first groove; Each of the first dam portion and the second dam portion includes a first inclined surface below the protruding pattern and defining the first groove; and The first inorganic layer includes a first portion on the upper surface of the tip portion, a second portion on the lower surface of the tip portion, and a third portion on the first inclined surface. in: The thickness of the second part is more than 30% of the thickness of the first part; and The thickness of the third part is more than 40% of the thickness of the first part.

9. A method for manufacturing an electronic device, the method comprising: A base layer is provided, the base layer having module holes defined therein; A circuit layer is provided, the circuit layer including a plurality of insulating layers on the substrate layer, a dam pattern and a protruding pattern spaced apart from the plurality of insulating layers; and An encapsulation layer is provided on the circuit layer. in: The dam pattern includes a first dam portion, which is spaced apart from the plurality of insulating layers and defines at least one groove between the plurality of insulating layers and the first dam portion; The raised pattern is on at least a portion of the first dam section; The first dam portion includes a first inclined surface beneath the protruding pattern; and The protruding pattern includes a pointed portion protruding from the first inclined surface. in: The provision of the encapsulation layer includes providing a first inorganic layer covering the tip portion and the first inclined surface; and The first inorganic layer includes a first portion on the upper surface of the tip portion, a second portion on the lower surface of the tip portion, and a third portion on the first inclined surface. in: The thickness of the second part is more than 30% of the thickness of the first part; and The thickness of the third part is more than 40% of the thickness of the first part.

10. The method according to claim 9, wherein, The provision of the first inorganic layer includes: A first deposition material is applied by any one of plasma-enhanced atomic layer deposition, sputtering, and electron beam evaporation methods to provide a preliminary first inorganic layer; and A second deposition material is applied to the initial first inorganic layer using a plasma-enhanced chemical vapor deposition method.

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