Spin-orbit moment memory cell, preparation method thereof and magnetic random access memory

Abstract

The invention discloses a spin-orbit moment memory cell, a preparation method thereof and a magnetic random access memory. The spin-orbit moment memory cell includes: a magnetic tunnel junction having a first outer peripheral surface; the track layer is located on one side of the magnetic tunnel junction, the track layer is provided with a second peripheral surface coplanar with the first peripheral surface, and the surface of the side, away from the magnetic tunnel junction, of the track layer is a first surface; and the bottom electrode comprises two spaced electrode parts, the orthographic projection part of each electrode part in the first direction falls into the first surface, and the first direction is the direction in which the track layer points to the magnetic tunnel junction. By adopting the spin-orbit moment storage unit, the etching yield can be improved, so that the yield and uniformity of a device are improved, the writing efficiency of the device can be improved, and the writing current is reduced.

Description

Technical Field

[0001] This application relates to the field of memory chips, and more specifically, to a spin orbital moment memory cell, its fabrication method, and a magnetic random access memory. Background Technology

[0002] Spin-orbit torque magnetic tunnel junction (SOT-MTJ) devices are one of the core structural types of MRAM products. Compared to spin-transfer torque magnetic tunnel junction (STT-MTJ) devices, SOT-MTJ devices feature faster write speeds, unlimited erase / write cycles, and read / write separation. A key structural feature of SOT-MTJ devices is the orbital layer, only a few nanometers thick, which provides an independent channel for write current, enabling read / write separation. However, the industrialization of SOT-MRAM currently faces several challenges:

[0003] 1. When performing MTJ etching, it is necessary to stop precisely at the SOT orbital layer, which results in an excessively small etching window;

[0004] 2. The flip current of SOT-MTJ devices is proportional to the track layer width, which can easily lead to photolithographic alignment errors during miniaturization;

[0005] 3. During mass production, SOT-MTJ devices are prone to problems with poor yield and uniformity.

[0006] Currently, there is an urgent need to provide a SOT-MTJ device to overcome the aforementioned technical problems that exist during its industrialization. Summary of the Invention

[0007] This application provides a spin orbital moment storage cell, its fabrication method, and a magnetic random access memory to solve the problems of poor yield and uniformity of SOT-MTJ devices in related technologies.

[0008] According to one aspect of this application, a spin-orbit moment storage cell is provided, comprising: a magnetic tunnel junction having a first outer peripheral surface; an orbital layer located on one side of the magnetic tunnel junction, the orbital layer having a second outer peripheral surface coplanar with the first outer peripheral surface, and the side surface of the orbital layer facing away from the magnetic tunnel junction being a first surface; and a bottom electrode comprising two spaced-apart electrode portions, each electrode portion having a projection portion in a first direction falling into the first surface, the first direction being the direction in which the orbital layer points towards the magnetic tunnel junction.

[0009] Optionally, the side surface of each electrode portion facing away from the track layer is a second surface. The electrode portion also has a third surface and a first over-etched surface that are respectively opposite to the second surface. The third surface and the first over-etched surface are not coplanar. The orthographic projection of the third surface in the first direction falls at least partially into the first surface, and the orthographic projection of the first over-etched surface in the first direction is outside the first surface.

[0010] Optionally, the first etched surface is a non-flat surface.

[0011] Optionally, the first etched surface is a curved surface.

[0012] Optionally, the first etched surface has a first end and a second end opposite to each other, the first end being in contact with the third surface, and the vertical distance between the first end and the second surface being greater than the vertical distance between the second end and the second surface.

[0013] Optionally, the orbital layer has a fourth surface opposite to the first surface, and the maximum vertical distance between the first etched surface and the fourth surface is greater than 2 nm.

[0014] Optionally, the spin orbital moment storage unit further includes: an output portion, located one-to-one with the electrode portion on the side opposite to the orbital layer; and a first insulating layer, located at least in the spacing region between the electrode portions and surrounding the outer periphery of the output portion.

[0015] Optionally, the first insulating layer has a second etched surface that contacts the first etched surface and the second surface respectively. The second etched surface has a third end and a fourth end opposite to each other. The third end contacts the first etched surface, and the vertical distance between the third end and the first surface is less than the vertical distance between the fourth end and the first surface.

[0016] Optionally, the orbital layer has a fourth surface opposite to the first surface, and the maximum vertical distance between the second over-etched surface and the fourth surface is less than 100 nm.

[0017] Optionally, the spin orbital moment storage cell further includes a bottom metal, which is located on the side of the lead-out portion away from the electrode portion. The first insulating layer also surrounds the outer periphery of the bottom metal. The side of the magnetic tunnel junction near the first surface has a fifth surface. Each bottom metal has a first orthographic projection falling into the fifth surface in a first direction. The proportion of the first orthographic projection in the fifth surface is greater than or equal to 60%.

[0018] Optionally, the track layer has a fourth surface opposite to the first surface, and the line connecting any point on the edge of the first surface and any point on the edge of the fourth surface with the shortest distance is a first connecting line, and the angle between the first connecting line and the first surface is 45° to 85°.

[0019] According to one aspect of this application, a method for fabricating a spin-orbit moment storage cell is provided, comprising the following steps: providing a substrate having a bottom electrode, the bottom electrode including two spaced-apart electrode portions, one side surface of the electrode portions being exposed; forming an orbital layer and a magnetic tunnel junction on the substrate, the magnetic tunnel junction having a first outer peripheral surface, the orbital layer being located between the magnetic tunnel junction and the substrate, the orbital layer having a second outer peripheral surface coplanar with the first outer peripheral surface, and the side surface of the orbital layer facing away from the magnetic tunnel junction being a first surface, the orthogonal projection portion of each electrode portion falling into the first surface in a first direction, the first direction being the direction in which the orbital layer points towards the magnetic tunnel junction.

[0020] Optionally, the substrate further includes a lead-out portion and a first insulating layer, the first insulating layer being located in the spacer region between the electrode portions and surrounding the outer periphery of the lead-out portion. The step of forming the orbital layer and the magnetic tunnel junction includes: sequentially depositing an orbital layer material, a magnetic tunnel junction material, and a mask material on the substrate to form a sequentially stacked orbital material layer, a magnetic tunnel junction material layer, and a mask material layer; patterning the mask material layer to obtain a mask layer, so that the magnetic tunnel junction material layer has an exposed surface; forming a first protective layer covering the mask layer and the exposed surface; and etching the orbital material layer and the magnetic tunnel junction material layer through the mask layer and the first protective layer to form the orbital layer and the magnetic tunnel junction.

[0021] Optionally, the thickness of the first protective layer is 5–100 nm.

[0022] Optionally, the step of etching the orbital material layer and the magnetic tunnel junction material layer includes: performing preliminary etching on the orbital material layer and the magnetic tunnel junction material layer to form a first intermediate layer and a second intermediate layer; performing over-etching on the first intermediate layer, the second intermediate layer and the electrode portion to form the orbital layer from the first intermediate layer and the magnetic tunnel junction from the second intermediate layer, wherein the surface of the electrode portion facing away from the orbital layer after over-etching is a second surface, and the electrode portion also has a third surface and a first over-etched surface respectively opposite to the second surface, wherein the third surface and the first over-etched surface are not coplanar, and the orthogonal projection of the third surface in the first direction at least partially falls into the first surface, and the orthogonal projection of the first over-etched surface in the first direction is outside the first surface.

[0023] Optionally, during the over-etching process, the electrode portion and the first insulating layer are etched simultaneously, so that the electrode portion and the first insulating layer respectively form a smooth transition between the first over-etched surface and the second over-etched surface.

[0024] Optionally, the depth of the over-etching is 2 to 100 nm.

[0025] Optionally, after forming the orbital layer and the magnetic tunnel junction, the fabrication method further includes: depositing a second protective layer on the substrate to cover the outer periphery of the mask layer, the first outer peripheral surface, the second outer peripheral surface, and the first over-etched surface; and forming a second insulating layer covering the second protective layer.

[0026] According to one aspect of this application, a magnetic random access memory is provided, comprising a plurality of spin-orbit moment storage cells, wherein at least one of the spin-orbit moment storage cells is a spin-orbit moment storage cell, or at least one of the spin-orbit moment storage cells is prepared by the method for preparing the spin-orbit moment storage cell.

[0027] This application provides a spin-orbit-time memory cell, wherein the surface of the orbital layer facing away from the magnetic tunnel junction is a first surface, and the orthogonal projection of the bottom electrode in the direction of the orbital layer pointing towards the magnetic tunnel junction is located in the first surface. The magnetic tunnel junction and the orbital layer have a coplanar outer periphery. Since the aforementioned coplanar magnetic tunnel junction and the orbital layer are formed through the same etching step, it is not necessary to stop at the orbital layer during the etching of the magnetic tunnel junction. This not only allows for the simultaneous definition of the dimensions of the orbital layer and the magnetic tunnel junction, avoiding alignment deviations in the etching process, but also allows for over-etching of the magnetic tunnel junction, increasing the etching window and reducing photolithographic alignment deviations in the etching step. This avoids the low etching yield and uniformity caused by the need for precise stopping at the orbital layer during the etching of the magnetic tunnel junction in the prior art, which results in an excessively small etching window. Furthermore, since the magnetic tunnel junction in the spin-orbit-time memory cell has a coplanar outer periphery with the orbital layer, the width and length of the orbital layers on both sides of the magnetic tunnel junction can be reduced, making the dimensions of the magnetic tunnel junction and the orbital layer similar, avoiding the impact of large size differences on device write efficiency and write current. Therefore, using the aforementioned spin orbital moment storage cell can not only improve etching yield, thereby improving device yield and uniformity, but also improve device write efficiency and reduce write current. Attached Figure Description

[0028] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1 This is a cross-sectional structural schematic diagram of a spin orbital moment storage cell provided according to an embodiment of this application;

[0030] Figure 2 yes Figure 1 The diagram shows a top view of the spin orbital moment storage cell.

[0031] Figure 3 This is a schematic cross-sectional view of the substrate provided in a method for fabricating a spin orbital moment storage cell according to an embodiment of this application.

[0032] Figure 4 Is Figure 3 A schematic cross-sectional view of the structure after the bottom electrode is formed on the substrate is shown.

[0033] Figure 5 Is Figure 4 The diagram shows a cross-sectional structure of the structure after the track layer, tunnel junction material layer and mask material layer are formed on the substrate;

[0034] Figure 6 It is Figure 5 The diagram shows a cross-sectional structure of the structure after the mask material layer forms a mask layer and a second protective layer;

[0035] Figure 7 It is Figure 6 The diagram shows a cross-sectional structure of the magnetic tunnel junction after the material layer of the magnetic tunnel junction has been etched to form a magnetic tunnel junction.

[0036] Figure 8 It is Figure 7 A schematic cross-sectional view of the magnetic tunnel junction after sidewall modification is shown.

[0037] Figure 9 It is to form a cover Figure 8 A schematic cross-sectional view of the structure behind the first protective layer on both sides of the magnetic tunnel junction is shown.

[0038] Figure 10 exist Figure 9 The diagram shows a cross-sectional structure of the structure after the top electrode is formed on the mask layer.

[0039] The above figures include the following reference numerals:

[0040] 10. Bottom metal; 20. Lead-out section; 30. Bottom electrode; 31. Electrode section; 40. Track layer; 41. Track material layer; 50. Magnetic tunnel junction; 51. Magnetic tunnel junction material layer; 501. First material; 510. Reference layer; 502. Second material; 520. Barrier layer; 503. Third material; 530. Free layer; 60. Mask layer; 61. Mask material layer; 70. Top electrode; 80. Insulating dielectric layer; 810. First insulating layer; 820. Second insulating layer; 90. First protective layer; 100. Second protective layer; 110. Top interconnect metal. Detailed Implementation

[0041] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0044] As described in the background section, existing SOT-MRAM requires precise stopping at the SOT orbital layer during MTJ etching, resulting in an excessively small etching window. Furthermore, during the miniaturization of SOT-MTJ devices, photolithographic alignment errors are prone to occur, leading to poor yield and uniformity issues in large-scale manufacturing. To address these technical problems, this application provides a spin-orbit moment memory cell, its fabrication method, and a magnetic random access memory.

[0045] According to an embodiment of this application, a spin orbital moment storage cell is provided. Figure 1 and Figure 2 This is a schematic diagram of the structure of the spin-orbit moment storage unit provided in the embodiments of this application. For example... Figure 1 and Figure 2 As shown, the spin-orbit moment storage cell includes: a magnetic tunnel junction 50 having a first outer peripheral surface; an orbital layer 40 located on one side of the magnetic tunnel junction 50, the orbital layer 40 having a second outer peripheral surface coplanar with the first outer peripheral surface, and the side surface of the orbital layer 40 facing away from the magnetic tunnel junction 50 being the first surface; and a bottom electrode 30 including two spaced electrode portions 31, each electrode portion 31 having its orthographic projection portion in a first direction falling into the first surface, the first direction being the direction from the orbital layer 40 to the magnetic tunnel junction 50.

[0046] In the above embodiments of this application, since the coplanar magnetic tunnel junction 50 and the orbital layer 40 are formed through the same etching step, it is not necessary to stop at the orbital layer 40 when etching the magnetic tunnel junction 50. This not only allows the dimensions of the orbital layer 40 and the magnetic tunnel junction 50 to be defined simultaneously, avoiding the alignment deviation problem in the etching process, but also allows the magnetic tunnel junction 50 to be over-etched, increasing the etching window. This avoids the low device yield and poor uniformity caused by the need to precisely stop at the orbital layer 40 when etching the magnetic tunnel junction 50, which is a problem in the prior art.

[0047] Furthermore, since the magnetic tunnel junction 50 in the spin-orbit-momentum memory cell is coplanar with the outer periphery of the orbital layer 40, the width and length of the orbital layers 40 on both sides of the magnetic tunnel junction 50 can be reduced, making the dimensions of the magnetic tunnel junction 50 and the orbital layer 40 similar. This avoids the impact of large size differences on device write efficiency and write current. Therefore, using the above-mentioned spin-orbit-momentum memory cell can not only improve etching yield but also improve device write efficiency and reduce write current.

[0048] In the spin-orbit moment (SOT) memory cell described in this embodiment, the magnetic tunnel junction 50 is a multilayer structure. The magnetic tunnel junction 50 can take various forms depending on the application, including but not limited to in-plane MTJs, vertical MTJs, top-pinned MTJs, double-layer MgO MTJs, single-layer MgO MTJs, and polymorphic MTJs. For example, as... Figure 1 and Figure 2 As shown, the magnetic tunnel junction 50 in the embodiments of this application includes a free layer 530, a barrier layer 520, and a reference layer 510.

[0049] For example, the magnetic tunnel junction 50 described above adopts a vertically magnetized vertical MTJ, and the horizontal cross-sectional shape of the magnetic tunnel junction 50 is independently selected from one or more of the shapes of circles, ellipses and rectangles, preferably circles.

[0050] In another example, the magnetic tunnel junction 50 described above adopts an in-plane magnetized in-plane MTJ, and the horizontal cross-sectional shape of the magnetic tunnel junction 50 is independently selected from ellipse or rectangle, preferably ellipse.

[0051] Specifically, the materials of the free layer 530 and the reference layer 510 can be ferromagnetic materials, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum, etc., while the barrier layer 520 is a very thin insulating layer, and the insulating material of the barrier layer can include magnesium oxide, aluminum oxide, silicon oxide, etc. Those skilled in the art can reasonably select the types of materials for the free layer 530, the barrier layer 520, and the reference layer 510 according to actual needs, and the embodiments of this application do not make specific limitations.

[0052] In the above-described SOT storage unit of the embodiments of this application, such as Figure 1 and Figure 2 As shown, the magnetic tunnel junction 50 and the orbital layer 40 have a bottom electrode 30 and a top electrode 70 on their respective sides. The bottom electrode 30 is located on the side of the orbital layer 40 away from the magnetic tunnel junction 50, and the top electrode 70 is located on the side of the magnetic tunnel junction 50 located on the orbital layer 40. The bottom electrode 30 includes two spaced electrode portions 31, and the orthographic projection of each electrode portion 31 in the first direction falls into the first surface of the orbital layer 40.

[0053] The material of the aforementioned track layer 40 can be a heavy metal material, such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium, or a combination of these alloys. The electrode materials of the aforementioned bottom electrode 30 and the aforementioned top electrode 70 can be independently selected from any one or more alloys of silver, copper, aluminum, gold, titanium, platinum, palladium, tantalum, tantalum nitride, titanium nitride, cobalt, iron, nickel, and cobalt iron, but are not limited to the aforementioned types. The embodiments of this application do not impose specific limitations.

[0054] In some alternative embodiments, the side surface of each electrode portion 31 in the bottom electrode 30 facing away from the track layer 40 is a second surface. The electrode portion 31 also has a third surface and a first over-etched surface opposite to the second surface, respectively. The third surface and the first over-etched surface are not coplanar. The orthographic projection of the third surface in the first direction at least partially falls into the first surface, and the orthographic projection of the first over-etched surface in the first direction is outside the first surface.

[0055] Specifically, a portion of the surface of the electrode portion 31 is covered by the orbital layer 40. The magnetic tunnel junction 50 and the orbital layer 40 have a coplanar outer periphery. Thus, in the fabrication process of the magnetic tunnel junction 50 and the orbital layer 40, the magnetic tunnel junction 50 and the orbital layer 40 can be formed by the same etching process. The magnetic tunnel junction 50 can also be over-etched to increase the etching window. Since the bottom electrode 30 is formed before the magnetic tunnel junction 50 and the orbital layer 40, the portion of the electrode portion 31 not covered by the orbital layer 40 is also etched while the magnetic tunnel junction 50 is over-etched. This results in the formation of an over-etched surface on the upper surface of the electrode portion 31, namely the first over-etched surface. The area on the upper surface of the electrode portion 31 covered by the orbital layer 40 constitutes the third surface. At this time, the thickness of the area of ​​the electrode portion 31 with the first over-etched surface gradually decreases in the direction away from the orbital layer, resulting in the first over-etched surface and the third surface not being coplanar. Therefore, the first over-etched surface of the electrode portion 31 indicates that the magnetic tunnel junction 50 is over-etched during the fabrication process of the magnetic tunnel junction 50, thereby having a larger etching window and increasing the etching yield.

[0056] In the above-described optional embodiments, the first over-etched surface of the electrode portion 31 can be a non-flat surface. The degree of non-flatness of the aforementioned non-flat surface can also reflect the degree of over-etching of the magnetic tunnel junction 50. By making the electrode portion 31 have a non-flat over-etched surface, the etching window of the magnetic tunnel junction 50 can be ensured to be sufficiently large, thereby more effectively reducing the etching yield. Furthermore, the aforementioned first over-etched surface can be a curved surface. By making the over-etched surface of the electrode portion 31 a relatively smooth curved surface, the etching process in the over-etching step of the magnetic tunnel junction 50 can be made to have excellent stability.

[0057] In the above optional embodiments, the first over-etched surface of the electrode portion 31 may have a first end and a second end opposite to each other, the first end being in contact with the third surface, and the vertical distance between the first end and the second surface being greater than the vertical distance between the second end and the second surface.

[0058] Specifically, such as Figure 1 As shown, since part of the upper surface of the electrode portion 31 is covered by the orbital layer 40, and the bottom electrode 30 is formed before the magnetic tunnel junction 50 and the orbital layer 40, during the fabrication process of the magnetic tunnel junction 50 and the orbital layer 40, while the magnetic tunnel junction 50 is being over-etched, the portion of the electrode portion 31 not covered by the orbital layer 40 is also etched to form an over-etched surface, namely the first over-etched surface. This causes the thickness of the region in the electrode portion 31 corresponding to the first over-etched surface to gradually decrease along the direction away from the magnetic tunnel junction 50, making the vertical distance between the first end of the first over-etched surface and the lower surface of the electrode portion 31 greater than the vertical distance between the second end and the second surface.

[0059] In some alternative embodiments, the orbital layer 40 has a fourth surface opposite to its first surface, and the maximum vertical distance between the first over-etched surface of the electrode portion 31 and the fourth surface is greater than 2 nm.

[0060] In the above optional embodiments, the maximum vertical distance between the first over-etched surface of the electrode portion 31 and the lower surface of the orbital layer 40 (i.e., the fourth surface) can be used to characterize the over-etching depth of the magnetic tunnel junction 50. By setting the maximum vertical distance between the first over-etched surface of the electrode portion 31 and the fourth surface to meet the above range, the magnetic tunnel junction 50 can have a sufficient over-etching depth, thereby ensuring a large etching window and effectively reducing etching yield. Further optionally, the maximum vertical distance between the first over-etched surface of the electrode portion 31 and the fourth surface is greater than 5 nm.

[0061] like Figure 1 and Figure 2 As shown, the SOT memory cell described in this application embodiment may further include lead-out portions 20 and a first insulating layer 810. The lead-out portions 20 are located on the side of the electrode portions 31 away from the track layer 40, and the insulating dielectric layer 80 is located in the interval region between the electrode portions 31 and surrounds the outer periphery of the lead-out portions 20.

[0062] Specifically, the lead-out portion 20 is connected one-to-one with the electrode portion 31 in the bottom electrode 30 to lead out the electrode. The conductive material of the lead-out portion 20 may include a low resistivity metal, such as one or more of iron, cobalt, tungsten, tantalum, tantalum nitride and titanium copper nitride. The first insulating layer 810 may be silicon dioxide. This application embodiment does not make specific limitations.

[0063] In some alternative implementations, such as Figure 1 As shown, the first insulating layer 810 has a second etched surface that is in contact with the first etched surface and the second surface respectively. The second etched surface has a third end and a fourth end opposite to each other. The third end is in contact with the first etched surface, and the vertical distance between the third end and the first surface is less than the vertical distance between the fourth end and the first surface.

[0064] Specifically, such as Figure 1As shown, a portion of the surface of the electrode portion 31 is covered by the orbital layer 40. The magnetic tunnel junction 50 and the orbital layer 40 have a coplanar outer periphery. Therefore, in the fabrication process of the magnetic tunnel junction 50 and the orbital layer 40, the magnetic tunnel junction 50 and the orbital layer 40 can be formed by the same etching process. Furthermore, the magnetic tunnel junction 50 can be over-etched to increase the etching window. Since the bottom electrode 30 and the first insulating layer 810 are formed before the magnetic tunnel junction 50 and the orbital layer 40, the portion of the electrode portion 31 not covered by the orbital layer 40 will also be etched during the over-etching of the magnetic tunnel junction 50, resulting in the electrode portion 31... An etched surface, namely the first etched surface, is formed on the upper surface of the magnetic tunnel junction 50. The thickness of the portion of the electrode portion 31 with the first etched surface gradually decreases in the direction away from the orbital layer. At this time, by further increasing the depth of over-etching the magnetic tunnel junction 50, a portion of the first insulating layer 810 near the electrode portion 31 is also etched, resulting in an etched surface, namely the second etched surface, forming on the upper surface of the first insulating layer 810. The thickness of the region of the electrode portion 31 with the first etched surface and the region of the first insulating layer 810 with the second etched surface gradually decreases in the direction away from the orbital layer, causing the first and second etched surfaces to be coplanar. Therefore, the first and second etched surfaces indicate that the magnetic tunnel junction 50 has sufficient over-etching depth in the fabrication process, thereby increasing the etching yield by further increasing the etching window.

[0065] In the above optional embodiments, the orbital layer 40 has a fourth surface opposite to its first surface, and the maximum vertical distance between the second over-etched surface and the fourth surface is less than 100 nm.

[0066] In the above optional embodiments, the maximum vertical distance between the second over-etched surface of the first insulating layer 810 and the lower surface of the orbital layer 40 (i.e., the fourth surface) can also be used to characterize the over-etching depth of the magnetic tunnel junction 50. By setting the maximum vertical distance between the second over-etched surface of the first insulating layer 810 and the fourth surface to meet the above range, the magnetic tunnel junction 50 can have sufficient over-etching depth, thereby ensuring a larger etching window and effectively reducing etching yield. Further optionally, the maximum vertical distance between the second over-etched surface of the first insulating layer 810 and the fourth surface is greater than 50 nm.

[0067] Specifically, in the embodiments of this application, by setting different over-etching depths, the structure after over-etching can have the following characteristics: an over-etched surface (i.e., the first over-etched surface) is formed on the upper surface of the electrode portion 31 through over-etching, and an over-etched surface (i.e., the second over-etched surface) is also formed on the upper surface of the first insulating layer 810.

[0068] like Figure 1 As shown, the SOT memory cell in this embodiment further includes a bottom metal 10, and the bottom metal 10 is located on the side of the lead-out portion 20 opposite to the electrode portion 31. The bottom metal 10 is electrically connected to the bottom electrode 30 through the lead-out portion 20. At this time, the first insulating layer 810 surrounds and wraps around the bottom metal 10 and the outer periphery of the lead-out portion 20. The horizontal cross-sectional shape of the bottom metal 10 can be trapezoidal or irregular polygonal. The bottom metal 10 can be copper, but this embodiment does not specifically limit its use.

[0069] In some alternative implementations, the magnetic tunnel junction 50 has a fifth surface on the side near the first surface of the orbital layer 40, and each bottom metal 10 has a first orthographic projection falling into the fifth surface in a first direction, the first orthographic projection accounting for more than or equal to 60% of the fifth surface.

[0070] Specifically, by setting the overlap area ratio between the bottom metal 10 and the magnetic tunnel junction 50 to meet the above-mentioned range, it can be ensured that the critical switching current of the magnetic tunnel junction 50 does not change with the overlap area of ​​the bottom metal 10 and the magnetic tunnel junction 50. Therefore, even if the magnetic tunnel junction 50 is over-etched, it will not affect the critical switching current of the magnetic tunnel junction 50. Furthermore, by increasing the process window, a larger alignment deviation can be allowed, thereby increasing the etching yield.

[0071] In some alternative implementations, such as Figure 2 As shown, in the direction parallel to the first surface of the orbital layer 40, any cross-section of the orbital layer 40 is a symmetrical figure with a first axis of symmetry. The two bottom electrodes 30 are mirror-symmetrical about the first plane of symmetry, and the first axis of symmetry is located in the first plane of symmetry. By giving the orbital layer 40 and the bottom electrodes 30 the above-described structure, it is beneficial to fabricate the spin orbital moment memory cell. In the fabrication process of the spin orbital moment memory cell, the etching difficulty of the orbital layer 40 and the bottom electrodes 30 can be reduced, thereby improving the etching yield and thus improving the device yield and uniformity.

[0072] In some alternative embodiments, the track layer 40 has a fourth surface opposite to its first surface, and the line connecting any point on the edge of the first surface and any point on the edge of the fourth surface with the shortest distance is a first connecting line, and the angle between the first connecting line and the first surface is 45° to 85°.

[0073] Specifically, the angle between the first connecting line and the first surface of the orbital layer 40 can be used to characterize the sidewall tilt of the orbital layer 40. In the fabrication process of the magnetic tunnel junction 50 and the orbital layer 40, the etching is usually performed from top to bottom, that is, the magnetic tunnel junction 50 and the orbital layer 40 are etched sequentially. This results in the orbital layer 40 having a larger interface size than the magnetic tunnel junction 50. Furthermore, by forming the magnetic tunnel junction 50 and the orbital layer 40 in the same etching process, the magnetic tunnel junction 50 and the orbital layer 40 can have approximately the same sidewall tilt. That is, the sidewall tilt of both can be characterized as the angle between the first connecting line and the first surface of the orbital layer 40 being in the range of 45° to 85°.

[0074] In the above-described SOT storage unit of the embodiments of this application, such as Figure 1 As shown, a mask layer 60 may also be provided on the magnetic tunnel junction 50 so that the top electrode 70 is located on the side of the mask layer 60 away from the magnetic tunnel junction 50. Then, a top interconnect metal 110 may be further provided on the top electrode 70 so that the top electrode 70 can be led out through the top interconnect metal 110.

[0075] Specifically, in the fabrication process of the magnetic tunnel junction 50 and the orbital layer 40, a stacked orbital layer 40 material layer and a magnetic tunnel junction material layer can be formed first. Then, a mask layer 60 is set on the magnetic tunnel junction material layer. In the same etching process, the underlying orbital layer 40 material layer and the magnetic tunnel junction material layer are sequentially etched through the mask layer 60 to obtain the magnetic tunnel junction 50 and the orbital layer 40. Then, a top electrode 70 is set on the mask layer 60.

[0076] The materials of the mask layer 60 and the top interconnect metal 110 can be reasonably selected according to the prior art. For example, the mask layer 60 can be a tantalum nitride layer and the top interconnect metal 110 can be a tungsten metal layer. The embodiments of this application do not make specific limitations.

[0077] In the above-described SOT storage unit of this application embodiment, such as Figure 1 As shown, a second protective layer 100 may also be covered on the outer periphery of the mask layer 60, the first outer peripheral surface of the magnetic tunnel junction 50, the second outer peripheral surface of the orbital layer 40, and the first over-etched surface of the electrode portion 31. In the fabrication process of the SOT memory cell, after the formation of the second protective layer 100, a second insulating layer 820 is formed covering the second protective layer 100. The second insulating layer 820 and the first insulating layer 810 constitute an insulating dielectric layer 80.

[0078] Specifically, after etching to form the magnetic tunnel junction 50 and the orbital layer 40, a protective layer material, such as silicon nitride, is deposited to form a second protective layer 100 covering the first outer peripheral surface of the magnetic tunnel junction 50, the second outer peripheral surface of the orbital layer 40, and the first etched surface of the electrode portion 31. Figure 1 As shown, an insulating material is deposited on the substrate to encapsulate the second protective layer 100. The insulating material and the second protective layer 100 are then sequentially planarized until the top surface of the mask layer 60 is exposed. For example, chemical mechanical polishing (CMP) is used for this planarization process.

[0079] The second insulating layer 820 and the first insulating layer 810 may have the same insulating material or different insulating materials. For example, both the first insulating layer 810 and the second insulating layer 820 may include silicon dioxide. The second protective layer 100 may be formed using a material with high hardness, such as silicon nitride. This application does not specifically limit the application to this material.

[0080] According to an embodiment of this application, a method for fabricating a spin-orbit moment storage cell is also provided, comprising the following steps:

[0081] S1, a substrate is provided, the substrate having a bottom electrode, the bottom electrode including two spaced-apart electrode portions, one side surface of the electrode portions being exposed;

[0082] S2, an orbital layer and a magnetic tunnel junction are formed on the substrate. The magnetic tunnel junction has a first outer peripheral surface. The orbital layer is located between the magnetic tunnel junction and the substrate. The orbital layer has a second outer peripheral surface that is coplanar with the first outer peripheral surface. The side of the orbital layer that is away from the magnetic tunnel junction is the first surface. The orthogonal projection of each electrode portion in a first direction falls into the first surface. The first direction is the direction in which the orbital layer points to the magnetic tunnel junction.

[0083] In the above embodiments of this application, since the coplanar magnetic tunnel junction and the orbital layer are formed through the same etching step, it is not necessary to stop at the orbital layer when etching the magnetic tunnel junction. This not only allows the dimensions of the orbital layer and the magnetic tunnel junction to be defined simultaneously, avoiding the alignment deviation problem in the etching process, but also allows the magnetic tunnel junction to be over-etched, increasing the etching window and reducing the photolithographic alignment deviation in the etching step. This avoids the impact of low etching yield on device yield and uniformity caused by the need to precisely stop at the orbital layer during the etching of the magnetic tunnel junction in the prior art, which results in an excessively small etching window.

[0084] The following will be combined with the appendix Figures 1 to 10Exemplary embodiments of the method for fabricating a spin-orbit moment storage cell according to the present invention are described in more detail below. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0085] First, proceed to step S1, as follows: Figure 3 and Figure 4 As shown, a substrate is provided, the substrate having a bottom electrode 30, the bottom electrode 30 including two spaced electrode portions 31, one side surface of the electrode portions 31 being exposed.

[0086] In some optional embodiments, the preparation method in this application further includes the step of forming the above-mentioned substrate, including: forming two spaced-apart bottom metals 10 on a substrate (not shown in the figure); depositing an insulating material on the substrate to form a first insulating layer 810 covering the bottom metals 10; etching the first insulating layer 810 to form a bottom through-hole extending to the bottom metals 10; filling the bottom through-hole with a conductive material to form a lead-out portion 20 extending to the bottom metals 10, such as... Figure 3 As shown; insulating material is deposited again on the first insulating layer 810 and the lead-out portion 20, and etched to form a groove, the lead-out portion 20 being exposed through the bottom of the groove. Then, electrode material is deposited in the groove to form the aforementioned bottom electrode 30, as shown. Figure 4 As shown.

[0087] The deposition processes for the aforementioned lead-out portion 20, the first insulating layer 810, and the bottom electrode 30 can be reasonably selected according to actual needs, such as chemical vapor deposition. The substrate material can include any one or more of silicon, silicon carbide, gallium nitride, and aluminum nitride. The conductive material forming the lead-out portion 20 can include any one or more of copper, tungsten, aluminum, tantalum, tantalum nitride, and titanium nitride. The first insulating layer 810 can be silicon dioxide. The electrode material forming the bottom electrode 30 can be independently selected from alloys composed of any one or more of silver, copper, aluminum, gold, titanium, platinum, palladium, tantalum, tantalum nitride, titanium nitride, cobalt, iron, nickel, and cobalt iron. This application embodiment does not specifically limit the specific materials used.

[0088] After providing the substrate with the bottom electrode, step S2 is performed, as follows: Figures 5 to 8As shown, an orbital layer 40 and a magnetic tunnel junction 50 are formed on a substrate. The magnetic tunnel junction 50 has a first outer peripheral surface. The orbital layer 40 is located between the magnetic tunnel junction 50 and the substrate. The orbital layer 40 has a second outer peripheral surface that is coplanar with the first outer peripheral surface. The side of the orbital layer 40 that is away from the magnetic tunnel junction 50 is the first surface. The orthographic projection of each electrode portion 31 in a first direction falls into the first surface. The first direction is the direction in which the orbital layer 40 points towards the magnetic tunnel junction 50.

[0089] Specifically, the orbital layer 40 and the magnetic tunnel junction 50 are formed in the same etching process, which allows the dimensions of the orbital layer and the magnetic tunnel junction to be defined simultaneously, avoiding alignment deviations in the etching process of the orbital layer. In order to increase the etching yield, the magnetic tunnel junction can also be over-etched to increase the etching window. The over-etching will cause an over-etched surface to be formed on the upper surface of the electrode portion 31, namely the first over-etched surface. The area on the upper surface of the electrode portion 31 covered by the orbital layer 40 constitutes the third surface. At this time, the thickness of the area of ​​the electrode portion 31 with the first over-etched surface gradually decreases in the direction away from the orbital layer 40, resulting in the first over-etched surface and the third surface being non-coplanar.

[0090] In some alternative embodiments, the steps of forming the orbital layer 40 and the magnetic tunnel junction 50 include: sequentially depositing orbital layer material, magnetic tunnel junction material, and masking material on a substrate having a bottom electrode 30 to form a sequentially stacked orbital material layer 41, magnetic tunnel junction material layer 51, and masking material layer 61, such as... Figure 5 As shown; the mask material layer 61 is patterned to obtain the mask layer 60, so that the magnetic tunnel junction material layer 51 has an exposed surface; a first protective layer 90 is formed covering the mask layer 60 and the exposed surface, as shown. Figure 6 As shown; the orbital material layer 41 and the magnetic tunnel junction material layer 51 are etched through the mask layer 60 and the first protective layer 90 to form the orbital layer 40 and the magnetic tunnel junction 50, as shown. Figure 7 As shown.

[0091] Specifically, after forming the mask layer 60, a first protective layer 90 is formed covering the exposed surfaces of the mask layer 60 and the magnetic tunnel junction material layer 51, thereby partially covering the sidewall of the magnetic tunnel junction material layer 51 with the second protective layer 100. Compared to the tilt of the sidewall of the magnetic tunnel junction material layer 51, the surface of the first protective layer 90 located on the sidewall of the magnetic tunnel junction material layer 51 can have a greater tilt, thereby reducing the impact of backsplashing of the orbital layer material and the magnetic tunnel junction material on the magnetic tunnel junction 50 during the subsequent etching process to form the orbital layer 40 and the magnetic tunnel junction 50.

[0092] In the above optional embodiments, the orbital layer material can be a heavy metal material, such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium or a combination of these alloys, the mask material can be silicon nitride, and the second protective layer 100 can be formed of a material with high hardness, such as silicon nitride. The embodiments of this application do not make specific limitations.

[0093] In some optional embodiments, the thickness of the first protective layer 90 is 5–100 nm. By forming a first protective layer 90 with the above-mentioned thickness, it is possible to ensure that the surface of the second protective layer 100 located on the sidewall of the magnetic tunnel junction material layer 51 can have a greater tilt, thereby more effectively reducing the impact of orbital layer material and magnetic tunnel junction material backsplashing on the magnetic tunnel junction 50. Further optionally, the thickness of the first protective layer is 25–50 nm.

[0094] For example, the steps of forming the above-mentioned magnetic tunnel junction include: sequentially depositing a first material 501, a second material 502, and a third material 503, such as... Figure 5 As shown, the first material 501 and the third material 503 are ferromagnetic materials used to form the reference layer 510 and the free layer 530, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum, cobalt iron, cobalt iron boron, etc. The second material 502 is an insulating material used to form the barrier layer 520, such as magnesium oxide, aluminum oxide, silicon oxide, etc. After patterning the mask material layer 61 to obtain the mask layer 60, the magnetic tunnel junction material layer 51 and the orbital material layer 41 are etched through the mask layer 60 to form a magnetic tunnel junction 50 located on the orbital layer 40. The magnetic tunnel junction 50 includes a free layer 530, a barrier layer 520 and a reference layer 510 stacked together, such as... Figure 7 As shown.

[0095] It should be noted that the magnetic tunnel junctions prepared in the embodiments of this application are not limited to the above-described structures. The magnetic tunnel junctions can take many forms depending on the application, including but not limited to in-plane MTJs, vertical MTJs, top-pinned MTJs, bottom-pinned MTJs, double-layer MgO MTJs, single-layer MgO MTJs, and polymorphic MTJs.

[0096] In some optional embodiments, the step of etching the orbital material layer 41 and the magnetic tunnel junction material layer 51 includes: performing preliminary etching on the orbital material layer 41 and the magnetic tunnel junction material layer 51 to form a first intermediate layer and a second intermediate layer, and performing over-etching on the first intermediate layer, the second intermediate layer, and the electrode portion 31 to form the first intermediate layer into the orbital layer 40 and the second intermediate layer into the magnetic tunnel junction 50, such as... Figure 7As shown, the side surface of the electrode portion 31 facing away from the track layer 40 after etching is the second surface. The electrode portion 31 also has a third surface and a first over-etched surface that are respectively opposite to the second surface. The third surface and the first over-etched surface are not coplanar. The orthographic projection of the third surface in the first direction falls at least partially into the first surface. The orthographic projection of the first over-etched surface in the first direction is outside the first surface.

[0097] In the above optional embodiments, the track material layer 41 and the magnetic tunnel junction material layer 51 can be etched first, such as... Figure 7 As shown, the sidewalls of the formed track material layer 41 and magnetic tunnel structure material layer 51 are then modified, such as... Figure 8 As shown. During the etching process to form the orbital material layer 41 and the magnetic tunnel junction material layer 51, the orbital layer material and the magnetic tunnel junction material may sputter, resulting in impurities remaining on the sidewalls of the orbital material layer 41 and the magnetic tunnel junction material layer 51. Therefore, by etching the first and second intermediate layers obtained by etching again, the sidewalls of the orbital layer 40 and the magnetic tunnel junction 50 can be modified, effectively removing the impurities remaining on the sidewalls of the orbital material layer 41 and the magnetic tunnel junction material layer 51, thus avoiding the impact of impurity residue on device performance.

[0098] Specifically, the sidewall modification can be performed using an etching gas containing at least one of oxygen, nitrogen, and argon. Furthermore, the sidewall modification can be performed using a smaller etching power and a smaller etching angle. The embodiments of this application do not specifically limit the process conditions such as etching power and etching angle in the sidewall modification.

[0099] In the above optional embodiments, during the etching process of forming the track layer 40 and the magnetic tunnel junction 50, the electrode portion 31 and the first insulating layer 810 can also be etched simultaneously, so that the electrode portion 31 and the first insulating layer 810 respectively form a smooth transition first over-etched surface and a second over-etched surface. The second over-etched surface has a third end and a fourth end opposite to each other. The third end is in contact with the first over-etched surface, and the vertical distance between the third end and the first surface is less than the vertical distance between the fourth end and the first surface.

[0100] Specifically, such as Figure 7As shown, in the steps of etching to form the magnetic tunnel junction 50 and the orbital layer 40, the magnetic tunnel junction 50 and the orbital layer 40 are formed by the same etching process. In order to increase the etching yield, the magnetic tunnel junction 50 can be over-etched to increase the etching window. Since the bottom electrode 30 and the first insulating layer 810 are formed before the magnetic tunnel junction 50 and the orbital layer 40, the portion of the electrode portion 31 not covered by the orbital layer 40 will also be etched while the magnetic tunnel junction 50 is over-etched. This will result in an over-etched surface being formed on the upper surface of the electrode portion 31, i.e., the aforementioned first... Over-etched surfaces: The thickness of the portion of electrode 31 with the first over-etched surface gradually decreases in the direction away from the orbital layer. At this time, by further increasing the depth of over-etching the magnetic tunnel junction 50, a portion of the first insulating layer 810 near the electrode 31 is also etched, resulting in the formation of an over-etched surface, i.e., the aforementioned second over-etched surface, on the upper surface of the first insulating layer 810. The thickness of the region of electrode 31 with the first over-etched surface and the region of the first insulating layer 810 with the second over-etched surface gradually decreases in the direction away from the orbital layer 40, resulting in the first over-etched surface and the second over-etched surface being coplanar.

[0101] In some optional embodiments, the over-etching depth of the magnetic tunnel junction 50 is 2–100 nm. By setting the over-etching depth to meet the above range, a larger etching window can be ensured, effectively reducing etching yield. More optionally, the over-etching depth of the magnetic tunnel junction 50 is 5–50 nm.

[0102] In some alternative embodiments, after the steps of forming the orbital layer 40 and the magnetic tunnel junction 50, such as Figure 9 As shown, the preparation method provided in this application embodiment further includes: depositing a second protective layer 100 on a substrate so that the second protective layer 100 covers the outer periphery of the mask layer 60, the first outer peripheral surface of the magnetic tunnel junction 50, the second outer peripheral surface of the orbital layer 40, and the first over-etched surface of the electrode portion 31; forming a second insulating layer 820 covering the second protective layer 100, wherein the second insulating layer 820 and the first insulating layer 810 constitute an insulating dielectric layer 80.

[0103] The second insulating layer 820 and the first insulating layer 810 may have the same insulating material or different insulating materials. For example, both the first insulating layer 810 and the second insulating layer 820 may include silicon dioxide. The second protective layer 100 may be formed using a material with high hardness, such as silicon nitride. This application does not specifically limit the application to this material.

[0104] After forming the second insulating layer 820 as described above, the preparation method provided in this application embodiment may further include: forming a top electrode 70 on the mask layer 60, such as... Figure 10As shown; then a top interconnect metal 110 can be further provided on the top electrode 70 to lead out the top electrode 70 through the top interconnect metal 110, as shown. Figure 1 As shown.

[0105] The electrode material of the top electrode 70 can be independently selected from any one or more alloy materials composed of silver, copper, aluminum, gold, titanium, platinum, palladium, tantalum, tantalum nitride and titanium nitride. The top interconnect metal 110 can be a tungsten layer, but is not limited to the above types. The embodiments of this application do not make specific limitations.

[0106] According to an embodiment of this application, a magnetic random access memory is also provided, including a plurality of spin-orbit moment storage cells, wherein the spin-orbit moment storage cells are the spin-orbit moment storage cells in the foregoing embodiments, or are prepared by the preparation method of the spin-orbit moment storage cells in the foregoing embodiments.

[0107] The following description, in conjunction with specific embodiments, will explain the above-mentioned spin orbital moment storage unit, its preparation method, and the magnetic random access memory having it.

[0108] Example 1

[0109] This embodiment provides a method for fabricating a spin orbital moment storage cell, including the following steps:

[0110] S01, a substrate is provided, the substrate having a bottom metal 10, a lead-out portion 20, a bottom electrode 30, and a first insulating layer 810 surrounding the above structure, the bottom electrode 30 including two spaced electrode portions 31, one side surface of the electrode portion 31 being exposed, such as Figure 4 As shown, the bottom metal 10 is Cu, the lead-out part 20 is Cu, the bottom electrode 30 is TaN, and the first insulating layer 810 is SiO2.

[0111] S02, orbital layer material, magnetic tunnel junction material, and masking material are sequentially deposited on the substrate to form a sequentially stacked orbital material layer 41, magnetic tunnel junction material layer 51, and masking material layer 61, such as Figure 5 As shown, the orbital layer material is tantalum, the magnetic tunnel junction material includes a first material 501, a second material 502 and a third material 503 deposited sequentially, the first material 501 and the third material 503 are CoFeB, the second material 502 is MgO, and the mask material is SiN.

[0112] S03, the mask material layer 61 is patterned to obtain the mask layer 60, so that the magnetic tunnel junction material layer 51 has an exposed surface, and a first protective layer 90 is formed covering the mask layer 60 and the exposed surface, such as... Figure 6 As shown, the material of the first protective layer 90 is SiN;

[0113] S04, preliminary etching is performed on the track material layer 41 and the magnetic tunnel junction material layer 51 to form a first intermediate layer and a second intermediate layer. Then, over-etching is performed on the first intermediate layer, the second intermediate layer, and the electrode portion 31 to form the track layer 40 from the first intermediate layer and the magnetic tunnel junction 50 from the second intermediate layer. A first over-etched surface is formed on the upper surface of the electrode portion 31. Figure 7 As shown;

[0114] S05, sidewall modification of orbital layer 40 and magnetic tunnel junction 50, such as... Figure 8 As shown;

[0115] S06, a second protective layer 100 is deposited on the substrate to form a second protective layer 100, such that the second protective layer 100 covers the outer periphery of the mask layer 60, the first outer peripheral surface of the magnetic tunnel junction 50, the second outer peripheral surface of the orbital layer 40, and the first over-etched surface of the electrode portion 31, and a second insulating layer 820 is formed covering the second protective layer 100, such as... Figure 9 As shown, the material of the second protective layer 100 is SiN, and the material of the second insulating layer 820 is SiO2;

[0116] S07, a top electrode 70 is formed on the mask layer 60, such as Figure 10 As shown, the material of the top electrode 70 is TiN;

[0117] S08, a top interconnect metal 110 is further provided on the top electrode 70 to lead out the top electrode 70 through the top interconnect metal 110, such as... Figure 1 As shown, the top interconnect metal 110 is Cu.

[0118] Comparative Example 1

[0119] The difference between this comparative example and Example 1 is as follows:

[0120] After patterning the mask material layer 61 to obtain the mask layer 60 in step S03, the first protective layer 90 is not covered, and step S04 is performed directly.

[0121] Comparative Example 2

[0122] The difference between this comparative example and Example 1 is as follows:

[0123] In step S04, etching stops at the surface of orbital layer 40, and no over-etching is performed.

[0124] Using the SOT memory cells prepared in Examples 1-13 and Comparative Examples 1-2, respectively, corresponding SOT MRAM devices were prepared. Each SOT MRAM device includes a memory array, word lines, bit lines, and source lines composed of the same number of SOT memory cells periodically distributed.

[0125] In Examples 1-5 and Comparative Example 1 above, the thickness of the first protective layer 90 in the spin orbital moment memory cell and the yield of the corresponding SOT MRAM device are shown in Table 1. In Examples 1-5 and Comparative Example 1 above, the over-etching depth of S04 is 20 nm, and the overlap area between the bottom metal 10 and the magnetic tunnel junction 50 is 30%.

[0126] Table 1

[0127]

[0128] As can be seen from Table 1, after the mask layer 60 is etched, the first protective layer 90 is covered before etching the magnetic tunnel junction 50 and the orbital layer 40, which can improve the yield. The thickness of the first protective layer 90 is in the range of 5 to 100 nm, preferably between 25 and 50 nm.

[0129] In Examples 6-9 and Comparative Example 2 above, the over-etching depth in S04 and the corresponding yield of the SOT MRAM device are shown in Table 2, wherein the over-etching depth is represented by the fourth surface of the orbital layer 40 ( Figure 7 The maximum vertical distance between the upper surface of the electrode 31 and the over-etch stop position varies depending on the over-etch depth. The over-etch stop position can be located in the first over-etch surface of the electrode 31 or in the second over-etch surface of the first insulating layer 810. In the above embodiments 6 to 9 and comparative example 2, the overlap area between the bottom metal 10 and the magnetic tunnel junction 50 is 30%, and the thickness of the first protective layer 90 in the spin orbital moment storage cell is 40 nm.

[0130] Table 2

[0131] Example 6 Example 7 Example 8 Example 9 Comparative Example 2 Over-etch depth / nm 5 10 15 20 / Yield / % 95.4 98.8 100 100 82.5

[0132] As can be seen from Table 2, over-etching during the etching process to form the magnetic tunnel junction 50 and the orbital layer 40 can improve the yield. The over-etching depth ranges from 2 to 100 nm, preferably from 5 to 50 nm.

[0133] In the above embodiments 10 to 13, the overlap area ratio of the bottom metal 10 and the magnetic tunnel junction 50 and the corresponding flip current of the SOT MRAM device are shown in Table 3. The overlap area ratio is the ratio of the projected area of ​​the bottom metal 10 in the magnetic tunnel junction 50 to the bottom surface area of ​​the magnetic tunnel junction 50. In the above embodiments 10 to 13, the thickness of the first protective layer 90 in the spin orbital moment memory cell is 40 nm, and the over-etching depth in S04 is 20 nm.

[0134] Table 3

[0135] Example 10 Example 11 Example 12 Example 13 Overlap area ratio / % 15 25 35 45 Switching current / μA 540 550 546 548

[0136] As can be seen from Table 3, the critical switching current of the magnetic tunnel junction 50 does not change with the overlap area between the bottom metal 10 and the magnetic tunnel junction 50. Therefore, over-etching the magnetic tunnel junction 50 will not affect the critical switching current of the magnetic tunnel junction 50. Furthermore, by increasing the process window, a larger alignment deviation can be allowed, thereby increasing the etching yield.

[0137] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0138] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A spin-orbit moment storage cell, characterized in that, include: A magnetic tunnel junction having a first outer peripheral surface; An orbital layer is located on one side of the magnetic tunnel junction. The orbital layer has a second outer peripheral surface that is coplanar with the first outer peripheral surface, and the side surface of the orbital layer facing away from the magnetic tunnel junction is the first surface. The bottom electrode includes two spaced-apart electrode portions, each of which has its orthographic projection portion falling into the first surface in a first direction, the first direction being the direction from which the orbital layer points to the magnetic tunnel junction.

2. The spin-orbit moment storage unit according to claim 1, characterized in that, Each electrode portion has a second surface on the side facing away from the track layer. The electrode portion also has a third surface and a first over-etched surface that are respectively opposite to the second surface. The third surface and the first over-etched surface are not coplanar. The orthographic projection of the third surface in the first direction falls at least partially into the first surface. The orthographic projection of the first over-etched surface in the first direction is outside the first surface.

3. The spin orbital moment storage unit according to claim 2, characterized in that, The first etched surface is a non-flat surface.

4. The spin orbital moment storage unit according to claim 3, characterized in that, The first etched surface is a curved surface.

5. The spin-orbit moment storage unit according to claim 2, characterized in that, The first etched surface has a first end and a second end opposite to each other, the first end being in contact with the third surface, and the vertical distance between the first end and the second surface being greater than the vertical distance between the second end and the second surface.

6. The spin-orbit moment storage unit according to claim 2, characterized in that, The orbital layer has a fourth surface opposite to the first surface, and the maximum vertical distance between the first etched surface and the fourth surface is greater than 2 nm.

7. The spin orbital moment storage unit according to claim 5, characterized in that, Also includes: Each lead-out portion is located on the side of the electrode portion opposite to the track layer, corresponding to the lead-out portion. A first insulating layer is located at least in the spacer region between the electrode portions and surrounds the outer periphery of the lead-out portion.

8. The spin-orbit moment storage unit according to claim 7, characterized in that, The first insulating layer has a second etched surface that contacts the first etched surface and the second surface respectively. The second etched surface has a third end and a fourth end opposite to each other. The third end contacts the first etched surface, and the vertical distance between the third end and the first surface is less than the vertical distance between the fourth end and the first surface.

9. The spin-orbit moment storage unit according to claim 8, characterized in that, The orbital layer has a fourth surface opposite to the first surface, and the maximum vertical distance between the second over-etched surface and the fourth surface is less than 100 nm.

10. The spin-orbit moment storage unit according to claim 8, characterized in that, The spin orbital moment storage unit also includes a bottom metal, which is located on the side of the lead-out portion away from the electrode portion. The first insulating layer also surrounds the outer periphery of the bottom metal. The side of the magnetic tunnel junction near the first surface has a fifth surface. Each bottom metal has a first orthographic projection falling into the fifth surface in a first direction. The proportion of the first orthographic projection in the fifth surface is greater than or equal to 60%.

11. The spin-orbit moment storage unit according to any one of claims 1 to 10, characterized in that, The track layer has a fourth surface opposite to the first surface. The line connecting any point on the edge of the first surface and any point on the edge of the fourth surface with the shortest distance is the first connecting line. The angle between the first connecting line and the first surface is 45° to 85°.

12. A method for fabricating a spin-orbit moment storage cell, characterized in that, Includes the following steps: A substrate is provided, the substrate having a bottom electrode, the bottom electrode comprising two spaced-apart electrode portions, one side surface of the electrode portions being exposed; An orbital layer and a magnetic tunnel junction are formed on the substrate. The magnetic tunnel junction has a first outer peripheral surface. The orbital layer is located between the magnetic tunnel junction and the substrate. The orbital layer has a second outer peripheral surface that is coplanar with the first outer peripheral surface. The side of the orbital layer facing away from the magnetic tunnel junction is the first surface. The orthogonal projection of each electrode portion in a first direction falls into the first surface. The first direction is the direction in which the orbital layer points towards the magnetic tunnel junction.

13. The preparation method according to claim 12, characterized in that, The substrate further includes a lead-out portion and a first insulating layer, the first insulating layer being located in the spacing region between the electrode portions and surrounding the outer periphery of the lead-out portion, the step of forming the orbital layer and the magnetic tunnel junction includes: The orbital layer material, magnetic tunnel junction material and mask material are sequentially deposited on the substrate to form a sequentially stacked orbital material layer, magnetic tunnel junction material layer and mask material layer; The mask material layer is patterned to obtain a mask layer, so that the magnetic tunnel junction material layer has an exposed surface; A first protective layer is formed covering the mask layer and the exposed surface; The orbital material layer and the magnetic tunnel junction material layer are etched through the mask layer and the first protective layer to form the orbital layer and the magnetic tunnel junction.

14. The preparation method according to claim 13, characterized in that, The thickness of the first protective layer is 5–100 nm.

15. The preparation method according to claim 13 or 14, characterized in that, The steps of etching the orbital material layer and the magnetic tunnel junction material layer include: The orbital material layer and the magnetic tunnel junction material layer are initially etched to form a first intermediate layer and a second intermediate layer; The first intermediate layer, the second intermediate layer, and the electrode portion are over-etched to form the orbital layer from the first intermediate layer and the magnetic tunnel junction from the second intermediate layer. The side of the electrode portion facing away from the orbital layer after over-etching is the second surface. The electrode portion also has a third surface and a first over-etched surface that are respectively opposite to the second surface. The third surface and the first over-etched surface are not coplanar. The orthographic projection of the third surface in the first direction at least partially falls into the first surface. The orthographic projection of the first over-etched surface in the first direction is outside the first surface.

16. The preparation method according to claim 15, characterized in that, During the over-etching process, the electrode portion and the first insulating layer are etched simultaneously, so that the electrode portion and the first insulating layer respectively form a smooth transition of the first over-etched surface and the second over-etched surface.

17. The preparation method according to claim 15, characterized in that, The depth of the over-etching is 2–100 nm.

18. The preparation method according to claim 15, characterized in that, After the steps of forming the orbital layer and the magnetic tunnel junction, the preparation method further includes: A second protective layer is deposited on the substrate to cover the outer periphery of the mask layer, the first outer peripheral surface, the second outer peripheral surface, and the first over-etched surface; A second insulating layer is formed to cover the second protective layer.

19. A magnetic random access memory, comprising a plurality of spin-orbit moment storage cells, characterized in that, At least one of the said spin orbit moment storage units is a spin orbit moment storage unit as described in any one of claims 1 to 11, or at least one of the said spin orbit moment storage units is prepared by the method for preparing a spin orbit moment storage unit as described in any one of claims 12 to 18.

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