Semiconductor test method and system, intelligent device and storage medium

Abstract

The invention belongs to the field of wafer testing, and provides a semiconductor testing method and system, intelligent equipment and a storage medium in order to solve the problem that a semiconductor testing method often pays attention to a wafer and cannot well meet the actual requirements of cost reduction and the like, and the method comprises the steps that batch-level wafer testing data is acquired and analyzed; when the abnormal wafer exists, obtaining manufacturing process parameters of the abnormal wafer; obtaining manufacturing process parameters of the target normal wafer; the manufacturing process steps of the abnormal wafer and the target normal wafer are the same; and analyzing the manufacturing process parameters of the abnormal wafer and the manufacturing process parameters of the target normal wafer, and determining whether the manufacturing process is abnormal or not. Whether the wafer manufacturing process steps are abnormal or not is detected, and if the wafer manufacturing process steps are abnormal, the corresponding steps are adjusted, so that greater loss is avoided, abnormal wafers are reduced, the wafer production efficiency is improved, and the wafer production cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of chip testing (wafer testing), and more specifically, relates to a method, system, smart device, and storage medium for semiconductor testing. Background Technology

[0002] The primary purpose of semiconductor testing is to verify the electrical characteristics, functionality, and performance of chips to ensure they meet design standards. The testing process helps identify and eliminate defective chips, thereby improving product yield and reliability. CP (Chip Probing) testing involves probe testing on each die (chip cell) on the wafer, primarily occurring before chip packaging. Its core objective is to screen out defective chips through electrical performance testing, thus avoiding wasted resources in subsequent packaging and testing. Current semiconductor testing methods often focus on the wafer itself and cannot adequately meet practical needs such as cost reduction. Summary of the Invention

[0003] This application provides a method, system, smart device, and storage medium for semiconductor testing. By detecting whether there are abnormalities in the wafer fabrication process steps, it reduces the generation of abnormal wafers, improves wafer production efficiency, and reduces wafer production costs.

[0004] In a first aspect, embodiments of this application provide a method for semiconductor testing, including: S101, acquire batch-level wafer test data and analyze it; S103, when an abnormal wafer exists, obtain the fabrication process parameters of the abnormal wafer; obtain the fabrication process parameters of the target normal wafer, wherein the target normal wafer is the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer; the fabrication process steps of the abnormal wafer and the target normal wafer are the same. S105, analyze the fabrication process parameters of the abnormal wafer and the target normal wafer to determine whether there is an abnormality in the fabrication process.

[0005] In step S105, the manufacturing process parameters of historical abnormal wafers and normal wafers are obtained; the obtained manufacturing process parameters are normalized; a machine learning algorithm is used to train the normalized manufacturing process parameters to establish a prediction model; the manufacturing process parameters of the abnormal wafers and the manufacturing process parameters of the target normal wafers are input into the prediction model, and the prediction model outputs the result of whether there is an abnormality in the manufacturing process.

[0006] This also includes: before wafer testing, checking on the PRVX equipment whether the pressure (pin resistance) of all pins on the probe card is within the threshold range of 1.2g / mil + / -20%. The wafer is tested only after the probe card passes the inspection to ensure test quality.

[0007] This includes: determining the grain at the center of the wafer under test, establishing a coordinate system with the grain at the center as the origin, and determining the coordinates of other grains on the wafer based on the established coordinate system; selecting a target grain, determining a preset region based on the coordinates of the grain, the preset region including multiple grains, comparing the standard deviation and mean of the target grain parameters with the standard deviation and mean of the parameters of other grains in the preset region, and if the fluctuation exceeds the threshold, the target grain is abnormal.

[0008] The manufacturing process parameters include temperature, humidity, and the model of the manufacturing equipment.

[0009] Secondly, this application provides a semiconductor testing system, comprising: The first acquisition unit is used to acquire and analyze batch-level wafer test data. The second acquisition unit is used to acquire the manufacturing process parameters of the abnormal wafer when an abnormal wafer exists; and to acquire the manufacturing process parameters of a target normal wafer, wherein the target normal wafer is the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer; the manufacturing process steps of the abnormal wafer and the target normal wafer are the same. The determination unit is used to analyze the fabrication process parameters of abnormal wafers and the fabrication process parameters of target normal wafers to determine whether there are any abnormalities in the fabrication process.

[0010] The determining unit is used to: acquire the manufacturing process parameters of historical abnormal wafers and normal wafers; normalize the acquired manufacturing process parameters; train the normalized manufacturing process parameters using a machine learning algorithm to establish a prediction model; input the manufacturing process parameters of the abnormal wafers and the manufacturing process parameters of the target normal wafers into the prediction model, and the prediction model outputs the result of whether there is an abnormality in the manufacturing process.

[0011] The system is also used to: check the pressure (pin resistance) of all pins on the probe card on the PRVX equipment before wafer testing to ensure that the pressure is within the threshold range of 1.2g / mil + / -20%. The wafer is tested only after the probe card is qualified to ensure test quality.

[0012] Thirdly, embodiments of this application provide a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0013] Fourthly, embodiments of this application provide an intelligent device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0014] The semiconductor testing method and system described in this application have the following beneficial effects: In this application, when an abnormal wafer is present, the fabrication process parameters of the abnormal wafer are obtained; and the fabrication process parameters of a target normal wafer are also obtained. The target normal wafer is either the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer, and the fabrication process steps of the abnormal wafer and the target normal wafer are the same. Finally, the fabrication process parameters of the abnormal wafer and the target normal wafer are analyzed and compared to determine whether there is an abnormality in the fabrication process. This achieves the detection of whether there is an abnormality in the wafer fabrication process steps. If an abnormality is found, the corresponding steps are adjusted to avoid greater losses, reduce the generation of abnormal wafers, improve the efficiency of wafer production, and reduce the cost of wafer production. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the semiconductor testing method according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a semiconductor testing system according to an embodiment of this application. Detailed Implementation

[0016] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0017] In the following description, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The following description provides multiple embodiments of the invention, which can be substituted or combined with each other. Therefore, this application can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then this application should also be considered to include embodiments containing one or more other possible combinations of features A, B, C, and D, even if such embodiments are not explicitly described in the following text.

[0018] like Figure 1As shown, a semiconductor testing method according to this application includes: S101, acquiring and analyzing batch-level wafer test data; S103, when an abnormal wafer exists, acquiring the manufacturing process parameters of the abnormal wafer; acquiring the manufacturing process parameters of a target normal wafer, wherein the target normal wafer is the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer; the manufacturing process steps of the abnormal wafer and the target normal wafer are the same; S105, analyzing the manufacturing process parameters of the abnormal wafer and the target normal wafer to determine whether there is an abnormality in the manufacturing process. Manufacturing process parameters include, for example, temperature, humidity, and the model of the manufacturing equipment.

[0019] In this application, when an abnormal wafer is present, the fabrication process parameters of the abnormal wafer are obtained; and the fabrication process parameters of a target normal wafer are also obtained. The target normal wafer is either the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer, and the fabrication process steps of the abnormal wafer and the target normal wafer are the same. Finally, the fabrication process parameters of the abnormal wafer and the target normal wafer are analyzed and compared to determine whether there is an abnormality in the fabrication process. This achieves the detection of whether there is an abnormality in the wafer fabrication process steps. If an abnormality is found, the corresponding steps are adjusted to avoid greater losses, reduce the generation of abnormal wafers, improve the efficiency of wafer production, and reduce the cost of wafer production.

[0020] Wafer testing involves probing each die on the wafer. A probe attached to a testing head contacts the pads on the die to test its electrical characteristics. Defective dies are marked, and when the wafer is diced into individual dies, the marked defective dies are discarded and not proceeded to the next process to avoid increasing manufacturing costs. Wafer testing is a crucial step after wafer fabrication. During testing, the electrical parameters and circuit functions of each chip are detected. Wafer test results can be fed back to the front-end manufacturing process, helping to quickly identify and correct production problems and optimize the manufacturing process. The wafer-level testing process typically includes: Alignment: Using optical or other alignment techniques, the test points on the wafer are precisely aligned with the probe card. Probe Card Inspection: The probe card is used to probe the electrical contacts of each bare die for functional testing. Recording and Analysis: Test data is recorded and transmitted to a back-end system for analysis to obtain performance data for each bare die. Defective chip marking: After a defective chip is detected, it is marked as unqualified so that it can be excluded in the subsequent wafer dicing and packaging process.

[0021] In some embodiments, in step S105, the fabrication process parameters of historical abnormal wafers and normal wafers are obtained; the obtained fabrication process parameters are normalized to scale the data to a specific range to eliminate the influence of dimensions and facilitate comparison and analysis; a machine learning algorithm is used to train the normalized fabrication process parameters to establish a prediction model; the fabrication process parameters of the abnormal wafer and the target normal wafer are input into the prediction model, and the prediction model outputs the result indicating whether there is an anomaly in the fabrication process. By establishing a prediction model using a machine learning algorithm and using the prediction model to predict whether there is an anomaly in the fabrication process, the accuracy of determining whether there is an anomaly in the fabrication process is improved. Machine learning is a technique that trains models using data to achieve prediction and decision-making, and is widely used in tasks such as classification, regression, and clustering.

[0022] In some embodiments, this application further includes: before wafer testing, checking on the PRVX device whether the pressure (pin resistance) of all pins on the probe card is within the threshold range of 1.2g / mil + / -20%, and testing the wafer only after the probe card has passed the inspection, so as to ensure test quality.

[0023] In some embodiments, this application further includes: determining a grain at the center of the wafer under test; establishing a coordinate system with the grain at the center as the origin; determining the coordinates of other grains on the wafer based on the established coordinate system; selecting a target grain; determining a preset region based on the coordinates of the grain, the preset region including multiple grains; comparing the standard deviation and mean of the target grain's parameters with the standard deviation and mean of the parameters of other grains in the preset region; if the fluctuation exceeds a threshold, the target grain is abnormal. If the fluctuation (obtained by comparing the standard deviation and mean of the parameters) of the target grain is too large compared to the grains in the adjacent region, it indicates that the target grain is highly likely to be abnormal, thereby enabling the prediction of grain quality.

[0024] like Figure 2 As shown, this application also provides a semiconductor testing system, including: a first acquisition unit 201, used to acquire and analyze batch-level wafer test data; a second acquisition unit 202, used to acquire the manufacturing process parameters of the abnormal wafer when an abnormal wafer exists; acquire the manufacturing process parameters of a target normal wafer, wherein the target normal wafer is the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer; the manufacturing process steps of the abnormal wafer and the target normal wafer are the same; and a determination unit 203, used to analyze the manufacturing process parameters of the abnormal wafer and the manufacturing process parameters of the target normal wafer to determine whether there is an abnormality in the manufacturing process.

[0025] In some embodiments, the determining unit is configured to: acquire the manufacturing process parameters of historical abnormal wafers and normal wafers; normalize the acquired manufacturing process parameters; train the normalized manufacturing process parameters using a machine learning algorithm to establish a prediction model; input the manufacturing process parameters of the abnormal wafers and the manufacturing process parameters of the target normal wafers into the prediction model, and the prediction model outputs the result of whether the manufacturing process is abnormal.

[0026] In some embodiments, the semiconductor testing system of this application is also used to: check on the PRVX equipment whether the pressure (pin resistance) of all pins on the probe card is within the threshold range of 1.2g / mil + / -20% before wafer testing, and test the wafer after the probe card is qualified to ensure test quality.

[0027] In this application, the system embodiments for semiconductor testing are basically similar to the method embodiments for semiconductor testing. For relevant details, please refer to the description of the method embodiments for semiconductor testing.

[0028] This application also provides an intelligent device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0029] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described semiconductor testing method steps. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0030] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or units, and may be electrical, mechanical, or other forms.

[0031] In the various embodiments of the present invention, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for semiconductor testing, characterized in that, include: S101, acquire batch-level wafer test data and analyze it; S103, when an abnormal wafer exists, obtain the fabrication process parameters of the abnormal wafer; Obtain the fabrication process parameters of the target normal wafer, wherein the target normal wafer is the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer; the fabrication process steps of the abnormal wafer and the target normal wafer are the same. S105, analyze the fabrication process parameters of the abnormal wafer and the target normal wafer to determine whether there is an abnormality in the fabrication process.

2. The semiconductor testing method according to claim 1, characterized in that, In step S105, the fabrication process parameters of historical abnormal wafers and normal wafers are obtained; the obtained fabrication process parameters are then normalized. A machine learning algorithm is used to train the normalized manufacturing process parameters to establish a prediction model. The manufacturing process parameters of the abnormal wafer and the target normal wafer are input into the prediction model, and the prediction model outputs the result of whether the manufacturing process is abnormal.

3. The semiconductor testing method according to claim 1 or 2, characterized in that, Also includes: Before wafer testing, check on the PRVX equipment whether the pressure of all pins on the probe card is within the threshold range of 1.2g / mil + / -20%. Only after the probe card passes the check can the wafer be tested to ensure test quality.

4. The semiconductor testing method according to claim 1 or 2, characterized in that, Also includes: The center of the wafer to be tested is identified, and a coordinate system is established with the center of the wafer as the origin. The coordinates of other wafers on the wafer are then determined based on the established coordinate system. Select a target grain and determine a preset region based on the grain's coordinates. This preset region includes multiple grains. Compare the standard deviation and mean of the target grain's parameters with the standard deviation and mean of the parameters of other grains in the preset region. If the fluctuation exceeds a threshold, the target grain is considered to have an anomaly.

5. The semiconductor testing method according to claim 1 or 2, characterized in that, The manufacturing process parameters include temperature, humidity, and the model of the manufacturing equipment.

6. A semiconductor testing system, characterized in that, include: The first acquisition unit is used to acquire and analyze batch-level wafer test data. The second acquisition unit is used to acquire the manufacturing process parameters of the abnormal wafer when an abnormal wafer exists; and to acquire the manufacturing process parameters of a target normal wafer, wherein the target normal wafer is the normal wafer closest to the abnormal wafer or a normal wafer adjacent to the abnormal wafer; the manufacturing process steps of the abnormal wafer and the target normal wafer are the same. The determination unit is used to analyze the fabrication process parameters of abnormal wafers and the fabrication process parameters of target normal wafers to determine whether there are any abnormalities in the fabrication process.

7. The semiconductor testing system according to claim 6, characterized in that, The determination unit is used to: acquire the fabrication process parameters of historical abnormal wafers and normal wafers; and normalize the acquired fabrication process parameters. A machine learning algorithm is used to train the normalized manufacturing process parameters to establish a prediction model. The manufacturing process parameters of the abnormal wafer and the target normal wafer are input into the prediction model, and the prediction model outputs the result of whether the manufacturing process is abnormal.

8. The semiconductor testing system according to claim 6 or 7, characterized in that, The system is also used to: check on the PRVX equipment before wafer testing whether the pressure of all pins on the probe card is within the threshold range of 1.2g / mil + / -20%. The wafer is tested only after the probe card passes the inspection to ensure test quality.

9. A storage medium having a computer-readable program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method described in any one of claims 1-5.

10. A smart device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-5.

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