Method of fabricating multiple layer stacks with different chips based on same base chip and lithography offset parameters

Abstract

The application discloses a method for preparing different chips for multilayer stacking based on same basic chips and photoetching offset parameters, and the method comprises the following steps: using a first mask to make the same hole structure on N pieces of basic chips with the same structure to obtain N pieces of basic chips with the same hole structure, wherein the basic chips comprise a first basic chip, a second basic chip,..., and an Nth basic chip; using a second mask to sequentially complete the following steps: loading the first basic chip on a photoetching machine, photoetching a first hole structure by using a pre-set second mask-first photoetching offset parameter to obtain a first chip; and obtaining an Nth chip by analogy; the first hole structure, the second hole structure,..., and the Nth hole structure are different from each other in that at least one hole of each hole structure is connected to the inside of the chip. The method provided by the application can realize the preparation of different chips for multilayer stacking.

Description

Technical Field

[0001] This invention relates to photolithography technology, three-dimensional stacked chip integration method and multi-layer stacked chip in the field of semiconductor technology, and in particular to a method for obtaining different hole structures on the same base chip by setting photolithographic offset parameters. Background Technology

[0002] As the critical dimensions of integrated circuits have shrunk dramatically, now approaching the nanometer scale, the challenges posed by quantum tunneling leakage current have become increasingly severe. With the reduction in device size, the integration density of a single chip has not increased proportionally according to Moore's Law. Therefore, three-dimensional integration has become one of the core methods for improving chip integration density.

[0003] To address the challenges of 3D integration, common approaches include using TSV (ultra-deep via) and µBUMP (microsphere) technologies to interconnect multiple layers of chips with tens of thousands to hundreds of thousands of nodes, or achieving high-density planar connections through RDL (rewiring hierarchy) of the interposer, interconnecting multiple chips with thousands to tens of thousands of interconnect lines. While these methods can achieve communication bandwidths in the TB / s range, the still large size of µBUMPs poses a significant challenge for achieving even higher-density interconnects.

[0004] High-bandwidth memory (HBM) is a core chip technology urgently needed for artificial intelligence. Its characteristic is the three-dimensional stacking of multiple chips from the same base chip. Currently, it is mainly solved using the aforementioned traditional high-performance packaging technologies. However, this presents serious challenges for future higher-level stacking and higher-bandwidth connections. The challenge stemming from the inability to proportionally increase integration density as devices shrink makes it difficult to increase the number of devices per chip according to Moore's Law. Separating and stacking memory chips from computing chips, or even stacking multiple memory chips and computing chips from the same base chip, also urgently requires technologies with higher stacking density and less parasitic interconnection.

[0005] In existing technology 1, a wafer-level packaging method for an HBM packaging structure is disclosed (Invention Patent, 2023, Zhang Li, Guo Hongyan et al., CN117712033A). This method uses a wafer-level fan-out process to place solder joints on the sides of the memory chip and logic chip, and replaces the TSV connection of the original packaging structure with a metal pillar channel that runs through all chip modules on the chip side, thus simplifying the process. However, although this prior art simplifies the TSV connection process, it still uses a solder joint structure with relatively large solder joint sizes, which limits the high-density packaging of the chip and results in relatively large parasitic parameters in the packaging structure.

[0006] In prior art 2, a packaging structure and its formation method are disclosed (Invention Patent, 2025, Pan Zhijian, Wang Bu et al., CN120015715A). The packaging structure includes: a substrate; a packaging component bonded to the substrate; a cap disposed above the packaging component and the substrate; and an interface structure sandwiched between the packaging components. The packaging component includes: a first die; a second die laterally spaced from the first die by an underfill; and a molding compound adjacent to the first and second dies. The interface structure includes: an adhesive layer disposed above the underfill and the molding compound; and a thermal interface material (TIM) layer located above the adhesive layer, the first die, and the second die. However, in this prior art, the first and second dies are interconnected using an interposer, and the chip and the interposer are connected using microbumps. Both are relatively large, making it difficult to increase the connection density and reduce the parasitic parameters of the connection structure.

[0007] In prior art 3, a packaging structure and a high-bandwidth memory (HBM) device are disclosed (Utility Model Patent, 2023, Zhuang Xueli, Huang Wenduo, CN220774364U). This packaging structure includes: a first substrate including logic transistors; a first interconnect structure on the first substrate; a first bonding layer on the first interconnect structure; a second bonding layer on and bonded to the first bonding layer; a second interconnect structure above the second bonding layer; a second substrate above the second interconnect structure, the second substrate including a memory device; a protective film on the second substrate; a first through-path extending through a portion of the second interconnect structure and a first portion of the second substrate; and a second through-path extending through the protective film and a second portion of the second substrate to contact the top surface of the first through-path, wherein the first diameter of the first through-path is larger than the second diameter of the second through-path. However, although this prior art reduces the connection size through the second through-path, the size of the first through-path is not reduced, and the connection density and parasitic behavior cannot overcome the limitations of the first through-path size, thus no significant improvement is achieved. Summary of the Invention

[0008] Therefore, embodiments of the present invention provide a method for fabricating different hole structures on the same base chip based on the setting of photolithographic offset parameters, thereby fabricating different chips for multilayer stacking. This method utilizes the same base chip and adopts the setting and adjustment of photolithographic offset parameters to achieve the purpose of fabricating different hole structures on the same base chip, thereby realizing the fabrication of different chips for multilayer stacking.

[0009] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0010] A method for fabricating multilayer stacked chips based on the same base chip and photolithographic offset parameters, based on N base chips with the same structure, the method comprising:

[0011] Using a first mask, the same hole structure is fabricated on N base chips with the same structure to obtain N base chips with the same hole structure. The base chips include a first base chip, a second base chip, ..., an Nth base chip.

[0012] Using the second photomask, complete the following steps in sequence:

[0013] The first base chip is loaded into a lithography machine, and the first hole structure is formed by photolithography using the pre-set second mask-first lithography offset parameters to obtain the first chip;

[0014] The second base chip is loaded into a lithography machine, and the second hole structure is lithographically fabricated using the pre-set second mask-second lithography offset parameters to obtain the second chip;

[0015] And so on;

[0016] The Nth basic chip is loaded into a photolithography machine, and the Nth hole structure is photolithographically fabricated using the pre-set second mask-Nth photolithographic offset parameters to obtain the Nth chip;

[0017] The first hole structure, the second hole structure, ..., the Nth hole structure, each hole structure has at least one hole that is connected to the inside of the chip and is different from the other hole structures.

[0018] In some embodiments, a second mask is used, and the first chip-second lithography offset parameter to the Nth chip-second lithography offset parameter are set. By performing a second lithography on some or all of the first chips to the Nth chips using the second mask, more first chips, second chips, ..., the Nth chip with different holes can be obtained.

[0019] In some embodiments, the method further includes:

[0020] Using a third photomask, complete at least one of the following steps:

[0021] The first chip is loaded into a lithography machine, and the first chip is subjected to third mask lithography by using the pre-set third mask-first lithography offset parameters to obtain a first chip with an additional first hole structure.

[0022] The second chip is loaded into a lithography machine, and the second chip is subjected to third mask lithography by using the pre-set third mask-second lithography offset parameters to obtain a second chip with an additional second hole structure.

[0023] And so on;

[0024] The Nth chip is loaded into a lithography machine, and the Nth chip is subjected to secondary lithography using a pre-set third mask-Nth lithography offset parameter to obtain an Nth chip with an additional Nth hole structure.

[0025] In some embodiments, the first lithography offset parameter is a mask lithography offset parameter and / or a lithography stage lithography offset parameter for mounting the chip;

[0026] The second lithography offset parameter is the mask lithography offset parameter and / or the lithography stage offset parameter for mounting the chip.

[0027] In some embodiments, some of the hole structures in the first hole structure, the second hole structure, ..., the Nth hole structure overlap.

[0028] In some embodiments, the hole structure is one of the following:

[0029] Internal chip connection holes connect the connection pads to the interior of the corresponding chip.

[0030] Ultra-deep holes;

[0031] Ultra-deep hole connection hole, wherein the ultra-deep hole connection hole is a connection hole that communicates with an ultra-deep hole.

[0032] In some embodiments, each of the same hole structures includes a portion of vias or a portion of non-functional holes; and / or, each of the different hole structures includes a portion of vias or a portion of non-functional holes.

[0033] In some embodiments, the first chip, the second chip, ..., the Nth chip are further provided with connection pads; the provision of connection pads means that the first chip, the second chip, ..., the Nth chip are fabricated using the same mask for the connection pads, and at least a portion of the connection pads are connected to the hole structure.

[0034] In some embodiments, the connection pad is connected to the internal circuitry of the corresponding chip; or it is not connected to the internal circuitry of the corresponding chip, forming an over-connection pad or a non-functional connection pad.

[0035] In some embodiments, the connector pad is an etchable material, or the connector pad is a removable sacrificial structure.

[0036] In one or more specific embodiments, this invention obtains different hole structures for the same base chip by setting photolithographic offset parameters. By using photolithography techniques with these parameters, at least two photomasks can be used to differentiate N identical base chips, satisfying the requirement for distinguishable three-dimensional stacking of identical base chips. The method provided by this invention, on the one hand, requires only a minimum of two photomasks to differentiate N identical base chips, significantly reducing photomask manufacturing costs; on the other hand, combined with direct bonding of interconnect pads or ultra-deep hole etching processes, this invention can achieve connections of 1µm or even smaller, enabling high-speed, high-density communication between stacked chips, and even meeting the device-level high-speed, high-density communication requirements between stacked chips, providing technical support for improving the integration density of processor circuits such as CPUs, GPUs, and TPUs. Attached Figure Description

[0037] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0038] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0039] Figure 1 This is an example diagram illustrating the method provided by the present invention for obtaining different interconnect holes of the same basic chip by setting photolithographic offset parameters;

[0040] Figure 2 Example diagram of the photolithography equipment and alignment structure used in the photolithography technology implementation method provided by the present invention;

[0041] Figure 3 This is a schematic diagram illustrating how different hole structures are obtained through the setting of second mask-first chip-second photolithography offset parameters provided by the present invention; wherein... Figure 3 Figure (A) shows one of the schematic diagrams of the different pore structures obtained; Figure 3 Figure (B) shows a second schematic diagram of the different pore structures obtained;

[0042] Figure 4This is an example diagram illustrating the method for obtaining different interconnect holes by setting the photolithographic offset parameters of a third mask, as provided in this invention.

[0043] Figure 5 Example diagrams of different chips that can be stacked in multiple layers by changing the hole structure provided by the present invention; Figure 5 (A) is a schematic diagram of one type of hole structure; Figure 5 (B) is a schematic diagram of another form of hole structure;

[0044] Figure 6 Example diagram of a via or non-functional connection hole provided by the present invention;

[0045] Figure 7 An example diagram of a through-connection pad or a non-functional connection hole pad provided by the present invention;

[0046] Figure 8 This is an example diagram illustrating the interconnection structure of two chips formed by setting photolithographic offset parameters in conjunction with over-connection pads and non-functional connection pads, as provided by the present invention.

[0047] Figure 9 This is an example diagram of the three-dimensional stacked chip structure provided by the present invention; Figure 9 (A) is one of the three-dimensional stacked chip structures; Figure 9 (B) is the second type of three-dimensional stacked chip structure.

[0048] Explanation of reference numerals in the attached figures:

[0049] 10. Basic chip; 101. First basic chip; 102. Second basic chip; 10N. Nth basic chip; 201. First chip; 202. Second chip; 203. Third chip; 20N. Nth chip; 311. Identical hole structure; 331. First ultra-deep hole; 332. Second ultra-deep hole; 333. Non-functional connection hole; 341. First ultra-deep hole connection hole; 351. Second ultra-deep hole connection hole; 400. Stage; 401. Chip a; 402, Chip b; 403, Chip c; 3000, Fourth connection pad; 3001, First connection pad; 3002, Second connection pad; 3003, Third connection pad; 3011, Connection pad; 3012, Through connection pad; 3013, Non-functional connection pad; 3112, First hole structure; 3122, Second hole structure; 31N2, Nth hole structure; 3113, First chip hole structure; 3123, Second chip hole structure; 31N3, Nth chip hole Structure; 31121, Hole structure a; 31222, Hole structure b; 31223, Hole structure c; 31321, Hole structure d; 31323, Hole structure e; 321, Connecting hole a; 323, Connecting hole b; 3216, Connecting hole c; 3225, Connecting hole d; 3234, Connecting hole e; 3222, Connecting hole f; 322, Internal chip connecting hole a; 3213, Internal chip connecting hole b; 3231, Internal chip connecting hole c; 652 0. First alignment mark; 6530. Second alignment mark; 9201. First mask; 9202. Second mask; 9203. Third mask; 9100. Light source; 9200. Mask; 9232. Hole pattern; 9300. Projection system; 9510. Primary alignment device; 31122. Different hole structures; 311221. Different hole structure A; 311222. Different hole structure B; 31221. Different hole structures on the second chip. Detailed Implementation

[0050] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] To address the shortcomings of existing technologies, this invention primarily solves the problem of distinguishing the same underlying chips in high-density interlayer interconnections of three-dimensional stacked chips. When fabricating high-bandwidth memory (HBM), or integrating the logic circuits of CPUs (Central Processing Units), GPUs (Graphics Processing Units), and TPUs (Tensor Processing Units) with cache circuits and / or memory circuits in a three-dimensional stack, the issue of multi-layer stacking of the same underlying chips arises. The most important aspect of solving these problems is obtaining higher bandwidth and greater interconnect density. This invention aims to solve this technical problem.

[0052] In one specific embodiment, the present invention provides a method for fabricating multilayer stacked chips by preparing different hole structures on the same base chip through photolithographic offset parameter settings. The method is based on N base chips with the same structure and includes:

[0053] Using a first mask, the same hole structure is fabricated on N base chips with the same structure to obtain N base chips with the same hole structure. The base chip 10 includes a first base chip 101, a second base chip 102, ..., an Nth base chip 10N.

[0054] Using the second photomask, complete the following steps in sequence:

[0055] The first base chip 101 is loaded into a photolithography machine, and the first hole structure is formed by photolithography using the pre-set second mask-first photolithography offset parameters to obtain the first chip 201;

[0056] The second base chip 102 is loaded into a photolithography machine, and the second hole structure is made by photolithography using the pre-set second mask-second photolithography offset parameters to obtain the second chip 202;

[0057] And so on;

[0058] The Nth basic chip 10N is loaded into a photolithography machine, and the Nth hole structure is fabricated by photolithography using the pre-set second mask-Nth photolithography offset parameters to obtain the Nth chip 20N;

[0059] The first hole structure, the second hole structure, ..., the Nth hole structure, each hole structure has at least one hole that is connected to the inside of the chip and is different from the other hole structures.

[0060] Specifically, in order to achieve high-density interconnection of multiple layers of the same base chip, this application proposes a method for obtaining different interconnect holes of the same base chip by setting photolithographic offset parameters. For example... Figure 1 As shown, the method is based on N base chips 10 with the same structure. The existing chip pattern on the base chip 10 can be one or more of the following: integrated circuit pattern, optical path pattern, microfluidic path, metal wiring, and sensor pattern. The method includes:

[0061] Using the first mask 9201, the same hole structure 311 is fabricated on N basic chips 10 with the same structure to obtain N basic chips with the same structure and the same hole structure.

[0062] Using the second mask 9202:

[0063] For the first base chip 101, set a photolithography program or photolithography subroutine, set the first chip-first photolithography offset parameters, load the first base chip, and use photolithography to fabricate the first hole structure 3112 to obtain the first chip 201.

[0064] For the second base chip 102, set a photolithography program or photolithography subroutine, set the second chip-second photolithography offset parameters, load the second base chip, and use photolithography to fabricate the second hole structure 3122 to obtain the second chip 202.

[0065] Repeat the above steps multiple times until the Nth basic chip 10N photolithography is completed to fabricate the Nth hole structure 31N2, and the Nth chip 20N is obtained.

[0066] The first hole structure 3112, the second hole structure 3122, ..., the Nth hole structure 31N2, each hole structure has at least one hole connected to the inside of the chip that is different from the other hole structures.

[0067] Figure 1 The number of holes is exemplary; the specific number can be consistent with actual needs, ranging from tens to tens of thousands or even millions. Furthermore, this embodiment involves N chips stacked sequentially from back to front from 1 to N. This approach is common when chips are thicker (e.g., 50µm), with aligned positions stacked together, resulting in vertical overlap. However, when working with ultra-thin chips (e.g., 1µm thick silicon wafers), thinning the wafer individually makes it difficult to clamp, requiring a substrate for support during stacking. After bonding, the substrate is removed, leading to the possibility of front-to-front and back-to-back stacking. Therefore, whether using the same hole structure 311 or different hole structures, such as the first hole structure 3112, the second hole structure 3122, ..., the Nth hole structure 31N2, different rotation and mirror placement issues need to be considered.

[0068] Furthermore, a second photomask is used, and the first chip-second photolithography offset parameters are set to the Nth chip-second photolithography offset parameters. By performing a second photolithography on some or all of the first chips to the Nth chips using the second photomask, more first chips, second chips, ..., Nth chips with different holes can be obtained.

[0069] The lithography offset parameters mentioned above are the photomask offset parameters and / or the lithography stage offset parameters for mounting the chip. It should be understood that the lithography offset parameters may be the same or different for each chip, depending on the actual application.

[0070] Specifically, Figure 2 The lithography machine equipment and alignment structure of the present invention are illustrated. Figure 2 The lithography machine includes a light source 9100, a photomask 9200 (the photomask stage is not shown), a projection system 9300, and a stage 400. The first photomask 9201 and the second photomask 9202 are both mounted on the lithography machine's photomask stage. In other words... Figure 2 Mask 9200 is either the first mask 9201 or the second mask 9202. The base chip 10 is mounted on the stage 400. Figure 2 The example shown is the base chip 10 on stage 400. It should be noted that this lithography machine example uses a single mask, a single stage, and a transmissive projection system. The light source can be a mercury lamp or an excimer laser, or it can be an immersion lithography machine. When using an EUV (Extreme Ultraviolet) lithography machine, the mask 9200 is a reflective mask, and the projection system 9300 is a reflective projection system. Alternatively, two masks can be used, with two, three, or even four stages 400 alternating for lithography to improve efficiency. In particular, this invention relates to a single-layer resist coating and two lithography steps; using a two-mask, four-stage lithography machine can significantly improve efficiency. Other structural details of the lithography machine itself can be found in existing technologies and will not be elaborated here.

[0071] Figure 2 The alignment structure of the chip is also shown, taking the base chip 10 as an example. The base chip 10 is initially positioned by its own features or by the primary alignment device 9510 on the base chip, and further precisely positioned by the first alignment mark 6520. Subsequently, the base chip also has a second alignment mark 6530. When the stage delivers each exposure area to the projection system, it is only necessary to precisely align the second alignment mark 6530 to attach the mask pattern to the silicon wafer pattern.

[0072] For the first mask 9201 of this application, its mask layout is usually consistent with other masks of the base chip 10. Normal alignment and exposure can be used to complete the transfer of the pattern of the first mask 9201 onto the base chip 10.

[0073] When the base chip 10 exposed by the first mask 9201 is further exposed using the second mask 9202 of this application, a photolithography program or photolithography subroutine needs to be created for each chip (or batch). By setting photolithography offset parameters, the same second mask 9202 pattern is offset and projected onto the same base chip 10 (i.e., the first base chip 101, the second base chip 102, ..., the Nth base chip 10N) to form different chips. There are two methods for this photolithography offset parameter. Because the so-called alignment of the photolithography machine is to accurately overlay the mask pattern with the pattern in the chip exposure area, if the two are offset and overlaid, on the one hand, the mask can be offset, and the silicon wafer can be accurately aligned according to the alignment system using conventional alignment methods, resulting in an offset; or the mask can be accurately aligned using conventional alignment methods, but the alignment in the chip exposure area is offset, then both are also offset, or each is offset by a portion, and the overall offset distance is achieved. The lithography offset parameter can be the lithography offset parameter of the mask 9200, or the lithography offset parameter of the lithography stage on which the chip is mounted (i.e., the alignment offset parameter of the second alignment mark 6530). If the offset parameters of a chip (such as the first base chip 101) or a batch are different, the exposure position of the pattern of the second mask 9202 on the original pattern will be different, such as the first hole structure 3112 of the first base chip 101, the second hole structure 3122 of the second base chip 102, and the Nth hole structure 31N2 of the Nth base chip 10N.

[0074] One advantage of this invention is that it solves the problem of distinguishing identical base chips required for 3D stacking using a single photomask. In other words, if identical base chips are stacked together without differentiation, signals cannot be distinguished as to which chip to send to. Using this method, a first mask is used to mark the interconnected holes, such as address and data connection holes. Since there are many of these holes, chip select signals can differentiate them even though they are connected together. To distinguish different chips, each chip's hole structure must have at least one hole that connects to the chip's interior and is different from the other hole structures, serving as the chip select signal interface. Thus, if different chip select connection holes are created, only the chip select signal is allowed to operate, effectively solving this problem. These holes are usually relatively few in number. By using photolithographic offset parameters, the pattern of the same mask is projected onto different areas on different chips, achieving chip differentiation.

[0075] Figure 1The example illustrates completely different via structures 3112, 3122, ..., Nth via structure 31N2. In reality, it's possible that a signal needs to be connected to two chips. To address this, one approach is to fabricate a sufficient number of via structures 3112, 3122, ..., Nth via structure 31N2, defining two different via structures connected to the same external signal. Another approach is to further fabricate the two chips that need to be connected using a second or third mask. Figure 3 Image (A) illustrates a method for further obtaining different hole structures 31122 on a first base chip 101 by setting second mask-first base chip-second photolithography offset parameters. After stacking the different hole structures 31122 on the first base chip, a connection can be formed with the second base chip 102, meaning external signals can be simultaneously sent to both the first base chip 101 and the second base chip 102. This method allows for setting first chip-second photolithography offset parameters up to Nth chip-second photolithography offset parameters. By performing a second photolithography on some or all of the first to Nth chips using the second mask, more first chips, second chips, ..., Nth chips with different hole structures can be obtained. It should be noted that, as... Figure 1 , Figure 3 A simple example, Figure 1 If the second base chip 102 is not identified, a connection signal that cannot be distinguished from the second base chip 102 will appear. The solution to this problem can be as follows: Figure 3 As shown in (B), when setting the offset parameters of the second mask-first chip-second photolithography, in addition to the vertical offset, it is also horizontally offset. Then, the different hole structure A311221 will be connected to one of the holes in the second hole structure 3122 of the second base chip 102. The different hole structure B311222 (there are multiple different hole structures 31122 on the first chip. For ease of description, they are named different hole structure A with reference to 311221 and different hole structure B with reference to 311222 respectively) is redundant or used for other purposes. In this way, the different hole structures 31221 on the second chip can be used to distinguish the second base chip 102 separately.

[0076] Furthermore, the method also includes:

[0077] Using a third photomask, complete at least one of the following steps:

[0078] The first chip is loaded into a lithography machine, and the first chip is subjected to third mask lithography by using the pre-set third mask-first lithography offset parameters to obtain a first chip with an additional first hole structure.

[0079] The second chip is loaded into a lithography machine, and the second chip is subjected to third mask lithography by using the pre-set third mask-second lithography offset parameters to obtain a second chip with an additional second hole structure.

[0080] And so on;

[0081] The Nth chip is loaded into a lithography machine, and the Nth chip is subjected to third mask lithography by using the pre-set third mask-Nth lithography offset parameters to obtain the Nth chip with an additional Nth hole structure.

[0082] Specifically, Figure 4 An example using a third mask 9203 is shown. This third mask 9203 further obtains different hole structures for some or all of the chips (first chip, second chip, ..., Nth chip) using the aforementioned photolithographic offset parameter setting method. Examples include hole structure 3113 for the first chip, hole structure 3123 for the second chip, ..., hole structure 31N3 for the Nth chip. In this example, because the photolithographic offset parameters of the second and third masks are different in the first chip, and also different in the second chip, ..., and also different in the Nth chip, independent mask settings are required. It should be noted that adding masks increases mask cost. Furthermore, if all chips require photolithography using the added mask, it increases the number of photolithography steps by N. For large-scale chip manufacturing (e.g., 10,000 or even 100,000 chips), the photolithography cost must also be considered.

[0083] Although in the embodiments, the first hole structure 3112, the second hole structure 3122, ..., the Nth hole structure 31N2 are exemplaryly completely separated, this is mainly for better illustrating the differences in the chip implementation of the present invention. In specific implementations, the first hole structure 3112, the second hole structure 3122, ..., the Nth hole structure 31N2 typically have hundreds, thousands, or even millions of holes. In some embodiments, some hole structures in the first hole structure 3112, the second hole structure 3122, ..., the Nth hole structure 31N2 overlap. Whether there is partial overlap of hole structures can be determined according to actual needs, and the present invention does not specifically limit it.

[0084] In some embodiments, both the identical hole structure and the different hole structures are one of the following:

[0085] Internal chip connection holes connect the connection pads to the interior of the corresponding chip.

[0086] Ultra-deep holes;

[0087] Ultra-deep hole connection hole, wherein the ultra-deep hole connection hole is a connection hole that communicates with an ultra-deep hole.

[0088] Wherein, each of the same hole structures includes some through holes or some non-functional holes; and / or, each of the different hole structures includes some through holes or some non-functional holes.

[0089] Specifically, in the method of obtaining different hole structures of the same basic chip through photolithographic offset parameter settings in this invention, the hole structure can be a connection hole connecting the connection pad to the inside of the chip, or an ultra-deep hole, or an ultra-deep hole connection hole perpendicularly connected to the ultra-deep hole. Examples of the relative positions of each hole structure are shown below. Figure 5 As shown in (A), the connector pad is connected to the connector hole a321, the first ultra-deep via 331, the first ultra-deep via connector hole 341, and the second ultra-deep via connector hole 351 inside the chip (only one of these can be selected when using ultra-deep via connector holes to implement this invention). Both the first ultra-deep via connector hole 341 and the second ultra-deep via connector hole 351 can be present; or one can be present, with the other location penetrated by the first ultra-deep via 331 to the chip surface or the lower surface of the connector pad; alternatively, the first ultra-deep via 331 can exist alone, directly penetrating to the chip surface or the lower surface of the connector pad (i.e., the locations of the first ultra-deep via connector hole 341 and the second ultra-deep via connector hole 351 are penetrated by ultra-deep vias); the specific requirements will prevail, but all can be used in this invention to obtain different connector holes on the same basic chip through photolithographic offset parameter settings. Figure 5 (B) illustrates a structure for etching ultra-deep vias after stacking. In this structure, the connecting pads are connected to the connecting vias a321 inside the chip for adjustment, and then the signal transmission of the fully stacked chip is achieved by etching through the first ultra-deep via 331.

[0090] It should be noted here that when the connection pad is changed to the internal chip connection hole a321, the connection pad 3011 and the first ultra-deep via 331 (and if necessary, the first ultra-deep via connection hole 341 and / or the second ultra-deep via connection hole 351) form an over-connection structure. That is, in three-dimensional stacking, each ultra-deep via can be connected to external signals; the difference lies only in whether or not a via is connected to the internal chip. Figure 1 , Figure 3 , Figure 4The examples are all simple, direct, and effective. However, for chips without a first ultra-deep via 331, or a first ultra-deep via connection 341, or a second ultra-deep via connection 351, the signal will not be able to pass through the chip. Therefore, when using photolithography offset parameter settings to obtain chips with different first ultra-deep vias 331, or first ultra-deep via connection 341, or second ultra-deep via connection 351 on the same base chip, it is necessary to consider the transmission of distinguishable signals between the chips with the fabricated vias. To address this issue, one possible approach is to connect portions of the chips with different first ultra-deep vias 331, or first ultra-deep via connection holes 341, and second ultra-deep via connection holes 351 that require signal transmission to a common via structure 311. The related vias of the common via structure 311 used for this function are not connected to the chip's internal structure when fabricating their own connection pads, and the required signal transmission is provided by the vias of this common via structure 311. Alternatively, the first via structure 3112, the second via structure 3122, ..., the Nth via structure 31N2 can be aligned and overlapped to form the necessary signal transmission channel.

[0091] As previously described, the hole structures of the present invention involve vias or non-functional connection holes, and the connection pads involve via pads or non-functional connection pads, wherein the via pads or non-functional connection pads are not connected to the chip interior. The vias or non-functional connection holes, exemplarily, include... Figure 6 As shown, the first ultra-deep via 331 and the connection hole a321 are normal functional ultra-deep vias and internal chip connection holes, which can form a connection between the ultra-deep via and the inside of the chip with the connection pad 3011 and realize signal transmission between chips; the second ultra-deep via 332 can provide connection between the upper and lower chips, but it is not connected to the internal chip connection hole a322 and cannot transmit signals with the inside of the chip, so it is a via; the non-functional connection hole 333 can neither connect to the inside of the chip nor provide connection between the upper and lower chips.

[0092] It should be understood that the above-mentioned hole structure refers to a single internal chip connection hole, a single ultra-deep via, or a single ultra-deep via connection hole, etc. The internal chip connection hole may also be formed by multiple internal chip connection holes (including but not limited to the hole structure of conventional chips) to connect the connection pad to the interior of the corresponding chip (a common method in small-size process nodes). Alternatively, multiple internal interconnects and multiple internal chip connection holes may be combined to form a combined internal chip connection hole to connect the connection pad to the interior of the corresponding chip. During fabrication, only the internal chip connection holes connected to the connection pads need to be fabricated. If it is convenient for process implementation, other internal chip connection holes in the combined internal chip connection hole can be selected to implement this invention, or an internal interconnection line connecting two internal chip connection hole layers in the combined internal chip connection hole can be selected to implement this invention (i.e., controlling the on / off state of the combined internal chip connection hole by fabricating the interconnection line), and this is not limited.

[0093] For ultra-deep vias, just as internal chip vias may be formed by multiple internal chip vias, especially for ultra-deep vias on the front side of a chip, multiple ultra-deep vias (including but not limited to those using conventional chip hole structures) may be formed into combined ultra-deep vias, or even multiple internal interconnects and multiple ultra-deep vias may be formed into combined ultra-deep vias. During fabrication, only the ultra-deep vias connected to the connection pads need to be fabricated. If it is convenient for process implementation, other ultra-deep vias in the combined ultra-deep vias can be selected to implement the present invention, or one of the internal interconnects connecting two ultra-deep via layers in the combined ultra-deep vias can be selected to implement the present invention (i.e., controlling the on / off state of the combined ultra-deep vias by fabricating interconnects), and there is no limitation.

[0094] In some embodiments, the first chip, the second chip, ..., the Nth chip are further provided with connection pads. The connection pads are fabricated using the same mask across the first chip, the second chip, ..., the Nth chip, and at least a portion of the connection pads are connected to the via structure. The connection pads may or may not be connected to the internal circuitry of the corresponding chip, forming over-connection pads or non-functional connection pads. In some embodiments, the connection pads are made of an etchable material, or the connection pads are removable sacrificial structures.

[0095] Specifically, Figure 7 It showed both over-connecting pads and non-functional connecting pads. Figure 7Interconnect pad 3011 is a normal connector pad, which can form an internal connection with the first ultra-deep via 331 and the connector a321 and enable signal transmission between chips. Through connector pad 3012 is not connected to the internal connector a322 of the chip and cannot transmit signals to the inside of the chip, but it is connected to the second ultra-deep via 332 and can provide a connection between the upper and lower chips, forming a through connector pad. Non-functional connector pad 3013 is neither connected to the connector b323 connected to the inside of the chip nor connected to it by an ultra-deep via, so it has no signal transmission to the inside of the chip and cannot provide a connection between the upper and lower chips, and is a non-functional connector pad.

[0096] It should be noted that, apart from deep hole etching, the aforementioned connector pads are generally fabricated after the fabrication of each hole structure, or deep hole etching can be completed before fabricating the connector pads. Therefore, in practical application, the first chip, the second chip, ..., the Nth chip typically also include connector pad fabrication.

[0097] also, Figure 8 It also shows a structure in which two chips are interconnected by setting photolithographic offset parameters in conjunction with over-connection pads and non-functional connection pads. Figure 8 The connecting pad is shown before the hole structure, mainly for location marking, and its actual fabrication usually follows the hole structure fabrication. Figure 8 The dashed boxes in the diagram represent reserved spaces for connecting two chips. The first connecting pad 3001, second connecting pad 3002, and third connecting pad 3003, which are filled, connect the base chip to the ultra-deep via, and already possess the function of connecting upper and lower chips. The fourth connecting pad 3000 is a position marker; it is either not made as a connecting pad or does not have an ultra-deep via connection pad (a non-functional connecting pad). For example, different hole structures 31122, hole structure a31121, hole structure b31222, hole structure c31223, hole structure d31321, and hole structure e31323 (it can be understood that there are multiple hole structures here; for ease of description, they are respectively named hole structure a (labeled 31121), hole structure b (labeled 31222), hole structure c (labeled 31223), hole structure d (labeled 31321), and hole structure e (labeled 31323) as internal connection holes connected to the inside of the chip. When the internal interconnects of a chip fall within an area where no interconnect pads are made or where there are no functional interconnect pads, the internal interconnects of that chip have no signal transmission function. For example... Figure 8The method shown transfers the hole patterns 9232 of the second mask 9202 to the first chip 201, the second chip 202, and the third chip 203 through photolithography offset parameter settings and photolithography. This forms connections between the first chip 201 and the second chip 202, between the first chip 201 and the third chip 203, and between the second chip 202 and the third chip 203. That is, external signals connected to different hole structures 31122 can be simultaneously transmitted to the first chip 201 and the second chip 202; external signals connected to hole structure a31121 can be simultaneously transmitted to the first chip 201 and the third chip 203; and external signals connected to hole structure c31223 can be simultaneously transmitted to the second chip 202 and the third chip 203, allowing each external signal to control two different chips.

[0098] Figure 9 An example of three-dimensional stacking using chips fabricated using the present invention is provided. Figure 9 (A) Figure 9 In both cases (B), the same basic chip is distinguished from different chips by setting photolithographic offset parameters to obtain different connection pads connecting to the chip's internal connection holes. Figure 9Example (A) illustrates the effect of three-dimensional stacked chips obtained by direct bonding stacking of chips using the present invention. First, chips a401, b402, and c403 all have a first ultra-deep via 331 and a connecting pad, which will not be described in detail. As mentioned earlier, the first mask 9201 is used to fabricate connection pads for the base chips a401, b402, and c403, connecting them to the same hole structure 311 inside the chip. Each chip can transmit signals or supply power to the outside through the same hole structure 311. Then, the second mask 9202 is replaced, and connection pads are fabricated for chip a401 to connect to the connection hole c3216 inside the chip, for chip b402 to connect to the connection hole d3225 inside the chip, and for chip c403 to connect to the connection hole e3234 inside the chip (it can be understood that there are multiple connection holes here, which are named connection hole a (labeled 321), connection hole b (labeled 323), connection hole c (labeled 3216), connection hole d (labeled 3225), connection hole e (labeled 3234), and connection hole f (labeled 3222) respectively for ease of description). After chips a401, b402, and c403 are stacked and bonded together, external signals connected to the connection hole c3216 can only be transmitted with chip a401; external signals connected to the connection hole d3225 can only be transmitted with chip b402; and external signals connected to the connection hole e3234 can only be transmitted with chip c403. Assuming these connection holes are connected to chip select signals, although external signals connected to the same hole structure 311 can be connected to chips a401, b402, and c403 simultaneously, due to chip select, if the signal connected to the connection hole c3216 controls the chip selected chip a401, then chip a401 connected to the same hole structure 311 is effective, while chips b402 and c403 do not participate in signal transmission, thus achieving the effect of chip differentiation.

[0099] Figure 9Example (B) illustrates the use of the present invention to obtain a three-dimensional stacked chip effect by performing the same ultra-deep hole etching on stacked chips. First, each chip a401, chip b402, and chip c403 (it can be understood that three chips are used as an example here, and for ease of description, they are respectively named chip a with reference to 401, chip b with reference to 402, and chip c with reference to 403) has a connecting pad 3011, which will not be described in detail. As mentioned earlier, the first mask 9201 is used to fabricate connection pads for the base chips a401, b402, and c403, which are connected to the same hole structure 311 inside the chip. Each chip can transmit signals or supply power to the outside through the same hole structure 311. Then, the second mask 9202 is replaced, and the connection pads for chip a401 are fabricated to connect to the internal connection hole b3213, the connection pads for chip b402 are fabricated to connect to the internal connection hole f3222, and the connection pads for chip c403 are fabricated to connect to the internal connection hole c3231. (It can be understood that there are three internal connection holes here. For ease of description, they are named internal connection hole a, internal connection hole b, and internal connection hole c, respectively. The reference numeral for internal connection hole a is 322, the reference numeral for internal connection hole b is 3213, and the reference numeral for internal connection hole c is 3231.) After chips a401, b402, and c403 are stacked and bonded together, ultra-deep via etching is performed to create the first ultra-deep via 331 connecting each connection pad, enabling each connection pad to form a connection with the outside. It should be noted that the connection pads described in this embodiment are etchable or removable sacrificial structures. Taking an integrated circuit as an example, if the material is aluminum, it can be etched to form an aluminum via, retaining the pad structure. After the ultra-deep via is filled, it forms a connection with the external connection pad; or the aluminum can be removed, and electrical connection material can be refilled, forming a connection with the external connection pad together with the filled ultra-deep via material; or a sacrificial material, such as silicon nitride or other materials, can be etched and removed, and electrical connection material can be filled, forming a connection with the external connection pad together with the filled ultra-deep via material. Thus, in a complete three-dimensional stacked chip, external signals connected to the internal connection hole b3213 can only transmit signals to chip a401; external signals connected to the connection hole f3222 can only transmit signals to chip b402; and external signals connected to the internal connection hole c3231 can only transmit signals to chip c403. Assuming these connection holes are connected to chip select signals, although external signals connected to the same hole structure 311 can simultaneously connect to chips a401, b402, and c403, due to chip select, if the signal connected to the internal connection hole b3213 controls the chip select chip a401, then chip a401 connected to the same hole structure 311 is effective, while chips b402 and c403 do not participate in signal transmission, achieving the effect of chip differentiation.

[0100] In one or more specific embodiments, this invention obtains different hole structures for the same base chip by setting photolithographic offset parameters. By using photolithography techniques with these parameters, at least two photomasks can be used to differentiate N identical base chips, satisfying the requirement for distinguishable three-dimensional stacking of identical base chips. The method provided by this invention, on the one hand, requires only a minimum of two photomasks to differentiate N identical base chips, significantly reducing photomask manufacturing costs; on the other hand, combined with direct bonding of interconnect pads or ultra-deep hole etching processes, this invention can achieve connections of 1µm or even smaller, enabling high-speed, high-density communication between stacked chips, and even meeting the device-level high-speed, high-density communication requirements between stacked chips, providing technical support for improving the integration density of processor circuits such as CPUs, GPUs, and TPUs.

[0101] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating multilayer stacked chips based on the same base chip and photolithographic offset parameters, characterized in that, Based on N basic chips with the same structure, the method includes: Using a first mask, the same hole structure is fabricated on N base chips with the same structure to obtain N base chips with the same hole structure. The base chips include a first base chip, a second base chip, ..., an Nth base chip. Using the second photomask, complete the following steps in sequence: The first base chip is loaded into a lithography machine, and the first hole structure is formed by photolithography using the pre-set second mask-first lithography offset parameters to obtain the first chip; The second base chip is loaded into a lithography machine, and the second hole structure is lithographically fabricated using the pre-set second mask-second lithography offset parameters to obtain the second chip; And so on; The Nth basic chip is loaded into a photolithography machine, and the Nth hole structure is photolithographically fabricated using the pre-set second mask-Nth photolithographic offset parameters to obtain the Nth chip; The first hole structure, the second hole structure, ..., the Nth hole structure, each hole structure has at least one hole that is connected to the inside of the chip and is different from the other hole structures.

2. The method according to claim 1, characterized in that, Using a second mask, the first chip-second lithography offset parameters are set to the Nth chip-second lithography offset parameters. By performing a second lithography on some or all of the first chips to the Nth chips using the second mask, more first chips, second chips, ..., Nth chips with different holes can be obtained.

3. The method according to claim 1, characterized in that, The method further includes: Using a third photomask, complete at least one of the following steps: The first chip is loaded into a lithography machine, and the first chip is subjected to third mask lithography by using the pre-set third mask-first lithography offset parameters to obtain a first chip with an additional first hole structure. The second chip is loaded into a lithography machine, and the second chip is subjected to third mask lithography by using the pre-set third mask-second lithography offset parameters to obtain a second chip with an additional second hole structure. And so on; The Nth chip is loaded into a lithography machine, and the Nth chip is subjected to third mask lithography by using the pre-set third mask-Nth lithography offset parameters to obtain the Nth chip with an additional Nth hole structure.

4. The method according to claim 1, characterized in that, Each lithography offset parameter is a photomask offset parameter and / or a lithography stage offset parameter for mounting the chip.

5. The method according to claim 1, characterized in that, Some of the hole structures in the first hole structure, the second hole structure, ..., the Nth hole structure overlap.

6. The method according to claim 1, characterized in that, Each hole has one of the following structures: Internal chip connection holes connect the connection pads to the interior of the corresponding chip. Ultra-deep holes; Ultra-deep hole connection hole, wherein the ultra-deep hole connection hole is a connection hole that is perpendicularly connected to the ultra-deep hole.

7. The method according to any one of claims 1-6, characterized in that, Each identical hole structure includes some vias or some non-functional holes; and / or, each different hole structure includes some vias or some non-functional holes.

8. The method according to any one of claims 1-6, characterized in that, The first chip, the second chip, ..., the Nth chip are also provided with connection pads; the provision of connection pads means that the first chip, the second chip, ..., the Nth chip are made using the same mask to fabricate the connection pads, and at least a portion of the connection pads are connected to the hole structure.

9. The method according to claim 8, characterized in that, The connection pad is connected to the internal circuitry of the corresponding chip; or it is not connected to the internal circuitry of the corresponding chip, forming an over-connection pad or a non-functional connection pad.

10. The method according to claim 8, characterized in that, The connector pad is made of an etchable material, or the connector pad is a removable sacrificial structure.

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