Multi-layer stacked chip based on photoetching equipment and multi-layer stacking method

Abstract

The invention discloses a multi-layer stacked chip based on photoetching equipment and a multi-layer stacking method. The multi-layer stacked chip comprises the following steps: manufacturing same basic connecting pads for N basic chips with the same structure by adopting a first mask; replacing with a second mask plate; adopting a first basic chip, setting a first mask offset distance and / or a first offset distance of a photoetching machine carrying platform of the first basic chip, and manufacturing a first connecting pad after exposure so as to obtain a first chip; and the rest can be done in the same way until the Nth basic chip is adopted, the offset distance of the Nth mask and / or the Nth offset distance of the photoetching machine platform of the Nth basic chip are / is set, and the Nth chip is obtained. At least one of the connecting pads among the chips is different; and / or at least one of the connecting pads between the chips and the connecting structure in the corresponding chip is different from the connecting structure in the corresponding chip. The problem of improving the integration level of a complex chip is solved.

Description

Technical Field

[0001] This invention relates to photolithography technology, three-dimensional stacked chip integration method, and multi-layer stacked chip in the field of semiconductor technology, and in particular to a method for realizing different chips and multi-layer stacking methods by setting photolithographic offset and using different connection pads to obtain the same base chip. Background Technology

[0002] As the critical dimensions of integrated circuits have shrunk dramatically, now approaching the nanometer scale, the challenges posed by quantum tunneling leakage current have become increasingly severe. With the reduction in device size, the integration density of a single chip has not increased proportionally according to Moore's Law. Therefore, three-dimensional integration has become one of the core methods for improving chip integration density.

[0003] To address the challenges of 3D integration, common approaches include using TSV (ultra-deep via) and µBUMP (microsphere) technologies to interconnect multiple layers of chips with tens of thousands to hundreds of thousands of nodes, or achieving high-density planar connections through RDL (rewiring hierarchy) of the interposer, interconnecting multiple chips with thousands to tens of thousands of interconnect lines. While these methods can achieve communication bandwidths in the TB / s range, the still large size of µBUMPs poses a significant challenge for achieving even higher-density interconnects.

[0004] High-bandwidth memory (HBM) is a core chip technology urgently needed for artificial intelligence. Its characteristic is the three-dimensional stacking of multiple chips from the same base chip. Currently, it is mainly solved using the aforementioned traditional high-performance packaging technologies. However, this presents serious challenges for future higher-level stacking and higher-bandwidth connections. The challenge stemming from the inability to proportionally increase integration density as devices shrink makes it difficult to increase the number of devices per chip according to Moore's Law. Separating and stacking memory chips from computing chips, or even stacking multiple memory chips and computing chips from the same base chip, also urgently requires technologies with higher stacking density and less parasitic interconnection.

[0005] In existing technology 1, a wafer-level packaging method for an HBM packaging structure is disclosed (Invention Patent, 2023, Zhang Li, Guo Hongyan et al., CN117712033A). This method uses a wafer-level fan-out process to place solder joints on the sides of the memory chip and logic chip, and replaces the TSV connection of the original packaging structure with a metal pillar channel that runs through all chip modules on the chip side, thus simplifying the process. However, although this prior art simplifies the TSV connection process, it still uses a solder joint structure with relatively large solder joint sizes, which limits the high-density packaging of the chip and results in relatively large parasitic parameters in the packaging structure.

[0006] In prior art 2, a packaging structure and its formation method are disclosed (Invention Patent, 2025, Pan Zhijian, Wang Bu et al., CN120015715A). The packaging structure includes: a substrate; a packaging component bonded to the substrate; a cap disposed above the packaging component and the substrate; and an interface structure sandwiched between the packaging components. The packaging component includes: a first die; a second die laterally spaced from the first die by an underfill; and a molding compound adjacent to the first and second dies. The interface structure includes: an adhesive layer disposed above the underfill and the molding compound; and a thermal interface material (TIM) layer located above the adhesive layer, the first die, and the second die. However, in this prior art, the first and second dies are interconnected using an interposer, and the chip and the interposer are connected using microbumps. Both are relatively large, making it difficult to increase the connection density and reduce the parasitic parameters of the connection structure.

[0007] In prior art 3, a packaging structure and a high-bandwidth memory (HBM) device are disclosed (Utility Model Patent, 2023, Zhuang Xueli, Huang Wenduo, CN220774364U). This packaging structure includes: a first substrate including logic transistors; a first interconnect structure on the first substrate; a first bonding layer on the first interconnect structure; a second bonding layer on and bonded to the first bonding layer; a second interconnect structure above the second bonding layer; a second substrate above the second interconnect structure, the second substrate including a memory device; a protective film on the second substrate; a first through-path extending through a portion of the second interconnect structure and a first portion of the second substrate; and a second through-path extending through the protective film and a second portion of the second substrate to contact the top surface of the first through-path, wherein the first diameter of the first through-path is larger than the second diameter of the second through-path. However, although this prior art reduces the connection size through the second through-path, the size of the first through-path is not reduced, and the connection density and parasitic behavior cannot overcome the limitations of the first through-path size, thus no significant improvement is achieved. Summary of the Invention

[0008] Therefore, embodiments of the present invention provide a multilayer stacked chip and a multilayer stacking method based on photolithography equipment to solve at least one problem existing in the prior art.

[0009] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0010] A multilayer stacking method based on photolithography equipment includes: Using a first mask, N base chips with the same structure are fabricated to create identical base connection pads, resulting in N base chips with identical base connection pads. The base chips are respectively the first base chip, the second base chip, ..., and the Nth base chip. Replace the first photomask with the second photomask; Using a first base chip, setting a first mask offset distance, and / or a first offset distance of the first base chip lithography stage, and after exposure, fabricating a first bonding pad to obtain the first chip; Using a second base chip, setting a second mask offset distance, and / or a second offset distance of the second base chip lithography stage, a second bonding pad is fabricated after exposure to obtain a second chip; This process continues until the Nth base chip is used. The offset distance of the Nth mask is set, and / or the offset distance of the Nth base chip lithography stage is set. After exposure, the Nth bonding pad is fabricated to obtain the Nth chip. Among the first chip, the second chip, ..., and the Nth chip, at least one of the connection pads between each chip is different; and / or, at least one of the connection pads between each chip and the connection structure inside the corresponding chip is different from the connection structure inside the corresponding chip.

[0011] In some embodiments, when the connecting pad is an opaque pattern on the first mask and the second mask, the first mask comprises: The graphic area is used to create identical base connection pads; The transition area is a light-transmitting area, and / or has no connection holes that connect to the chip interior with the connection pad layer. This area has no connection pads that connect to the chip interior after overlapping with the exposure pattern of the second mask. The second mask protection zone is an opaque area used to protect the first to Nth connecting pads made by the second mask. The second photomask includes: The graphics area is used to create the first to Nth connecting pads; The transition zone is a light-transmitting zone, used to expose and develop the photoresist that is not involved in the fabrication of the first to Nth connecting pads after the second mask protection zone of the first mask has been exposed. The first mask protection area is an opaque area used to protect the same base bonding pads made from the first mask.

[0012] In some embodiments, the base chip has a connection hole connected to the connection pad below the connection pad, the connection hole being an ultra-deep hole or a connection hole formed by a combination of an ultra-deep hole and a connecting hole communicating with the ultra-deep hole; or the base chip has a connection hole etchable area below the connection pad.

[0013] In some embodiments, a base chip with a connection hole connected to the connection pad under the connection pad is thinned to the required thinning thickness to expose an ultra-deep hole or an etch barrier layer connected to the connection pad. The etch barrier layer has an ultra-deep hole that penetrates the etch barrier layer, or a connecting hole communicating with the ultra-deep hole is further formed on the back side to obtain a thinned chip with a connection hole in the first to Nth layers. Alternatively, a base chip with a connection hole to be etched is located below the connection pad. After the first to Nth chip substrates are thinned to the required thinning thickness or to the etch barrier layer, ultra-deep holes are etched in the connection hole to be etched area on the back side. At least a portion of the ultra-deep holes are connected to the connection pad, or connected to the connection pad through a connecting hole connected to the ultra-deep hole; thus obtaining a thinned chip with connection holes in the first to Nth layers.

[0014] In some embodiments, the thinned chip with connection holes is fabricated with an easy-bonding layer. The easy-bonding layer includes connection structure easy-bonding layers on both the connection hole surface on the back side and the connection pad surface on the front side of the thinned chip with connection holes. Non-connection structure easy-bonding layers are also present on the non-connection hole and non-connection pad areas on the front and back sides of the thinned chip with connection holes. The front connection pad connection structure easy-bonding layer is flush with the front non-connection structure easy-bonding layer, and the back connection hole connection structure easy-bonding layer is flush with the back non-connection structure easy-bonding layer.

[0015] In some embodiments, after activating the bonding layers of the first to Nth thinned chips with interconnecting holes, they are sequentially aligned and stacked, and then bonded to form a three-dimensional stacked chip.

[0016] A multilayer stacking method, based on a first chip, a second chip, ..., and an Nth chip obtained by the method described above; further comprising one and / or multiple other substrates; wherein the other substrates include at least one of other chips, intermediate layers, and carriers, and the other substrates have the easy-bonding layer on at least one side of both the front and back sides, and the surfaces involved in bonding all have the easy-bonding layer; the method includes: After activating the easy bonding layers of the other substrates and the thinned chips with easy bonding layers and connection holes from the first to the Nth layers, the thinned chips with easy bonding layers and connection holes from the first to the Nth layers are sequentially aligned and stacked. One layer and / or multiple layers of other substrates are aligned and stacked with the thinned chips with easy bonding layers and connection holes from the first layer and / or the Nth layer. After stacking multiple layers of other substrates, they are aligned and stacked with the thinned chips with easy bonding layers and connection holes from the first layer and / or the Nth layer. Bonding is then performed to form a three-dimensional stacked chip.

[0017] A multi-layer stacking method is based on a first chip, a second chip, ..., and an Nth chip obtained by the method described above; the method is a method for constructing multi-layer stacked chips based on a photolithography device, wherein the base chip has a connection hole to be etched area under the connection pad; The first to Nth chip substrates with connection holes to be etched under the connection pads are thinned to the required thinning thickness to obtain thinned chips with connection holes to be etched under the first to Nth connection pads.

[0018] In some embodiments, a thinned chip with a connection hole to be etched area is located below the first to Nth connection pads, and the back and front sides of the thinned chip with the connection hole to be etched area below the connection pads have easy bonding layers; wherein, the easy bonding layer on the front side is one of the following forms: The front easy-bond layer covers both the front non-connection pad area and the connection pad area; The non-connecting pad area on the front has a non-connecting structure easy-to-bond layer and is flush with the connecting pad. The non-connecting pad area has a non-connecting structure easy-bonding layer, and the connecting pad has a connecting structure easy-bonding layer, and the non-connecting structure easy-bonding layer and the connecting structure easy-bonding layer are flush.

[0019] In some embodiments, the chip with a thinning chip having a connection hole to be etched under the connection pad with the easy bonding layer is activated. After the easy bonding layers of the first to Nth chips with the easy bonding layers are activated, they are sequentially aligned and stacked, and bonded to form a three-dimensional stacked chip with a connection hole to be etched under the connection pad.

[0020] In some embodiments, the method further includes one and / or multiple layers of other substrates; the other substrates include at least one of other chips, intermediate layers, and carriers, and the other substrates have the easy-bonding layer on at least one side of the front and back surfaces, and the surfaces involved in bonding all have the easy-bonding layer; the method includes: After activating the bonding layers of the other substrates and the thinning chip with the bonding pads of the first to Nth bonding layers having bonding holes under the bonding pads, the thinning chips with the bonding pads of the first to Nth bonding layers having bonding holes under the bonding pads are sequentially aligned and stacked. The one layer and / or multiple layers of other substrates are aligned and stacked with the thinning chip with the bonding pads of the first bonding layers having bonding holes under the bonding pads and / or the thinning chip with the bonding pads of the Nth bonding layers having bonding holes under the bonding pads. After stacking multiple layers of other substrates, they are aligned and stacked with the thinning chip with the bonding pads of the first bonding layers having bonding holes under the bonding pads and / or the thinning chip with the bonding pads of the Nth bonding layers having bonding holes under the bonding pads; bonding is then performed to form a three-dimensional stacked chip with bonding holes under the bonding pads.

[0021] In some embodiments, chip thinning and stacking are performed by thinning followed by stacking, and / or stacking-thinning are performed alternately, wherein the stacking is one or more of back-to-front stacking, back-to-back stacking, and front-to-front stacking.

[0022] In some embodiments, the three-dimensional stacked chip with a connection hole to be etched area under the connection pad also includes ultra-deep hole fabrication. The connection pad is an etching barrier layer. By etching, depositing or growing connection material in the connection hole to be etched area under the connection pad, and removing excess connection material, a connection hole structure of a thinned chip with a connection hole to be etched area under the connection pad and a three-dimensional stacked chip are formed.

[0023] A multilayer stacked chip based on photolithography equipment is fabricated by the method described above.

[0024] To address the shortcomings of existing technologies, this invention employs a first mask to fabricate identical interconnect pads on N base chips with the same structure, resulting in N base chips with identical interconnect pads. A second mask is then used to create different interconnect pads on the same base chips through photolithographic offset settings, fabricating first to Nth chips with different interconnect pads, thus solving the problem of different interconnections required for the same base chips. Through thinning, activation of easily bonded layers, and bonding, a three-dimensional stacked chip is formed. For chips without vias under the interconnect pads (chips with vias to be etched below the interconnect pads), the interconnect pads are used as etch barrier layers for further etching to create vias, forming a three-dimensional stacked chip. Since this invention does not require a µBUMP structure, it can achieve interlayer interconnections in three-dimensional stacked chips at the µm level and smaller, significantly increasing the interlayer via density and reducing parasitics. This significantly increases the interlayer bandwidth of the three-dimensional stacked chip, and because the via size is reduced, the area occupied by the via under the same via is greatly reduced, allowing for an increase in the number of layers to improve the memory chip capacity. Furthermore, due to the significant increase in connection density, complex chips can be broken down into multiple chips (such as splitting the CPU or GPU chip's computing unit and cache unit into one or more computing chips and multiple cache chips). By integrating multiple identical basic chips with other substrates through the method of this invention, the chip integration density can be greatly improved within the same area, thus solving the problem of improving the integration density of complex chips. Attached Figure Description

[0025] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0026] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0027] Figure 1 This is an example diagram illustrating the implementation method of obtaining different connection pads of the same base chip through photolithographic offset settings provided by the present invention; Figure 2 This is an example diagram illustrating the connection method between the connection pad and the base chip provided by the present invention; wherein, Figure 2 (A) is a schematic diagram showing the small connecting hole located at the corner of the connecting pad. Figure 2 (B) is a schematic diagram showing the small connecting hole located next to the connecting pad. Figure 2 (C) is a schematic diagram showing the connecting pad not connected to the small connecting hole; Figure 3 A schematic diagram of the photolithography equipment used in the photolithography technology implementation method provided by the present invention; Figure 4 This is a schematic diagram of the structure of the EUV light source-based lithography equipment provided by the present invention; Figure 5 A schematic diagram of a single exposure area and its alignment structure of the basic chip provided by the present invention; Figure 6 This is a schematic diagram illustrating the pattern area processing of the first and second photomasks using positive resist photoresist and metal bonding pads, and the pattern overlap after repeated exposure and development on the base chip, as provided by the present invention; wherein, Figure 6 Image (A) is a schematic diagram of the graphic area of ​​the first photomask. Figure 6 Image (B) is a schematic diagram of the graphic area of ​​the second photomask. Figure 6 (C)-(E) are schematic diagrams showing the pattern overlap after repeated exposure and development on the base chip, with the first mask and the second mask set at different mask offset distances (and / or the offset distance of the lithography stage); Figure 7 A schematic diagram of a photolithography device used in the photolithography technology implementation method provided by the present invention; Figure 8 This is a schematic diagram of a chip structure with a connection hole below the connection pad provided by the present invention. Figure 8 Figures (A)-(F) show schematic diagrams of several different structural forms of the connecting pad and connecting hole; Figure 9This is a schematic diagram of the thinned structure of a chip with connection holes beneath the connection pads. Figure 9 Figures (A)-(G) and (I) are schematic diagrams of several different structural forms of the connecting pad and connecting hole after thinning; Figure 10 This is a schematic diagram of a thinned chip bonding layer structure with connection holes below the connection pad; Figure 11 This is a schematic diagram of a three-dimensional stacked chip structure formed by bonding. Figure 11 (A)-(C) are schematic diagrams of three-dimensional stacked chips with different structures; Figure 12 This is a schematic diagram of a three-dimensional stacked chip structure formed using front-to-front and front-to-back bonding methods; Figure 13 This is a schematic diagram of a three-dimensional stacked chip formed by using other substrates and the chip of this invention. Figure 13 (A)-(C) are schematic diagrams of different structures of three-dimensional stacked chips; Figure 14 This is a schematic diagram of a chip structure with a connection hole to be etched below the connection pad. Figure 14 (A) is a schematic diagram of the structure when the chip is a conventional semiconductor. Figure 14 (B) is a schematic diagram of the structure of a semiconductor chip with an etch barrier layer; Figure 15 This is a schematic diagram of the structure of a thinned chip with an easily bonded layer containing a connection hole to be etched below the connection pad. Figure 15 (A) is a schematic diagram of the structure when the front easy-bonding layer covers the front non-connecting pad area and the connecting pad area; Figure 15 (B) is a schematic diagram of the structure when the non-connecting pad area on the front has a non-connecting structure that is easy to bond and is flush with the connecting pad; Figure 15 (C) is a schematic diagram of a structure when the non-connecting pad area has a non-connecting structure easy-bonding layer, the connecting pad has a connecting structure easy-bonding layer, and the non-connecting structure easy-bonding layer and the connecting structure easy-bonding layer are flush. Figure 16 This is a schematic diagram of a three-dimensional stacked chip structure with interconnecting holes to be etched below the interconnecting pads, formed by front-back, front-front, and back-back configurations; where... Figure 16 Image (A) is a schematic diagram of a front-back stacking configuration. Figure 16 (B) is a schematic diagram of a front-to-front or back-to-back stacking structure; Figure 17 This is a schematic diagram illustrating the structure of a 3D stacked chip formed by fabricating a 3D stacked chip with connection holes beneath the connection pads and an area to be etched using ultra-deep vias; where... Figure 17 Image (A) shows a structural example of a three-dimensional stacked chip formed by etching ultra-deep holes from the front side of the top-layer chip. Figure 17(B) shows a structural example of a three-dimensional stacked chip formed by etching ultra-deep holes from the back of the underlying chip; Figure 18 This is a schematic diagram of a three-dimensional stacked chip formed with the chip of this invention by using other substrates through ultra-deep holes; Figure 19 This is a schematic diagram illustrating the structure of a three-dimensional stacked chip formed by fabricating a chip with a sacrificial structure through ultra-deep vias; where, Figure 19 Image (A) shows an example of using a bonding pad as an etch barrier layer to etch a sacrificial structure ultra-deep via. Figure 19 (B) shows an example of using a separate layer as an etch barrier layer to etch a sacrificial structure ultra-deep via; Figure 20 Another schematic diagram of a three-dimensional stacked chip structure formed by fabricating a chip with a sacrificial structure through ultra-deep vias; Figure 21 This is a schematic diagram of a three-dimensional stacked chip formed by a bonding method with a sacrificial structure. Figure 22 A schematic diagram of a three-dimensional stacked chip structure formed by sacrificing the connector pads and connector holes; Explanation of reference numerals in the attached figures: 10. Base chip; 40. Thinned chip; 91. Etching barrier layer; 92. Insulating layer; 93. Protective layer; 101. First base chip; 102. Second base chip; 10N. Nth base chip; 201. First chip; 202. Second chip; 20N. Nth chip; 301. Identical base connection pad; 311. Connection structure; 321. Small connection hole; 341. First connecting hole; 351. Second connecting hole; 373. First external connection pad; 374. Second external connection pad; 383. Connection line; 391. First sacrificial structure; 392. Second sacrificial structure; 393. Third sacrificial structure; 400. Stage; 410. First stage; 420. Second stage; 430. Third stage Stage; 440, Fourth stage; 416, First carrier board; 417, Second carrier board; 401, First thinned chip; 402, Second thinned chip; 403, Third thinned chip; 404, Fourth thinned chip; 511, Front connection pad connection structure easy bonding layer; 521, Back connection hole connection structure easy bonding layer; 531, Front non-connection structure easy bonding layer; 541, Back non-connection structure easy bonding layer; 930, First silicon wafer measurement system; 940, Second silicon wafer measurement system; 3012, First connection pad; 3022, Second connection pad; 3032, Third connection pad; 30N2, Nth connection pad; 3011, Same base connection pad as the first chip; 3021, Same base connection pad as the second chip; 30N1, Identical base connection pad for the Nth chip; 3001, First mask pattern; 3002, Second mask pattern; 3031, Connection pad; 331, Connection hole A; 332, Connection hole B; 3321, Connection hole C; 3311, Connection hole D; 3316, Connection hole E; 3331, Connection hole F; 3335, Connection hole G; 3325, Connection hole H; 3314, Connection hole I; 3315, Connection hole J; 3326, Connection hole K; 3336, Connection hole L; 3334, Connection hole M; 3324, Connection hole N; 3332, First ultra-deep via; 3322, Second ultra-deep via; 3361, Third ultra-deep via; 6520, First alignment mark; 6530, Second alignment mark. 9010, Platform; 9100, Light Source; 9101, First Upper and Lower Silicon Wafer System; 9102, Second Upper and Lower Silicon Wafer System; 9200, Mask; 9300, Projection System; 9201, First Mask; 9202, Second Mask; 9210, Mask A; 9220, Mask B; 9310, First Projection System; 9320, Second Projection System; 9510, Primary Alignment Device; 92012, First Mask Transition Area; 92013, Second Mask Protection Area; 92011, First Pattern Area; 92021, Second Mask Pattern Area; 92022, Second Mask Transition Area; 92023, First Mask Protection Area; 92014, First BLIND Masking Structure;92024, Second BLIND shielding structure; 30122, Connecting pad for the second chip. Detailed Implementation

[0028] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Based on the reasons mentioned in the background art, in order to achieve high-density interconnection of multi-layer stacked chips with the same base chip, this application proposes a method for obtaining different interconnect pads of the same base chip through photolithographic offset setting and a multi-layer stacking method.

[0030] In one specific implementation, such as Figure 1 As shown, the method provided by this invention is a multilayer stacking method for obtaining identical base chips with different interconnect pads through photolithography offset settings. This multilayer stacking method based on photolithography equipment includes N base chips 10 with the same structure, and: Using a first mask, N base chips 10 with the same structure are used to fabricate identical base connection pads 301, resulting in N base chips 10 with identical base connection pads 301; for ease of description, each base chip is referred to as the first base chip, the second base chip, ..., and the Nth base chip; Replace the first photomask with the second photomask; Using the first base chip 101, setting the first mask offset distance, and / or the first offset distance of the first base chip lithography stage, exposure is performed to fabricate the first connection pad 3012 and obtain the first chip 201; Using the second base chip 102, setting the second mask offset distance, and / or the second offset distance of the second base chip lithography stage, exposure is performed to fabricate the second connection pad 3022 and obtain the second chip 202; Repeat the above steps multiple times until the Nth base chip 10N is used, set the Nth mask offset distance, and / or the Nth offset distance of the Nth base chip lithography stage, expose, fabricate the Nth connection pad 30N2, and obtain the Nth chip 20N; The first chip, the second chip, ..., the Nth chip, each chip has at least one different connection pad, and / or, each chip has at least one connection pad that is different from the connection structure inside the corresponding chip. The first connection pad, the second connection pad, ..., the Nth connection pad are exemplarily listed as one each, only to distinguish the different connection pad situations of the first chip, the second chip, and the Nth chip. In reality, there is no limit to the number.

[0031] The connection pads are fabricated using the same base connection pad 301 (i.e., the same base connection pad 3011 for the first chip, the same base connection pad 3021 for the second chip, ..., the same base connection pad 30N1 for the Nth chip) using the first mask. This is mainly to allow one connection signal to drive multiple chips simultaneously. The first to Nth chips use different connection pads fabricated using the second mask, primarily because the chip select and other signals between chips are different and need to be distinguished. Visually, if N chips are stacked sequentially from back-side to front-side and connected via connection holes, connection pads in the same position are connected together, while those in different positions are not. In actual stacking, to accelerate stacking efficiency, front-to-back, front-to-front, and back-to-back stacking may be performed. Therefore, the placement of the connection pads needs to be considered in advance during fabrication to address different rotations, mirroring, and other placement issues.

[0032] Taking integrated circuits as an example, the connection between the connector pad and the inside of the chip is generally achieved by creating small connection holes at appropriate locations on the corresponding connector pads to connect to the inside of the chip, such as... Figure 2 As shown, the corner of the same base connection pad 3011 of the first chip (such as...) Figure 2 (as shown in (A)) or next to (such as) Figure 2 As shown in (B), a suitable location is selected to fabricate the connection structure 311. The connection structure 311 is then connected to the small connection hole 321, thus connecting the same base connection pad 3011 of the first chip to the internal circuitry of the integrated circuit. It should be noted that if a connection pad needs to be connected to the inside of the integrated circuit, it is connected using the small connection hole 321. If only one chip in the stacked chips is connected to the outside, and this chip does not need to be connected to the inside of the chip, then the connection structure 311 is not fabricated when fabricating the connection pad. The same base connection pad 3011 of the first chip is not connected to the small connection hole 321, forming a transition structure, such as... Figure 2 As shown in (C). Thus, the distinction between connection pads can be made not only by whether the connection pads themselves are made or not, but also by whether or not a connection structure 311 is made, even if all connection pads are made. In this case, for the first chip, the second chip, ..., the Nth chip, at least one connection pad is different between each chip, and / or, for each chip, at least one connection pad in the corresponding chip's internal connection structure is different from the corresponding chip's internal connection structure 311; or, in other words, if the pad structures are the same but the fine connection structure is used for distinction, the effect is consistent in terms of whether or not a connection is made.

[0033] Here, if the chip connection pads are not differentiated, the chips cannot be distinguished and used because the base chips are identical. When different connection pads exist between chips, such as different chip select signal connection pads, even if multiple chips with the same connection pad are connected together, only the chip select signal chip can operate. In this case, among multiple chips connected together with the same connection pad, only the chip select signal chip's connection pad will function. This achieves chip differentiation and use in a 3D integrated chip with more than 10 layers of the same base chip stacked together. The actual situation regarding "same" and "different" is much more complex. It can be that most of them are the same (each identical base chip must have at least one connection pad or a finely connected structure of the connection pads to be distinguishable), or several are the same but most are different, or all are different. The specific setting depends on the actual functional requirements.

[0034] In the specific implementation of photolithography, such as Figure 3 The diagram shown is a structural diagram of the photolithography equipment used in the implementation method of the photolithography technology provided in this application embodiment. The photolithography equipment includes: Light source 9100 is used to provide the exposure beam required for photolithography. This light source 9100 can be, but is not limited to, a light source generated by a mercury lamp, a light source generated by an excimer laser, or an extreme ultraviolet (EUV) light source. Mercury lamps can emit light of multiple discrete wavelengths, including g-lines (436 nm) and i-lines (365 nm), which are suitable for photolithography processes with different resolution requirements. Excimer lasers can generate shorter wavelengths of ultraviolet light, such as KrF (248 nm) and ArF (193 nm). Shorter wavelengths help improve photolithography resolution and are suitable for fine patterning requirements. The wavelength of the EUV light source is 13.5 nm, much shorter than that of traditional DUV light sources. This allows for photolithography at extremely high resolution, suitable for state-of-the-art semiconductor manufacturing processes. Methods for generating EUV light sources include, but are limited to, converting the material into a plasma state having at least one element with one or more emission lines in the EUV range (e.g., xenon, lithium, or tin).

[0035] Mask 9200 is used to provide the preset pattern required for exposure.

[0036] The projection system 9300 is used to transfer the preset pattern on the mask 9200 onto the base chip 10 to be exposed.

[0037] Stage 400 is used to load the base chip 10 to be exposed and to complete the stepping motion of the base chip 10.

[0038] exist Figure 3In the lithography apparatus shown, the light source 9100 forms an exposure beam through the illumination system. The exposure beam passes through the mask 9200 and transfers the preset pattern on the mask 9200 to the base chip 10 mounted on the stage 400 through the projection system 9300. Then, photolithography is performed on the photoresist material to form the exposure area pattern.

[0039] It should be noted that if the light source 9100 is an EUV light source, and the projection system 9300 is a reflective projection system, such as... Figure 4 The diagram shown is a structural diagram of a lithography device based on an EUV light source provided in an embodiment of this application. Figure 4 In the lithography apparatus shown, the light source 9100 forms an exposure beam through an illumination system. This beam passes through the mask 9200, and a reflective projection system 9300 reflects a preset pattern from the mask 9200 onto the base chip 10 mounted on the stage 400. Then, photolithography is performed on the photoresist material to form the exposure area pattern. This avoids the problem of extreme ultraviolet (EUV) light being easily absorbed by light-transmitting materials, preventing the exposure beam from reaching the base chip.

[0040] If the light source 9100 is a mercury lamp or an excimer laser, the space between the projection system 9300 and the base chip 10 is filled with an immersion liquid (such as deionized water). Compared to the traditional photolithography method where the exposure beam directly reaches the silicon wafer surface from the projection system, this embodiment increases the refractive index of the medium by filling with an immersion liquid, thereby increasing the numerical aperture NA of the optical system and reducing the minimum size of the pattern.

[0041] The existing chip pattern on the base chip 10 can be one or more of the following: integrated circuit pattern, optical path pattern, microfluidic path, metal wiring, and sensor pattern. The type of integrated circuit can include, but is not limited to, integrated circuits integrating electrical functions, integrated circuits integrating optical-optoelectronic functions, and integrated circuits integrating sensor functions. In other words, the photolithography technology provided in this application embodiment can be applied to integrated circuits with the above-mentioned functions to achieve large-area, high-density interconnection of the chip. The type of integrated circuit can be specifically selected according to actual needs; this application does not specifically limit this selection.

[0042] The base chip 10 is characterized by its own features or by a primary alignment device on the base chip (such as...). Figure 3 , Figure 4 as well as Figure 5 The primary alignment device 9510 shown performs initial positioning of the base chip 10. For example... Figure 5As shown, the base chip 10 has a first alignment mark 6520. Taking a NIKON lithography machine as an example, it can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA). One or more first alignment marks 6520 can be provided on the base chip 10. The first alignment marks 6520 can be set in the dicing track to avoid affecting the functional areas of the chip, and are mainly used for the precise positioning of the base chip 10.

[0043] like Figure 5 As shown, the base chip also has a second alignment mark 6530, similar to the first alignment mark 6520. The second alignment mark 6530 can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA), or an alignment mark designed for the alignment system of the lithography equipment involved in this application. One or more second alignment marks 6530 can be provided on the base chip 10. The second alignment marks 6530 can be provided in the dicing path to avoid affecting the functional areas of the chip. The second alignment mark is mainly used for the precise alignment of each exposure area of ​​the base chip.

[0044] For the first mask of this application, when its mask layout is consistent with other masks of the base chip 10, normal alignment and exposure can be used to complete the transfer of the first mask pattern to the base chip 10.

[0045] When the base chip exposed by the first mask is further exposed using the second mask of this application, such as Figure 1As shown, assuming normal alignment and exposure, the pattern of the second mask can be transferred to the first base chip 101, i.e., the pattern of the first connection pad 3012 on the first base chip 101. However, if the pattern of the second connection pad is to be fabricated on the second base chip, and if the second mask and the second base chip 102 are not aligned or offset, the connection pad 30122 of the second chip will be identical to that of the first chip 201. To overcome this problem, taking the fabrication of the second chip-second connection pad as an example, the second base chip 102 needs to be used, the offset distance of the second mask needs to be set, and / or the second offset distance of the lithography machine stage needs to be set, exposure is performed, the second connection pad 3022 is fabricated, and the second chip 202 is obtained. Here, the offset distance of the second mask can be set for alignment offset when loading the mask; the offset distance of the lithography machine stage can also be set for offset when aligning the base chip 10; or both the mask and the chip stage can be set with offset distances, and the corresponding alignment effect can be obtained through comprehensive offset. No specific limitation is made here. It should be noted that here it is assumed that the graphic position corresponding to the second mask is exactly the position of the first connection pad 3012 of the first chip 201. In this case, the first mask offset distance and the first offset distance of the second mask are both set to zero. Otherwise, the actual values ​​are set according to the actual needs and the layout of the second mask.

[0046] In specific implementation, after the first mask is used to fabricate the same basic connection pads on N basic chips with the same structure and obtain N basic chips with the same basic connection pads, an independent photolithography program or independent subroutine is made for the second mask corresponding to the first to N different chips. Taking the fabrication of the second chip 202 as an example, before photolithography begins, the offset distance of the second mask is set in the photolithography program, and / or the second offset distance of the second base chip 102 on the photolithography machine stage. When loading the second mask, if the second offset distance is set to a non-zero value, the mask is loaded at the set second offset distance. When loading the second base chip to be exposed, it is transferred from the crystal boat to the stage of the photolithography equipment using a robotic arm or vacuum adsorption system. At this time, the second chip 202 is roughly placed at a certain position on the stage. Then, the second chip 202 is scanned by a high-resolution camera or other sensors installed on the photolithography equipment. Preliminary alignment is performed by the primary alignment device 9510 or the shape features of the second chip 202 itself, and precise alignment of the second chip 202 is performed by one or more first alignment marks 6520, completing the pre-exposure preparation work, such as... Figure 5As shown. Then, stepping to the first exposure area requiring exposure, precise alignment is performed using the second alignment mark 6530. If a second offset distance of the lithography machine stage is set (i.e., not zero), the base chip mounted on the stage is offset by the second offset distance of the lithography machine stage, and exposure occurs. Regardless of whether the second mask offset distance of the second mask is set, and / or the second offset distance of the second base chip lithography machine stage is set, the position of the second connection pad in the current exposure area of ​​the second chip corresponds to the position of the second connection pad 3022. Then, stepping to the next area to be exposed, the precise alignment, offset, and exposure using the second alignment mark 6530 are repeated to complete the exposure of each exposure area of ​​the second chip 202 and the fabrication of each connection pad corresponding to the second chip 202 (including the same base connection pad and the second connection pad).

[0047] Repeat the above steps multiple times until the Nth base chip 10N is used, set the offset distance between the second mask and the Nth mask, and / or the Nth offset distance of the Nth base chip 10N on the lithography stage, expose, fabricate the Nth connection pad, and obtain the Nth chip 20N; The first chip 201, the second chip 202, ..., the Nth chip 20N, each chip has at least one different connection pad, and / or, at least one connection pad in the connection structure between each chip and the corresponding chip's internal connection structure is different from the corresponding chip's internal connection structure.

[0048] Since this invention relates to a single photoresist coating process, two photomasks, and corresponding two exposure processes, if the pad pattern on the photomask is a transparent pattern, then there is no need to further process the first and second photomasks by repeatedly exposing them to the same photoresist. For example, in the case of fabricating metal pads for integrated circuits using a negative photoresist (photoresist retained after exposure) process, the pad area is the final photoresist retention area. During exposure, the exposed portion of the negative photoresist cross-links and solidifies, becoming more difficult to dissolve in the developer. That is, the unexposed portion of the photoresist is removed by the developer, while the exposed portion remains on the wafer. In this case, as mentioned above, only the pads need to be fabricated using the first and second photomasks; there is no need for further processing by repeatedly exposing the first and second photomasks to the same photoresist. Alternatively, if the photoresist used is a positive photoresist, the parts exposed to light during exposure will undergo chemical changes, making these parts easier to dissolve with the developer. In other words, the photoresist in the exposed areas will be removed, while the unexposed areas will remain. In this case, if the bonding pad is the part to be etched, such as the liquid / gas flow channel connection between chips in a microfluidic system, this also falls under the category of the bonding pad pattern being a transparent pattern on the photomask. Therefore, there is no need to repeat the exposure of the first and second photomasks on the same photoresist for further processing.

[0049] In some embodiments, when the connecting pad is an opaque pattern on the first mask and the second mask, the first mask comprises: The graphic area is used to create identical base connection pads; The transition area is a light-transmitting area, and / or has no connection holes that connect to the chip interior with the connection pad layer. This area has no connection pads that connect to the chip interior after overlapping with the exposure pattern of the second mask. The second mask protection zone is an opaque area used to protect the first to Nth connecting pads made by the second mask. The second photomask includes: The graphics area is used to create the first to Nth connecting pads; The transition zone is a light-transmitting zone, used to expose and develop the photoresist that is not involved in the fabrication of the first to Nth connecting pads after the second mask protection zone of the first mask has been exposed. The first mask protection area is an opaque area used to protect the same base bonding pads made from the first mask.

[0050] Specifically, in another scenario, where positive photoresist is used and the pad pattern on the photomask is opaque, such as when using positive photoresist to fabricate metal pads for integrated circuits, if no special treatment is performed—that is, only the opaque areas of the pads are preserved while the rest are made transparent—the first photomask will expose and develop the area of ​​the second photomask's pads that requires photoresist on the same photoresist, or the second photomask will expose and develop the pads already made on the first photomask, ultimately leaving no pattern. Furthermore, because the second photomask requires multiple alignment and offset processes, the position of the pad pattern on the second photomask on the base chip, relative to the same base pad pattern on the first photomask, is not fixed. Figure 1 The first base chip 101, the second base chip 102, ..., the Nth base chip 10N are shown. If the entire area of ​​the non-connector pad pattern on the first mask is set to opaque, and the entire area of ​​the non-connector pad pattern on the second mask is also set to opaque, then a metal problem will occur in the non-connector pad area of ​​the base chip (e.g., the connection pad 30122 position of the second chip). As mentioned above, for positive photoresist, and the reserved area is the opaque area on the mask, if the metal connector pads of the integrated circuit are fabricated using a positive photoresist process, it is necessary to perform one photoresist coating, two masks, and two corresponding exposure processes to repeatedly expose the first and second masks for mask pattern processing.

[0051] In this situation, as mentioned above, when the connecting pad is an opaque pattern on the photomask, such as... Figure 6As shown in (A), the first mask 9201 includes a first pattern area 92011 for fabricating identical base connection pads 301, wherein the first mask pattern 3001 corresponding to the identical base connection pads 301 is opaque, and the non-connection pad area of ​​the first pattern area 92011 is transparent; the first mask transition area 92012 is transparent and / or has no small connection holes connected to the chip interior, so that after overlapping with the exposure pattern of the second mask, this area has no connection pads connected to the chip interior; the second mask protection area 92013 is an opaque area for protecting the first to Nth connection pads fabricated by the second mask; in the non-mask pattern area, a first BLIND shielding structure 92014 is also included, which is an opaque area for blocking light from passing through the first mask 9201 and damaging the connection pads fabricated on the base chip. Figure 6 In section (B), the second mask 9202 includes a second mask pattern area 92021 for fabricating the first to Nth connection pads, wherein the second mask pattern 3002 corresponding to the fabrication of the first connection pads 3012 to the Nth connection pads 30N2 is opaque, while the non-connection pad area of ​​the second mask pattern area 92021 is transparent; the second mask transition area 92022 is a transparent area, used to expose and develop away the photoresist that is not involved in the fabrication of the first connection pads 3012 to the Nth connection pads 30N2 after exposure of the second mask protection area 92013 of the first mask 9201; the first mask protection area 92023 is an opaque area, used to protect the same base connection pads 301 fabricated by the first mask 9201; in the non-mask pattern area, a second BLIND shielding structure 92024 is also included, which is an opaque area, used to block light from passing through the second mask 9202 and damaging the connection pads fabricated on the base chip 10.

[0052] The upper edge of the first mask transition area 92012 must cover the maximum value of the upward offset of the second mask transition area 92022 (the corresponding alignment offset distance generated by the lithography stage); the lower edge of the first mask transition area 92012 must cover the maximum value of the downward offset of the second mask transition area 92022 (the corresponding alignment offset distance generated by the lithography stage). This is to prevent the second mask 9202 from offsetting (or the corresponding alignment offset distance generated by the lithography stage) and creating connection structures connected to the chip interior other than the first to Nth connection pads. Furthermore, the second mask protection area 92013 of the first mask can meet the requirements for the second mask 9202 to create the first to Nth connection pads.

[0053] Regardless of whether the second mask transition area 92022 is offset upwards (or by the corresponding alignment offset distance generated by the lithography stage) to its maximum value or downwards (or by the corresponding alignment offset distance generated by the lithography stage) to its maximum value, it can completely cover the area of ​​the second mask protection zone 92013 of the first mask 9201 that is not covered by the second mask pattern area 92021. This is used to fully expose the unexposed photoresist remaining on the unexposed photoresist on the second mask protection zone 92013 of the first mask 9201 after the first connection pad 3012 (first chip), or the second connection pad 3022 (second chip), ..., or the Nth connection pad 30N2 (Nth chip) is fabricated on the unexposed photoresist retained on the base chip 10.

[0054] To prevent additional patterns from being generated during lithography alignment, the transition area 92012 of the first mask can be made slightly larger than the maximum value of the upward offset (or the corresponding alignment offset distance generated by the lithography stage) or downward offset (or the corresponding alignment offset distance generated by the lithography stage) of the transition area 92022 of the second mask (the left and right sides can also be slightly larger). The maximum value of the upward offset (or the corresponding alignment offset distance generated by the lithography stage) or downward offset (or the corresponding alignment offset distance generated by the lithography stage) of the transition area 92022 of the second mask covers an area slightly larger than the second mask protection area 92013 of the first mask 9201 (the left and right sides can also be slightly larger). If the requirements for fabricating the bonding pad pattern are met, the coverage area can be... Figure 6 As shown in (A), the second mask protection zone 92013 of the first mask 9201 is reduced by 1µm; and / or the transition zone 92012 of the first mask is expanded by 1µm.

[0055] As mentioned above, since this invention relates to a process of one coating, two photomasks, and corresponding two exposures, this application can further use a multi-stage or even multi-photomask stage lithography machine for lithography, thus achieving a more efficient lithography process.

[0056] Specifically, such as Figure 7 The diagram shown is a structural diagram of another example of the photolithography equipment used in the implementation method of the photolithography technology provided in this application embodiment. The photolithography equipment includes one stage (e.g., the first stage 410), or two stages (e.g., the first stage 410 and the third stage 430), or three stages (e.g., the first stage 410, the second stage 420, and the third stage 430), or four stages (e.g., the first stage 410, the second stage 420, the third stage 430, and the fourth stage 440). When there are two stages (e.g., the first stage 410 and the third stage 430), both stages are loaded with the base chip 10. Figure 7In the example, a first base chip 101 is mounted on a first stage 410, and a second base chip 102 is mounted on a third stage 430. The two stages alternately move under the first projection system 9310 to complete the exposure. Furthermore, when there are two stages, the lithography equipment is equipped with an independent first silicon wafer measurement system 930. Although this method requires the mask to be loaded twice or separately on different lithography machines, the loading of the base chip and the lithography of the base chip can be performed simultaneously, which can nearly double the lithography efficiency.

[0057] In practical implementation, for a single photolithography machine with a mask worktable, it is only necessary to load the first mask 9201 onto the first photolithography machine and the second mask 9202 onto the second photolithography machine. The photolithography program or subroutine of the second photolithography machine can be changed for each batch of chips from the first to the Nth chip.

[0058] Furthermore, such as Figure 7 As shown, the photolithography equipment includes two mask stages, one for mask A9210 and the other for mask B9220. Each mask stage is equipped with an independent projection system. Figure 7 In the example, the stage corresponding to mask A9210 corresponds to the first projection system 9310, and the stage corresponding to mask B9220 (it can be understood that there are two masks here, which are named mask A and mask B respectively for ease of description, where the reference numeral for mask A is 9210 and the reference numeral for mask B is 9220) corresponds to the second projection system 9320. Thus, the first mask 9201 can be mounted on the stage corresponding to mask A9210, and the second mask 9202 can be mounted on the stage corresponding to mask B9220.

[0059] In the case where the photolithography equipment includes two mask stages and comprises one stage (e.g., the first stage 410), two stages (e.g., the first stage 410 and the third stage 430), three stages (e.g., the first stage 410, the second stage 420, and the third stage 430), or four stages (e.g., the first stage 410, the second stage 420, the third stage 430, and the fourth stage 440), the one, two, three, or four stages are respectively moved to the projection systems corresponding to the two mask stages (respectively...). Figure 7 Exposure under the first projection system 9310 and the second projection system 9320.

[0060] Furthermore, such as Figure 7As shown, when the lithography equipment includes two mask stages and three stages (such as the first stage 410, the second stage 420, and the third stage 430) or four stages (such as the first stage 410, the second stage 420, the third stage 430, and the fourth stage 440), the lithography equipment also includes two upper and lower silicon wafer systems (respectively...). Figure 7 The first upper and lower silicon wafer system 9101 and the second upper and lower silicon wafer system 9102) and two silicon wafer measurement systems (respectively) Figure 7 The first silicon wafer measurement system 930 and the second silicon wafer measurement system 940 in the process.

[0061] In contrast, in the case of only one silicon wafer measurement system (such as the first silicon wafer measurement system 930), assuming there are three stages (such as the first stage 410, the second stage 420, and the third stage 430), where the first stage 410 and the second stage 420 have their wiring in front and the third stage 430 has its wiring in the back, since there is only one silicon wafer measurement system, the wiring system needs to be bypassed. The first stage 410 needs to be moved to the left of the first silicon wafer measurement system 930 so that the second stage 420 can be moved to the measurement position. If the first stage 410 is moved below the second projection system 9320, then the second stage 420 needs to be moved to the right of the second projection system 9320.

[0062] Using two upper and lower silicon wafer systems (such as the first upper and lower silicon wafer system 9101 and the second upper and lower silicon wafer system 9102) and two silicon wafer measurement systems (such as the first silicon wafer measurement system 930 and the second silicon wafer measurement system 940), taking four stages (such as the first stage 410, the second stage 420, the third stage 430, and the fourth stage 440) as an example, the third stage 430 and the first stage 410 use the first silicon wafer measurement system 930 and the first upper and lower silicon wafer system 9101, with the wiring system one in front (third stage 430) and one behind (first stage 410); the fourth stage 440 and the second stage 420 use the second silicon wafer measurement system 940 and the second upper and lower silicon wafer system 9102, with the wiring system one in front (second stage 420) and one behind (fourth stage 440). Throughout the process, the photomasks (such as photomask A9210 and photomask B9220) and the projection systems (such as the first projection system 9310 and the second projection system 9320) are shared resources. Through reasonable stage rotation and path planning, it can be ensured that each stage can smoothly perform measurement, film loading / unloading preparation, and projection exposure operations without operational interruptions or delays caused by path conflicts.

[0063] It is evident that when the lithography equipment includes two mask worktables and three or four stages, and when the lithography equipment includes two upper and lower silicon wafer systems and two silicon wafer measurement systems, mutual interference between the wiring systems can be effectively avoided, thereby improving the flexibility and efficiency of the lithography equipment and ensuring that each stage can smoothly perform measurement, preparation, and projection exposure actions.

[0064] For a lithography machine with two mask stages, simply load the first mask 9201 onto the mask stage corresponding to mask A9210 and the second mask 9202 onto the mask stage corresponding to mask B9220. Then, for each batch of chips (first chip, second chip, up to Nth chip), simply change the lithography program or subroutine on the stage corresponding to mask B9220.

[0065] It should be understood that the left, right, front, and back mentioned above are all relative, and in actual operation, the platform runs on platform 9010.

[0066] The base chip 10 has a connection hole below the connection pad that connects to the connection pad. The connection hole is an ultra-deep hole or a connection hole formed by a combination of an ultra-deep hole and a connecting hole communicating with the ultra-deep hole; or the base chip 10 has a connection hole to be etched area below the connection pad.

[0067] Figure 8 This illustrates an example of a chip structure with connection holes beneath the connection pads for connection to the pads. For example... Figure 8 As shown in (A), for example, in a traditional bulk silicon process, the first chip has a connection hole A331 below the same basic connection pad 3011, while the connection hole B332 does not participate in the inter-chip connection in this chip, so no connection pad is made. Or as... Figure 8 (C) Figure 8 As shown in (E), this illustrates a chip structure with a semiconductor structure (such as a silicon-on-insulator structure) having an etch barrier layer and interconnecting vias beneath the pads. The etch barrier layer 91 of the semiconductor structure with the etch barrier layer can serve as a barrier layer for substrate etching, used for ultra-thin semiconductor thinning using etching methods. Connecting vias A331 are located beneath the same basic interconnecting pads 3011 of the first chip. Connecting vias A331 may or may not penetrate the etch barrier layer 91, depending primarily on subsequent processes. The connecting vias A331 are ultra-deep vias, such as... Figure 8 (A) Figure 8 (C) Figure 8 The connecting hole A331 in (E) is formed by a combination of an ultra-deep hole and a connecting hole communicating with the ultra-deep hole, such as... Figure 8 (B) Figure 8 (D) Figure 8The connection hole A331 in the middle (F) forms a connection hole through the first connecting hole 341 and connects to the same base connection pad 3011 of the first chip. Even as Figure 9 (C) Figure 9 (D) Figure 9 As shown in (E) Figure 8 The structure shown is further connected by a second connecting hole 351.

[0068] In some embodiments, a base chip with a connection hole connected to the connection pad under the connection pad is thinned to the required thinning thickness to expose an ultra-deep hole or an etch barrier layer connected to the connection pad. The etch barrier layer has an ultra-deep hole that penetrates the etch barrier layer, or a connecting hole communicating with the ultra-deep hole is further formed on the back side to obtain a thinned chip with a connection hole in the first to Nth layers. Alternatively, a base chip with a connection hole to be etched is located below the connection pad. After thinning the first to Nth chip substrates to the required thinning thickness or to the etch barrier layer, ultra-deep holes are etched in the connection hole to be etched area on the back side. At least a portion of the ultra-deep holes are connected to the connection pads, or connected to the connection pads through connecting holes connected to the ultra-deep holes, to obtain thinned chips with connection holes in the first to Nth layers.

[0069] Specifically, the base chip with connection holes below the connection pads is thinned to the required thickness. This exposes ultra-deep vias or etch stop layers connected to the connection pads. The etch stop layer contains ultra-deep vias that penetrate it, or a connecting via is further fabricated on the back side to communicate with the ultra-deep vias, resulting in a thinned chip with connection holes below the first to Nth layers. An example of the thinned structure after removing the connection holes below the base chip is shown below. Figure 9As shown. The advantage of using the first connecting via 341 and the connecting via A331 on the front side to form a connecting via is that it reduces the area of ​​the connecting via on the chip device layer and / or wiring layer, reducing the impact of the connecting via on the wiring of the integrated circuit (taking an integrated circuit as an example). The advantage of using the second connecting via 351 is that it can create a deformation via, providing the low-temperature plastic deformation required for direct chip bonding, reducing the adverse stress-strain effect of the connecting via A331 on the thinned chip 40. Below the connecting pad is a base chip with connecting vias connected to the connecting pad. As mentioned earlier, the connecting vias can be made during the fabrication of the base chip, or they can be formed by etching ultra-deep vias in the area to be etched on the back side after the base chip substrate is thinned to the required thinning thickness or to the etch stop layer. At least a portion of these ultra-deep vias are connected to the connecting pads, or connected to the connecting pads through connecting vias connected to the ultra-deep vias, to obtain thinned chips with connecting vias from the first to the Nth. Because the interconnect pads implemented using this method can distinguish between different base chips used for 3D stacking of the same type, base chips with interconnect holes connected to the interconnect pads can also be fabricated by etching ultra-deep holes from the back side of the base chip with interconnect holes to be etched below the interconnect pads. In the method of etching ultra-deep holes through the back-side interconnect hole etchable area, each identical base chip can have the same hole etched at once. The interconnect pads act as etching barriers to obtain an etching stop signal and stop the etching. Thus, a certain number of interconnect holes will not be connected to the interconnect pads. Figure 10 The connecting hole E3316 is shown in the figure.

[0070] In some embodiments, the thinned chip with connection holes is fabricated with an easy-bonding layer. The easy-bonding layer includes connection structure easy-bonding layers on both the connection hole surface on the back side and the connection pad surface on the front side of the thinned chip with connection holes. Non-connection structure easy-bonding layers are also present on the non-connection hole and non-connection pad areas on the front and back sides of the thinned chip with connection holes. The front connection pad connection structure easy-bonding layer is flush with the front non-connection structure easy-bonding layer, and the back connection hole connection structure easy-bonding layer is flush with the back non-connection structure easy-bonding layer.

[0071] The thinned chip with a connection hole below the connection pad, such as Figure 10As shown, the back side of the thinned chip 40 with the connection hole A331 and the front side with the same basic connection pad 3011 are both fabricated with a back connection hole connection structure easy-bonding layer 521 and a front connection pad connection structure easy-bonding layer 511. The front non-connection pad and back non-connection hole areas of the thinned chip have a front non-connection structure easy-bonding layer 531 and a back non-connection structure easy-bonding layer 541. The front connection pad connection structure easy-bonding layer 511 is flush with the front non-connection structure easy-bonding layer 531; the back connection hole connection structure easy-bonding layer 521 is flush with the back non-connection structure easy-bonding layer 541. Currently, one of the main methods for solving high-density interconnection in three-dimensional stacked chips is bonding. Bonding requires the fabrication of easy-bonding layers, which are characterized by the ability of two attached easy-bonding layers to bond tightly at low temperatures. This achieves mechanical and electrical (or optical) connections between the chips. The easy-bonding layer can be a fusible material or a solid bonding material; or it can be a commonly used chip material (such as copper, low-melting-point glass, etc.), and the easy-bonding surface (atomic-level thickness easy-bonding layer) can be created using methods such as polishing. It should be noted that when the connector pad is a solid material structure, an easy-bonding layer for the connector structure is required, while when the connector pad is a cavity structure, such as the microfluidic connector microgroove structure, an easy-bonding layer for the connector structure is not required; or when the connector pad is a solid material structure, but the requirement for the connection strength between the connector hole and the connector pad is low, such as when the connector hole and the connector pad are sacrificial structures, an easy-bonding layer for the connector structure can also be decided whether to create one based on actual needs.

[0072] The thinned chip with easy-bonding layers and connecting holes is formed by activating the easy-bonding layers of the first to Nth thinned chip with easy-bonding layers and connecting holes, then sequentially aligning and stacking them for bonding to form a three-dimensional stacked chip. For example... Figure 11 As shown, existing bonding processes require stringent conditions, generally necessitating activation before stacking and bonding. Figure 11 As shown in (A), the first thinning chip 401, the second thinning chip 402, and the third thinning chip 403 are stacked together by bonding. Connecting holes D3311, C3321, and F3331 form interconnecting holes. Signals can be transmitted through connecting hole F3331 to the three chips: the third thinning chip 403, the second thinning chip 402, and the first thinning chip 401, using the functions of each chip according to the settings. Connecting hole F3331 is an ultra-deep via; alternatively, connecting holes N3324 and I3314 can connect the first thinning chip 401 and the second thinning chip 402; or connecting holes G3335 and H3325 can transmit signals to the third thinning chip 403 and the second thinning chip 402. Here, it is assumed that the connecting pads are all connected to the internal circuitry, and the connection method is as follows... Figure 2 (A) or Figure 2As shown in (B). If the connection pad of the third thinning chip 403 and the connection hole G3335 is not connected to the internal circuitry of the third thinning chip 403, the method is as follows: Figure 2 The example in (C) is as follows: Figure 11 In the case of connection (C), the signal is transmitted through connection holes G3335, H3325, and J3315 only to the internal circuits of the second thinning chip 402 and the first thinning chip 401, while the signal is transmitted through connection hole L3336 to the internal circuit of the first thinning chip 401. It should be noted that... Figure 11 The structural example in (A) is a structure in which an external signal connection pad extends from the back of the third thinned chip 403, while Figure 11 The middle (B) is the structure of the external signal connection pad from the front of the first thinned chip 401, which can be determined according to the actual needs.

[0073] It is understood that there are multiple connecting holes here. For ease of description, they are named connecting hole A, connecting hole B, connecting hole C, connecting hole D, connecting hole E, connecting hole F, connecting hole G, connecting hole H, connecting hole I, connecting hole J, connecting hole K, connecting hole L, connecting hole M, and connecting hole N, respectively. Among them, the reference numeral for connecting hole A is 331, the reference numeral for connecting hole B is 332, the reference numeral for connecting hole C is 3321, the reference numeral for connecting hole D is 3311, the reference numeral for connecting hole E is 3316, the reference numeral for connecting hole F is 3331, the reference numeral for connecting hole G is 3335, the reference numeral for connecting hole H is 3325, the reference numeral for connecting hole I is 3314, the reference numeral for connecting hole J is 3315, the reference numeral for connecting hole K is 3326, the reference numeral for connecting hole L is 3336, and the reference numeral for connecting hole M is 3334.

[0074] exist Figure 11 (A) Figure 11 In section (B), no connecting pads were fabricated as part of the transition structure (e.g., ...). Figure 11 (A) Connector hole K3326 is not fabricated with a connector pad on the second thinned chip 402, and connector hole E3316 is not fabricated with a connector pad on the first thinned chip 401. This can reduce parasitic connections in the connection structure. However, to achieve better mechanical or thermal consistency, connector pads can actually be fabricated without the need for a transition structure, as shown in the example. Figure 2 As shown in (C), no connection structure 311 is made to connect with the small connection hole 321, that is, no connection is made to the interior. The advantage of this approach is that the connection pads of each identical base chip are consistent, only the connection structure 311 will be different, resulting in better chip consistency, and the parasitic connection holes and connection pads are basically the same. The disadvantage is that the parasitic connection of some connection holes, which originally only involved a few holes and a few connection pads, now requires the parasitic connection holes and connection pads of all identical base chips to be stacked. Figure 11 The stacked structure obtained by using the method of whether or not to create a connection structure 311 in (B) is as follows: Figure 11 As shown in (C).

[0075] It needs to be explained that, although Figure 2 The method shown in (C) of not fabricating the connection structure 311 and connecting the small connection hole 321 can solve the problem of having a connection pad but not being connected to the inside. However, the second mask used in the method of this application is used to fabricate the first to Nth connection pads. The mask used is the same. If the second mask contains each connection pad structure and related connection structure, the offset will inevitably lead to the phenomenon that the area of ​​the second mask that was originally exposed but not exposed this time (such as the first connection pad area of ​​the second chip) has the same basic connection pad 3011 structure without the first chip.

[0076] In order to obtain Figure 11 As described above, when the connection pads on the mask are transparent patterns, the first mask only needs to fabricate the same basic connection pads and also fabricate the first to Nth connection pads without connection structure 311 on the first to Nth basic chips (the first to Nth connection pads without connection structure 311 are fabricated on each chip, that is, the structural pattern of the first to Nth connection pads without connection structure 311 is also fabricated on the first mask). The second mask can then complete the fabrication of the connection structure 311 of the corresponding first to Nth connection pads of the first to Nth basic chips (such as the connection structure of the first connection pad of the first chip).

[0077] When the connecting pad is an opaque pattern on the photomask, in order to obtain Figure 11 In the (C) effect, one method is to use a first mask to fabricate the same basic connection pads, and also to fabricate the first to Nth connection pads containing connection structures 311 on the first to Nth basic chips (each chip has the first to Nth connection pads containing connection structures 311 fabricated, that is, the structural pattern of the first to Nth connection pads containing connection structures 311 is also fabricated on the first mask). The second mask completes the fabrication of the connection structures 311, that is, the connection structures 311 of the first to Nth connection pads that do not need to be connected are destroyed (exposed and developed away), while the connection structures 311 of the first to Nth connection pads that need to be connected to the inside of the chip are retained. If this method is used to fabricate the second chip, the connection structures 311 of the first and third to Nth connection pads that have been fabricated by the first mask are destroyed (exposed and developed away), while the connection structure 311 of the second connection pad is retained. And so on, without going into detail. The specific implementation method is to fabricate the same basic connection pads on the first mask ( Figure 6 The first graphic area 92011 shown in the figure), the corresponding graphic of the first to Nth connecting pads ( Figure 6The second mask protection area 92013 shown in the diagram is fabricated in the area shown (including the connection structure 311). The second mask pattern area 92021 is used to fabricate the connection pad (including the connection structure 311) protection structure, or the entire area is made opaque to protect the first, second, ..., or Nth connection pads from damage during exposure. The second mask transition area 92022 is used to fabricate the connection pad (excluding the connection structure 311) protection block (opaque) and the connection structure 311 destruction structure (transparent) (e.g., all except the connection pad protection block are transparent). This achieves the effect that the first to Nth connection pads fabricated in the area shown in the second mask protection area 92013 are preserved, except for the Mth connection pad (including the connection structure 311) of the Mth chip, while the connection structures of other connection pads are developed away, thus completing the complete fabrication of the first to Nth connection pads. This achieves the effect that each chip has the same connection pad fabrication, but the internal connections of each chip can still be distinguished through the fine connection structure fabrication of the connection pads.

[0078] The stacking method described above also includes one and / or multiple layers of other substrates. Figure 13 As shown, the other substrates include at least one of other chips, intermediate layers, and carriers, and each of the other substrates has the aforementioned easy-bonding layer on at least one side (both front and back), and all surfaces involved in bonding also have the easy-bonding layer. The multilayer stacked chip fabricated using this invention can perform chip functions independently, or it can perform functions together with other chips, or it can be further connected to intermediate layers, carriers, etc., using the method of this invention, and then connected to the outside. This connection can be a single layer or multiple layers, depending on the actual needs. Specifically, as shown... Figure 13 As shown, other chips are stacked together with the first thinned chip 401, the second thinned chip 402, and the third thinned chip 403 on the front or back, or further stacked together with the intermediate layer or the second carrier board 417 to complete more complex functions and connections.

[0079] In terms of specific stacking, after activating the easy-bonding layers of the other substrates and the thinned chips with connection holes in the first to Nth easy-bonding layers, the thinned chips with connection holes in the first to Nth easy-bonding layers are sequentially aligned and stacked. One or more other substrates are aligned and stacked with the thinned chips with connection holes in the first and / or Nth easy-bonding layers, and / or multiple other substrates are stacked and aligned and stacked with the thinned chips with connection holes in the first and / or Nth easy-bonding layers. Bonding is then performed to form a three-dimensional stacked chip.

[0080] Alternatively, the aforementioned chip thinning and sequential stacking may involve a single thinning followed by stacking, and / or alternating between stacking and thinning. The stacking may be one or more of the following: back-to-front stacking, back-to-back stacking, and front-to-front stacking. Back-to-back stacking and front-to-front stacking methods are as follows: Figure 12 As shown, Figure 12 In this process, the first thinned chip 401 is stacked front-to-front with the second thinned chip 402, the third thinned chip 403, and the fourth thinned chip 404, while the second thinned chip 402 and the third thinned chip 403 are stacked back-to-back. In terms of the fabrication process, for example, after the second thinned chip 402 is bonded to the first thinned chip 401, the substrate of the second thinned chip 402 is removed; after the third thinned chip 403 is bonded to the fourth thinned chip 404, the substrate of the third thinned chip 403 is removed; then the first thinned chip 401, with the substrate removed from the second thinned chip 402, is bonded to the third thinned chip 403, and the substrate of the first thinned chip 401 is removed; if necessary, the substrate of the fourth thinned chip 404 is further removed; the effect is as follows. Figure 12 As shown.

[0081] The above mainly describes the method where the basic chip has a connection hole below the connection pad that connects to the connection pad. Figure 14 The diagram illustrates a chip fabricated from a base chip with a connection hole to be etched beneath the connection pad. This chip can be a conventional semiconductor (such as...). Figure 14 As shown in (A), it can also be a semiconductor with an etch stop layer (such as...). Figure 14 (As shown in (B)). Figure 14 In this process, the base chip does not have interconnects below the same base interconnect pad 3011 as the first chip, but it has areas to be etched for the interconnects. The chip substrate with the areas to be etched for the interconnects below the interconnect pads is thinned to the required thinning thickness to obtain thinned chips with interconnects to be etched below the first to Nth interconnect pads. It should be noted that thinning-stacking can be done in one step followed by stacking, or stacking-thinning can be performed alternately, depending on the stacking method. For example, if a relatively thick thinning wafer (e.g., greater than 50um) is used, it can be thinned in one step and then stacked; however, if a relatively thinning wafer (e.g., less than 5um) is used, it is recommended to stack first and then thin, and to perform stacking and thinning alternately to prevent the thinning wafer from becoming too thin, which could lead to a large number of breakages during stacking.

[0082] As mentioned above, the thinned chip has a connection hole area to be etched below the first to Nth connection pads. The back and front sides of the thinned chip with the connection hole area to be etched below the connection pads have easy-bonding layers. The front side has an easy-bonding layer, such as... Figure 15As shown, the bonding layer is of one of the following forms: the front bonding pad connection structure easy bonding layer 511 covers the front non-bonding pad area and the same base bonding pad 3011 area of ​​the first chip (e.g., Figure 15 (as shown in (A)); or the front non-connection pad area has a front non-connection structure easy-bonding layer 531 that is flush with the same base connection pad 3011 of the first chip (as shown in (A)). Figure 15 (as shown in B); or the non-connection pad area has a front non-connection structure easy-bonding layer 531, and the same base connection pad 3011 of the first chip has a front connection pad connection structure easy-bonding layer 511, and the front non-connection structure easy-bonding layer 531 is flush with the front connection pad connection structure easy-bonding layer 511 (as shown in B); Figure 15 (as shown in (C)).

[0083] As previously described, for chips with easily bonded layers and interconnecting holes below the bonding pads to be etched, the easily bonded layers of the first to Nth chips with easily bonded layers and interconnecting holes below the bonding pads to be etched are activated, then sequentially aligned and stacked for bonding to form a three-dimensional stacked chip with interconnecting holes below the bonding pads to be etched. Figure 16 As shown, the stack can be front-back, such as... Figure 16 As shown in (A), this method is typically used for sequential stacking after a single thinning process. Or, as... Figure 16 The front-to-front and back-to-back stacking method shown in Figure (B) is a complex stacking method. When the substrate is thinned to a very thin thickness, in order to prevent the substrate from breaking due to excessive thinness, the stacking and thinning are carried out alternately. Figure 16 In terms of the fabrication process of the stacked structure in (B), for example, after the second thinned chip 402 is bonded to the first thinned chip 401, the substrate of the second thinned chip 402 is removed; after the third thinned chip 403 is bonded to the fourth thinned chip 404, the substrate of the third thinned chip 403 is removed; then the first thinned chip 401, with the substrate removed from the second thinned chip 402, is bonded to the third thinned chip 403, and the substrate of the first thinned chip 401 is removed; if necessary, the substrate of the fourth thinned chip 404 is further removed, and the effect is as follows. Figure 16 As shown in (B).

[0084] Other substrates include at least one of other chips, intermediate layers, and carriers, and each of the other substrates has the easy-bonding layer on at least one side (both front and back), and all surfaces involved in bonding have the easy-bonding layer. After activating the easy-bonding layers of the other substrates and the thinning chips with connection holes under the connection pads of the first to Nth easy-bonding layers, the thinning chips with connection holes under the connection pads of the first to Nth easy-bonding layers are sequentially aligned and stacked. One or more other substrates are aligned and stacked with the thinning chips with connection holes under the connection pads of the first and / or the Nth easy-bonding layers. After stacking, the other substrates are aligned and stacked with the thinning chips with connection holes under the connection pads of the first and / or the Nth easy-bonding layers. Bonding is then performed to form a three-dimensional stacked chip with connection holes under the connection pads. A specific stacking structure example is shown below. Figure 18 As shown, the first carrier plate 416 can be bonded to the first thinning chip 401 to form a three-dimensional stacked structure consisting of the third thinning chip 403, the second thinning chip 402, the first thinning chip 401, and the first carrier plate 416. The second external connection pad 374, the first external connection pad 373, etc. can be led out from the first carrier plate 416, or a connecting line 383 can be made to connect the internal connection pads together.

[0085] As mentioned earlier, there are interconnecting holes beneath the bonding pads in the area to be etched to thin the chip. The chips are stacked in three dimensions, and there are no ultra-deep vias connecting the individual chips. Therefore, it is also desired to include the fabrication of ultra-deep vias, such as... Figure 17 , Figure 18 The diagram shows the connection hole F3331, the first ultra-deep via 3332, the second ultra-deep via 3322, and the third ultra-deep via 3361. In the fabrication of these ultra-deep vias, the connection pads act as etching barrier layers. By etching, depositing, or growing connection material in the area to be etched below the connection pads, and removing excess connection material, a thinned chip connection hole structure and a three-dimensional stacked chip with the area to be etched below the connection pads are formed. Furthermore, in the specific fabrication process, an insulating layer 92 can also be fabricated to electrically isolate the first external connection pad 373 and the second external connection pad 374 from the base chip or other chip connection pads, and a protective layer 93 can be further fabricated to isolate external environmental influences. If the thinned chip is very thin, it is recommended to fabricate a protective layer 93 on both the front and back sides of the stacked chip to isolate external environmental influences.

[0086] The chip or other substrate includes a sacrificial structure, which is a sacrificial interconnect pad, or a sacrificial interconnect pad and a sacrificial interconnect via structure connected to the sacrificial interconnect pad. The sacrificial structure is removed by etching, and further material is deposited or grown to form an interconnect structure. Figure 19An example of a chip with a sacrificial structure in the area to be etched, where there are connection holes below the connection pads, is shown. Figure 19 In (A), a second connecting pad 3022 is used as an etching barrier structure in the third thinned chip 403. The second connecting pad 3022 is connected to or not connected to the interior of the third thinned chip 403. The first sacrificial structure 391, the second sacrificial structure 392, and the third sacrificial structure 393 are connected to the interior of the chip. Assuming that all connecting pads are connected to the interior of the chip, the first external connecting pad 373, the connecting hole F3331, and the connecting pad 3031 form a connection between the first external connecting pad 373 and the connecting pad 3031 of the third thinned chip 403. The second external connecting pad 374, the first sacrificial structure 391, the second sacrificial structure 392, the first ultra-deep hole 3332, and the second connecting pad 3022 form a connection between the second external connecting pad 374 and the first thinned chip 401, the second thinned chip 402, and the third thinned chip 403. Figure 19 In section (B), an etching barrier layer 91 is used as the etching barrier layer for the first ultra-deep via 3332 of the sacrificial structure. The first thinned chip 401, the second thinned chip 402, and the third thinned chip 403 are all connected to the second external connection pad 374 through the first ultra-deep via 3332 using the first sacrificial structure 391, the second sacrificial structure 392, and the third sacrificial structure 393. The method for forming the connection using the sacrificial structure is as described above: after etching the first ultra-deep via 3332, the first sacrificial structure 391, the second sacrificial structure 392, and the third sacrificial structure 393 (… Figure 19 The middle (B) is removed, and then new material is deposited or grown to form a connection with the first ultra-deep hole 3332 and connected to the second external connection pad 374, so as to achieve the purpose of connecting the first thinned chip 401, the second thinned chip 402 and the third thinned chip 403 by a first ultra-deep hole 3332.

[0087] Figure 20 This example illustrates another sacrificial structure for fabricating 3D stacked chips, where the chip is thinned by etching the area beneath the connector pads. In this connection method, the connector pads are fabricated as sacrificial structures during the fabrication process. The specific method is as follows: Figure 2The middle (C) determines whether the sacrificial structure of the connector pad forms a connection with the interior. If only the connector pad 3031 of the third thinned chip 403 needs to form a connection with the chip interior, then after the etching, material growth or filling of the stacked chip sacrificial structure is completed, only the internal circuit of the third thinned chip 403 forms a connection with the first external connector pad 373. However, the first connector pad 3012, the second connector pad 3022 and the third connector pad 3032 connected to the first ultra-deep hole 3332 all form a connection with the internal circuit. Therefore, after the etching, material growth or filling of the stacked chip sacrificial structure is completed, the first thinned chip 401, the second thinned chip 402 and the third thinned chip 403 all form a connection with the second external connector pad 374.

[0088] Examples of sacrificial structures where the base chip has a connection hole below the connection pad that connects to the connection pad, such as... Figure 21 , Figure 22 As shown. Figure 21 This approach combines bonding and sacrificial structures. This method is primarily effective because bonding requires high precision in preventing particle contamination. Large-area bonding structures may suffer from unbonded via connections. Therefore, a small number of connections (such as chip select devices) can utilize bonding (e.g., the connection between via L3336 and K3326), while a large number of structures (such as memory signal lines) can be fabricated using sacrificial structures. For example, the first sacrificial structure 391, the second sacrificial structure 392, and the third sacrificial structure 393 are connected via via F3331. In this approach, one method involves using a first mask to fabricate the sacrificial structure and a second mask to fabricate the connection pad structure.

[0089] Figure 22 This example illustrates a connection where both the connecting pads and the connecting holes are sacrificial structures. This is mainly used to solve the problem of poor bonding performance caused by particulate contamination in the bonding of multiple connecting pads and connecting holes. By etching away the sacrificial structures of the bonded connecting pads and connecting holes, materials are further deposited or grown to form new connection structures, resulting in connection structures with better connectivity. Figure 22As shown, the connection hole M3334 of the third thinned chip 403 lacks a connection pad, and the connection hole N3324 of the second thinned chip 402 cannot form a sacrificial structure connection with the connection hole M3334 of the third thinned chip 403. During the etching of the sacrificial structure, the etching chemicals cannot reach the connection hole N3324. When the sacrificial structure is an insulator, the connection holes I3314 and N3324 cannot form an effective connection with the chip interior. That is, the signal from the connection hole M3334 (assuming the external signal of this three-dimensional stacked chip enters from the bottom third thinned chip 403) cannot enter the third thinned chip 403, the second thinned chip 402, and the first thinned chip 401. Similarly, the signal from the connection hole G3335 cannot reach the first thinned chip 401, and the signal from the connection hole L3336 cannot reach the second thinned chip 402 or the first thinned chip 401.

[0090] The aforementioned three-dimensional stacked chip also includes the fabrication of interconnects and / or connection pads on the top layer (top surface) and / or bottom layer (bottom surface). For example... Figure 13 The third and fourth connecting pads are shown. Figure 17 , Figure 18 The first external connection pad 373 and the connection wire 383 are shown.

[0091] The aforementioned hole structures can be individual small interconnects connected to the chip's interior, individual ultra-deep vias, or individual connecting vias communicating with ultra-deep vias. In specific implementations, small interconnects connected to the chip's interior may also be formed by multiple small interconnects (including but not limited to those using conventional chip hole structures) to connect the connector pads to the chip's interior (a common method in small-size process nodes), or even by multiple internal chip interconnects and multiple small interconnects forming a combined small interconnect to connect the connector pads to the chip's interior. Specific details are not limited.

[0092] For ultra-deep vias, just as small connecting holes connected to the inside of a chip may be formed by multiple small connecting holes, especially for ultra-deep vias on the front side of a chip, they may also be formed by multiple ultra-deep vias (including but not limited to those using the hole structure of a conventional chip), or even by multiple internal chip interconnects and multiple ultra-deep vias, without limitation.

[0093] This invention utilizes photolithography offset setting technology, enabling the fabrication of multiple identical base chips with different interconnect pads using only two photomasks. This achieves high-density interconnect pads that are distinguishable within the same chip, at a low photomask cost. For structures with interconnect holes beneath the interconnect pads, thinning, activation of easily bonded layers, and bonding are employed. Alternatively, for structures without interconnect holes beneath the interconnect pads, interconnect holes can be fabricated using the interconnect pads as etching barriers, resulting in a high-density, low-parasitic-connection three-dimensional stacked chip. Particularly for chips with sacrificial structures, etching the sacrificial structure further facilitates multi-chip interconnection, increasing interconnect density and improving connectivity. This invention overcomes the problems of excessively large interconnect size, low interconnect density, and excessively high parasitic parameters associated with µBUMP or RDL interconnect structures. It significantly improves the storage capacity and bandwidth of urgently needed high-bandwidth memory chips and further enhances the integration of CPU / GPU / TPU chips. Furthermore, the effectiveness of this invention is even better when the silicon film thickness is reduced to 10 micrometers or even thinner.

[0094] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multilayer stacking method based on photolithography equipment, characterized in that, include: Using a first mask, N base chips with the same structure are fabricated to create identical base connection pads, resulting in N base chips with identical base connection pads. The base chips are respectively the first base chip, the second base chip, ..., and the Nth base chip. Replace the first photomask with the second photomask; Using a first base chip, setting a first mask offset distance, and / or a first offset distance of the first base chip lithography stage, and after exposure, fabricating a first bonding pad to obtain the first chip; Using a second base chip, setting a second mask offset distance, and / or a second offset distance of the second base chip lithography stage, a second bonding pad is fabricated after exposure to obtain a second chip; This process continues until the Nth base chip is used. The offset distance of the Nth mask is set, and / or the offset distance of the Nth base chip lithography stage is set. After exposure, the Nth bonding pad is fabricated to obtain the Nth chip. Among the first chip, the second chip, ..., and the Nth chip, at least one of the connection pads between each chip is different; and / or, at least one of the connection pads between each chip and the connection structure inside the corresponding chip is different from the connection structure inside the corresponding chip.

2. The multilayer stacking method based on photolithography equipment according to claim 1, characterized in that, When the connecting pad is an opaque pattern on the first and second photomasks, the first photomask comprises: The graphic area is used to create identical base connection pads; The transition area is a light-transmitting area, and / or has no connection holes that connect to the chip interior with the connection pad layer. This area has no connection pads that connect to the chip interior after overlapping with the exposure pattern of the second mask. The second mask protection zone is an opaque area used to protect the first to Nth connecting pads made by the second mask. The second photomask includes: The graphics area is used to create the first to Nth connecting pads; The transition zone is a light-transmitting zone, used to expose and develop the photoresist that is not involved in the fabrication of the first to Nth connecting pads after the second mask protection zone of the first mask has been exposed. The first mask protection area is an opaque area used to protect the same base bonding pads made from the first mask.

3. The multilayer stacking method based on photolithography equipment according to claim 1, characterized in that, The base chip has a connection hole below the connection pad that connects to the connection pad. The connection hole is an ultra-deep hole or a connection hole formed by a combination of an ultra-deep hole and a connecting hole communicating with the ultra-deep hole; or the base chip has a connection hole to be etched area below the connection pad.

4. The multilayer stacking method based on photolithography equipment according to claim 3, characterized in that, A base chip with a connection hole connected to the connection pad is placed below the connection pad. The first to Nth chip substrates with connection holes connected to the connection pad below the connection pad are thinned to the required thinning thickness to expose an ultra-deep hole or an etch barrier layer connected to the connection pad. The etch barrier layer has an ultra-deep hole that penetrates the etch barrier layer, or a connecting hole connected to the ultra-deep hole is further made on the back side to obtain a thinned chip with a connection hole in the first to Nth chips. Alternatively, a base chip with a connection hole to be etched is located below the connection pad. After thinning the first to Nth chip substrates to the required thinning thickness or to the etch barrier layer, ultra-deep holes are etched in the connection hole to be etched area on the back side. At least a portion of the ultra-deep holes are connected to the connection pads, or connected to the connection pads through connecting holes connected to the ultra-deep holes, to obtain thinned chips with connection holes in the first to Nth layers.

5. The multilayer stacking method based on photolithography equipment according to claim 4, characterized in that, The thinned chip with connection holes has an easy-bonding layer. The easy-bonding layer has a connection structure easy-bonding layer on both the connection hole surface on the back side and the connection pad surface on the front side of the thinned chip with connection holes. The non-connection hole and non-connection pad areas on the front and back sides of the thinned chip with connection holes have a non-connection structure easy-bonding layer. The connection structure easy-bonding layer on the front side is flush with the non-connection structure easy-bonding layer on the front side, and the connection structure easy-bonding layer on the back side is flush with the non-connection structure easy-bonding layer on the back side.

6. The multilayer stacking method based on photolithography equipment according to claim 5, characterized in that, After activating the bonding layers of the thinned chips with interconnecting holes in the first to Nth bonding layers, they are sequentially aligned and stacked for bonding to form a three-dimensional stacked chip.

7. The multilayer stacking method based on photolithography equipment according to claim 5, characterized in that, The obtained first chip, second chip, ..., and Nth chip further include one and / or multiple layers of other substrates; the other substrates include at least one of other chips, intermediate layers, and carrier boards, and the other substrates have an easy-bonding layer on at least one side of the front and back surfaces, and all surfaces involved in bonding have an easy-bonding layer; the method includes: After activating the easy bonding layers of the other substrates and the thinned chips with easy bonding layers and connection holes from the first to the Nth layers, the thinned chips with easy bonding layers and connection holes from the first to the Nth layers are sequentially aligned and stacked. One layer and / or multiple layers of other substrates are aligned and stacked with the thinned chips with easy bonding layers and connection holes from the first layer and / or the Nth layer. After stacking multiple layers of other substrates, they are aligned and stacked with the thinned chips with easy bonding layers and connection holes from the first layer and / or the Nth layer. Bonding is then performed to form a three-dimensional stacked chip.

8. The multilayer stacking method based on photolithography equipment according to claim 3, characterized in that, The method described is a method for constructing multilayer stacked chips based on photolithography equipment, where the base chip has a connection hole to be etched area under the connection pad. The base chip has a connection hole to be etched area under the connection pad. The first to Nth chip substrates with connection holes to be etched under the connection pads are thinned to the required thinning thickness to obtain thinned chips with connection holes to be etched under the first to Nth connection pads.

9. The multilayer stacking method based on photolithography equipment according to claim 8, characterized in that, The thinned chip has a connection hole etchable area under the first to Nth connection pads. The back and front sides of the thinned chip with the connection hole etchable area under the connection pads have easy bonding layers; wherein, the easy bonding layer on the front side is one of the following forms: The front easy-bond layer covers both the front non-connection pad area and the connection pad area; The non-connecting pad area on the front has a non-connecting structure easy-to-bond layer and is flush with the connecting pad. The non-connecting pad area has a non-connecting structure easy-bonding layer, and the connecting pad has a connecting structure easy-bonding layer, and the non-connecting structure easy-bonding layer and the connecting structure easy-bonding layer are flush.

10. The multilayer stacking method based on photolithography equipment according to claim 9, characterized in that, The chip with a thinning chip having a connection hole under the connection pad with an easy bonding layer is thinned by activating the easy bonding layers of the first to Nth chips with a connection hole under the connection pad with an easy bonding layer. The chips are then aligned and stacked sequentially and bonded to form a three-dimensional stacked chip with a connection hole under the connection pad with an etchable area.

11. The multilayer stacking method based on photolithography equipment according to claim 9, characterized in that, It also includes one and / or multiple other substrates; the other substrates include at least one of other chips, intermediate layers, and carriers, and the other substrates have the easy-bonding layer on at least one side of the front and back surfaces, and all surfaces involved in bonding have the easy-bonding layer; the method includes: After activating the bonding layers of the other substrates and the thinning chip with the bonding pads of the first to Nth bonding layers having bonding holes under the bonding pads, the thinning chips with the bonding pads of the first to Nth bonding layers having bonding holes under the bonding pads are sequentially aligned and stacked. The one layer and / or multiple layers of other substrates are aligned and stacked with the thinning chip with the bonding pads of the first bonding layers having bonding holes under the bonding pads and / or the thinning chip with the bonding pads of the Nth bonding layers having bonding holes under the bonding pads. After stacking multiple layers of other substrates, they are aligned and stacked with the thinning chip with the bonding pads of the first bonding layers having bonding holes under the bonding pads and / or the thinning chip with the bonding pads of the Nth bonding layers having bonding holes under the bonding pads; bonding is then performed to form a three-dimensional stacked chip with bonding holes under the bonding pads.

12. The multilayer stacking method based on photolithography equipment according to any one of claims 7-11, characterized in that, Chip thinning and stacking can be performed by thinning followed by stacking, and / or by alternating between stacking and thinning; wherein the stacking method includes one or more of back-to-front stacking, back-to-back stacking, and front-to-front stacking.

13. The multilayer stacking method based on photolithography equipment according to claim 10 or 11, characterized in that, The chip has a three-dimensional stacked chip with a connection hole to be etched area under the connection pad, and also includes the fabrication of ultra-deep holes. The connection pad is an etching barrier layer. By etching, depositing or growing connection material in the connection hole to be etched area under the connection pad, and removing excess connection material, a thinned chip connection hole structure and a three-dimensional stacked chip with a connection hole to be etched area under the connection pad are formed.

14. A multilayer stacked chip based on photolithography equipment, characterized in that, Prepared by the method described in any one of claims 1-13.

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