Package carrier and preparation method thereof

Abstract

The invention provides a packaging carrier plate and a preparation method thereof. The packaging carrier plate comprises a carrier plate main body and a wiring structure. The carrier plate body comprises a first main surface and a second main surface which are opposite to each other, at least one cavity is formed in the carrier plate body, and the cavity is located between the first main surface and the second main surface. The wiring structure comprises a first wiring layer, a second wiring layer and a middle wiring layer, the first wiring layer is arranged on the first main surface of the carrier plate body, the middle wiring layer is arranged in the cavity, and the second wiring layer is arranged on the second main surface of the carrier plate body. According to the package carrier, the wiring space and the wiring flexibility are improved, so that the problem that the wiring space of the package carrier is limited is solved.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging technology, and more specifically, to a packaging substrate and its preparation method. Background Technology

[0002] With the rapid development of semiconductor technology, the integration level of chips has increased exponentially. From early small-scale integrated circuits to today's very large-scale integrated circuits, the number of transistors integrated on a chip is increasing. This requires more pins to connect the chip to external circuits to perform functions such as signal transmission and power supply. As a bridge between the chip and external circuits, the packaging substrate can provide a large number of pin connection points to meet the ever-increasing connectivity needs of the chip. However, the packaging substrate suffers from limited wiring space. Summary of the Invention

[0003] This disclosure provides a packaging carrier and its preparation method. By designing the packaging carrier, wiring structures can be set on both main surfaces of the carrier body and in the middle cavity, thus improving the problem of limited wiring space in the packaging carrier without changing the thickness of the packaging carrier.

[0004] The first aspect of this disclosure provides a packaging carrier board, which includes a carrier board body and a wiring structure. The carrier board body includes a first main surface and a second main surface that are opposite to each other. At least one cavity is provided in the carrier board body, which is located between the first main surface and the second main surface. The wiring structure includes a first wiring layer, a second wiring layer and an intermediate wiring layer. The first wiring layer is disposed on the first main surface of the carrier board body, the intermediate wiring layer is disposed in the cavity, and the second wiring layer is disposed on the second main surface of the carrier board body.

[0005] In the above scheme, the first main surface, the second main surface, and the cavity between the first main surface and the second main surface of the carrier board can all be used to set up the wiring structure, thereby proposing the wiring space of the packaging carrier board, improving the wiring flexibility without increasing the thickness of the packaging carrier board.

[0006] In one specific embodiment of the first aspect of this disclosure, the carrier board body includes a main board and at least one sub-board. The main board includes at least one groove, and at least one sub-board corresponds to the groove. The sub-board is disposed at the opening of the groove and forms a cavity with the groove.

[0007] In the above solution, at least one sub-board is used to form a cavity on the carrier board body by cooperating with at least one groove on the main board. This not only has a mature process and is easy to manufacture, but also allows for the setting of cavities in different positions according to wiring requirements, thereby improving the flexibility of wiring.

[0008] Optionally, multiple recesses are provided, and these recesses are arranged in an array on the motherboard. This effectively increases the wiring space on the package carrier board.

[0009] Optionally, on the side of the motherboard with the groove, the portion of the motherboard surface outside the groove and the surface of the sub-board away from the groove form a first main surface. This helps improve the stability of the cavity structure formed by the motherboard and sub-board.

[0010] Optionally, the first main surface and / or the second main surface are continuous planes. This facilitates the fabrication of the packaging substrate and subsequent chip packaging processes using the packaging substrate, thereby saving production costs.

[0011] Optionally, the depth of the groove is less than or equal to half the thickness of the motherboard.

[0012] Optionally, the spacing between adjacent grooves is greater than or equal to 100 μm.

[0013] In one specific embodiment of the first aspect of this disclosure, the wiring structure further includes a first conductive layer, which is located on the side of the sub-board facing the intermediate wiring layer and is bonded to the intermediate wiring layer.

[0014] In the above solution, bonding is used to achieve the connection and electrical connection between the sub-board and the main board. The technology is mature and saves production costs.

[0015] In one specific embodiment of the first aspect of this disclosure, the intermediate wiring layer is vertically electrically connected to the first wiring layer and / or the second wiring layer.

[0016] In the above scheme, the method of not using vertical electrical connections of the wiring layer not only helps to improve the integration and space utilization of the package structure obtained by using the package carrier board, but also helps to improve electrical performance by shortening the signal transmission path, reducing signal loss and reducing signal crosstalk.

[0017] In one specific embodiment of the first aspect of this disclosure, a plurality of first through holes are provided on the sub-plate, the first through holes penetrating the sub-plate in a direction perpendicular to the main body of the carrier plate, and the first through holes are filled with a first metal layer, and / or, a plurality of second through holes are provided at the bottom of the groove, the second through holes penetrating to the second main surface of the main body of the carrier plate, and the second through holes are filled with a second metal layer.

[0018] In the above solution, through-holes with metal layers are used to achieve vertical electrical connections between different wiring layers. The technology is mature and saves production costs.

[0019] In one specific embodiment of the first aspect of this disclosure, a plurality of third through holes are provided on the motherboard. The third through holes are located around the groove, connect the first main surface and the second main surface of the carrier board body, and are filled with a third metal layer.

[0020] In the above scheme, the use of through-holes with metal layers to provide vertical electrical connections between multiple wiring layers improves the applicability of the package substrate.

[0021] The second aspect of this disclosure provides a method for preparing a packaging carrier board. The method includes preparing a carrier board body, the carrier board body including a first main surface and a second main surface opposite to each other, and at least one cavity provided in the carrier board body, the cavity being located between the first main surface and the second main surface to form a wiring structure. The wiring structure includes a first wiring layer, a second wiring layer and an intermediate wiring layer, the first wiring layer being disposed on the first main surface of the carrier board body, the intermediate wiring layer being disposed in the cavity, and the second wiring layer being disposed on the second main surface of the carrier board body.

[0022] In the above scheme, the wiring space of the packaging substrate obtained by the preparation method includes not only the first main surface and the second main surface, but also the cavity, which increases the wiring space of the packaging substrate without increasing the thickness of the packaging substrate.

[0023] In one specific embodiment of the second aspect of this disclosure, the step of preparing the carrier plate body includes obtaining a main plate, forming at least one groove on the main plate, obtaining at least one sub-plate, the sub-plate corresponding to the groove one by one, and placing the sub-plate at the opening of the groove to form a cavity between the sub-plate and the groove.

[0024] In the above scheme, the method of forming a cavity on the carrier board body by utilizing the cooperation between the sub-board and the main board is simple in process and easy to implement.

[0025] Optionally, multiple recesses are provided, and the multiple recesses are arranged in an array on the motherboard.

[0026] In one specific embodiment of the second aspect of this disclosure, the step of forming a wiring structure includes forming an intermediate wiring layer in a groove after the step of acquiring the motherboard and before the step of forming a cavity, forming a first wiring layer on a first main surface of the carrier board body after the step of forming the cavity, and forming a second wiring layer on a second main surface of the carrier board body.

[0027] Optionally, after obtaining the sub-board, the method further includes forming a first conductive layer on the side of the sub-board facing the intermediate wiring layer, and the first conductive layer is bonded to the intermediate wiring layer.

[0028] Optionally, a semi-additive method can be used to form the intermediate wiring layer.

[0029] Optionally, the intermediate wiring layer is electrically connected vertically to the first wiring layer and / or the second wiring layer.

[0030] In one specific embodiment of the second aspect of this disclosure, prior to the step of forming an intermediate wiring layer in the groove, a first type of through-hole is formed on the motherboard, and a metal layer is electroplated in the first type of through-hole.

[0031] Optionally, the first type of through hole includes a second through hole located within the groove, the second through hole extending to the second main surface of the carrier plate body, and / or a third through hole located around the groove, the third through hole connecting the first main surface and the second main surface of the carrier plate body.

[0032] Optionally, before the step of setting the sub-plate at the opening of the groove, the method further includes: forming a first through hole on the sub-plate; and electroplating a metal layer in the first through hole. Attached Figure Description

[0033] Figure 1 This is a planar schematic diagram of a packaging carrier provided in one embodiment of the present disclosure.

[0034] Figure 2 Provided for an embodiment of this disclosure Figure 1 A schematic diagram of a cross-section of a packaging carrier in the M1-N1 direction.

[0035] Figure 3 This is a schematic planar view of a packaging carrier board provided in one embodiment of the present disclosure.

[0036] Figure 4 Provided for an embodiment of this disclosure Figure 1 A cross-sectional schematic diagram of another type of packaging substrate in the M1-N1 direction.

[0037] Figure 5 Provided for an embodiment of this disclosure Figure 1 A cross-sectional schematic diagram of another type of packaging substrate in the M1-N1 direction.

[0038] Figure 6 Provided for an embodiment of this disclosure Figure 1 A schematic diagram of a cross-section of a packaging carrier in the M-1N1 direction.

[0039] Figure 7 Provided for an embodiment of this disclosure Figure 1 A cross-sectional schematic diagram of another type of packaging substrate in the M1-N1 direction.

[0040] Figure 8 Provided for an embodiment of this disclosure Figure 1 A cross-sectional schematic diagram of another type of packaging substrate in the M1-N1 direction.

[0041] Figure 9 Provided for an embodiment of this disclosure Figure 1 A cross-sectional schematic diagram of another type of packaging substrate in the M1-N1 direction.

[0042] Figure 10 Provided for an embodiment of this disclosure Figure 1 A schematic diagram of a cross-section of a packaging carrier in the M-1N1 direction.

[0043] Figure 11 Provided for an embodiment of this disclosure Figure 1 A cross-sectional schematic diagram of another type of packaging substrate in the M1-N1 direction.

[0044] Figure 12 Provided for an embodiment of this disclosure Figure 1 A schematic diagram of a cross-section of a packaging carrier in the M1-N1 direction.

[0045] Figure 13 This is a schematic flowchart illustrating a method for preparing a packaging substrate according to an embodiment of the present disclosure.

[0046] Figure 14 This is a flowchart illustrating some steps of a method for preparing a packaging substrate according to an embodiment of the present disclosure.

[0047] Figure 15 This is a schematic flowchart illustrating a method for preparing a packaging substrate according to an embodiment of the present disclosure.

[0048] Figure 16 This is a schematic flowchart illustrating a method for preparing a packaging substrate according to an embodiment of the present disclosure.

[0049] Explanation of reference numerals in the attached figures: 100 - Packaging carrier board; 110 - Carrier board body; S1 - First main surface; S2 - Second main surface; C - Cavity; 111 - Main board; G - Groove; 111a - Second through hole; 111b - Second metal layer; 111c - Third through hole; 111d - Third metal layer; 112 - Sub-board; 112a - First through hole; 112b - First metal layer; 120 - Wiring structure; 121 - First wiring layer; 121a - First wiring layer; 121b - Second wiring layer; 121c - First insulating layer; 122 - Second wiring layer; 122a - Third wiring layer; 123 - Intermediate wiring layer; 123a - Fourth wiring layer; 123b - Fifth wiring layer; 123c - Second insulating layer; 124 - First conductive layer. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0051] This disclosure provides a packaging substrate and its fabrication method. The packaging substrate includes a substrate body and a wiring structure. The substrate body includes a first main surface and a second main surface opposite to each other. At least one cavity is provided within the substrate body, located between the first and second main surfaces. The wiring structure includes a first wiring layer, a second wiring layer, and an intermediate wiring layer. The first wiring layer is disposed on the first main surface of the substrate body, the intermediate wiring layer is disposed within the cavity, and the second wiring layer is disposed on the second main surface of the substrate body. Thus, not only can the first and second main surfaces of the substrate body be respectively provided with the first wiring layer and the second wiring layer, but an intermediate wiring layer can also be disposed within the cavity of the substrate body. This increases the corresponding wiring space without increasing the thickness of the packaging substrate. The larger wiring space not only improves wiring flexibility and provides high quality and stability of signal transmission after packaging by effectively avoiding signal interference sources and reducing signal crossover and interference, but also reduces wiring difficulty and chip packaging area.

[0052] The following describes, with reference to the accompanying drawings, at least one embodiment of the encapsulation substrate and its preparation method according to the present disclosure. Furthermore, as shown in the drawings, in at least one embodiment of the present disclosure, a spatial rectangular coordinate system is established with the surface of the encapsulation substrate as a reference to define the positions of each film layer in the encapsulation substrate. In this spatial rectangular coordinate system, the X-axis and Y-axis are parallel to the surface of the encapsulation substrate, and the Z-axis is perpendicular to the surface of the encapsulation substrate.

[0053] In one embodiment of this disclosure, a packaging carrier board is provided, such as Figure 1 and Figure 2 As shown, the packaging carrier 100 includes a carrier body 110 and a wiring structure 120.

[0054] The carrier body 110 is a rigid material such as a glass substrate. Therefore, the carrier body 110 not only has good electrical properties but also good thermal stability, high strength, rigidity, and flatness. The carrier body 110 includes a first main surface S1 and a second main surface S2 extending along the length direction (i.e., the extension direction) of the carrier body 110 and opposite to each other. At least one cavity C is provided within the carrier body 110, for example, a single cavity C located between the first main surface S1 and the second main surface S2, for accommodating the intermediate wiring layer 123 mentioned later. The cross-sectional shape of the cavity C in the direction perpendicular to the thickness of the carrier body 110 is rectangular.

[0055] The wiring structure 120 includes a first wiring layer 121, a second wiring layer 122, and an intermediate wiring layer 123. The first wiring layer 121 is disposed on the first main surface S1 of the carrier board body 110, the intermediate wiring layer 123 is disposed within the cavity C, and the second wiring layer 122 is disposed on the second main surface S2 of the carrier board body 110. That is, the wiring space of the carrier board body 110 is not limited to the first main surface S1 and the second main surface S2, but also includes the cavity C within the carrier board body 110, thereby increasing the wiring space of the carrier board body 110.

[0056] It should be noted that the structure of the encapsulation carrier 100 in this disclosure is not limited to the examples and illustrations above. For example, the carrier body 110 can also be other rigid materials, such as FR-4 made of epoxy resin and fiberglass cloth, where "FR" stands for "Flame Retarda" and the number "4" indicates that the material used is a standard "4" type or E-grade glass epoxy resin. For example, the number of cavities C is not limited to one, but can be two or more. Furthermore, the cross-sectional shape of the cavity C in the direction perpendicular to the thickness of the carrier body 110 is not limited to a rectangle, but can be other shapes such as U-shaped, trapezoidal, etc. These can be designed according to actual needs, and will not be elaborated here.

[0057] Based on the above embodiments, the specific structure of the carrier plate body 110 is further described below.

[0058] In one embodiment of this disclosure, the packaging carrier 100 is provided, such as Figure 3 and Figure 4 As shown, the carrier board body 110 includes a main board 111 having at least one groove G, for example, and at least one sub-board 112, for example, a sub-board 112. The sub-board 112 corresponds one-to-one with the groove G, and the sub-board 112 is disposed at the opening of the groove G, forming a cavity C between the sub-board 112 and the groove G.

[0059] In the packaging substrate 100 provided in at least one embodiment of this disclosure, a plurality of grooves G are provided, and the plurality of grooves G are arranged in an array on the main board 111.

[0060] For example, such as Figure 3 As shown, in this packaging substrate 100, multiple grooves G are correspondingly provided on the motherboard 111, and the multiple grooves G are arranged in an array on the motherboard 111. Figure 4As shown, in the same package carrier board 100, multiple sub-boards 112 are provided corresponding to the main board 111, and each sub-board 112 corresponds one-to-one with a groove G on the main board 111. Each sub-board 112 is located at the opening of the corresponding groove G, and cooperates with the groove G to form a corresponding cavity C. In this way, the array of grooves G not only enhances the structural strength and stability of the main board 111 by dispersing the stress when the main board 111 is subjected to external forces, but also facilitates the heat dissipation management of the main board 111. At the same time, the multiple cavities C formed by the multiple grooves G and the multiple sub-boards 112 also effectively increase the wiring space of the carrier board body 110.

[0061] Based on the above embodiments, this disclosure also introduces a specific scheme for the structure between the sub-board 112 and the main board 111 to form a carrier board body 110 with cavity C.

[0062] In the packaging carrier 100 provided in at least one embodiment of this disclosure, on the side of the main board 111 where the groove G is provided, the portion of the surface of the main board 111 outside the groove G and the surface of the sub-board 112 away from the groove G constitute a first main surface S1.

[0063] In the encapsulation carrier 100 provided in at least one embodiment of this disclosure, the first main surface S1 and / or the second main surface S2 are continuous planes.

[0064] For example, such as Figure 4 As shown, in the packaging carrier 100, the sub-board 112 is located on the opening of the groove G of the main board 111, forming a cavity C corresponding to the groove G. The surface of the main board 111 facing away from the groove G constitutes the second main surface S2 of the carrier body 110. The portion of the surface of the main board 111 opposite to the first main surface S1 located outside the groove G, together with the surface of the sub-board 112 facing away from the groove G, constitutes the first main surface S1. The surface of the sub-board 112 facing away from the groove G is flush with and connected to the portion of the main board 111 that constitutes the first main surface S1, i.e., the first main surface S1 is a continuous plane. At the same time, the second main surface S2 can be a continuous plane and is arranged parallel to the first main surface S1.

[0065] It should be noted that the structure of the packaging carrier 100 provided in this disclosure is not limited to the above examples. For example, the first main surface S1 and the second main surface S2 of the carrier body 110 are both arranged on a continuous plane but are not parallel to each other; for example, the plane containing the first main surface S1 is parallel to the plane containing the second main surface S2, but the first main surface S1 is not a continuous plane, or the second main surface S2 is not a continuous plane, and the two may be respectively provided with protrusions or grooves G. All of the above can be designed according to actual needs, and will not be elaborated here.

[0066] Based on the above embodiments, in the packaging substrate 100 provided in at least one embodiment of this disclosure, the depth of the groove G is less than or equal to half the thickness of the motherboard 111. Reasonable planning of the groove G not only ensures the strength of the substrate body 110, but also improves the strength and stability of the substrate body 110 by improving the stress distribution. Furthermore, limiting the depth of the groove G also helps to improve the efficiency of subsequent processes such as chip packaging, thereby optimizing the assembly performance of the packaging substrate 100.

[0067] For example, the depth of groove G is equal to half the thickness of motherboard 111, the depth of groove G is equal to one-third the thickness of motherboard 111, the depth of groove G is equal to one-quarter the thickness of motherboard 111, the depth of groove G is equal to one-fifth the thickness of motherboard 111, and so on.

[0068] Based on the above embodiments, in the packaging carrier 100 provided in at least one embodiment of this disclosure, the spacing between adjacent grooves G is greater than or equal to 100 μm. Limiting the spacing between grooves G on the carrier body 110 reduces the processing difficulty of the grooves G while ensuring the structural strength of the carrier body 110, facilitating processing and standardized production, and improving production efficiency.

[0069] For example, the spacing between adjacent grooves G is equal to any one of 100μm, 102μm, 104μm, 106μm, 108μm, 110μm, 112μm, 114μm, 116μm, 118μm, 120μm, 122μm, 124μm, 126μm, 128μm, 130μm, 132μm, 134μm, 136μm, 138μm, 140μm, 142μm, 144μm, 146μm, 148μm, 150μm, etc.

[0070] After describing the structure of the carrier board body 110 in the packaging carrier board 100, the present disclosure embodiment also designed the wiring structure 120, and the specific scheme is as follows.

[0071] In one embodiment of this disclosure, the packaging carrier 100 is provided, such as Figure 5 As shown, a first conductive layer 124 is disposed on the side of the sub-board 112 facing the intermediate wiring layer 123, and the first conductive layer 124 is bonded to the intermediate wiring layer 123. The bonding connection between the first conductive layer 124 and the intermediate wiring layer 123 achieves the physical connection between the sub-board 112 and the main board 111, forming a cavity C between them to accommodate the intermediate wiring layer 123. This not only achieves the electrical connection between the first conductive layer 124 and the intermediate wiring layer 123, but also saves production costs due to the mature and easy processing technology.

[0072] In a packaging substrate 100 provided in one embodiment of this disclosure, an intermediate wiring layer 123 is perpendicularly electrically connected to a first wiring layer 121 and / or a second wiring layer 122. Thus, the intermediate wiring layer 123 serves as additional wiring space for the first wiring layer 121 and / or the second wiring layer 122, acting as a supplementary wiring layer for the first wiring layer 121 and / or the second wiring layer 122. This increases the wiring space of the packaging substrate 100 while reducing the difficulty of wiring.

[0073] For example, such as Figure 6 As shown, in this package carrier 100, the first wiring layer 121 located on the first main surface S1 of the carrier body 110 is perpendicularly electrically connected to the intermediate wiring layer 123 located in the groove G of the motherboard 111. In this way, by more rationally distributing the lines originally located on the first main surface S1 of the carrier body 110 to the first wiring layer 121 and the intermediate wiring layer 123, the chip can be connected to the package carrier 100 or other chips in a more rational manner, thereby increasing the flexibility and scalability of chip connections, while improving the signal transmission quality and reliability of the chip package structure.

[0074] For example, such as Figure 7 As shown, in this package carrier 100, the intermediate wiring layer 123 located in the recess G of the motherboard 111 is perpendicularly electrically connected to the second wiring layer 122 located on the second main surface S2 of the carrier body 110. In this way, the lines originally located on the second main surface S2 of the carrier body 110 can be more rationally distributed to the second wiring layer 122 and the intermediate wiring layer 123, increasing the design flexibility of the second wiring layer 122 and improving chip packaging efficiency.

[0075] For example, such as Figure 8 As shown, in this packaging substrate 100, the intermediate wiring layer 123 located in the groove G of the motherboard 111 is perpendicularly electrically connected to the first wiring layer 121 located on the first main surface S1 of the substrate body 110 and the second wiring layer 122 located on the second main surface S2 of the substrate body 110. This allows for more flexible design of the first and second wiring layers 122, reducing wiring complexity and improving chip packaging efficiency.

[0076] The following embodiments of the present disclosure also design a specific scheme for achieving vertical electrical connection between the intermediate wiring layer 123 and the first wiring layer 121 and / or the second wiring layer 122 in the packaging carrier board 100.

[0077] In one embodiment of the present disclosure, a packaging carrier 100 is provided with a plurality of first through holes 112a on a sub-board 112. The first through holes 112a penetrate the sub-board 112 in a direction perpendicular to the carrier body 110, and the first through holes 112a are filled with a first metal layer 112b. And / or, a plurality of second through holes 111a are provided at the bottom of the groove G. The second through holes 111a penetrate to the second main surface S2 of the carrier body 110, and the second through holes 111a are filled with a second metal layer 111b.

[0078] For example, such as Figure 6 As shown, in the packaging substrate 100, the sub-board 112 is provided with a plurality of first through holes 112a. The plurality of first through holes 112a are distributed perpendicular to the direction of the substrate body 110, i.e., the Z direction. The first wiring layer 121 located on the substrate body 110 is electrically connected perpendicularly to the intermediate wiring layer 123 located in the groove G of the main board 111 through the first through holes 112a. The first through holes 112a are filled with a first metal layer 112b, such as a first metal plating layer. The first metal plating layer realizes the electrical connection between the first wiring layer 121 and the first conductive layer 124 of the sub-board 112 facing the groove G side. The first conductive layer 124 is bonded to the intermediate wiring layer 123, thereby finally realizing the electrical connection between the first wiring layer 121 and the intermediate wiring layer 123.

[0079] For example, such as Figure 7 As shown, in the packaging substrate 100, a plurality of second through holes 111a are provided at the bottom of the groove G of the main board 111. The second through holes 111a penetrate to the second main surface S2 of the main board 110 in the Z direction perpendicular to the substrate body 110. The intermediate wiring layer 123 located at the bottom of the groove G of the main board 111 is vertically electrically connected to the second wiring layer 122 located on the second main surface S2 of the substrate body 110 through the second through holes 111a. Specifically, a second metal layer 111b, such as a second metal plating layer, is provided in the second through hole 111a. The second metal plating layer is located at both ends of the second through hole 111a and is electrically connected to the intermediate wiring layer 123 and the second wiring layer 122, respectively, thereby finally realizing the electrical connection between the intermediate wiring layer 123 and the second wiring layer 122.

[0080] For example, such as Figure 8 As shown, in the packaging substrate 100, the sub-board 112 is provided with a plurality of first through holes 112a, and the bottom of the groove G of the main board 111 is provided with a plurality of second through holes 111a. The intermediate wiring layer 123 is perpendicularly electrically connected to the first wiring layer 121 and the second wiring layer 122 through the first through holes 112a and the second through holes 111a, respectively. The specific connection method can be referred to the description in the above example, and will not be repeated here.

[0081] In one embodiment of the present disclosure, a packaging substrate 100 has a plurality of third through holes 111c on the main board 111. The third through holes 111c are located around the groove G and connect the first main surface S1 and the second main surface S2 of the substrate body 110. The third through holes 111c are filled with a third metal layer 111d, such as a third metal plating layer. In this way, the utilization of the wiring space of the packaging substrate 100 can be further improved, and the crossing and interference between signals can be reduced. Thus, while reducing the volume of the packaging structure using the packaging substrate 100, the signal transmission quality and stability of the packaging structure can also be improved.

[0082] For example, such as Figure 9 As shown, in the packaging carrier 100, the sub-board 112 is provided with a plurality of first through holes 112a, and the main board 111 is provided with a plurality of third through holes 111c. The third through holes 111c are located around the groove G, and the first through holes 112a, second through holes 111a, and third through holes 111c are all vertically distributed in the direction perpendicular to the carrier body 110, i.e., the Z direction. Specifically, a first metal layer 112b, such as a first metal plating layer, is provided in the first through hole 112a to realize the vertical electrical connection between the first wiring layer 121 and the intermediate wiring layer 123; a third metal layer 111d, such as a third metal plating layer, is provided in the third through hole 111c to realize the vertical electrical connection between the first wiring layer 121 and the second wiring layer 122.

[0083] For example, such as Figure 10 As shown, in the packaging substrate 100, a plurality of second through holes 111a are provided at the bottom of the groove G of the motherboard 111, and a plurality of third through holes 111c are provided on the periphery of the groove G outside the motherboard 111. Specifically, a second metal layer 111b, such as a second metal plating layer, is provided in the second through hole 111a to realize the vertical electrical connection between the intermediate wiring layer 123 and the second wiring layer; a third metal layer 111d, such as a third metal plating layer, is provided in the third through hole 111c to realize the vertical electrical connection between the first wiring layer 121 and the second wiring layer 122.

[0084] For example, such as Figure 11As shown, in the packaging substrate 100, the sub-board 112 is provided with a plurality of first through holes 112a, the bottom of the groove G of the main board 111 is provided with a plurality of second through holes 111a, and the part outside the groove G of the main board 111, i.e., the periphery of the groove G, is provided with a plurality of third through holes 111c. Specifically, a first metal layer 112b is provided in the first through hole 112a to realize the vertical electrical connection between the first wiring layer 121 and the intermediate wiring layer 123; a second metal layer 111b is provided in the second through hole 111a to realize the vertical electrical connection between the intermediate wiring layer 123 and the second wiring layer; and a third metal layer 111d is provided in the third through hole 111c to realize the vertical electrical connection between the first wiring layer 121 and the second wiring layer 122.

[0085] It should be noted that the structure of the packaging carrier 100 in this embodiment is not limited to the above examples. For example, the design, size, and distribution of the first through hole 112a, the second through hole 111a, and the third through hole 111c are not limited to the above examples and can be designed according to actual needs, which will not be elaborated here. As another example, the first through hole 112a, the second through hole 111a, and the third through hole 111c are through holes perpendicular to the main board 111 or the sub-board 112, respectively. In addition to the first metal layer 112b, the second metal layer 111b, and the third metal layer 111d respectively, a buffer layer or other structure can be provided between the corresponding metal layer (e.g., a metal plating layer) and the corresponding through hole sidewall. This can also be designed according to actual needs, which will not be elaborated here.

[0086] This disclosure does not specifically limit the wiring structure 120. The first wiring layer 121, the intermediate wiring layer 123, and the second wiring layer 122 included in the wiring structure 120 can include various design methods. For example, the first wiring layer 121, the intermediate wiring layer 123, and the second wiring layer 122 may include one trace layer; as another example, at least one of the first wiring layer 121, the intermediate wiring layer 123, and the second wiring layer 122 may be configured as a multi-layer structure, including at least two trace layers. The specific design methods of the wiring structure 120 are described below.

[0087] For example, such as Figure 11 and Figure 12As shown, the packaging substrate 100 includes a main board 111 and a sub-board 112 constituting the substrate body 110, and a first wiring layer 121, a second wiring layer 122, and an intermediate wiring layer 123 constituting the wiring structure 120. The main board 111 of the substrate body 110 has multiple grooves G, and a sub-board 112 is correspondingly disposed at the opening of each groove G. The sub-boards 112 and grooves G are arranged in a one-to-one correspondence, forming a cavity C located between the first main surface S1 and the second main surface S2 of the substrate body 110. The first wiring layer 121 is disposed on the first main surface S1 of the substrate body 110, the second wiring layer 122 is disposed on the second main surface S2 of the substrate body 110, and the intermediate wiring layer 123 is disposed within the cavity C of the substrate body 110, i.e., at the bottom of the grooves G of the main board 111.

[0088] The carrier board body 110 also includes a first conductive layer 124 located on the side of the sub-board 112 facing the groove G, and the first conductive layer 124 is bonded to the intermediate wiring layer 123 in the groove G.

[0089] The first wiring layer 121 includes two wiring layers and a first insulating layer 121c located between the two wiring layers, namely the first wiring layer 121a and the second wiring layer 121b, and the first wiring layer 121a is close to the first main surface S1 of the carrier board body 110. The second wiring layer 122 includes a third wiring layer 122a. The intermediate wiring layer 123 includes a fourth wiring layer 123a, a fifth wiring layer 123b, and a second insulating layer 123c located between the fourth wiring layer 123a and the fifth wiring layer 123b, and the fourth wiring layer 123a is close to the bottom of the groove G. The electrical connection relationship between the first wiring layer 121, the second wiring layer 122, and the third wiring layer is as follows.

[0090] The sub-board 112 is provided with a plurality of first through holes 112a. The first through holes 112a are filled with a first metal filler layer, and the first metal filler layer is electrically connected to the first wiring layer 121a and the first conductive layer 124. The first conductive layer 124 is bonded to the intermediate wiring layer 123, thereby realizing the electrical connection between the first wiring layer 121a and the intermediate wiring layer 123 in the first wiring layer 121. At the same time, the second wiring layer 121b is electrically connected to the first wiring layer 121a through a via, and finally realizes the vertical electrical connection between the first wiring layer 121 and the intermediate wiring layer 123. The bottom of the recess G of the motherboard 111 is provided with multiple second vias, and the second vias are filled with a second metal layer 111b to realize the electrical connection between the fourth routing layer 123a and the third routing layer 122a, i.e. the second wiring layer 122. At the same time, the fifth routing layer 123b is electrically connected to the fourth routing layer 123a through the vias, and finally realizes the vertical electrical connection between the intermediate wiring layer 123 and the second wiring layer 122.

[0091] It should be noted that the structure of the packaging substrate 100 in this embodiment is not limited to the examples above. For example, the specific wiring arrangement of the first wiring layer 121, the second wiring layer 122, and the intermediate wiring layer 123 is not limited to the examples above; each wiring layer may also include more wiring layers or other functional film layers such as barrier layers. Furthermore, the wiring layout of the first conductive layer 124 is not limited to the examples above; it can be designed according to the design requirements of the first wiring layer 121 and the intermediate wiring layer 123. For another example, the second via 111a and the third via 111c can be formed using the same process, and the second metal layer 111b and the third metal layer 111d can be formed using the same process. For another example, the second wiring layer 122 may also include other structures, such as solder balls disposed on the side of the wiring layer facing away from the motherboard 111. For another example, the specific details regarding the electrical connection between different wiring layers within the same wiring layer vias can also be designed according to actual needs, and will not be elaborated here.

[0092] This disclosure also provides a method for preparing a packaging carrier board. The method includes preparing a carrier board body, the carrier board body including a first main surface and a second main surface opposite to each other, and at least one cavity provided within the carrier board body, the cavity being located between the first main surface and the second main surface. A wiring structure is formed, the wiring structure including a first wiring layer, a second wiring layer, and an intermediate wiring layer, the first wiring layer being disposed on the first main surface of the carrier board body, the intermediate wiring layer being disposed within the cavity, and the second wiring layer being disposed on the second main surface of the carrier board body.

[0093] For example, such as Figure 13 As shown, the method for preparing the packaging substrate includes the following steps.

[0094] Step S100: Prepare a carrier plate body. The carrier plate body includes a first main surface and a second main surface that are opposite to each other. The carrier plate body has at least one cavity located between the first main surface and the second main surface.

[0095] Step S200: Form a wiring structure, which includes a first wiring layer, a second wiring layer and an intermediate wiring layer. The first wiring layer is disposed on the first main surface of the carrier board body, the intermediate wiring layer is disposed in the cavity, and the second wiring layer is disposed on the second main surface of the carrier board body.

[0096] In a method for preparing a packaging carrier provided in this disclosure embodiment, such as Figure 14 As shown, step S100, which involves preparing the carrier plate body, includes the following steps.

[0097] Step S110: Obtain the motherboard.

[0098] Step S120: Form at least one groove on the motherboard.

[0099] Step S130: Obtain at least one sub-plate, with each sub-plate corresponding to a groove.

[0100] Step S140: Place the sub-plate at the opening of the groove to form a cavity between it and the groove.

[0101] In the method for preparing a packaging substrate provided in at least one embodiment of this disclosure, in step S120, a plurality of grooves are provided on the motherboard, and the plurality of grooves are arranged in an array on the motherboard.

[0102] In a method for preparing a packaging substrate provided in this embodiment, step S200, forming a wiring structure, includes: after obtaining the motherboard and before forming the cavity, forming an intermediate wiring layer in the groove; after forming the cavity, forming a first wiring layer on the first main surface of the substrate body and forming a second wiring layer on the second main surface of the substrate body.

[0103] In the method for preparing a packaging substrate provided in at least one embodiment of this disclosure, the steps after obtaining the sub-board further include forming a first conductive layer on the side of the sub-board facing the intermediate wiring layer, and the first conductive layer being bonded to the intermediate wiring layer.

[0104] For example, such as Figure 15 As shown, the method for preparing the packaging substrate includes the following steps.

[0105] Step S100a: Obtain the motherboard.

[0106] Step S200a: Form at least one groove on the motherboard.

[0107] Step S300a: Form an intermediate wiring layer in the groove.

[0108] Step S400a: Obtain at least one sub-plate, with each sub-plate corresponding to a groove.

[0109] Step S500a: A first conductive layer is formed on the side of the sub-board facing the intermediate wiring layer, and the first conductive layer is bonded to the intermediate wiring layer.

[0110] Step S600a: Place the sub-plate at the opening of the groove to form a cavity between it and the groove.

[0111] Step S700a: Form a first wiring layer on the first main surface of the carrier board body.

[0112] Step S800a: Form a second wiring layer on the second main surface of the carrier board body.

[0113] In the method for fabricating a packaging substrate provided in at least one embodiment of this disclosure, an intermediate wiring layer is formed using a semi-additive process. The semi-additive process (SAP) for forming the intermediate wiring layer is an important process for fabricating fine circuits, which employs a principle based on a combination of addition and etching.

[0114] Specifically, a thin metal seed layer, such as a copper layer, is first deposited on the bottom surface of the recess in an insulating substrate, such as a motherboard, using chemical plating or similar methods. This seed layer provides the basis for subsequent electroplating. Then, a photoresist pattern is formed on the seed layer using photolithography. The areas covered by the photoresist are the wiring portions that need to be retained, while the uncovered areas are etched away in subsequent steps. Next, a metal layer is thickened within the area defined by the photoresist pattern using electroplating to form the desired wiring pattern. Finally, the photoresist is removed, and the metal seed layer not protected by the photoresist is removed using etching, resulting in a precise intermediate wiring layer. The specific steps for forming the intermediate wiring layer using a semi-additive method can be designed according to the structure of the packaging substrate and actual requirements, and will not be elaborated here.

[0115] In the method for preparing a packaging substrate provided in at least one embodiment of this disclosure, the intermediate wiring layer is electrically connected perpendicularly to the first wiring layer and / or the second wiring layer.

[0116] In a method for preparing a packaging substrate provided in this embodiment, before the step of forming an intermediate wiring layer in the groove, the method further includes: forming a first type of through hole on the motherboard; and electroplating a metal layer in the first type of through hole.

[0117] In a method for preparing a packaging carrier provided in at least one embodiment of this disclosure, a first type of through hole includes a second through hole located in a groove, the second through hole extending to the second main surface of the carrier body, and / or a third through hole located around the groove, the third through hole connecting the first main surface and the second main surface of the carrier body.

[0118] In a method for preparing a packaging substrate provided in this embodiment, before the step of setting the sub-plate at the opening of the groove, the method further includes: forming a first through hole on the sub-plate; and electroplating a metal layer in the first through hole.

[0119] For example, such as Figure 16 As shown, the method for preparing the packaging substrate includes the following steps.

[0120] Step S10: Obtain the motherboard.

[0121] Step S20: Form multiple Type I through holes on the motherboard.

[0122] For example, a type I via penetrates both the first and second main surfaces of the substrate. For instance, if the motherboard is a glass substrate, a glass via, i.e., a type I via, is formed according to the design of the packaging substrate, penetrating the glass substrate in the thickness direction, i.e., the Z-direction. Specifically, the glass substrate can be any one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, or quartz glass, and the glass via can be formed using laser-induced etching; alternatively, a motherboard with type I vias can be made using photosensitive glass.

[0123] Step S30: Form at least one groove on the motherboard, and the first type of through hole located in the groove is the second through hole, and the first type of through hole located outside the groove is the third through hole.

[0124] For example, according to the design of the packaging substrate, glass micromachining is performed in a designated area of ​​the motherboard to form at least one groove, or multiple grooves, and glass vias in the groove area still exist. The glass vias located in the groove are the second vias, and the glass vias located outside the groove are the third vias.

[0125] Step S40: Electroplating to form a metal layer in the first type of through hole.

[0126] For example, a Ti / Cu seed layer is deposited using PVD, and then Cu is filled into the via using electroplating equipment; copper on the first and second main surfaces of the glass substrate is removed, and corresponding metal layers, such as metal plating, are formed in the first type of via, namely the second and third vias.

[0127] Step S50: Form an intermediate wiring layer in the groove.

[0128] Step S60: Obtain at least one sub-plate, with each sub-plate corresponding to a groove.

[0129] Step S70: Form the first through hole on the sub-plate. The specific method described in the steps above will not be repeated here.

[0130] Step S80: A first conductive layer is formed on one side of the sub-plate, and a metal layer is electroplated in the first through hole in the same process.

[0131] Step S90: Place the sub-board at the opening of the groove, and bond the first conductive layer to the intermediate wiring layer to form a cavity between the sub-board and the groove.

[0132] For example, according to the design, a sub-board with a matching groove size is bonded to the groove to form an electrical connection. This bonding method can be solder ball bonding, ACF (anisotropic conductive film) bonding, or Cu-Cu direct bonding. After the sub-board is bonded to the main board, a cavity is formed between the sub-board and the groove, which is equivalent to accommodating the intermediate wiring layer.

[0133] Step S100b: Form a first wiring layer on the first main surface of the carrier board body.

[0134] Step S110b: Form a second wiring layer on the second main surface of the carrier board body.

[0135] It should be noted that the method for preparing the packaging substrate according to the embodiments of this disclosure is not limited to the examples above. For example, it may also include other steps. Specifically, after forming the second wiring layer on the second main surface of the substrate body, solder balls may be formed on the surface of the second wiring layer away from the cavity, thereby facilitating electrical connection between the packaging substrate and external circuitry. For example, the order of forming grooves and forming through holes on the substrate may be adjusted. In addition, other steps may be adjusted according to actual needs, which will not be elaborated here.

[0136] It should be noted that the embodiments disclosed herein do not describe the entire structure of the packaging substrate. To achieve the necessary functions of the packaging substrate, those skilled in the art can configure other structures according to specific application scenarios.

[0137] This disclosure also provides a packaged chip manufactured using the above-described packaging substrate. This packaged chip not only has a small package size but also flexible wiring, improving packaging efficiency while also enhancing signal stability.

[0138] In at least one embodiment of this disclosure, the packaged chip can be assembled in an electronic device, such as a display device, which may be an organic light-emitting diode display device, a liquid crystal display device, an electronic paper display device, etc.

[0139] For example, the display device in the embodiments of this disclosure can be any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator.

[0140] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A packaging carrier board, characterized in that, include: The carrier plate body includes a first main surface and a second main surface that are opposite to each other, and the carrier plate body has at least one cavity located between the first main surface and the second main surface. as well as The wiring structure includes a first wiring layer, a second wiring layer, and an intermediate wiring layer, wherein the first wiring layer is disposed on the first main surface of the carrier board body, the intermediate wiring layer is disposed within the cavity, and the second wiring layer is disposed on the second main surface of the carrier board body.

2. The packaging carrier board according to claim 1, characterized in that, The carrier plate body includes: The motherboard includes at least one recess; and At least one sub-plate corresponds to each of the grooves, and the sub-plate is disposed at the opening of the groove, forming the cavity between the sub-plate and the groove; Preferably, multiple grooves are provided, and the multiple grooves are arranged in an array on the motherboard; Preferably, on the side of the motherboard where the groove is provided, the portion of the surface of the motherboard outside the groove and the surface of the sub-board away from the groove constitute the first main surface; Preferably, the first main surface and / or the second main surface are continuous planes; Preferably, the depth of the groove is less than or equal to half the thickness of the motherboard; Preferably, the spacing between adjacent grooves is greater than or equal to 100 μm.

3. The packaging carrier board according to claim 2, characterized in that, The wiring structure further includes a first conductive layer, which is located on the side of the sub-board facing the intermediate wiring layer and is bonded to the intermediate wiring layer.

4. The packaging carrier board according to claim 2, characterized in that, The intermediate wiring layer is electrically connected perpendicularly to the first wiring layer and / or the second wiring layer.

5. The packaging carrier board according to claim 4, characterized in that, The sub-plate is provided with a plurality of first through holes, which penetrate the sub-plate in a direction perpendicular to the main body of the carrier plate, and are filled with a first metal layer. And / or, the bottom of the groove is provided with a plurality of second through holes, which penetrate to the second main surface of the main body of the carrier plate, and are filled with a second metal layer.

6. The packaging carrier board according to claim 5, characterized in that, The motherboard has multiple third through holes located around the groove, connecting the first main surface and the second main surface of the carrier board body, and the third through holes are filled with a third metal layer.

7. A method for preparing a packaging carrier, characterized in that, include: A carrier plate body is prepared, the carrier plate body includes a first main surface and a second main surface that are opposite to each other, and at least one cavity is provided in the carrier plate body, the cavity being located between the first main surface and the second main surface; as well as A wiring structure is formed, the wiring structure including a first wiring layer, a second wiring layer and an intermediate wiring layer, wherein the first wiring layer is disposed on the first main surface of the carrier board body, the intermediate wiring layer is disposed in the cavity, and the second wiring layer is disposed on the second main surface of the carrier board body.

8. The preparation method according to claim 7, characterized in that, The steps for preparing the carrier plate body include: Obtain the motherboard; At least one groove is formed on the motherboard; Obtain at least one sub-plate, wherein each sub-plate corresponds to one of the grooves; The sub-plate is positioned at the opening of the groove, forming the cavity between it and the groove; Preferably, multiple grooves are provided, and the multiple grooves are arranged in an array on the motherboard.

9. The preparation method according to claim 8, characterized in that, The step of forming the wiring structure includes: After the step of obtaining the motherboard, and before forming the cavity, the intermediate wiring layer is formed in the groove; After the cavity is formed, the first wiring layer is formed on the first main surface of the carrier body, and the second wiring layer is formed on the second main surface of the carrier body. Preferably, the steps after obtaining the sub-board further include forming a first conductive layer on the side of the sub-board facing the intermediate wiring layer, wherein the first conductive layer is bonded to the intermediate wiring layer. Preferably, the intermediate wiring layer is formed using a semi-additive method; Preferably, the intermediate wiring layer is electrically connected perpendicularly to the first wiring layer and / or the second wiring layer.

10. The preparation method according to claim 9, characterized in that, The method further includes, prior to the step of forming the intermediate wiring layer within the groove: A first type of through-hole is formed on the motherboard; A metal layer is formed by electroplating inside the first type of through-hole; Preferably, the first type of through hole includes a second through hole located within the groove, the second through hole extending to the second main surface of the carrier plate body, and / or a third through hole located around the groove, the third through hole connecting the first main surface and the second main surface of the carrier plate body; Preferably, before the step of placing the sub-plate at the opening of the groove, the method further includes: A first through hole is formed on the sub-plate; A metal layer is formed by electroplating inside the first through hole.

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