Packaging structure and electronic equipment

Abstract

The invention provides a packaging structure and electronic equipment. The packaging structure comprises a first substrate which comprises a first side and a second side which are oppositely arranged; the second substrate is located on the first side, at least one first groove is formed in the second substrate, and the first groove penetrates through the second substrate; and the third substrate is located on the second side, at least one second groove is formed in the third substrate, and the second groove penetrates through the third substrate. According to the technical scheme, the containing substrates with the grooves are arranged on the two sides of the first substrate, and chips of different sizes can be packaged by designing the sizes and the distribution rules of the first grooves and the second grooves. According to the design, the packaging structure can be suitable for various different applications and products, and the flexibility of the packaging structure is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip packaging technology, and in particular to a packaging structure and electronic device. Background Technology

[0002] Multi-chip packaging (MCP) is an advanced technology that integrates multiple semiconductor chips into a single package structure, aiming to improve system integration, reduce power consumption, and enhance performance. As electronic products evolve towards higher performance, miniaturization, and multi-functionality, MCP is increasingly widely used in the semiconductor industry. However, existing MCP technologies have certain structural limitations, primarily in their low flexibility, which restricts their adaptability when integrating chips of different sizes. Summary of the Invention

[0003] In view of this, the embodiments of this application aim to provide a packaging structure and electronic device to solve the problem of low packaging structure flexibility.

[0004] The first aspect of this application provides a packaging structure, including: a first substrate, including a first side and a second side disposed opposite to each other; a second substrate, located on the first side, the second substrate having at least one first groove penetrating through the second substrate; and a third substrate, located on the second side, the third substrate having at least one second groove penetrating through the third substrate.

[0005] In one embodiment, the packaging structure further includes: a first adhesive layer located between the second substrate and the first substrate; and a second adhesive layer located between the third substrate and the first substrate.

[0006] In one embodiment, the first substrate includes a carrier plate and a first circuit layer and a second circuit layer distributed on both sides of the carrier plate, the first circuit layer being located on a first side and the second circuit layer being located on a second side; the carrier plate includes a plurality of first holes, the first holes penetrating the carrier plate along its thickness direction; the encapsulation structure further includes a first conductive post, the first conductive post filling the first hole, and the two ends of the first conductive post being electrically connected to the first circuit layer and the second circuit layer, respectively; the second substrate includes a plurality of second holes, the second holes penetrating the second substrate along its thickness direction; the encapsulation structure further includes a second conductive post, the second conductive post filling the second hole, and the second conductive post being electrically connected to the first circuit layer; the third substrate includes a plurality of third holes, the third holes penetrating the third substrate along its thickness direction; the encapsulation structure further includes a third conductive post, the third conductive post filling the third hole, and the third conductive post being electrically connected to the second circuit layer.

[0007] In one embodiment, the packaging structure further includes: a third circuit layer located on the side of the second substrate away from the first substrate, the third circuit layer covering the sidewall and at least part of the bottom wall of the first groove, the third circuit layer being electrically connected to the second conductive pillar; and a fourth circuit layer located on the side of the third substrate away from the first substrate, the fourth circuit layer covering the sidewall and at least part of the bottom wall of the second groove, the fourth circuit layer being electrically connected to the third conductive pillar.

[0008] In one embodiment, the packaging structure further includes: a first chip located in a first recess, the first chip being electrically connected to a third circuit layer; a second chip located in a second recess, the second chip being electrically connected to a fourth circuit layer; preferably, the cross-sectional shape of the first recess is trapezoidal; preferably, the bottom wall shape of the first recess is circular or rectangular; preferably, the cross-sectional shape of the second recess is trapezoidal; preferably, the bottom wall shape of the second recess is circular or rectangular.

[0009] In one embodiment, the package structure further includes: an insulating layer located on the side of the fourth circuit layer facing away from the first substrate; preferably, the insulating layer includes a plurality of fourth holes, the fourth holes penetrating the insulating layer along the thickness direction of the insulating layer; the package structure further includes a fourth conductive post, the fourth conductive post filling the fourth hole, the fourth conductive post being electrically connected to the fourth circuit layer; preferably, the package structure further includes a metal layer located on the side of the insulating layer facing away from the fourth circuit layer, the metal layer being electrically connected to the fourth conductive post; preferably, the package structure further includes a plurality of solder balls located on the side of the metal layer facing away from the insulating layer, the plurality of solder balls being electrically connected to the metal layer, and the plurality of solder balls having intervals between them.

[0010] In one embodiment, the packaging structure further includes: a first molding structure that fills a first groove; a second molding structure that fills a second groove; preferably, the packaging structure further includes a molding layer located on the side of the third circuit layer opposite to the second substrate, the molding layer covering a portion of the surface of the first molding structure.

[0011] In one embodiment, the first substrate is provided with at least one third groove, the opening of the third groove facing the first side; preferably, the cross-sectional shape of the third groove is trapezoidal; preferably, the bottom wall shape of the third groove is circular or rectangular.

[0012] In one embodiment, the first substrate further comprises at least one fourth groove, the opening of which faces the second side; preferably, the cross-sectional shape of the fourth groove is trapezoidal; preferably, the bottom wall shape of the fourth groove is circular or rectangular; preferably, the third and fourth grooves are arranged alternately; preferably, the third and fourth grooves are arranged symmetrically about the center plane of the first substrate.

[0013] A second aspect of this application provides an electronic device, including a packaging structure as mentioned in any of the above embodiments.

[0014] The technical solution provided in this application forms a packaging structure capable of integrating chips of various sizes by setting an independent first substrate, and setting a second substrate and a third substrate respectively on a first side and a second side opposite to the first substrate. At least one first groove penetrating the second substrate is formed in the second substrate, and at least one second groove penetrating the third substrate is formed in the third substrate. This configuration allows for the packaging of chips of different sizes by designing the size and distribution of the first and second grooves. This design makes the packaging structure suitable for a variety of different applications and products, improving the flexibility of the packaging structure.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 The diagram shown is a schematic diagram of the packaging structure provided in an embodiment of this application.

[0018] Figure 2 The diagram shown is a schematic diagram of the packaging structure provided in another embodiment of this application.

[0019] Figure 3 The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0020] Figure 4 The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0021] Figure 5a The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0022] Figure 5b The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0023] Figure 6 The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0024] Figure 7 The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0025] Figure 8 The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0026] Figure 9 The diagram shown is a structural schematic of the packaging structure provided in another embodiment of this application.

[0027] Figure 10 The diagram shown is a flowchart of an embodiment of the encapsulation method provided in this application.

[0028] Figures 11a-11h The diagram shown is a structural schematic of an intermediate product with a packaging structure provided in an embodiment of this application. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] Figure 1 The diagram shown is a schematic representation of the packaging structure provided in one embodiment of this application. See also... Figure 1 The packaging structure includes: a first substrate 101, including a first side 1011 and a second side 1012 disposed opposite to each other; a second substrate 102, located on the first side 1011, the second substrate 102 having at least one first groove 1021 penetrating the second substrate 102; and a third substrate 103, located on the second side 1012, the third substrate 103 having at least one second groove 1031 penetrating the third substrate 103.

[0031] Specifically, the first substrate 101 includes two opposing surfaces, namely a first side 1011 and a second side 1012. Exemplarily, wiring is provided on both sides of the first substrate 101 for redistributing or expanding circuit connections to accommodate different packaging requirements. The second substrate 102 is located on the first side 1011 of the first substrate 101 and is used to mount chips. The second substrate 102 has at least one first groove 1021, which penetrates the second substrate 102 in the thickness direction. Exemplarily, the first groove 1021 is used to accommodate and fix chips, and the chips located within the first groove 1021 are electrically connected to the first substrate 101. The third substrate 103 is located on the second side 1012 of the first substrate 101 and is also used to mount chips. The third substrate 103 has at least one second groove 1031, which penetrates the third substrate 103 in the thickness direction. Exemplarily, the second groove 1031 is also used to accommodate and fix chips, and the chips located within the second groove 1031 are also electrically connected to the first substrate 101. The dimensions of the first groove 1021 and the second groove 1031 can be designed according to the chip size to be packaged. For example, the materials of the second substrate 102 and the third substrate 103 can both be glass. Glass has a low coefficient of thermal expansion and low dielectric loss, making the package structure less prone to warping when heated.

[0032] Furthermore, the area of ​​the surface of the first groove 1021 facing the first substrate 101 is smaller than the area of ​​the first substrate 101, and the area of ​​the surface of the second groove 1031 facing the first substrate 101 is smaller than the area of ​​the first substrate 101.

[0033] The technical solution of this embodiment, by setting an independent first substrate 101, and setting a second substrate 102 and a third substrate 103 on the first side 1011 and the second side 1012 opposite to the first substrate 101, respectively, forms a packaging structure that can integrate chips of various sizes by setting at least one first groove 1021 penetrating the second substrate 102 and at least one second groove 1031 penetrating the third substrate 103. This configuration allows for the packaging of chips of different sizes by designing the size and distribution of the first groove 1021 and the second groove 1031. This design makes the packaging structure suitable for a variety of different applications and products, improving the flexibility of the packaging structure.

[0034] Figure 2 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 2 As shown, the packaging structure further includes: a first adhesive layer 104 located between the second substrate 102 and the first substrate 101; and a second adhesive layer 105 located between the third substrate 103 and the first substrate 101.

[0035] Specifically, a first adhesive layer 104 is provided between the second substrate 102 and the first substrate 101 to firmly bond the second substrate 102 and the first substrate 101 together, providing mechanical support and ensuring the stability of the entire packaging structure. A second adhesive layer 105 is provided between the third substrate 103 and the first substrate 101 to firmly bond the third substrate 103 and the first substrate 101 together, providing mechanical support and ensuring the stability of the entire packaging structure. The advantage of this arrangement is that the first adhesive layer 104 and the second adhesive layer 105 provide strong adhesion, ensuring a firm connection between the second substrate 102 (third substrate 103) and the first substrate 101, preventing relative movement during assembly or use, and ensuring the continuity and reliability of the electrical connection.

[0036] Figure 3 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 3 As shown, the first substrate 101 includes a carrier plate 1013 and a first circuit layer 1014 and a second circuit layer 1015 distributed on both sides of the carrier plate 1013. The first circuit layer 1014 is located on the first side 1011, and the second circuit layer 1015 is located on the second side 1012. The carrier plate 1013 includes a plurality of first holes 1016, which penetrate the carrier plate 1013 along the thickness direction. The encapsulation structure also includes a first conductive post 1017, which fills the first holes 1016, and the two ends of the first conductive post 1017 are electrically connected to the first circuit layer 1014 and the second circuit layer 1015, respectively. The board 102 includes a plurality of second holes 1022, which penetrate the second substrate 102 along the thickness direction of the second substrate 102; the packaging structure also includes a second conductive post 1023, which fills the second holes 1022 and is electrically connected to the first circuit layer 1014; the third substrate 103 includes a plurality of third holes 1032, which penetrate the third substrate 103 along the thickness direction of the third substrate 103; the packaging structure also includes a third conductive post 1033, which fills the third holes 1032 and is electrically connected to the second circuit layer 1015.

[0037] Specifically, the carrier plate 1013 is used to support and isolate the first circuit layer 1014 and the second circuit layer 1015. For example, the carrier plate 1013 can be made of glass, which has a low coefficient of thermal expansion and low dielectric loss, making the encapsulation structure less prone to warping when heated. The first circuit layer 1014 and the second circuit layer 1015 are distributed on opposite sides of the carrier plate 1013, used to establish and distribute circuit connections. The carrier plate 1013 has multiple first holes 1016, which penetrate the carrier plate 1013 along its thickness direction, serving as conductive (thermal) channels within the carrier plate 1013. First conductive posts 1017 correspond one-to-one with the multiple first holes 1016 on the carrier plate 1013. The first conductive post 1017 is a columnar conductor filling the first hole 1016, used to establish electrical connection points on both sides of the carrier plate 1013. The first circuit layer 1014 and the second circuit layer 1015 are both electrically connected to the first conductive post 1017, and are used to transmit signals and power between the two sides of the carrier board 1013.

[0038] The second substrate 102 has a plurality of second holes 1022, which penetrate the second substrate 102 along its thickness direction and serve as conductive (thermal) channels within it. Second conductive pillars 1023 correspond one-to-one with the plurality of second holes 1022 on the second substrate 102. Each second conductive pillar 1023 is a columnar conductor filling the second hole 1022, used to establish electrical connection points on both sides of the second substrate 102. The second conductive pillars 1023 are electrically connected to the first circuit layer 1014, used to transmit signals from the first circuit layer 1014 to other components on the second substrate 102.

[0039] The third substrate 103 has multiple third holes 1032, which penetrate the third substrate 103 along its thickness direction and serve as conductive (thermal) channels within it. Each third conductive post 1033 corresponds one-to-one with one of the third holes 1032 on the third substrate 103. The third conductive post 1033 is a columnar conductor filling the third hole 1032, used to establish electrical connection points on both sides of the third substrate 103. The third conductive post 1033 is electrically connected to the second circuit layer 1015, used to transmit signals from the second circuit layer 1015 to other components on the third substrate 103.

[0040] The technical solution of this embodiment achieves circuit connection between the two sides of the carrier board 1013 by providing a first hole 1016 penetrating the carrier board 1013, filling the first hole 1016 with a first conductive post 1017, and providing a first circuit layer 1014 and a second circuit layer 1015 on opposite sides of the carrier board 1013, electrically connected to the first conductive post 1017, thus forming a first substrate 101. Furthermore, a second hole 1022 and a third hole 1032 are provided on the second substrate 102 and the third substrate 103, respectively. The second hole 1022 is filled with a second conductive post 1023, and the third hole 1032 is filled with a third conductive post 1033, so that the second conductive post 1023 is electrically connected to the first circuit layer 1014, and the third conductive post 1033 is electrically connected to the second circuit layer 1015, thereby achieving circuit connection between the second substrate 102 and the first substrate 101, and between the third substrate 103 and the first substrate 101. This arrangement achieves multi-layer circuit connection within a limited space, improving the compactness of the packaging structure.

[0041] Figure 4 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 4 As shown, the packaging structure further includes: a third circuit layer 106 located on the side of the second substrate 102 away from the first substrate 101, the third circuit layer 106 covering the sidewall and at least part of the bottom wall of the first groove 1021, and the third circuit layer 106 and the second conductive post 1023 being electrically connected; and a fourth circuit layer 107 located on the side of the third substrate 103 away from the first substrate 101, the fourth circuit layer 107 covering the sidewall and at least part of the bottom wall of the second groove 1031, and the fourth circuit layer 107 and the third conductive post 1033 being electrically connected.

[0042] Specifically, a third circuit layer 106 is disposed on the side of the second substrate 102 opposite to the first substrate 101. The third circuit layer 106 and the second conductive post 1023 are electrically connected, thereby establishing an electrical connection between the first circuit layer 1014 and the third circuit layer 106. Exemplarily, a chip is mounted in a first recess 1021, with the chip's pins facing the bottom wall of the first recess 1021. The third circuit layer 106 covers the sidewalls and at least part of the bottom wall of the first recess 1021, thereby achieving an electrical connection between the third circuit layer 106 and the chip. A fourth circuit layer 107 is disposed on the side of the third substrate 103 opposite to the first substrate 101. The fourth circuit layer 107 and the third conductive post 1033 are electrically connected, thereby establishing an electrical connection between the second circuit layer 1015 and the fourth circuit layer 107. Exemplarily, a chip is mounted in a second recess 1031, with the chip's pins facing the bottom wall of the second recess 1031. The fourth circuit layer 107 covers the sidewalls and at least part of the bottom wall of the second recess 1031, thereby achieving an electrical connection between the fourth circuit layer 107 and the chip.

[0043] The technical solution of this embodiment achieves electrical connection between the third circuit layer 106 and the first circuit layer 1014 by providing a third circuit layer 106 on the side of the second substrate 102 away from the first substrate 101, and electrically connecting the third circuit layer 106 and the second conductive pillar 1023; and achieves electrical connection between the fourth circuit layer 107 and the second circuit layer 1015 by providing a fourth circuit layer 107 on the side of the third substrate 103 away from the first substrate 101, and electrically connecting the fourth circuit layer 107 and the third conductive pillar 1033. By providing the third circuit layer 106 and the fourth circuit layer 107, it can be ensured that the first circuit layer 1014 and the second circuit layer 1015 form an electrical connection path with the external circuit. Furthermore, a third circuit layer 106 is provided to cover the sidewall and at least part of the bottom wall of the first groove 1021, and a fourth circuit layer 107 is provided to cover the sidewall and at least part of the bottom wall of the second groove 1031, so that the chips installed in the first groove 1021 and the second groove 1031 can communicate with external circuits through the third circuit layer 106 and the fourth circuit layer 107 respectively, which is beneficial to improving the reliability of the packaging structure.

[0044] Figure 5a The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 5a As shown, the packaging structure further includes: a first chip 108 located within a first groove 1021, the first chip 108 being electrically connected to a third circuit layer 106; a second chip 109 located within a second groove 1031, the second chip 109 being electrically connected to a fourth circuit layer 107; preferably, the cross-sectional shape of the first groove 1021 is trapezoidal; preferably, the bottom wall shape of the first groove 1021 is circular or rectangular; preferably, the cross-sectional shape of the second groove 1031 is trapezoidal; preferably, the bottom wall shape of the second groove 1031 is circular or rectangular.

[0045] Specifically, a first chip 108 is installed in a first recess 1021, with its pins facing the bottom or sidewall of the first recess 1021, enabling the first chip 108 to connect to the third circuit layer 106 for communication with other circuit elements. A second chip 109 is installed in a second recess 1031, with its pins facing the bottom or sidewall of the second recess 1031, enabling the second chip 109 to connect to the fourth circuit layer 107 for communication. Exemplarily, the first recess 1021 has a trapezoidal cross-sectional shape, a circular or rectangular bottom wall shape, and a cylindrical or trapezoidal three-dimensional shape. This arrangement is advantageous because the shape of the first recess 1021 is easily matched to the shape of the first chip 108, facilitating the installation and fixation of the first chip 108. Exemplarily, the second recess 1031 has a trapezoidal cross-sectional shape, a circular or rectangular bottom wall shape, and a cylindrical or trapezoidal three-dimensional shape. The advantage of this design is that the shape of the second groove 1031 is conducive to matching the shape of the second chip 109, making it easier to install and fix the second chip 109.

[0046] The technical solution of this embodiment involves placing the first chip 108 within the first recess 1021, electrically connecting the first chip 108 to the third circuit layer 106; and placing the second chip 109 within the second recess 1031, electrically connecting the second chip 109 to the fourth circuit layer 107. This arrangement reduces the space required for chip packaging, which is beneficial for reducing the size of the packaging structure. By setting the cross-sectional shape of the first recess 1021 (second recess 1031) to be trapezoidal, and the bottom wall shape to be circular or rectangular, the shapes of the first recess 1021 (second recess 1031) and the first chip 108 (second chip 109) are more closely matched, which is beneficial for fixing the first chip 108 (second chip 109) and thus improves the reliability of the packaging structure.

[0047] Figure 5b The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 5bAs shown, when the area of ​​at least one of the second substrate 102 and the third substrate 103 is smaller than the area of ​​the first substrate 101, a chip can also be placed in a position on the first substrate 101 not covered by the second substrate 102 or the third substrate 103. Specifically, the first chip 108 is mounted in the first recess 1021 with its pins facing the bottom wall or side wall of the first recess 1021, so that the first chip 108 is connected to the third circuit layer 106 for communication with other circuit elements. One of the second chips 109 is mounted in the second recess 1031 with its pins facing the bottom wall or side wall of the second recess 1031, so that the second chip 109 is connected to the fourth circuit layer 107 for communication. The other of the second chips 109 is mounted on the side of the first substrate 101 facing the third substrate 103 and is connected to the fourth circuit layer 107 for communication.

[0048] Figure 6 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 6 As shown, the packaging structure further includes: an insulating layer 110 located on the side of the fourth circuit layer 107 facing away from the first substrate 101; preferably, the insulating layer 110 includes a plurality of fourth holes 1101, the fourth holes 1101 penetrating the insulating layer 110 along the thickness direction of the insulating layer 110; the packaging structure further includes a fourth conductive post 1102, the fourth conductive post 1102 filling the fourth holes 1101, the fourth conductive post 1102 and the fourth circuit layer 107 being electrically connected; preferably, the packaging structure further includes a metal layer 111 located on the side of the insulating layer 110 facing away from the fourth circuit layer 107, the metal layer 111 and the fourth conductive post 1102 being electrically connected; preferably, the packaging structure further includes a plurality of solder balls 112 located on the side of the metal layer 111 facing away from the insulating layer 110, the plurality of solder balls 112 and the metal layer 111 being electrically connected, the plurality of solder balls 112 being spaced apart.

[0049] Specifically, an insulating layer 110 is provided on the side of the fourth circuit layer 107 facing away from the first substrate 101. Part of the insulating layer 110 and the fourth circuit layer 107 are disposed on the same layer to isolate a portion of the fourth circuit layer 107 from the metal layer 111, preventing short circuits. Multiple fourth holes 1101 penetrating the insulating layer 110 are provided as conductive channels. Fourth conductive posts 1102 fill the fourth holes 1101 to establish electrical connections on both sides of the insulating layer 110. The fourth conductive posts 1102 are electrically connected to the fourth circuit layer 107. A metal layer 111 is provided on the side of the insulating layer 110 facing away from the fourth circuit layer 107. The metal layer 111 is used to establish external electrical connections and is electrically connected to the fourth conductive posts 1102. The fourth circuit layer 107 is electrically connected to the metal layer 111 through the fourth conductive posts 1102. Solder balls 112, such as metal balls, are located on the side of the metal layer 111 facing away from the insulating layer 110, and are used to achieve electrical connection between the metal layer 111 and external circuitry. Spacing exists between multiple solder balls 112. As electrical connection points, the solder balls 112 need to be spaced sufficiently to prevent short circuits. If the solder balls 112 are too close together, solder diffusion or other factors may cause electrical connections between adjacent solder balls 112, resulting in circuit failure. Spacing reduces thermal coupling between multiple solder balls 112, helps to distribute heat more evenly, and prevents localized overheating. Based on the above embodiments, the chip located within the package structure can communicate with external circuitry through the metal layer 111, solder balls 112, and external circuitry.

[0050] The technical solution of this embodiment achieves electrical connection between the fourth circuit layer 107 and the metal layer 111 by sequentially setting an insulating layer 110, a metal layer 111, and solder balls 112 on the side of the fourth circuit layer 107 facing away from the first substrate 101. Multiple fourth holes 1101 are formed on the insulating layer 110, and fourth conductive pillars 1102 are filled within the fourth holes 1101, ensuring smooth signal transmission. The insulating layer 110 also ensures partial electrical isolation between the fourth circuit layer 107 and the metal layer 111, preventing short circuits and improving package reliability. Furthermore, the design of the solder balls 112 allows the package structure to be easily connected to an external circuit board, simplifying the assembly process.

[0051] Figure 7 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 7 As shown, the packaging structure further includes: a first molding structure 113, which fills the first groove 1021; a second molding structure 114, which fills the second groove 1031; preferably, the packaging structure further includes a molding layer 115, located on the side of the third circuit layer 106 away from the second substrate 102, and the molding layer 115 covers part of the surface of the first molding structure 113.

[0052] Specifically, the first molding compound 113 fills the first recess 1021, covering the exposed surface of the first chip 108, for fixing and protecting the first chip 108 and providing mechanical support. Exemplarily, the first molding compound 113 may be made of epoxy resin or other types of plastic. The second molding compound 114 fills the second recess 1031, covering the exposed surface of the second chip 109, for fixing and protecting the second chip 109 and providing mechanical support. Exemplarily, the second molding compound 114 may also be made of epoxy resin or other types of plastic. A molding compound 115 is also provided on the side of the third circuit layer 106 facing away from the second substrate 102, covering a portion of the surface of the first molding compound 113 and the surface of the third circuit layer 106 facing away from the second substrate 102. Exemplarily, the molding compound 115 may also be made of epoxy resin or other plastic materials. The molding compound has good thermal insulation properties, which helps maintain the operating temperature of the chip and prevents overheating. The molding compound also provides electrical insulation, preventing potential short circuit problems.

[0053] The technical solution of this embodiment fills the first molding compound 113 and the second molding compound 114 into the first groove 1021 and the second groove 1031 respectively, thereby protecting and further fixing the first chip 108 and the second chip 109, and extending the service life of the first chip 108 and the second chip 109. Furthermore, a molding compound 115 is provided on the side of the third circuit layer 106 facing away from the second substrate 102, enhancing the overall reliability of the package.

[0054] Figure 8 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 8 As shown, the first substrate 101 is provided with at least one third groove 116, the opening of the third groove 116 facing the first side 1011; preferably, the cross-sectional shape of the third groove 116 is trapezoidal; preferably, the bottom wall shape of the third groove 116 is circular or rectangular.

[0055] Specifically, at least one third groove 116 is provided on the first substrate 101, with its opening facing the first side 1011. Exemplarily, the third groove 116 can be used to accommodate a chip. Exemplarily, the cross-sectional shape of the third groove 116 is trapezoidal, the bottom wall shape of the third groove 116 is circular or rectangular, and the three-dimensional shape of the third groove 116 can be a cylinder or a trapezoid. The advantage of this arrangement is that the shape of the third groove 116 is conducive to matching the shape of the chip, facilitating chip installation and fixation. See also, for an example... Figure 8 The first circuit layer 1014 covers the sidewalls and at least part of the bottom wall of the third recess 116. The package structure also includes a third chip 118 disposed in the third recess 116, and the third chip 118 is electrically connected to the first circuit layer 1014.

[0056] The technical solution of this embodiment provides at least one third groove 116 on the first substrate 101, which allows chips to be mounted within the third groove 116, further increasing the number of chips that can be packaged in the packaging structure, improving packaging density, and reducing the size of multi-chip packages. By setting the cross-sectional shape of the third groove 116 to be trapezoidal and the bottom wall shape to be circular or rectangular, the third groove 116 is made more compatible with the shape of the chip, which is beneficial for chip fixation and thus helps to improve the reliability of the packaging structure.

[0057] Figure 9 The diagram shown is a structural schematic of a packaging structure provided in another embodiment of this application. Figure 9 As shown, the first substrate 101 is further provided with at least one fourth groove 117, the opening of the fourth groove 117 facing the second side 1012; preferably, the cross-sectional shape of the fourth groove 117 is trapezoidal; preferably, the bottom wall shape of the fourth groove 117 is circular or rectangular; preferably, the third groove 116 and the fourth groove 117 are arranged alternately; preferably, the third groove 116 and the fourth groove 117 are arranged symmetrically about the center plane of the first substrate 101.

[0058] Specifically, at least one fourth groove 117 is provided on the first substrate 101, with its opening facing the second side 1012. That is, the fourth groove 117 and the third groove 116 are distributed on opposite sides of the first substrate 101. Exemplarily, the fourth groove 117 can be used to accommodate a chip. Exemplarily, the cross-sectional shape of the fourth groove 117 is trapezoidal, the bottom wall shape of the fourth groove 117 is circular or rectangular, and the three-dimensional shape of the fourth groove 117 can be a cylinder or a trapezoid. The advantage of this arrangement is that the shape of the fourth groove 117 is conducive to matching the shape of the chip, facilitating chip installation and fixation. See also, for an example... Figure 9 The second circuit layer 1015 covers the sidewalls and at least part of the bottom wall of the fourth recess 117. The package structure also includes a fourth chip 119 disposed in the fourth recess 117, and the fourth chip 119 is electrically connected to the second circuit layer 1015.

[0059] In some embodiments, see Figure 8 The third groove 116 and the fourth groove 117 are arranged alternately on the first substrate 101. This arrangement can further increase the number of packageable chips and also ensure the support strength of the carrier plate 1013 in the first substrate 101.

[0060] In other embodiments, see Figure 9The third groove 116 and the fourth groove 117 are symmetrically arranged about the center plane of the first substrate 101. This arrangement makes the packaging structure simple and easy to implement, reduces the area required for multiple chips in the extension direction of the first substrate 101, and further reduces the volume of the multi-chip packaging structure.

[0061] For example, see Figure 8 and Figure 9 A packaging interconnection structure similar to the insulating layer 110, metal layer 111, and solder ball 112 is provided on the side of the second circuit layer 1015 away from the carrier board 1013. Molding material is filled in the third groove 116 and the fourth groove 117, and a protective layer similar to the molding layer 115 is provided on the side of the first circuit layer 1014 away from the carrier board 1013 to improve the reliability of the packaging.

[0062] The technical solution of this embodiment provides at least one fourth groove 117 on the first substrate 101, allowing chips to be mounted within the fourth groove 117. This further increases the number of chips that can be packaged, improves packaging density, and reduces the size of multi-chip packages. By setting the cross-sectional shape of the fourth groove 117 to be trapezoidal and the bottom wall shape to be circular or rectangular, the fourth groove 117 is better adapted to the shape of the chip, which is beneficial for chip fixation and thus improves the reliability of the packaging structure. The alternating arrangement of the third groove 116 and the fourth groove 117 ensures the support of the first substrate 101. The symmetrical arrangement of the third groove 116 and the fourth groove 117 about the center plane of the first substrate 101 makes more efficient use of the space of the first substrate 101, resulting in a more compact packaging structure.

[0063] Figure 10 The diagram shown is a schematic flowchart of a packaging method provided in an embodiment of this application. This packaging method is applicable to the packaging of chips. Figures 11a-11h The diagram shown is a structural schematic of an intermediate product with a packaging structure provided in one embodiment of this application. Figure 10 As shown, the encapsulation method includes: S110 provides a carrier board.

[0064] Specifically, see Figure 11a The carrier plate 1013 has a square shape. Exemplarily, the material of the carrier plate 1013 includes alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass.

[0065] S120, a third groove is formed on the first side of the carrier plate, and a fourth groove is formed on the second side of the carrier plate.

[0066] Specifically, see Figure 11bThe third groove 116 and the fourth groove 117 are arranged alternately on the carrier plate, and the third groove 116 and the fourth groove 117 can be opened by laser-induced etching process.

[0067] S130, multiple first holes are formed on the carrier plate, and the first holes penetrate the carrier plate along the thickness direction.

[0068] Specifically, see Figure 11c Using laser-induced etching technology, multiple first holes 1016 are precisely formed on the carrier plate 1013 according to a predetermined design pattern.

[0069] S140, a first conductive post is prepared in the first hole.

[0070] Specifically, see Figure 11d The first conductive pillar 1017 can be prepared in the first hole 1016 by electroplating or sputtering.

[0071] S150, a first circuit layer and a second circuit layer are respectively fabricated on both sides of the carrier board. The first circuit layer is electrically connected to the first conductive pillar, and the second circuit layer is electrically connected to the first conductive pillar.

[0072] Specifically, see Figure 11e Using exposure and development technology, a first circuit layer 1014 and a second circuit layer 1015 are respectively prepared on both sides of the carrier plate 1013. The first circuit layer 1014 covers the sidewall and at least part of the bottom wall of the third groove 116, and the second circuit layer 1015 covers the sidewall and at least part of the bottom wall of the fourth groove 117.

[0073] S160, a third chip is installed in the third recess, and the third chip is electrically connected to the first circuit layer; a fourth chip is installed in the fourth recess, and the fourth chip is electrically connected to the second circuit layer.

[0074] Specifically, see Figure 11f A third chip 118 is placed on the first circuit layer 1014 within the third recess 116. The third chip 118 has electrical connection points that connect to the first circuit layer 1014. The surface of the third chip 118 with conductive connection points faces the bottom wall of the third recess 116, and the third chip 118 and the first circuit layer 1014 are soldered together. A fourth chip 119 is placed on the second circuit layer 1015 within the fourth recess 117. The fourth chip 119 has electrical connection points that connect to the second circuit layer 1015. The surface of the fourth chip 119 with conductive connection points faces the bottom wall of the fourth recess 117, and the fourth chip 119 and the second circuit layer 1015 are soldered together.

[0075] S170, the third and fourth grooves are filled with encapsulating material.

[0076] Specifically, see Figure 11gThe molding compound can be an encapsulation material or encapsulating adhesive with functions such as electrical insulation, fixation, and moisture protection, such as epoxy molding compound, low-temperature co-fired ceramic material, and aluminum nitride ceramic material. During filling, the structure obtained using S160 is placed into the mold, and the molding compound is poured into the third groove 116 and the fourth groove 117 through the mold. Then, by heating, the molding compound is liquefied, so that it encapsulates the third chip 118 and the fourth chip 119. Subsequently, the excess molding compound is removed, so that the surface of the molding compound is flush with the surface of the carrier board 1013.

[0077] S180, a protective layer is prepared on the side of the first circuit layer away from the carrier board, and a package interconnect structure is prepared on the side of the second circuit layer away from the carrier board.

[0078] Specifically, see Figure 11h A protective layer is prepared using a molding compound on the side of the first circuit layer 1014 away from the carrier board 1013, and an encapsulation interconnect structure is prepared on the side of the second circuit layer 1015 away from the carrier board 1013.

[0079] This application also provides an electronic device, including a packaging structure as mentioned in any of the above embodiments. The electronic device provided in this application has the beneficial effects of the packaging structure mentioned in the above embodiments, and its technical principles and effects are similar, so they will not be described again here.

[0080] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0081] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A packaging structure, characterized in that, include: The first substrate includes a first side and a second side disposed opposite to each other; A second substrate is located on the first side, and the second substrate is provided with at least one first groove, the first groove penetrating the second substrate; A third substrate is located on the second side, and the third substrate has at least one second groove that penetrates the third substrate.

2. The packaging structure according to claim 1, characterized in that, Also includes: A first adhesive layer is located between the second substrate and the first substrate; The second adhesive layer is located between the third substrate and the first substrate.

3. The packaging structure according to claim 1, characterized in that, The first substrate includes a carrier plate and a first circuit layer and a second circuit layer distributed on both sides of the carrier plate, wherein the first circuit layer is located on the first side and the second circuit layer is located on the second side; the carrier plate includes a plurality of first holes, wherein the first holes penetrate the carrier plate along the thickness direction of the carrier plate; The encapsulation structure further includes a first conductive post, which fills the first hole, and the two ends of the first conductive post are electrically connected to the first circuit layer and the second circuit layer, respectively. The second substrate includes a plurality of second holes, which penetrate the second substrate along the thickness direction of the second substrate; the packaging structure further includes second conductive pillars, which fill the second holes and are electrically connected to the first circuit layer; The third substrate includes a plurality of third holes, which penetrate the third substrate along the thickness direction; the packaging structure also includes a third conductive pillar, which fills the third holes and is electrically connected to the second circuit layer.

4. The packaging structure according to claim 3, characterized in that, Also includes: A third circuit layer is located on the side of the second substrate opposite to the first substrate. The third circuit layer covers the sidewall and at least part of the bottom wall of the first groove. The third circuit layer is electrically connected to the second conductive pillar. A fourth circuit layer is located on the side of the third substrate opposite to the first substrate. The fourth circuit layer covers the sidewall and at least part of the bottom wall of the second groove. The fourth circuit layer is electrically connected to the third conductive pillar.

5. The packaging structure according to claim 4, characterized in that, Also includes: A first chip is located in the first groove, and the first chip is electrically connected to the third circuit layer. The second chip is located in the second groove, and the second chip is electrically connected to the fourth circuit layer; Preferably, the cross-sectional shape of the first groove is trapezoidal; Preferably, the bottom wall of the first groove is circular or rectangular; Preferably, the cross-sectional shape of the second groove is trapezoidal; Preferably, the bottom wall of the second groove is circular or rectangular.

6. The packaging structure according to claim 4, characterized in that, Also includes: An insulating layer is located on the side of the fourth circuit layer that faces away from the first substrate; Preferably, the insulating layer includes a plurality of fourth holes, which penetrate the insulating layer along the thickness direction; the encapsulation structure further includes a fourth conductive post, which fills the fourth holes and is electrically connected to the fourth circuit layer; Preferably, the packaging structure further includes a metal layer located on the side of the insulating layer opposite to the fourth circuit layer, and the metal layer and the fourth conductive post are electrically connected; Preferably, the packaging structure further includes a plurality of solder balls located on the side of the metal layer away from the insulating layer, the plurality of solder balls being electrically connected to the metal layer, and the plurality of solder balls being spaced apart.

7. The packaging structure according to claim 4, characterized in that, Also includes: A first encapsulation structure, wherein the first encapsulation structure fills the first groove; A second molding structure, wherein the second molding structure fills the second groove; Preferably, the packaging structure further includes a molding layer located on the side of the third circuit layer opposite to the second substrate, and the molding layer covers a portion of the surface of the first molding structure.

8. The packaging structure according to claim 1, characterized in that, The first substrate is provided with at least one third groove, the opening of which faces the first side; Preferably, the cross-sectional shape of the third groove is trapezoidal; Preferably, the bottom wall of the third groove is circular or rectangular.

9. The packaging structure according to claim 8, characterized in that, The first substrate is further provided with at least one fourth groove, the opening of which faces the second side; Preferably, the cross-sectional shape of the fourth groove is trapezoidal; Preferably, the bottom wall of the fourth groove is circular or rectangular; Preferably, the third groove and the fourth groove are arranged alternately; Preferably, the third groove and the fourth groove are arranged symmetrically about the center face of the first substrate.

10. An electronic device, characterized in that, include: The packaging structure as described in any one of claims 1 to 9.

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