Ultrathin HBPOP packaging structure and packaging method based on Open MD and TMV technology

Abstract

The invention discloses an ultrathin HBPOP packaging structure and packaging method based on Open MD and TMV technologies, and relates to the technical field of IC manufacturing semiconductor chip packaging. The SOC chip is horizontally and inversely arranged in the central area of the upper surface of the substrate; the LPDDR chip is horizontally mounted on the upper portion of the SOC chip, and the distance between the lower surface of the LPDDR chip and the upper surface of the SOC chip is not larger than a first preset distance; and the solder balls are welded between the upper surface of the substrate and the lower surface of the LPDDR chip. According to the invention, the solder balls are pre-planted on the original substrate, and then the holes are formed to expose the solder balls for circuit connection, so that the process difficulty is low, a plastic package body is tighter, an adapter plate is not needed between the LPDDR chip and the SOC chip, the overall thickness can be reduced by about 100 microns, the cost is greatly reduced, and the thicknesses of electronic products such as mobile phones and the like can be thinner.

Description

Technical Field

[0001] This invention relates to the field of IC manufacturing semiconductor chip manufacturing technology, and in particular to an ultra-thin HBPOP chip packaging, specifically an ultra-thin HBPOP packaging structure and packaging method based on Open MD and TMV processes. Background Technology

[0002] Currently, as the growth focus of the IC industry shifts from traditional computer and communication fields to portable mobile devices, IC packaging technology is facing continuous pressure to innovate in order to meet the specific needs of mobile devices in terms of functional flexibility, miniaturization, and cost reduction. Against this backdrop, the POP stacking packaging solution in 3D packaging technology has emerged, and thanks to its high integration advantage, it has quickly become the preferred solution for integrating logic and memory ICs.

[0003] Point-of-Pack (POP) packaging technology has become the preferred solution for integrating logic and memory ICs, widely used in mobile devices, smart homes, industrial automation, and many other fields. Among these, mobile devices are undoubtedly the primary application area for POP technology, accounting for the majority of the market share. This is thanks to the high wafer utilization rate of POP packaging technology, enabling mobile devices to achieve more functions; at the same time, it saves substrate space, reduces circuit board area, and provides faster data generation rates, lowering overall costs. These advantages collectively improve the transmission efficiency, heat dissipation performance, image quality, and key performance characteristics such as low latency and low power consumption of terminal devices.

[0004] As mobile phones and other electronic products trend towards thinner and smaller designs, multiple components, such as SOC chips, memory chips, batteries, and sensors, need to be placed within limited space. By increasing the integration of different types of chips and reducing the overall chip size, larger batteries or larger lens modules can be accommodated. This invention provides an ultra-thin HBPOP packaging method based on OpenMD and TMV processes, which stacks and packages SOC chips and LPDDR chips together, thereby optimizing the internal space of mobile phones and other electronic products, and allowing for arbitrary combinations of LPDDR chips and SOC chips of different capacities. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an ultra-thin HBPOP packaging structure and method based on Open MD and TMV processes. This invention is applicable to problems such as the inability to optimize the internal space of mobile phones and other electronic products when stacking and packaging SOC chips and LPDDR chips together.

[0006] To achieve the above objectives, the first technical solution adopted by the present invention is: an ultra-thin HBPOP packaging structure based on Open MD and TMV processes, comprising: a substrate; a SOC chip, wherein the SOC chip is horizontally flip-chip mounted on the central region of the upper surface of the substrate; an LPDDR chip, wherein the LPDDR chip is horizontally mounted above the SOC chip, and the distance between the lower surface of the LPDDR chip and the upper surface of the SOC chip is not greater than a first predetermined distance, and the distance between the lower surface of the LPDDR chip and the upper surface of the substrate is not greater than a second predetermined distance; and solder balls, wherein the solder balls are soldered between the upper surface of the substrate and the lower surface of the LPDDR chip, and the height of the solder balls is not greater than the distance between the lower surface of the LPDDR chip and the upper surface of the substrate.

[0007] Optionally, the distance between the lower surface of the LPDDR chip and the upper surface of the SOC chip is not less than a third predetermined distance.

[0008] Optionally, the third predetermined distance is not less than zero.

[0009] Optionally, the LPDDR chip in the SOC chip mounting assembly may have various capacities or sizes.

[0010] Optionally, the bump area between the lower surface of the SOC chip and the upper surface of the substrate is filled with adhesive.

[0011] Optionally, the upper surface of the substrate, the outer side of the SOC chip in the horizontal direction, and the area surrounding the solder balls are encapsulated.

[0012] Optionally, the upper surface of the molding compound is at the same height as the upper surface of the SOC chip.

[0013] The second technical solution adopted in this invention is: a packaging method for an ultra-thin HBPOP packaging structure based on Open MD and TMV processes as described in any of the first technical solutions, wherein a SOC chip is mounted on a substrate using a flip-chip mounting process, and solder balls are soldered in a predetermined area around the substrate; the bump area of ​​the SOC chip is filled with filler adhesive, and the entire structure is encapsulated using a special Open MD molding die, so that the upper surface of the encapsulation body is flush with the upper surface of the SOC chip, and the solder balls are wrapped in the encapsulation body; the upper end of the solder balls protrudes from the encapsulation body, and the encapsulated LPDDR chip is soldered to the exposed solder balls to form a package.

[0014] Optionally, the step of mounting the SOC chip on the substrate using a flip-chip mounting process and soldering solder balls in a preset area around the substrate further includes: the height of the solder balls after soldering is 10µm lower than the upper surface of the SOC chip.

[0015] Optionally, the step of exposing the upper end of the solder ball to the molding compound specifically includes: at the position of the solder ball below the upper surface of the molding compound, using a TMV process, removing the molding compound above the solder ball, so that the upper end of the solder ball exposes the molding compound.

[0016] The beneficial effects of this invention are:

[0017] This invention optimizes the internal space of mobile phones and other electronic products by stacking and packaging SOC chips and LPDDR chips together. It also allows for the arbitrary combination of LPDDR chips and SOC chips of different capacities, greatly improving the applicability of the structure. By pre-planting solder balls on the original substrate and then exposing them through holes for circuit connection, the process is simpler and the molding compound is more compact. Furthermore, since no adapter board is needed between the LPDDR chip and the SOC chip, the overall thickness can be reduced by about 100um, and the cost is also greatly reduced, allowing mobile phones and other electronic products to be made thinner and thinner. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall HBPOP packaging structure of the SOC chip and LPDDR chip of the present invention;

[0019] Figure 2 This is a schematic diagram of the SOC chip and solder ball mounting structure of the present invention;

[0020] Figure 3 This is a schematic diagram of the glue structure for filling the bump area of ​​the SOC chip of the present invention;

[0021] Figure 4 This is a schematic diagram of the SOC chip and solder ball encapsulation structure of the present invention;

[0022] Figure 5 This is a schematic diagram of the exposed solder ball structure in the SOC chip and solder ball molding compound of the present invention;

[0023] Figure 6 This is a schematic diagram of the LPDDR chip package and solder ball welding structure of the present invention.

[0024] Reference numerals: 1. Solder ball; 2. SOC chip; 3. Substrate; 4. Molded package; 5. Filler adhesive; 6. LPDDR chip. Detailed Implementation

[0025] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0027] This invention provides an ultra-thin HBPOP packaging structure based on Open MD and TMV processes. During chip packaging, if the SoC and memory plane are placed side-by-side, the distance between them is still too large. The best solution to this problem is to place the memory directly on top of the SoC, thereby shortening the distance and reducing power consumption. This is the PoP stacked packaging technology, strictly speaking mostly HB-PoP, but for ease of understanding, it is still collectively referred to as PoP. The top of the package contains the LPDDR memory, and the bottom is the SoC. The top substrate is responsible for connecting the top memory; the central embedded layer contains the bare chip; and the surrounding copper solder balls are used to conduct signals from the lower layer to the upper layer. The bottom substrate has the most complex structure. It not only bears the heavy responsibility of signal transmission for numerous precise electrical connections between the chip and the external circuit board, but also serves as the base of the SoC, supporting the memory module above. To ensure that the chip will not experience problems such as poor soldering even if dropped under reasonable heat conditions, which could lead to chip burnout or even complete device damage, the packaging structure must balance sealing and shock resistance, further increasing the design complexity.

[0028] In one specific embodiment of this application, as follows: Figure 1As shown, the packaging structure includes: a SOC chip 2, which is horizontally flip-chip mounted on the central area of ​​the upper surface of a substrate 3; an LPDDR chip 6, which is horizontally positioned above the SOC chip 2, with the LPDDR chip 6 and the SOC chip 2 arranged parallel to each other and facing each other, with the distance between the LPDDR chip 6 and the SOC chip 2 not exceeding a first predetermined distance; and the distance between the lower surface of the LPDDR chip 6 and the upper surface of the substrate not exceeding a second predetermined distance, ensuring that the overall structure size is not too large. Solder balls 1 are soldered between the upper surface of the substrate 3 and the lower surface of the LPDDR chip 6. By pre-planting solder balls 1 on the original substrate 3 and then exposing them through openings for circuit connection, the process is simpler, and because an adapter board is not needed, the overall thickness can be reduced by about 100µm, significantly reducing costs and allowing for increasingly thinner mobile phones and other electronic products. Chip packaging essentially involves wrapping a manufactured chip to provide physical protection while simultaneously bringing out circuitry for external connections. For most components, the traditional approach is to directly mount them onto a pre-fabricated PCB board. For chips like mobile SoCs that require extensive high-speed data interaction with memory, the requirements for power consumption and speed are even more stringent. Compared to planar packaging, POP (Position-in-Pack) has a shorter signal transmission path and lower resistance. According to the power formula, under the same current conditions, reduced resistance means reduced power consumption. Furthermore, switching from planar packaging to 3D packaging can save approximately 50% of power loss.

[0029] In one specific embodiment of this application, a filler adhesive 5 is disposed between the lower surface of the SOC chip 2 and the upper surface of the substrate 3. The filler adhesive 5 on the lower part of the SOC chip 2 is mainly used to enhance packaging reliability by filling the tiny gap between the chip and the substrate 3, thus alleviating stress problems caused by the difference in thermal expansion coefficients. Its main functions include: enhancing mechanical strength: filling the gap between the chip and the substrate 3, improving drop and shock resistance, and preventing solder joint detachment; alleviating thermal stress: reducing the thermal expansion coefficient mismatch stress between the chip and the substrate 3 caused by temperature changes, and improving thermal shock resistance; and preventing moisture and oxidation: preventing moisture and contaminants from entering, protecting solder joint stability, and extending service life.

[0030] In one specific embodiment of this application, the upper surface of the substrate 3, the outer side of the SOC chip 2 in the horizontal direction, the area around the solder balls 1, and the area below the LPDDR chip 6 form a molding compound 4. Molding involves pressing a mass of thermoplastic resin material into a mold at high temperature, completely encapsulating the chip, bonding wires, and support structure to form the black "IC package shell" that we ultimately see.

[0031] In one specific embodiment of this application, at least four solder balls 1 are provided. Specifically, in this embodiment, four are provided and are symmetrically arranged on the substrate 3 with respect to the SOC chip 2. Two solder balls 1 are provided on each side, and the distance between the solder balls 1 is not less than a predetermined distance to avoid short circuits during the melting process due to excessively small distance between the solder balls 1.

[0032] In one specific embodiment of this application, the distance between the lower surface of the LPDDR chip and the upper surface of the SOC chip is not less than a third predetermined distance. The third predetermined distance is not less than zero. This ensures that a gap remains between the lower surface of the LPDDR chip and the upper surface of the SOC chip, facilitating both soldering and heat dissipation.

[0033] In one specific embodiment of this application, the LPDDR chip 6 combined with the SOC chip 2 can have various capacities or sizes. This application stacks and packages the SOC chip 2 and LPDDR chip 6 together, thereby optimizing the internal space of electronic products such as mobile phones, and allowing for arbitrary combinations of LPDDR chips 6 of different capacities and the SOC chip 2. This greatly improves the applicability of the packaging structure.

[0034] This invention also provides a packaging method for an ultra-thin HBPOP packaging structure based on Open MD and TMV processes, specifically as follows: Figures 2-6 As shown, the SOC chip 2 is mounted on substrate 3 using a flip-chip bonding process. The principle and advantages of flip-chip packaging technology are: by directly interconnecting the chip bumps with substrate 3, the inductance and capacitance problems of traditional wire bonding are eliminated, achieving shorter signal paths, higher I / O density, and better heat dissipation efficiency. It is suitable for high-performance computing, MEMS sensors, and smartphone CPUs. Die mounting, as a key process in semiconductor packaging, refers to the process of precisely fixing the bare chip to substrate 3 or the lead frame carrier using conductive or insulating connections. This process combines mechanical fixation and electrical interconnection, requiring the creation of conditions for subsequent bonding, molding, and other processes while ensuring chip positioning accuracy.

[0035] In one specific embodiment of this application, solder balls 1 are soldered around the perimeter of the substrate 3. The solder balls 1 are pre-planted on the original substrate 3, then exposed through openings for circuit connections, avoiding the need for an adapter board that increases thickness. A specially designed Open MD molding die is used to encapsulate the entire assembly, making the molded body 4 flush with the upper surface of the SOC chip 2, encapsulating the solder balls 1 within the molded body 4. The solder balls 1 are then exposed outside the molded body 4, and the LPDDR chip 6 is soldered onto it. Molding involves pressing a mass of thermoplastic resin material into a mold at high temperature, completely encapsulating the chip, bonding wires, and support structure to form the final black "IC package shell" we see. This embodiment significantly improves integration by first encapsulating the entire assembly and then soldering it.

[0036] In one specific embodiment of this application, a SOC chip 2 is mounted on a substrate 3 using a flip-chip bonding process, and solder balls 1 are soldered around the substrate 3. The solder balls 1 are 10µm lower than the SOC chip 2 after soldering. This avoids excessive height of the solder balls 1, which could cause interference during soldering. The solder balls 1 are crucial components in the flip-chip process, primarily serving two functions: conductivity, connecting the chip's pads to the packaging substrate 3 to enable signal transmission between the chip and external components; and heat dissipation, transferring heat generated during chip operation to the substrate 3 for support.

[0037] In one specific embodiment of this application, a specially designed Open MD molding die is used to encapsulate the entire chip, making the four sides of the encapsulation body flush with the surface of the SOC chip 2, and encapsulating the solder ball 1 within the encapsulation body 4. The molding die is a key piece of equipment in semiconductor chip packaging technology, mainly used to fill the lead frame cavity with thermosetting molding compound under high pressure, achieving sealing protection for the chip and gold wire structure. Chip molding is a critical process in semiconductor packaging, primarily used to protect the chip from damage by the external environment and to provide electrical connections and mechanical support. The chip molding process includes multiple steps such as loading, preheating, mold closing, loading and material transfer, curing, demolding, and removal of gate material. Each step requires strict control of operating conditions and parameters to ensure stable and reliable molding quality.

[0038] In one specific embodiment of this application, the bump area of ​​the SOC chip 2 is filled with adhesive before molding. The adhesive bonding process specifically includes an insulating adhesive: epoxy resin-based, with a dielectric constant ε < 3.5, suitable for signal isolation scenarios.

[0039] In one specific embodiment of this application, exposing the solder ball 1 from the molding compound 4 and soldering the LPDDR chip 6 specifically includes: using a TMV process to remove the molding compound 4 above the solder ball 1 at the position below the molding compound 4, thus exposing the solder ball 1. TMV is a process at the packaging scale that effectively provides vertical interconnects for different packages in package-on-package and multi-chip embedded stacked packages through vertical vias (DV) and RDL technology. Currently, the aperture of TMV used for vertical interconnects is generally 25–150 μm, and the depth is 100–1000 μm. Furthermore, obtaining high-quality TMV still requires solving problems such as tube wall flatness, residue in the vias, and chip-mold delamination caused by heat dissipation during TMV fabrication. Molded through-hole (TMV) technology innovatively interconnects vertically on the molded package using laser drilling technology, improving packaging density and performance. In areas not yet covered by flip-chip and TSV packaging technologies, TMV technology demonstrates its unique advantages and has become a preferred solution. TMV offers advantages such as flexible design, low cost, and high efficiency, enhancing its market position in 3D packaging. First, the TMV (Thin-Metal Multi-Video) technology offers flexible and versatile stacked packaging designs, effectively supporting various application requirements, including single-chip, stacked chip, and FC (Flip Chip) designs. Second, compared to TSV (Thin-Metal Multi-Video) structures, TMV structures have lower manufacturing costs, a significant advantage in the market. Furthermore, the fabrication process for TMV structures is relatively simple, easy to implement, and ensures high yield rates, making production more flexible and efficient. These combined advantages have enabled TMV technology to secure a place in the 3D vertical interconnect field.

[0040] In one specific embodiment of this application, heterogeneous integration is used to extend and expand Moore's Law. Heterogeneous integration, demand-driven, flexibly modularizes and integrates discrete chips of different sizes, functions, and types, such as processors, memories, and sensors, in a three-dimensional direction. The key to the development and integration of heterogeneous integration technology lies in achieving multi-scale, multi-dimensional chip interconnection. Through three-dimensional interconnect technology, chips with different functions are heterogeneously integrated into a single package, thereby improving bandwidth and power efficiency and reducing latency, providing small-size, high-performance chips for high-performance computing, artificial intelligence, and smart terminals.

[0041] In one specific embodiment of this application, the process of exposing the solder ball 1 from the molding compound 4 and soldering the LPDDR chip 6 specifically includes: soldering the already packaged LPDDR chip 6 to the exposed solder ball 1. Whether it's a CPU, GPU, FPGA, or NPU, normal operation relies on RAM, especially DRAM, which has become synonymous with memory in various systems. Depending on the application, the system has different requirements for chip area and power consumption. Therefore, DRAM is divided into standard DDR, LPDDR, GDDR, etc., but these are the three main categories. DDR refers to the single data rate relative to SDR, doubling the I / O clock, primarily serving CPUs in PCs and data centers, and has now evolved to DDR5. LPDDR is low-power DDR, mainly used in portable devices such as mobile phones. GDDR is GPU-specific DRAM. LPDDR has lower power consumption and smaller size than DDR memory of the same generation, and this type of chip is mainly used in low-power devices such as mobile electronic products. Soldering the already packaged LPDDR chip 6 to the exposed solder ball 1 greatly simplifies the process and improves reliability.

[0042] The advantages of PoP packaging in this application include high design flexibility, reduced chip footprint, reduced chip weight, increased data transmission rate, increased bandwidth, reduced signal latency, reduced power consumption, reduced noise, and improved product yield. PoP packaging is suitable for scenarios requiring improved chip performance within a small space, and is mainly used in small electronic products such as smartphones, PDAs, wearable smart devices, digital cameras, and mobile gaming devices. Especially in the smartphone field, as smartphone performance continues to improve and functions increase, their internal space continues to shrink.

[0043] The typical process for Proof-of-Package (PoP) packaging involves packaging the logic chip and memory chip separately. The logic chip package is placed at the bottom of the PoP package, stacked on top of the memory chip, with 2-4 layers stacked on top of each other. BGA solder balls are then used to bond the multi-layer packages together, forming a unified package structure. PoP packaging is not simply a matter of stacking chips; its design requires comprehensive consideration of signal interference, heat dissipation, and durability, making it a more technologically advanced process compared to single-chip packaging.

[0044] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. An ultra-thin HBPOP packaging structure based on Open MD and TMV processes, characterized in that, include: substrate; SOC chip, wherein the SOC chip is horizontally flip-chip mounted on the central region of the upper surface of the substrate; An LPDDR chip is horizontally mounted above the SOC chip, and the distance between the lower surface of the LPDDR chip and the upper surface of the SOC chip is no greater than a first predetermined distance, and the distance between the lower surface of the LPDDR chip and the upper surface of the substrate is no greater than a second predetermined distance. Solder balls are soldered between the upper surface of the substrate and the lower surface of the LPDDR chip, and the height of the solder balls is not greater than the distance between the lower surface of the LPDDR chip and the upper surface of the substrate.

2. The ultra-thin HBPOP packaging structure based on Open MD and TMV processes according to claim 1, characterized in that, The distance between the lower surface of the LPDDR chip and the upper surface of the SOC chip is not less than a third predetermined distance.

3. The ultra-thin HBPOP packaging structure based on Open MD and TMV processes according to claim 2, characterized in that, The third predetermined distance is not less than zero.

4. The ultra-thin HBPOP packaging structure based on Open MD and TMV processes according to claim 1, characterized in that, The LPDDR chip in the SOC chip mounting assembly has various capacities or sizes.

5. The ultra-thin HBPOP packaging structure based on Open MD and TMV processes according to claim 1, characterized in that, The bump area between the lower surface of the SOC chip and the upper surface of the substrate is filled with adhesive.

6. The ultra-thin HBPOP packaging structure based on Open MD and TMV processes according to claim 1, characterized in that, The upper surface of the substrate, the outer side of the SOC chip in the horizontal direction, and the area surrounding the solder ball are encapsulated.

7. The ultra-thin HBPOP packaging structure based on Open MD and TMV processes according to claim 6, characterized in that, The upper surface of the molding compound is at the same height as the upper surface of the SOC chip.

8. A packaging method for the ultra-thin HBPOP packaging structure based on Open MD and TMV processes as described in any one of claims 1-7, characterized in that, The SOC chip is mounted on the substrate using a flip-chip mounting process, and solder balls are soldered in a predetermined area around the substrate. The bump area of ​​the SOC chip is filled with filler glue, and the entire structure is encapsulated using a special Open MD molding die, so that the upper surface of the encapsulation body is flush with the upper surface of the SOC chip, and the solder ball is wrapped in the encapsulation body; The upper end of the solder ball is exposed through the plastic package, and the already packaged LPDDR chip is soldered to the exposed solder ball.

9. The ultra-thin HBPOP packaging method based on Open MD and TMV technology according to claim 8, characterized in that, The process of mounting the SOC chip on the substrate using a flip-chip mounting process and soldering solder balls in a predetermined area around the substrate further includes: The height of the solder ball after soldering is 10µm lower than the upper surface of the SOC chip.

10. The ultra-thin HBPOP packaging method based on Open MD and TMV processes according to claim 8, characterized in that, The step of allowing the upper end of the solder ball to protrude from the encapsulation specifically includes: At the location of the solder ball below the upper surface of the corresponding molded body, the molded body above the solder ball is removed using the TMV process, so that the upper end of the solder ball is exposed above the molded body.

Images