Light-emitting assembly and display substrate

Abstract

A light emitting assembly (100) and a display substrate. The light-emitting assembly (100) comprises a light-emitting unit (101) and a driving unit (102). Wherein the third electrode (1021) of the driving unit (102) is electrically connected with the first electrode (1011) of the light-emitting unit (101), and the fourth electrode (1022) of the driving unit (102) is electrically connected with the second electrode (1012) of the light-emitting unit (101), so that the driving unit (102) drives the light-emitting unit (101) to emit light. A first transistor (T1) and a second transistor (T2) which are connected in series in an inverter (10231) included in a driving circuit (1023) in the driving unit (102) are different in type and are double-gate transistors. Since the current output of the dual-gate transistor is stable and the leakage current is low, the power consumption of the inverter (10231) can be low, which is beneficial to reducing the power consumption of the light-emitting component (100).

Description

Light-emitting assembly and display substrate TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a light-emitting assembly and a display substrate. BACKGROUND

[0002] The display substrate comprises a display backplane and a plurality of light-emitting assemblies connected with the display backplane, wherein the display backplane can provide driving signals for the light-emitting assemblies to make the light-emitting assemblies emit light, thereby realizing display.

[0003] SUMMARY

[0004] The present application provides a light-emitting assembly and a display substrate, and the technical solutions are as follows:

[0005] In one aspect, a light-emitting assembly is provided, comprising:

[0006] A light-emitting unit, comprising a first electrode, a second electrode, and a light-emitting part electrically connected with the first electrode and the second electrode respectively;

[0007] A driving unit, comprising a third electrode, a fourth electrode, and a driving circuit, the third electrode and the fourth electrode are located on a side of the driving unit facing the light-emitting unit, the third electrode and the fourth electrode are electrically connected with the driving circuit respectively, the third electrode is electrically connected with the first electrode, and the fourth electrode is electrically connected with the second electrode;

[0008] The driving circuit comprises an inverter, the inverter comprises a first transistor and a second transistor connected in series, the first transistor and the second transistor are different in type, and the first transistor and the second transistor are both double-gate transistors.

[0009] Optionally, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the first transistor comprises a first gate, a first source and a first drain, and the second transistor comprises a second gate, a second source and a second drain.

[0010] The first gate is connected with the second gate, the first source is connected with a first power supply end, the first drain is connected with the second drain, the second source is connected with a second power supply end, and a potential of a first power supply signal provided by the first power supply end is different from a potential of a second power supply signal provided by the second power supply end.

[0011] Optionally, the potential of the first power supply signal is higher than the potential of the second power supply signal.

[0012] Optionally, the threshold voltage condition of the first transistor and the second transistor is that:

[0013] The threshold voltage of the first transistor is less than 0, and the threshold voltage of the second transistor is greater than 0; the absolute value of the threshold voltage of the first transistor and the absolute value of the threshold voltage of the second transistor are less than or equal to 0.5V.

[0014] Optionally, the absolute value of the threshold voltage of the first transistor and the absolute value of the threshold voltage of the second transistor are less than or equal to 0.3V.

[0015] Optionally, the first transistor comprises a first active pattern, the first active pattern comprises a first source region, a first drain region and a first channel region, the first source region and the first drain region are both first doped regions, the first doped regions are doped with a first type of doped elements, the first channel region is a region where the first gate and the first active pattern overlap, the first source and the first source region are electrically connected, and the first drain and the first drain region are electrically connected.

[0016] The second transistor comprises a second active pattern, the second active pattern comprises a second source region, a second drain region and a second channel region, the second source region and the second drain region are both second doped regions, the second doped regions are doped with a second type of doped elements, the second channel region is a region where the second gate and the second active pattern overlap, the second source and the second source region are electrically connected, and the second drain and the second drain region are electrically connected.

[0017] Wherein, the first type of doped elements and the second type of doped elements are different.

[0018] Optionally, the first type of doped elements is boron, and the second type of doped elements is phosphorus.

[0019] Optionally, the first channel region is doped with a first target doped element, and the second channel region is doped with a second target doped element, the first target doped element and the second target doped element are one of the first type of doped elements and the second type of doped elements.

[0020] The threshold voltage of the first target transistor in the first transistor and the second transistor is a first threshold voltage, and the threshold voltage of the second target transistor is any second threshold voltage in a second threshold voltage set, the second threshold voltage set comprises a plurality of second threshold voltages, and each second threshold voltage and the first threshold voltage satisfy the threshold voltage condition.

[0021] The first threshold voltage corresponds to a first dose range of the first target doping element; each of the second threshold voltages corresponds to a second dose range of the second target doping element, and a dose range of the set of second threshold voltages is a union of second dose ranges of the second threshold voltages in the set.

[0022] Optionally, in a case where the length of the first channel region and the length of the second channel region are normalized lengths, the second width-length ratio of the second channel region is 75% to 85% of the first width-length ratio of the first channel region.

[0023] The first width-length ratio is a value of the width of the first channel region divided by the length of the first channel region, and the second width-length ratio is a value of the width of the second channel region divided by the length of the second channel region.

[0024] Optionally, the second width-length ratio is 80% of the first width-length ratio.

[0025] Optionally, in a case where the length of the first channel region and the length of the second channel region are equal, the width of the second channel region is 80% of the width of the first channel region.

[0026] Optionally, an absolute value of a difference between the logic threshold voltage of the inverter and half of the potential of the first power signal is less than or equal to 5% of the potential of the first power signal.

[0027] Optionally, the light-emitting component further comprises a pin, and the driving unit further comprises a substrate, a connection pad, and a connection trace.

[0028] The connection pad is located inside the substrate, the pin is located on a side of the substrate away from the driving unit, the pin and the connection pad are connected, and the connection trace is connected to the connection pad through a via on the substrate; the driving circuit is located on a side of the connection trace away from the substrate and is connected to the connection trace.

[0029] Optionally, the driving circuit comprises, in a direction away from the substrate, a barrier layer, a first gate layer, a buffer layer, an active layer, a gate insulating layer, a second gate layer, an interlayer dielectric layer, a source-drain layer, and a planarization layer; the third electrode and the fourth electrode are located on a side of the planarization layer away from the substrate.

[0030] The first gate layer comprises a first gate pattern, and the first gate pattern comprises a first pattern portion and a second pattern portion in an integral structure, the first pattern portion is a bottom gate of the first transistor, and the second pattern portion is a bottom gate of the second transistor.

[0031] The active layer comprises a first active pattern of the first transistor and a second active pattern of the second transistor, the first active pattern and the second active pattern are arranged in a spaced manner, a projection of the first active pattern on the substrate and a projection of the first pattern part on the substrate are overlapped, a projection of the second active pattern on the substrate and a projection of the second pattern part on the substrate are overlapped.

[0032] The second gate layer comprises a second gate pattern, the second gate pattern is connected with the first gate pattern through the via in the gate insulating layer and the buffer layer, the second gate pattern comprises a third pattern part and a fourth pattern part in an integrated structure, the third pattern part is a top gate of the first transistor, a projection of the third pattern part on the substrate and a projection of the first active pattern on the substrate are overlapped, the fourth pattern part is a top gate of the second transistor, a projection of the fourth pattern part on the substrate and a projection of the first active pattern on the substrate are overlapped.

[0033] The source-drain layer comprises a first source and a first drain of the first transistor, and a second source and a second drain of the second transistor, the first source is connected with a source region of the first active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer, the first drain is connected with a drain region of the first active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer, the second source is connected with a source region of the second active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer, and the second drain is connected with a drain region of the second active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer.

[0034] Optionally, the driving circuit further comprises:

[0035] a data writing circuit, the data writing circuit is coupled with the gate signal end, the data signal end and the first node respectively, and the data writing circuit is configured to control the data signal end and the first node in response to the gate driving signal provided by the gate signal end;

[0036] a pixel driving circuit, the driving circuit is coupled with the first node, the second node and the third node respectively, and the driving circuit is configured to transmit a driving signal to the second node in response to the potential of the first node and the potential of the third node;

[0037] a first light emitting control circuit coupled to the first light emitting control signal terminal, the driving power supply terminal and the first node, the first light emitting control circuit configured to control the first node and the driving power supply terminal in response to a light emitting control signal provided by the first light emitting control signal terminal;

[0038] a second light emitting control circuit coupled to the second node, the light emitting unit and the fourth node, the second light emitting control circuit configured to control the second node and the light emitting unit in response to a potential of the fourth node;

[0039] a compensation circuit coupled to the gate signal terminal, the second node and the third node, the compensation circuit configured to control the second node and the third node in response to the gate driving signal;

[0040] a first reset circuit coupled to the reset signal terminal, the pull-down power supply terminal and the third node, the first reset circuit configured to control the third node and the pull-down power supply terminal in response to a reset signal provided by the reset signal terminal;

[0041] a second reset circuit coupled to the reset signal terminal, the pull-down power supply terminal and the light emitting unit, the second reset circuit configured to control the light emitting unit and the pull-down power supply terminal in response to the reset signal;

[0042] a transmission gate circuit coupled to the fourth node, the signal input terminal and the inverter, the transmission gate circuit configured to transmit the first light emitting control signal or a second light emitting control signal provided by the second light emitting control signal terminal to the fourth node in response to an input signal of the signal input terminal and an output signal provided by the signal output terminal of the inverter;

[0043] an adjusting circuit coupled to the third node and the driving power supply terminal, the adjusting circuit configured to adjust a potential of the third node based on the driving power supply signal;

[0044] wherein the inverter is coupled to the transmission gate circuit and the signal input terminal, the inverter configured to transmit the first power supply signal or the second power supply signal to the transmission gate circuit in response to an input signal of the signal input terminal.

[0045] Optionally, the data writing circuit comprises a data writing transistor; a gate of the data writing transistor is coupled with the gate signal terminal, a first pole of the data writing transistor is coupled with the data signal terminal, and a second pole of the data writing transistor is coupled with the first node;

[0046] The pixel driving circuit comprises a driving transistor; a gate of the driving transistor is coupled with the third node, a first pole of the driving transistor is coupled with the first node, and a second pole of the driving transistor is coupled with the second node;

[0047] The first light emitting control circuit comprises a first light emitting control transistor; a gate of the first light emitting control transistor is coupled with the first light emitting control signal terminal, a first pole of the first light emitting control transistor is coupled with the driving power supply terminal, and a second pole of the first light emitting control transistor is coupled with the first node;

[0048] The second light emitting control circuit comprises a second light emitting control transistor; a gate of the second light emitting control transistor is coupled with the fourth node, a first pole of the second light emitting control transistor is coupled with the second node, and a second pole of the second light emitting control transistor is coupled with the light emitting unit;

[0049] The compensation circuit comprises a compensation transistor; a gate of the compensation transistor is coupled with the gate signal terminal, a first pole of the compensation transistor is coupled with the second node, and a second pole of the compensation transistor is coupled with the third node;

[0050] The first reset circuit comprises a first reset transistor; a gate of the first reset transistor is coupled with the reset signal terminal, a first pole of the first reset transistor is coupled with the pull-down power supply terminal, and a second pole of the first reset transistor is coupled with the third node;

[0051] The second reset circuit comprises a second reset transistor; a gate of the second reset transistor is coupled with the reset signal terminal, a first pole of the second reset transistor is coupled with the pull-down power supply terminal, and a second pole of the second reset transistor is coupled with the light emitting unit;

[0052] The transmission gate circuit comprises a first transmission gate and a second transmission gate, the first transmission gate comprises a first transmission transistor and a second transmission transistor, the gate of the first transmission transistor is coupled with the signal input end, the gate of the second transmission transistor is coupled with the signal output end, the first electrode of the first transmission transistor and the first electrode of the second transmission transistor are both coupled with the second light-emitting control signal end, and the second electrode of the first transmission transistor and the second electrode of the second transmission transistor are coupled; the second transmission gate comprises a third transmission transistor and a fourth transmission transistor, the gate of the third transmission transistor is coupled with the signal output end, the gate of the fourth transmission transistor is coupled with the signal input end, the first electrode of the third transmission transistor and the first electrode of the fourth transmission transistor are both coupled with the first light-emitting control signal end, and the second electrode of the third transmission transistor and the second electrode of the fourth transmission transistor are coupled; wherein the first transmission transistor and the second transmission transistor are of different types, and the third transmission transistor and the fourth transmission transistor are of different types.

[0053] Optionally, the data writing transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the compensation transistor, the second transmission transistor and the fourth transmission transistor are all P-type transistors and are prepared by using the same preparation process as the first transistor.

[0054] The first reset transistor, the second reset transistor, the first transmission transistor and the third transmission transistor are all N-type transistors and are prepared by using the same preparation process as the second transistor.

[0055] Optionally, the light-emitting component comprises a plurality of light-emitting units and a plurality of driving units corresponding to the plurality of light-emitting units.

[0056] The plurality of light-emitting units comprise light-emitting units of a first color, light-emitting units of a second color and light-emitting units of a third color, and the first color, the second color and the third color are different from each other.

[0057] Optionally, the light-emitting component further comprises a first substrate located away from the driving units with respect to the light-emitting units; the light-emitting part comprises, in sequence from the first substrate, a color film layer, a color conversion layer and a light-emitting layer; the light-emitting color of the light-emitting layer is blue.

[0058] The light-emitting layer comprises a first doped layer, a multi-quantum well layer and a second doped layer which are stacked, wherein the first doped layer is electrically connected with the first electrode, and the second doped layer is electrically connected with the second electrode.

[0059] In another aspect, a display substrate is provided, which includes a driving backplane, and a plurality of light emitting components as described in the above aspect arranged in an array on one side of the driving backplane.

[0060] The driving backplane is a passive matrix driving backplane, and is configured to carry the light emitting components and provide driving signals to the light emitting components. BRIEF DESCRIPTION OF DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0062] FIG. 1 is a structural schematic diagram of a light emitting component according to an embodiment of the present application;

[0063] FIG. 2 is a top view of an inverter according to an embodiment of the present application;

[0064] FIG. 3 is a sectional view of FIG. 2 along AA' direction;

[0065] FIG. 4 is a sectional view of FIG. 2 along BB' direction;

[0066] FIG. 5 is an equivalent circuit diagram of an inverter according to an embodiment of the present application;

[0067] FIG. 6 is a voltage curve diagram according to an embodiment of the present application;

[0068] FIG. 7 is a relationship curve diagram of on-state current and dopant amount according to an embodiment of the present application;

[0069] FIG. 8 is another relationship curve diagram of on-state current and dopant amount according to an embodiment of the present application;

[0070] FIG. 9 is a relationship curve diagram of off-state current and dopant amount according to an embodiment of the present application;

[0071] FIG. 10 is another relationship curve diagram of off-state current and dopant amount according to an embodiment of the present application;

[0072] FIG. 11 is a relationship curve diagram of sub-threshold swing and dopant amount according to an embodiment of the present application;

[0073] FIG. 12 is another relationship curve diagram of sub-threshold swing and dopant amount according to an embodiment of the present application;

[0074] FIG. 13 is a box plot of dopant amount and threshold voltage according to an embodiment of the present application;

[0075] FIG. 14 is another box plot of the dose of dopant and threshold voltage, according to embodiments of the present disclosure;

[0076] FIG. 15 is a voltage curve of a first transistor and a second transistor, according to embodiments of the present disclosure;

[0077] FIG. 16 is another voltage curve of a first transistor and a second transistor, according to embodiments of the present disclosure;

[0078] FIG. 17 is a schematic diagram of a linear region and a saturation region of a transistor, according to embodiments of the present disclosure;

[0079] FIG. 18 is a curve of stability values of current of transistors with different width-to-length ratios, according to embodiments of the present disclosure;

[0080] FIG. 19 is another voltage curve, according to embodiments of the present disclosure;

[0081] FIG. 20 is an equivalent circuit diagram of a driving circuit, according to embodiments of the present disclosure;

[0082] FIG. 21 is a schematic diagram of film layers of an inverter in a driving unit, according to embodiments of the present disclosure;

[0083] FIG. 22 is a schematic diagram of film layers of a transistor in a driving unit, according to embodiments of the present disclosure;

[0084] FIG. 23 is a schematic diagram of a structure of a light emitting unit, according to embodiments of the present disclosure;

[0085] FIG. 24 is another schematic diagram of a structure of a light emitting unit, according to embodiments of the present disclosure;

[0086] FIG. 25 is a flowchart of a method of manufacturing a light emitting assembly, according to embodiments of the present disclosure;

[0087] FIG. 26 is a flowchart of a method of manufacturing a driving unit, according to embodiments of the present disclosure;

[0088] FIG. 27 is a schematic diagram of a second substrate, a substrate, a connection pad, a third passivation layer, and a connection trace, according to embodiments of the present disclosure;

[0089] FIG. 28 is a top view of a first gate pattern, according to embodiments of the present disclosure;

[0090] FIG. 29 is a cross-sectional view of FIG. 28 along a CC’ direction, according to embodiments of the present disclosure;

[0091] FIG. 30 is a cross-sectional view of FIG. 28 along a DD’ direction, according to embodiments of the present disclosure;

[0092] FIG. 31 is a schematic diagram of forming an active thin film, according to embodiments of the present disclosure;

[0093] FIG. 32 is a top view of a first gate pattern and an active layer according to an embodiment of the present application;

[0094] FIG. 33 is a cross-sectional view of FIG. 32 along the direction of EE’;

[0095] FIG. 34 is a cross-sectional view of FIG. 32 along the direction of FF’;

[0096] FIG. 35 is a top view of forming a via in a first gate insulating layer according to an embodiment of the present application;

[0097] FIG. 36 is a cross-sectional view of FIG. 35 along the direction of GG’;

[0098] FIG. 37 is a cross-sectional view of FIG. 35 along the direction of HH’;

[0099] FIG. 38 is a schematic view of forming a second gate thin film according to an embodiment of the present application;

[0100] FIG. 39 is a schematic view of forming a third gate portion according to an embodiment of the present application;

[0101] FIG. 40 is a schematic view of doping a first doping region of a first active pattern according to an embodiment of the present application;

[0102] FIG. 41 is a schematic view of forming an initial fourth gate portion according to an embodiment of the present application;

[0103] FIG. 42 is a schematic view of doping a first partial region of a second doping region of a second active pattern according to an embodiment of the present application;

[0104] FIG. 43 is a schematic view of doping a second partial region of a second doping region of a second active pattern according to an embodiment of the present application;

[0105] FIG. 44 is a top view of forming a via in an interlayer dielectric layer according to an embodiment of the present application;

[0106] FIG. 45 is a cross-sectional view of FIG. 44 along the direction of II’;

[0107] FIG. 46 is a cross-sectional view of FIG. 44 along the direction of JJ’;

[0108] FIG. 47 is a structural flowchart of cutting a plurality of driving units according to an embodiment of the present application;

[0109] FIG. 48 is a schematic view of bonding a light emitting unit and a driving unit according to an embodiment of the present application;

[0110] FIG. 49 is a schematic view of peeling a second substrate according to an embodiment of the present application;

[0111] FIG. 50 is a schematic view of forming a pin according to an embodiment of the present application;

[0112] FIG. 51 is a structural schematic diagram of a display substrate provided by an embodiment of the present application. DETAILED DESCRIPTION

[0113] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0114] A micro light emitting diode (Micro LED) display substrate generally includes a display backplane, a driving unit integrated on the display backplane, and a light emitting chip bonded to the driving unit. In the preparation of the Micro LED display substrate, in order to realize color display, light emitting chips of different colors need to be transferred and bonded to the display backplane integrated with the driving unit. Moreover, light emitting chips of the same color are transferred at the same time, and light emitting chips of different colors are transferred in batches. That is, the number of transfer times is equal to the number of colors of the light emitting chips. Optionally, the light emitting chips include three colors of light emitting chips, such as red (R) light emitting chips, green (G) light emitting chips and blue light emitting chips, and thus three times of transfer are required. The number of transfer times in the preparation of the Micro LED display substrate according to the scheme is relatively large, and the process is relatively complex.

[0115] Moreover, in order to reduce the manufacturing cost of the Micro LED display substrate, the size of the display backplane cannot be designed to be too large (because if the size is designed to be too large, if some of the light emitting chips fail to emit light after transfer, the entire product is scrapped, and the cost is relatively high). Therefore, if large-size display is required, it can only be realized by splicing, and the display effect is poor.

[0116] For the red-green-blue three-color micro display chip (RGB Micro LED) and the driving unit to be bonded to form a new active-matrix light-emitting diode (AM-LED) chip with a driving circuit. The AM-LED chip includes red-green-blue three-color light emitting chips and a driving unit for driving the light emitting chips. Therefore, the size of the display substrate to be prepared requires a corresponding number of AM-LED chips to be transferred and bonded to the display backplane at one time, so as to realize the preparation of a glass-based light-emitting diode (LED) display substrate. At the same time, the scheme can only need to perform a transfer process, and the process is relatively simple. Moreover, large-size display can be realized without splicing, the glass utilization rate of the display backplane can be improved, and thus the cost can be reduced.

[0117] And, the AM-LED chip can realize electrical / optical double detection through detection technology, and screen out chips with required optical performance and driving performance. Therefore, compared with the scheme of integrating the driving circuit on the display back plate to form a display substrate, the scheme is more conducive to improving the yield of chips on the display substrate, and is also convenient for repairing and replacing the defective chips. However, the power consumption of the AM-LED chip is high.

[0118] FIG. 1 is a structural schematic diagram of a light-emitting assembly provided in an embodiment of the present application. Referring to FIG. 1, the light-emitting assembly 100 includes a light-emitting unit 101 and a driving unit 102.

[0119] The light-emitting unit 101 includes a first electrode 1011, a second electrode 1012, and a light-emitting part 1013 electrically connected to the first electrode 1011 and the second electrode 1012, respectively.

[0120] The driving unit 102 includes a third electrode 1021, a fourth electrode 1022, and a driving circuit 1023. The third electrode 1021 and the fourth electrode 1022 are located on a side of the driving unit 102 facing the light-emitting unit 101, that is, the third electrode 1021 and the fourth electrode 1022 are closer to the light-emitting unit 101 relative to the driving circuit 1023. The third electrode 1021 and the fourth electrode 1022 are electrically connected to the driving circuit 1023, the third electrode 1021 is electrically connected to the first electrode 1011, and the fourth electrode 1022 is electrically connected to the second electrode 1012.

[0121] The driving circuit 1023 includes an inverter 10231, and the inverter 10231 includes a first transistor T1 and a second transistor T2 connected in series, as shown in FIG. 2.

[0122] In the embodiment of the present application, the types of the first transistor T1 and the second transistor T2 can be different, that is, one of the first transistor T1 and the second transistor T2 is a P-type transistor, and the other is an N-type transistor. The double-gate transistor is a transistor with a double-gate structure, and its principle is to change the conductivity of the channel by controlling the gate voltage.

[0123] The double-gate transistor is composed of a channel separated by two gates and an insulating layer. One of the gates is used to connect to an input signal source for controlling the main flow path of the current, and the other gate is used to connect to a bias voltage source for auxiliary adjustment of the main flow path.

[0124] Compared with the single-gate transistor, the output current of the double-gate transistor is greater than that of the single-gate transistor, which can help to reduce the size of the light emitting unit 101 included in the light emitting assembly 100 and improve the pixel density (PPI). The stability of the on-state current of the double-gate transistor is higher than that of the single-gate transistor, so that the use of the double-gate transistor in the inverter 10231 can improve the stability of the current output and thus improve the uniformity of the display brightness. The leakage current of the double-gate transistor is smaller than that of the single-gate transistor, so that the power consumption of the light emitting assembly can be reduced. The subthreshold swing of the double-gate transistor is smaller than that of the single-gate transistor, which can improve the response speed of the inverter 10231.

[0125] In summary, the embodiment of the present application provides a light emitting assembly including a light emitting unit and a driving unit. The third electrode of the driving unit is electrically connected to the first electrode of the light emitting unit, and the fourth electrode of the driving unit is electrically connected to the second electrode of the light emitting unit, so that the driving unit drives the light emitting unit to emit light. The driving circuit in the driving unit includes first and second transistors in series in an inverter, and the types of the first and second transistors are different and are both double-gate transistors. Since the double-gate transistor has stable current output and low leakage current, the power consumption of the inverter can be reduced, which is beneficial to reduce the power consumption of the light emitting assembly.

[0126] Optionally, the first transistor T1 and the second transistor T2 can be low temperature poly-silicon (LTPS) transistors. The inverter 10231 can also be referred to as an LTPS CMOS.

[0127] Optionally, referring to FIGS. 2-5, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The first transistor T1 includes a first gate T1_g, a first source T1_s and a first drain T1_d, and the second transistor T2 includes a second gate T2_g, a second source T2_s and a second drain T2_d. FIG. 5 is an equivalent circuit diagram of an inverter provided by an embodiment of the present application. The first gate T1_g and the second gate T2_g are connected, the first source T1_s and a first power supply terminal are connected, the first drain T1_d and the second drain T2_d are connected, and the second source T2_s and a second power supply terminal are connected. The potential of a first power supply signal provided by the first power supply terminal is different from the potential of a second power supply signal provided by the second power supply terminal.

[0128] Optionally, the potential of the first power signal can be higher than the potential of the second power signal. Or the potential of the first power signal can be referred to as a high potential, and the potential of the second power signal can be referred to as a low potential. For example, referring to FIG. 5, the first power terminal can be a driving power terminal (VDD terminal), and the first power signal provided by the first power terminal can be a driving power signal (VDD signal). The second power terminal can be a pull-down power terminal (VSS terminal), and the second power signal provided by the second power terminal can be a pull-down power signal (VSS signal).

[0129] In the embodiment of the present application, the inverter 10231 can be used as a basic component of a digital circuit to form a timing circuit to generate a timing signal (such as a gate signal and a reset signal, etc.) required for the light-emitting unit 101 to emit light.

[0130] The first gate T1_g and the second gate T2_g are connected and can serve as a signal receiving end OUT of the inverter 10231, that is, the signal receiving end OUT can provide the same potential signal for the first gate T1_g and the second gate T2_g at the same time. The first transistor T1 and the second transistor T2 can be turned on or off under the control of the signal provided by the signal receiving end OUT.

[0131] Because the first transistor T1 and the second transistor T2 are of different types, the switching states of the first transistor T1 and the second transistor T2 under the control of signals of different potentials are different. That is, when the first transistor T1 in the inverter 10231 is in an on state, the first transistor T1 is in an off state; when the first transistor T1 is in an off state, the second transistor T2 is in an on state. Or it can be said that at each moment during the operation of the inverter 10231, one of the first transistor T1 and the second transistor T2 in the inverter 10231 is in an on state, and the other is in an off state.

[0132] Optionally, taking the first transistor T1 as a P-type transistor (the first transistor can be referred to as PMOS) and the second transistor T2 as an N-type transistor (the second transistor can be referred to as NMOS) as an example. In the case where the potential of the signal provided by the signal receiving end IN for the first gate T1_g and the second gate T2_g is a first potential, the first transistor T1 is on, and the second transistor T2 is off; in the case where the potential of the signal provided by the signal receiving end IN for the first gate T1_g and the second gate T2_g is a second potential, the first transistor T1 is off, and the second transistor T2 is on. Wherein, the first potential is a low potential relative to the second potential, and the second potential is a high potential relative to the first potential.

[0133] In addition, the first drain T1_d and the second drain T2_d are connected and can serve as a signal output end OUT of the inverter 10231. When the first transistor T1 is in an on state and the second transistor T2 is in an off state, a first power signal provided by the first power supply end can be transmitted to the signal output end OUT through the on first transistor T1. When the first transistor T1 is in an off state and the second transistor T2 is in an on state, a second power signal provided by the second power supply end can be transmitted to the signal output end OUT through the on second transistor T2.

[0134] Referring to FIG. 6, when the potential VIN (unit: volt (V)) of the signal provided by the first gate T1_g and the second gate T2_g at the signal receiving end IN changes (which can also be referred to as inverter 10231 switching), the potential VOUT (unit: volt) of the signal output by the signal output end OUT also changes (in a transition stage), and the change process can be a gradual change between the VDD signal (assuming 2.5 V) and the VSS signal (assuming 0 V).

[0135] In the embodiment of the present application, referring to FIG. 2, the first transistor T1 includes a first active pattern T11, and the first active pattern T11 includes a first source region, a first drain region, and a first channel region. The first channel region is an area where the first gate T1_g and the first active pattern T11 overlap. The first source region and the first drain region are both first doped regions doped with a first type of doped element. The first type of doped element can be boron. After the first source region and the first drain region are doped with the first type of doped element, the number of holes in the first source region and the first drain region can be increased.

[0136] The second transistor T2 includes a second active pattern T21, and the second active pattern T21 includes a second source region, a second drain region, and a second channel region. The second channel region is an area where the second gate T2_g and the second active pattern T21 overlap. The second source region and the second drain region are both second doped regions doped with a second type of doped element. The second type of doped element can be phosphorus. After the first source region and the first drain region are doped with the first type of doped element, the number of electrons in the first source region and the first drain region can be increased.

[0137] In the embodiment of the present application, the first channel region can be doped with a first target doped element, and the second channel region can be doped with a second target doped element. The first target doped element and the second target doped element are one of the first type of doped element and the second type of doped element. For example, the first target doped element and the second target doped element can both be boron elements or phosphorus elements. The first target doped element and the second target doped element can be the same or different.

[0138] In addition, the dopant amount of the doping element in the first channel region and the second channel region also affects the on-state current and the off-state current of the transistor. Generally, the transistor needs to have as large an on-state current Ion as possible and as small an off-state current Ioff as possible. A larger on-state current Ion can make the speed and driving ability of the transistor faster. A smaller off-state current Ioff can make the power consumption loss of the transistor smaller.

[0139] In the embodiments of the present application, with reference to FIG. 7, for the same dopant amount, the on-state current Ion of the first transistor T1 (P-type transistor) in the case of being a double-gate transistor is higher than that in the case of being a single-gate transistor, regardless of the dopant amount of the first target doping element in the first channel region of the first transistor T1. With reference to FIG. 8, for the same dopant amount, the on-state current Ion of the second transistor T2 (N-type transistor) in the case of being a double-gate transistor is higher than that in the case of being a single-gate transistor, regardless of the dopant amount of the second target doping element in the second channel region of the second transistor T2. That is, the first transistor T1 and the second transistor T2 are set to be double-gate transistors, which can make the on-state current larger and the speed and driving ability of the transistor faster.

[0140] With reference to FIG. 9, for the same dopant amount, the off-state current Ioff of the first transistor T1 (P-type transistor) in the case of being a double-gate transistor is higher than that in the case of being a single-gate transistor, regardless of the dopant amount of the first target doping element in the first channel region of the first transistor T1. With reference to FIG. 10, the off-state current Ioff of the second transistor T2 (N-type transistor) in the case of being a double-gate transistor is higher than that in the case of being a single-gate transistor at some dopant amounts of the second target doping element, but overall, the off-state current Ioff of the second transistor T2 in the case of being a double-gate transistor is lower than that in the case of being a single-gate transistor. That is, the first transistor T1 and the second transistor T2 are set to be double-gate transistors, which can make the off-state current smaller and the power consumption loss of the transistor smaller.

[0141] Referring to FIG. 11, no matter how much the dopant amount of the first type of doping element in the first channel region of the first transistor T1 (P-type transistor) is, for the same dopant amount, the subthreshold swing ss of the first transistor T1 in the case of being a double-gate transistor is smaller than the subthreshold swing ss of the first transistor T1 in the case of being a single-gate transistor. Referring to FIG. 12, no matter how much the dopant amount of the second type of doping element in the second channel region of the second transistor T2 (N-type transistor) is, for the same dopant amount, the subthreshold swing ss of the second transistor T2 in the case of being a double-gate transistor is lower than the subthreshold swing ss of the second transistor T2 in the case of being a single-gate transistor. That is, the first transistor T1 and the second transistor T2 being configured as double-gate transistors can make the subthreshold swing smaller. The smaller subthreshold swing means that the potential change of the signal receiving end corresponding to the transition stage of switching of the inverter 10231 is smaller, thereby improving the response speed of the inverter 10231.

[0142] In the embodiments of the present application, FIGS. 7 to 12 all take the width-length ratio of the transistor as 5 / 5 as an example. The abscissa all represents the dopant amount of the doping element (the first target doping element and the second target doping), in units of ion number per square centimeter. For example, 1.2E+12 in the abscissa of FIG. 7 can be used to represent that the number of the first target doping element (boron) doped in the P-type transistor is 1.2×10 12 For another example, -1.0E+12 in the abscissa of FIG. 8 can be used to represent that, in the case of the N-type transistor being doped with the second target doping element (boron), the number of the first type of doping element doped is 1×10 12 4.0E+12 in the abscissa of FIG. 8 can be used to represent that, in the case of the N-type transistor being doped with the second target doping element (phosphorus), the number of the second target doping element doped is 4×10 12 For another example, “skip” in the abscissa of FIG. 8 is used to represent that the channel region is not doped with any doping element in the process of preparing the active pattern. The abscissa of FIGS. 7 to 12 is the dopant amount of the doping element in the channel region, which can be referred to as the dopant amount of vth doping.

[0143] Optionally, in the process of preparing the active pattern of the P-type transistor and the N-type transistor, the active pattern can be used to dope the target doping element, so that the channel region of the active pattern is doped with the target doping element. Optionally, the first active pattern of the first transistor can be doped with the first target doping element, and the second active pattern of the second transistor can be doped with the second target doping element. The first target doping element and the second target doping element can both be boron element or phosphorus element. The first target doping element and the second target doping element can be the same or different.

[0144] For example, boron or phosphorus is doped in the first active pattern of the P-type transistor (the first transistor), and boron or phosphorus can be doped in the second active pattern of the N-type transistor (the second transistor). The specific element to be doped depends on the threshold voltage required by the transistor.

[0145] As can be seen from FIGS. 13 and 14, for both N-type and P-type transistors, the threshold voltage of the transistor changes in the negative direction as the doping dose of phosphorus (P) increases, and the threshold voltage of the transistor changes in the positive direction as the doping dose of boron (B) increases. The horizontal coordinate in FIGS. 13 and 14 is used to represent the doping dose. For example, P1.2E+12 is used to represent that the doped element is phosphorus, and the number of ions per square centimeter is 1.2E+12. B4.0E+11 is used to represent that the doped element is boron, and the number of ions per square centimeter is 4.0E+11. 12 11

[0146] In the embodiments of the present application, the first transistor T1 is a P-type transistor, and thus the first type of doping element (boron) can be doped in the first doping region in the first transistor T1, so that the threshold voltage of the first transistor T1 is less than 0. The second transistor T2 is an N-type transistor, and thus the second type of doping element (phosphorus) can be doped in the second doping region in the second transistor T2, so that the threshold voltage of the second transistor T2 is greater than 0.

[0147] As can be seen from FIGS. 13 and 14, the absolute value of the threshold voltage of the first transistor T1 increases as the doping dose of the first target doping element in the first channel region in the first active pattern increases. The absolute value of the threshold voltage of the second transistor T2 increases as the doping dose of the second target doping element in the second channel region in the second active pattern increases. That is, the threshold voltage of the transistor is affected by the doping dose of the doping element in the channel region in the active pattern.

[0148] After the threshold voltage required by the transistor is determined, the doping dose of the doping element in the active pattern can be adjusted so that the threshold voltage of the prepared transistor is approximately the threshold voltage required by the transistor. However, process deviation is unavoidable in the preparation process of the transistor, and thus it is only required that the difference between the threshold voltage of the prepared transistor and the threshold voltage required by the transistor be less than a certain threshold value.

[0149] In the embodiments of the present application, since the first transistor T1 and the second transistor T2 included in the inverter 10231 are connected in series, the absolute value of the threshold voltage of the first transistor T1 and the absolute value of the threshold voltage of the second transistor T2 are approximately equal, so that the inverter 10231 can better achieve switching. ​​

[0150] The approximately equal can be understood as: the first transistor T1 and the second transistor T2 satisfy a threshold voltage condition. The threshold voltage condition is: the threshold voltage of the first transistor T1 is less than 0, and the threshold voltage of the second transistor T2 is greater than 0; the absolute value of the threshold voltage of the first transistor T1 and the absolute value of the threshold voltage of the second transistor T2 have a difference less than or equal to 0.5V. Further, in order to make the inverter 10231 better realize switching, the absolute value of the threshold voltage of the first transistor T1 and the absolute value of the threshold voltage of the second transistor T2 can be made to have a difference less than or equal to 0.3V.

[0151] For example, the absolute value of the threshold voltage of the first transistor T1 and the absolute value of the threshold voltage of the second transistor T2 can have a difference less than or equal to 0.5V, which can include two cases: 1. The absolute value of the threshold voltage of the first transistor T1 is greater than the absolute value of the threshold voltage of the second transistor T2, and the difference between the absolute value of the threshold voltage of the first transistor T1 and the absolute value of the threshold voltage of the second transistor T2 is less than or equal to 0.5V; 2. The absolute value of the threshold voltage of the first transistor T1 is less than the absolute value of the threshold voltage of the second transistor T2, and the difference between the absolute value of the threshold voltage of the second transistor T2 and the absolute value of the threshold voltage of the first transistor T1 is less than or equal to 0.5V.

[0152] Before the first transistor T1 and the second transistor T2 are prepared, the threshold voltages required by the first transistor T1 and the second transistor T2 can be determined, and then the dopant dose of the dopant element required to be doped in the active pattern can be determined according to the required threshold voltages.

[0153] Without considering the process deviation of the preparation process, it is assumed that the threshold voltage of a first target transistor in the first transistor T1 and the second transistor T2 is a first threshold voltage, and the threshold voltage of a second target transistor is any second threshold voltage in a second threshold voltage set. The second threshold voltage set includes a plurality of second threshold voltages, and each second threshold voltage and the first threshold voltage satisfy a threshold voltage condition. The first target transistor is one of the first transistor T1 and the second transistor T2, and the second transistor T2 is the other of the first transistor T1 and the second transistor T2.

[0154] The first threshold voltage corresponds to a first dose range of a first target doping element of the active pattern, and the second threshold voltage corresponds to a second dose range of a second target doping element of the active pattern. The dose range of the second threshold voltage set is a union of the second dose ranges of the second threshold voltages included in the second threshold voltage set. That is, the first transistor has a threshold voltage of the first threshold voltage when the channel region of the first transistor is doped with the doping element of any dose in the first dose range, and the second transistor has a threshold voltage satisfying the threshold voltage condition when the channel region of the second transistor is doped with the doping element of any dose in the union of the second dose range.

[0155] Referring to FIG. 15, the threshold voltage of the P-type transistor is approximately -2.18 when boron is doped in the first active pattern T11 of the P-type transistor at a dose of 7.0 x 1014ions / cm2. 11 The threshold voltage of the N-type transistor is approximately 2.19 when phosphorus is doped in the second active pattern T12 of the N-type transistor at a dose of 4.0 x 1014ions / cm2. 12 The threshold voltage of the N-type transistor is approximately 2.19 when phosphorus is doped in the second active pattern T12 of the N-type transistor at a dose of 4.0 x 1014ions / cm2.

[0156] Referring to FIG. 16, the threshold voltage of the P-type transistor is approximately -0.86 when the first target doping element is not doped in the first active pattern T11 of the P-type transistor. The threshold voltage of the N-type transistor is approximately 0.68 when the second target doping element is not doped in the second active pattern T12 of the N-type transistor. The threshold voltage of the transistor can be the threshold voltage corresponding to the value of 1.00E-08 A of the ordinate in FIG. 16.

[0157] As can be seen from FIGS. 15 and 16, in both cases, the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 satisfy the threshold voltage condition.

[0158] In the embodiments of the present application, the working region of the transistor includes a cut-off region, an active region and a saturation region. The cut-off region can refer to that when the gate current of the transistor is small, the transistor is in the cut-off region, also known as the off region. In this region, the transistor is in the off state, and almost no current flows. The current flow from the drain to the source is blocked. The active region can refer to that when the gate current of the transistor gradually increases, the transistor enters the active region. In the active region, the transistor starts to conduct, and the change of the gate current will cause the change of the current from the drain to the source, thereby realizing the increase of the current. The saturation region can refer to that when the change of the gate current further increases, the transistor enters the saturation region. In the saturation region, the transistor is fully turned on, and the current flow from the drain to the source is not limited.

[0159] Referring to FIG. 17, the A region can be the active region of the transistor, and the B region can be the saturation region of the transistor. At the inflection point of the working region of the transistor from the active region to the saturation region, the voltage difference (source-drain voltage difference) Vds of the source and the drain of the transistor can reach the saturation voltage (Vds = Vgs-Vth). Wherein, Vgs is the voltage difference of the gate and the source of the transistor, and Vth is the threshold voltage of the transistor. When the source-drain voltage difference Vds of the transistor reaches the saturation voltage, the drain current of the transistor can be recorded as Id0. The stability of the on-state current is determined in the following manner: in the saturation region, and starting from the saturation voltage, the current of 1V (volt) voltage increase is recorded as Id, and the stability value of the current = [(Id-Id0) / Id0]x100%. Wherein, the smaller the stability value of the current, the better the stability of the current; the larger the stability value of the current, the worse the stability of the current.

[0160] Taking the gate voltage of the transistor as-4V (i.e. Vg=-4V) as an example, it can be seen from FIG. 18 and Table 1 that the stability value of the current of the double-gate transistor is much smaller than that of the single-gate transistor. That is, the stability of the current of the double-gate transistor is better than that of the single-gate transistor, which is one of the reasons why the two transistors of the inverter 10231 in the embodiments of the present application are double-gate transistors.

[0161] In FIG. 18 and Table 1, 25 / 10, 50 / 5, 100 / 5 and 100 / 10 are width-length ratios of the transistors. For the double-gate transistor with the width-length ratio of 25 / 10, the stability of the current is 3.07%; for the single-gate transistor with the width-length ratio of 25 / 10, the stability of the current is 23.18%. For the double-gate transistor with the width-length ratio of 50 / 5, the stability of the current is 3.45%; for the single-gate transistor with the width-length ratio of 50 / 5, the stability of the current is 10.71%. For the double-gate transistor with the width-length ratio of 100 / 5, the stability of the current is 3.74%; for the single-gate transistor with the width-length ratio of 100 / 5, the stability of the current is 12.08%. For the double-gate transistor with the width-length ratio of 100 / 10, the stability of the current is 2.40%; for the single-gate transistor with the width-length ratio of 100 / 10, the stability of the current is 23.42%.

[0162] Table 1

[0163] It should be noted that the width-length ratio of a transistor is an important parameter of the transistor, which represents the ratio of the distance between two adjacent electrodes (source and drain) of the transistor (also referred to as the width of the channel region) to the length of the channel region of the transistor. The width-length ratio is usually represented by "W / L", where W represents the width of the channel region of the transistor, and L represents the length of the channel region of the transistor. Alternatively, the first width-length ratio of the first transistor T1 can be a value of the width of the first channel region divided by the length of the first channel region, and the second width-length ratio of the second transistor T2 can be a value of the width of the second channel region divided by the length of the second channel region. The width-length ratio of a transistor is an important parameter for the transistor to effectively control the current and voltage. Generally, a larger width-length ratio means that the transistor has higher driving capability and lower on-resistance, which can improve the speed and working stability of the transistor.

[0164] In the embodiments of the present application, the width-length ratio of the first transistor T1 and the width-length ratio of the second transistor T2 in the inverter 10231 need to be matched to ensure that the driving capabilities of the two transistors are substantially the same (the driving capability can be represented by the on-state current Ion). The substantially same driving capability can make the inverter 10231 better achieve switching.

[0165] Alternatively, the width-length ratio of a transistor is related to the conductive factor (the conductive factor can also be referred to as the transconductance parameter) of the transistor, and the conductive factor of the inverter 10231 is related to the conductive factors of the two transistors included in the inverter 10231. Referring to the following formula (1), the conductive factor Kr of the inverter 10231 satisfies:

[0166] wherein, in the above formula (1), K N is a conductance factor of the N-type transistor, K P is a conductance factor of the P-type transistor. μ N is a mobility of the N-type transistor, μ P is a mobility of the P-type transistor, (W / L) N is a width-length ratio of the N-type transistor, (W / L) P is a width-length ratio of the P-type transistor, C ox is a gate capacitance per unit area, which is usually a constant.

[0167] When the conductance factor Kr of the inverter 10231 is equal to 1, the threshold voltage of the N-type transistor and the threshold voltage of the P-type transistor are symmetrical (symmetrical means that the absolute values of the threshold voltages are approximately equal), and according to the above formula (1), the following formula (2) can be derived:

[0168] As can be seen from the above formula (2), the ratio of the width-length ratio of the N-type transistor to the width-length ratio of the P-type transistor is equal to the ratio of the mobility of the P-type transistor to the mobility of the N-type transistor. That is, the width-length ratio of the transistor is inversely proportional to the mobility of the transistor.

[0169] According to actual tests, it is found that the mobility of the P-type transistor is less than the mobility of the N-type transistor, and the mobility of the P-type transistor is approximately 75% to 85% of the mobility of the N-type transistor, i.e., the mobility of the P-type transistor is approximately 80% of the mobility of the N-type transistor. Thus, in order to make the width-length ratio of the transistor and the mobility satisfy the above formula (2), the second width-length ratio of the second channel region of the second transistor T2 can be 75% to 85% of the first width-length ratio of the first channel region of the first transistor T1 in the case that the length of the first channel region of the first transistor T1 (P-type transistor) and the length of the second channel region of the second transistor T2 (N-type transistor) are normalized lengths.

[0170] Alternatively, the second width-length ratio of the second channel region of the second transistor T2 can be 80% of the first width-length ratio of the first channel region of the first transistor T1. Further, if the length of the first channel region of the first transistor T1 and the length of the second channel region of the second transistor T2 are equal, the width of the second channel region can be 80% of the width of the first channel region.

[0171] In the embodiment of the present application, referring to FIG. 6, if the driving capabilities of the first transistor T1 and the second transistor T2 are the same, the voltage curve (referred to as VTC curve) of the signal output end and the signal input end of the inverter 10231 is approximately curve 1. In this case, the intersection point of the curve 1 and curve 0 (curve 0 is a straight line represented by the function Vout=Vin) represents the logic threshold voltage Vm of the inverter 10231, which is approximately half of the potential of the VDD signal. The logic threshold voltage can also be referred to as a switching voltage or a threshold voltage of the inverter 10231. The logic threshold voltage Vm can be used to indicate that the first transistor T1 and the second transistor T2 are both in the saturation region.

[0172] If the driving capability of the first transistor T1 is better than that of the second transistor T2, the logic threshold voltage Vm will increase, and the voltage curve of the signal output end and the signal input end of the inverter 10231 is approximately curve 2. That is, compared with curve 1, curve 2 is right-shifted. If the driving capability of the second transistor T2 is better than that of the first transistor T1, the logic threshold voltage Vm will decrease, and the voltage curve of the signal output end and the signal input end of the inverter 10231 is approximately curve 3. That is, compared with curve 1, curve 3 is left-shifted.

[0173] That is, when the logic threshold voltage of the inverter 10231 is approximately half of the potential of the first power supply signal (VDD signal), the driving capabilities of the first transistor T1 and the second transistor T2 are approximately the same. Since process errors are inevitable in the preparation of transistors, it is only necessary to make the absolute value of the difference between the logic threshold voltage of the inverter 10231 and half of the potential of the first power supply signal less than a certain threshold. Alternatively, the absolute value of the difference between the logic threshold voltage of the inverter 10231 and half of the potential of the first power supply signal is less than or equal to 5% of the potential of the first power supply signal.

[0174] As shown in FIG. 19 and Table 2, taking the width-length ratio of the first transistor T1 as 5 / 5, the width-length ratio of the second transistor T2 as 4 / 5, and the voltage range of the signal input end and the signal output end as 0V to 10V as examples, the absolute value of the difference between the logic threshold voltage of each curve (9 curves are shown in the figure) in the voltage curve of the signal output end and the signal input end of the inverter 10231 and half of the potential of the first power supply signal (5V) is less than or equal to 0.5V. That is, the absolute value of the difference between the logic threshold voltage of each curve and half of the potential of the first power supply signal (5V) is less than or equal to 5% of the potential of the first power supply signal.

[0175] Table 2

[0176] In FIG. 19, a graph of a in FIG. 19 is used to represent the curve of the gate voltage Vg and the drain current Id of the first transistor T1. A graph of b in FIG. 19 is used to represent the curve of the gate voltage Vg and the drain current Id of the second transistor T2. A graph of c in FIG. 19 is used to represent the voltage curve of the signal output end OUT and the signal input end IN of the inverter 10231 composed of the first transistor T1 and the second transistor T2. Each transistor in the graph of a in FIG. 19 and the graph of b in FIG. 19 corresponds to form a corresponding inverter 10231. For example, the first transistor T1 numbered 1 in the graph of a in FIG. 19 and the second transistor T2 numbered 1 in the graph of b in FIG. 19 form the inverter 10231 numbered 1 in the graph of c in FIG. 19.

[0177] Table 3 is the threshold voltage, mobility, subthreshold swing, on-state current and off-state current of the nine first transistors T1 represented in the graph of a in FIG. 19. Table 4 is the threshold voltage, mobility, subthreshold swing, on-state current and off-state current of the nine first transistors T1 represented in the graph of b in FIG. 19. It can be seen from Table 3 and Table 4 that the absolute value of the threshold voltage of the first transistor T1 is approximately equal to the absolute value of the threshold voltage of the corresponding second transistor T2. The mobility of the first transistor T1 is approximately 80% of the mobility of the second transistor T2. The subthreshold swing of the first transistor T1 and the subthreshold swing of the second transistor T2 are both small. The on-state current of the first transistor T1 and the on-state current of the second transistor T2 are large, and the off-state current of the first transistor T1 and the off-state current of the second transistor T2 are small.

[0178] Table 3

[0179] Table 4

[0180] In the embodiment of the present application, referring to FIG. 1, the light-emitting component 100 further includes a pin 103. The driving unit 102 further includes a substrate 1024, a connection pad 1025 and a connection trace 1026. The connection pad 1025 is located inside the substrate 1024, that is, the connection pad 1025 is embedded in the substrate 1024. The pin 103 is located on the side of the substrate 1024 away from the driving unit 102, and the pin 103 is connected with the connection pad 1025. The side of the substrate 1024 away from the pin 103 includes a via K1, and the connection trace 1026 is electrically connected with the connection pad 1025 through the via K1 on the substrate 1024. The driving circuit 1023 is located on the side of the connection trace 1026 away from the substrate 1024, and is electrically connected with the connection trace 1026. In this way, the pin 103 can be connected with the connection pad 1025, the connection trace 1026 and the driving circuit 1023.

[0181] The electrical connection between the connection wire 1026 and the connection pad 1025 through the via K1 on the substrate 1024 can mean that, since the connection pad 1025 is located inside the substrate 1024, at least part of the area of the connection pad 1025 away from the pin 103 can be exposed by designing the via K1, and the connection wire 1026 can be electrically connected to at least part of the area of the connection pad 1025 exposed by the via K1. The material of the substrate 1024 can be a flexible material, for example, the material of the substrate 1024 can be polyimide (PI). The connection through the via in the substrate 1024 can be referred to as (Through PI Via, TPV).

[0182] The plurality of pins 103 included in the light emitting assembly 100 can be used to connect with a driving backboard in a display substrate, for receiving driving signals provided by the driving backboard. Optionally, the pin 103 can be prepared by chemical plating or electroplating using metal.

[0183] If the density of the pin 103 is large and the number is large, the yield of the bonding connection between the light emitting assembly 100 and the driving backboard will be low. Therefore, reducing the number of pins 103 can be beneficial to the bonding yield of the light emitting assembly 100 and the driving backboard. However, generally, reducing the number of pins 103 will result in an increase in the number of thin film transistors included in the driving circuit 1023 in the driving unit 102. In order to reduce the number of pins 103 while avoiding too many thin film transistors, an inverter 10231 can be added in the driving circuit 1023. This is one of the reasons why the driving circuit 1023 in the embodiment of the present application includes the inverter 10231.

[0184] In the embodiment of the present application, the inverter 10231 is designed in the driving circuit 1023, and the performance of the inverter 10231 is optimized to improve the performance of the inverter 10231. First, by making the first transistor T1 and the second transistor T2 included in the inverter 10231 be double-gate transistors, the power consumption of the inverter 10231 can be reduced. Second, by adjusting the dopant dose of the doping element of the first active pattern T11 of the first transistor T1 and the dopant dose of the doping element of the second active pattern T21 of the second transistor T2, the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 are made to be approximately equal. Third, by adjusting the first width-length ratio of the first channel region of the first transistor T1 and the second width-length ratio of the second channel region of the second transistor T2, the driving capabilities of the first transistor T1 and the second transistor T2 are made to be approximately the same.

[0185] In the embodiment of the present application, the driving circuit 1023 can further include other circuit parts in addition to the two transistors in the inverter 10231. Referring to FIG. 20, the driving circuit 1023 further includes a data writing circuit 10232, a pixel driving circuit 10233, a first light emitting control circuit 10234, a second light emitting control circuit 10235, a compensation circuit 10236, a first reset circuit 10237, a second reset circuit 10238, a transmission gate circuit 10239, and an adjusting circuit 102310.

[0186] The data writing circuit 10232 is coupled to the gate signal terminal Gate, the data signal terminal Data, and the first node J1, respectively. The data writing circuit 10232 is configured to control the connection between the data signal terminal Data and the first node J1 in response to a gate driving signal (Gate signal) provided by the gate signal terminal Gate.

[0187] The pixel driving circuit 10233 is coupled to the first node J1, the second node J2, and the third node J3, respectively. The pixel driving circuit 10233 is configured to transmit a pixel driving signal to the second node J2 in response to the potential of the first node J1 and the potential of the third node J3.

[0188] The first light emitting control circuit 10234 is coupled to the first light emitting control signal terminal EM, the driving power supply terminal VDD, and the first node J1, respectively. The first light emitting control circuit 10234 is configured to control the connection between the driving power supply terminal VDD and the first node J1 in response to a first light emitting control signal (EM signal) provided by the first light emitting control signal terminal EM.

[0189] The second light emitting control circuit 10235 is coupled to the second node J2, the light emitting unit 101, and the fourth node J4, respectively. The second light emitting control circuit 10235 is configured to control the connection between the second node J2 and the light emitting unit 101 in response to the potential of the fourth node J4.

[0190] The compensation circuit 10236 is coupled to the gate signal terminal Gate, the pull-down power supply terminal VSS, and the third node J3, respectively. The compensation circuit 10236 is configured to control the connection between the second node J2 and the third node J3 in response to the gate driving signal (Gate signal).

[0191] The first reset circuit 10237 is coupled to the reset signal terminal Rst, the pull-down power supply terminal VSS, and the third node J3, respectively. The first reset circuit 10237 is configured to control the connection between the pull-down power supply terminal VSS and the third node J3 in response to a reset signal (Rst signal) provided by the reset signal terminal Rst.

[0192] The second reset circuit 10238 is coupled to the reset signal terminal Rst, the pull-down power terminal VSS and the light emitting unit 101 respectively. The second reset circuit 10238 is configured to control the pull-down power terminal VSS and the light emitting unit 101 in response to the reset signal.

[0193] The transmission gate circuit 10239 is coupled to the fourth node J4, the signal input terminal IN and the inverter 10231 respectively. The transmission gate circuit 10239 is configured to transmit the first light emitting control signal (EM signal) or the second light emitting control signal (HF signal) provided by the second light emitting control signal terminal HF to the fourth node J4 in response to the input signal (DT signal) of the signal input terminal IN and the output signal (DTB signal) provided by the signal output terminal (OUT) of the inverter 10231.

[0194] The adjustment circuit 102310 is coupled to the third node J3 and the driving power terminal VDD respectively. The spring circuit 102310 is configured to adjust the potential of the third node J3 based on the driving power signal (VDD signal).

[0195] The inverter 10231 is coupled to the transmission gate circuit 10239 and the signal input terminal (IN) respectively. The inverter 10231 is configured to transmit the first power signal or the second power signal to the transmission gate circuit 10239 in response to the input signal (DT signal) of the signal input terminal IN.

[0196] In the embodiment of the present application, it is assumed that the input signal (DT signal) of the signal input terminal IN of the inverter 10231 is high potential, and then the signal (DTB signal) output by the signal output terminal OUT of the inverter 10231 is low potential after the inversion of the inverter 10231. It is assumed that the input signal (DT signal) of the signal input terminal IN of the inverter 10231 is low potential, and then the output signal (DTB signal) of the signal output terminal OUT of the inverter 10231 is high potential after the inversion of the inverter 10231. When the potential of the output signal (DTB signal) of the signal output terminal OUT of the inverter 10231 is low potential and high potential, the signals transmitted by the transmission gate circuit 10239 to the fourth node J4 are different. For example, when the potential of the output signal (DTB signal) of the signal output terminal OUT of the inverter 10231 is low potential, the transmission gate circuit 10239 transmits the second light emitting control signal (HF signal) to the fourth node J4. When the potential of the output signal (DTB signal) of the signal output terminal OUT of the inverter 10231 is high potential, the transmission gate circuit 10239 transmits the first light emitting control signal (EM signal) to the fourth node J4.

[0197] Referring to FIG. 20, the data writing circuit 10232 includes a data writing transistor M4. A gate of the data writing transistor M4 is coupled with a gate signal terminal Gate, a first pole of the data writing transistor M4 is coupled with a data signal terminal Data, and a second pole of the data writing transistor M4 is coupled with a first node J1.

[0198] The pixel driving circuit 10233 includes a driving transistor M3. A gate of the driving transistor M3 is coupled with a third node J3, a first pole of the driving transistor M3 is coupled with the first node J1, and a second pole of the driving transistor M3 is coupled with a second node J2.

[0199] The first light emitting control circuit 10234 includes a first light emitting control transistor M5. A gate of the first light emitting control transistor M5 is coupled with a first light emitting control signal terminal EM, a first pole of the first light emitting control transistor M5 is coupled with a driving power terminal VDD, and a second pole of the first light emitting control transistor M5 is coupled with the first node J1.

[0200] The second light emitting control circuit 102135 includes a second light emitting control transistor M6. A gate of the second light emitting control transistor M6 is coupled with a second light emitting control signal terminal HF, a first pole of the second light emitting control transistor M6 is coupled with the second node J2, and a second pole of the second light emitting control transistor M6 is coupled with the light emitting unit 101.

[0201] The compensation circuit 10236 includes a compensation transistor M2. A gate of the compensation transistor M2 is coupled with a gate signal terminal Gata, a first pole of the compensation transistor M2 is coupled with the second node J2, and a second pole of the compensation transistor M2 is coupled with the third node J3.

[0202] The first reset circuit 10237 includes a first reset transistor M1. A gate of the first reset transistor M1 is coupled with a reset signal terminal Rst, a first pole of the first reset transistor M1 is coupled with a pull-down power terminal VSS, and a second pole of the first reset transistor M1 is coupled with the third node J3.

[0203] The second reset circuit 10238 includes a second reset transistor M7. A gate of the second reset transistor M7 is coupled with the reset signal terminal Rst, a first pole of the second reset transistor M7 is coupled with the pull-down power terminal VSS, and a second pole of the second reset transistor M7 is coupled with the light emitting unit 101.

[0204] The transmission gate circuit 10239 comprises a first transmission gate 102391 and a second transmission gate 102392. The first transmission gate 102391 comprises a first transmission transistor K1 and a second transmission transistor K2. The gate of the first transmission transistor K1 is coupled with the signal input end IN, and the second transmission transistor K2 is coupled with the signal output end OUT. The first pole of the first transmission transistor K1 and the first pole of the second transmission transistor K2 are both coupled with the second light-emitting control signal end HF, and the second pole of the first transmission transistor K1 and the second pole of the second transmission transistor K2 are coupled. The second transmission gate 102392 comprises a third transmission transistor K3 and a fourth transmission transistor K4. The gate of the third transmission transistor K3 is coupled with the signal output end OUT, and the gate of the fourth transmission transistor is coupled with the signal input end IN. The first pole of the third transmission transistor K3 and the first pole of the fourth transmission transistor K4 are both coupled with the first light-emitting control signal end EM, and the second pole of the third transmission transistor K3 and the second pole of the fourth transmission transistor K4 are coupled. Wherein, the first transmission transistor K1 and the second transmission transistor K2 are different in type, and the third transmission transistor K3 and the fourth transmission transistor K4 are different in type.

[0205] Optionally, the first transmission transistor K1 and the third transmission transistor K3 are N-type transistors. The second transmission transistor K2 and the fourth transmission transistor K4 are P-type transistors.

[0206] Optionally, assuming that the input signal (DT signal) of the signal input end IN is high potential, after the inversion of the inverter 10231, the signal output end OUT of the inverter outputs a signal (DTB signal) of low potential. And, since the first transmission transistor K1 and the fourth transmission transistor K4 are both coupled with the signal input end, and the first transmission transistor K1 is an N-type transistor and the second transmission transistor K2 is a P-type transistor, the first transmission transistor K1 is turned on under the control of the high potential input signal (DT) of the signal input end (IN), and the fourth transmission transistor K1 is turned off under the control of the high potential input signal (DT) of the signal input end (IN). At the same time, since the second transmission transistor K2 and the third transmission transistor K3 are both coupled with the signal output end, and the second transmission transistor K2 is a P-type transistor and the third transmission transistor K3 is an N-type transistor, the second transmission transistor K1 is turned on under the control of the low potential output signal (DTB signal) of the signal output end (OUT), and the third transmission transistor K3 is turned off under the control of the low potential output signal (DTB signal) of the signal output end (OUT). In this case, the first transmission gate 102391 is turned on, the second transmission gate 102392 is turned off, and the second light-emitting control signal (HF signal) provided by the second light-emitting control signal end HF is transmitted to the fourth node J4 through the turned-on first transmission gate 102391.

[0207] When the input signal (DT signal) of the signal input terminal IN is low, the signal output terminal OUT of the inverter 10231 outputs a high signal (DTB signal) after inversion. Since the first and fourth transistors K1 and K4 are coupled to the signal input terminal, and the first transistor K1 is an N-type transistor and the second transistor K2 is a P-type transistor, the first transistor K1 is turned off under the control of the low input signal (DT) of the signal input terminal (IN), and the fourth transistor K1 is turned on under the control of the low input signal (DT) of the signal input terminal (IN). Since the second and third transistors K2 and K3 are coupled to the signal output terminal, and the second transistor K2 is a P-type transistor and the third transistor K3 is an N-type transistor, the second transistor K1 is turned off under the control of the high output signal (DTB signal) of the signal output terminal (OUT), and the third transistor K3 is turned on under the control of the high output signal (DTB signal) of the signal output terminal (OUT). In this case, the first transmission gate 102391 is turned off, the second transmission gate 102392 is turned on, and the first light-emitting control signal (EM signal) provided by the first light-emitting control signal terminal EM is transmitted to the fourth node J4 through the turned-on second transmission gate 102392.

[0208] In the embodiment of the present application, the inverter 10231 and the transmission gate circuit 10239 can provide different light-emitting control signals for the fourth node J4. The difference between the HF signal and the EM signal is that the frequency of the HF signal is higher than that of the EM signal, which facilitates improving the contrast of low gray scale display and high gray scale display.

[0209] In the embodiment of the present application, the data writing transistor M4, the driving transistor M3, the first light-emitting control transistor M5, the second light-emitting control transistor M6, the compensation transistor M2, the second transistor K2 and the fourth transistor K4 are all P-type transistors. The above embodiment also shows that the first transistor T1 in the inverter 10231 is a P-type transistor.

[0210] The first reset transistor M1, the second reset transistor M2, the first transistor K1 and the third transistor K3 are all N-type transistors. The above embodiment also shows that the second transistor T2 in the inverter 10231 is an N-type transistor.

[0211] Optionally, the same type of transistors in the driving circuit 1023 can be prepared by the same preparation process. For example, when doping elements in the active pattern of the transistor to adjust the threshold voltage of the transistor, the same process doping process can be used.

[0212] For example, the first transistor T1, the data writing transistor M4, the driving transistor M3, the first light emitting control transistor M5, the second light emitting control transistor M6, the compensation transistor M2, the second transfer transistor K2 and the fourth transfer transistor K4 can be prepared by using the same preparation process. The second transistor T2, the first reset transistor M1, the second reset transistor M2, the first transfer transistor K1 and the third transfer transistor K3 can be prepared by using the same preparation process.

[0213] Optionally, the other transistors in the driving circuit 1023 except the first transistor T1 and the second transistor T2 can be double-gate transistors or single-gate transistors, and the embodiments of the present application do not limit this.

[0214] In the embodiments of the present application, the driving circuit 1023 includes seven thin film transistors and one storage capacitor except the transistors in the inverter 10231 and the transfer gate circuit 10239. Such a driving circuit 1023 can be referred to as a 7T1C driving circuit. Alternatively, the driving circuit 1023 can include other numbers of thin film transistors and other numbers of storage capacitors except the transistors in the inverter 10231 and the transfer gate circuit 10239. The embodiments of the present application do not limit the number of thin film transistors included in the driving circuit 1023 and the number of storage capacitors included in the driving circuit 1023.

[0215] Each thin film transistor includes a gate, a source and a drain. The plurality of thin film transistors included in the driving circuit 1023 are connected to each other to achieve the function of driving the light emitting unit 101 to emit light.

[0216] In the embodiments of the present application, referring to FIGS. 21 and 22, the driving circuit 1023 includes, in the direction away from the substrate 1024, a barrier n1, a first gate layer (gate1) n2, a buffer layer (buffer) n3, an active layer (poly) n4, a gate insulator (GI) n5, a second gate layer (gate2) n6, an inter level dielectric (ILD) n7, a source-drain layer n8, a planarization layer (PLN) n9, a first passivation layer (PVX1) n10 and a second passivation layer (PVX2) n11. The third electrode 1021 and the fourth electrode 1022 are located between the first passivation layer n10 and the second passivation layer n11, and the second passivation layer n11 exposes the third electrode 1021 and the fourth electrode 1022. In addition, the connection trace 1026 also has a third passivation layer (PVX3) n12 on the side close to the substrate 1021.

[0217] The first gate layer n2 includes a first gate pattern n21, and the first gate pattern n21 includes a first pattern portion n211 and a second pattern portion n212 in an integrated structure. The first pattern portion n211 is a bottom gate of the first transistor T1, and the second pattern portion n212 is a bottom gate of the second transistor T2. The first pattern portion n211 and the second pattern portion n212 in an integrated structure can mean that the first pattern portion n211 and the second pattern portion n212 constitute an integral pattern, so that the bottom gate of the first transistor T1 and the bottom gate of the second transistor T2 are connected. In the case where the transistors other than the first transistor T1 and the second transistor T2 in the drive circuit 1023 are also double-gate transistors, the first gate layer n2 can also include gate patterns (which can serve as bottom gates) of the other transistors.

[0218] The active layer n4 includes a first active pattern T11 of the first transistor T1 and a second active pattern T21 of the second transistor T2. The first active pattern T11 and the second active pattern T21 are arranged at intervals, and the first active pattern T11 overlaps with a portion of the orthographic projection of the first pattern portion n211 on the substrate 1024, and the second active pattern T21 overlaps with a portion of the orthographic projection of the second pattern portion n212 on the substrate 1024. Among them, the portion where the first active pattern T11 and the first pattern portion n211 overlap can serve as a first channel region of the first active pattern T11. The portion where the second active pattern T21 and the second pattern portion n212 overlap can serve as a second channel region of the second active pattern T21. In addition, the active layer n4 can also include active patterns of other transistors.

[0219] The second gate layer n6 includes a second gate pattern n61 connected through the via holes in the gate insulating layer n5 and the buffer layer n3 and the first gate pattern n21. The second gate pattern n61 includes a third pattern portion n611 and a fourth pattern portion n612 in an integrated structure. The third pattern portion n611 is a top gate of the first transistor T1, and the orthographic projection of the third pattern portion n611 on the substrate 1024 and the orthographic projection of the first active pattern T11 on the substrate 1024 partially overlap. The fourth pattern portion n612 is a top gate of the second transistor T2, and the orthographic projection of the fourth pattern portion n612 on the substrate 1024 and the orthographic projection of the first active pattern T11 on the substrate 1024 partially overlap. The third pattern portion n611 and the fourth pattern portion n612 in an integrated structure can mean that the third pattern portion n611 and the fourth pattern portion n612 constitute an integral pattern, so that the top gate of the first transistor T1 and the top gate of the second transistor T2 are connected. In the case where the transistors other than the first transistor T1 and the second transistor T2 in the drive circuit 1023 are also double-gate transistors, the second gate layer n6 can also include the gate patterns (which can serve as the top gates) of the other transistors.

[0220] The source-drain layer n8 includes the first source T1_s and the first drain T1_d of the first transistor T1, and the second source T2_s and the second drain T2_d of the second transistor T2. The first source T1_s is connected through the via holes in the interlayer dielectric layer n7, the gate insulating layer n5 and the buffer layer n3 and the source region of the first active pattern T11. The first drain T1_d is connected through the via holes in the interlayer dielectric layer n7, the gate insulating layer n5 and the buffer layer n3 and the drain region of the first active pattern T11. The second source T2_s is connected through the via holes in the interlayer dielectric layer n7, the gate insulating layer n5 and the buffer layer n3 and the source region of the second active pattern T21. The second drain T2_d is connected through the via holes in the interlayer dielectric layer n7, the gate insulating layer n5 and the buffer layer n3 and the drain region of the second active pattern T21. In addition, the source-drain layer n8 also includes the sources and the drains of the other transistors, the source of each transistor is connected to the active region of the active pattern of the transistor, and the drain of each transistor is connected to the drain region of the active pattern of the transistor.

[0221] Optionally, referring to FIG. 2, the drain region of the first active pattern T11 of the first transistor T1 and the drain region of the second active pattern T21 of the second transistor T2 are located between the source region of the first active pattern T11 of the first transistor T1 and the source region of the second active pattern T21 of the second transistor T2. Thus, the drain regions of the two transistors are connected through one pattern in the source-drain layer n8.

[0222] In the embodiments of the present application, the light-emitting assembly 100 comprises a plurality of light-emitting units 101 and driving units 102 corresponding to the plurality of light-emitting units 101. The driving unit 102 can comprise a plurality of driving circuits 1023 corresponding to the plurality of light-emitting units 101, and some of the plurality of driving circuits 1023 can be common film layers. That is, each driving circuit 1023 in the driving unit 102 can be used to drive a corresponding light-emitting unit 101 to emit light.

[0223] Optionally, the plurality of light-emitting units 101 comprises light-emitting units of a first color, light-emitting units of a second color, and light-emitting units of a third color. The first color, the second color, and the third color are different from each other. For example, the first color is red (R), the second color is green (G), and the third color is blue (B).

[0224] In the embodiments of the present application, referring to FIG. 1, the light-emitting assembly 100 further comprises a first substrate 104 located away from the driving unit 102 of the light-emitting unit 101. FIG. 23 is a structural schematic diagram of a light-emitting unit according to an embodiment of the present application. Referring to FIG. 23, the light-emitting unit 101 comprises, in sequence from the first substrate 104, a color film layer 10131, a color conversion layer 10132, and a light-emitting layer 10133. The light-emitting layer 10133 emits blue light.

[0225] Referring to FIG. 24, the light-emitting layer 10133 comprises a first doped layer 101331, a multiple quantum well layer 101332, and a second doped layer 101333 arranged in sequence. The first doped layer 101331 is electrically connected to the first electrode 1011, and the second doped layer 101333 is electrically connected to the second electrode 1012.

[0226] Optionally, the first doped layer 101331 can be an N-type doped layer, and the second doped layer 101333 can be a P-type doped layer. Correspondingly, the first electrode 1011 can be referred to as an N-type electrode, and the second electrode 1012 can be referred to as a P-type electrode. Optionally, the material of the first doped layer 101331 can be N-type gallium nitride (GaN), and the first doped layer 101331 is denoted as N-GaN. The material of the second doped layer 101333 can be P-type gallium nitride (GaN), and the second doped layer 101333 is denoted as P-GaN.

[0227] Further, in the case where the light-emitting assembly 100 comprises three light-emitting units 101, the light-emitting layer 10133 comprises a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer. That is, the light-emitting colors of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are all blue. Only one light-emitting layer 10133 is shown in FIG. 24.

[0228] The color conversion layer 10132 includes a first color conversion portion, a second color conversion portion, and a transparent portion. In FIG. 24, only one color conversion portion 101321 is shown. The first color conversion portion overlaps the orthographic projection of the first light emitting portion on the first substrate 104, and is configured to convert the light emitted by the first light emitting layer into a color corresponding to the first color conversion portion (e.g., red). The second color conversion portion overlaps the orthographic projection of the second light emitting layer on the first substrate 104, and is configured to convert the light emitted by the second light emitting layer into a color corresponding to the second color conversion portion (e.g., green). The transparent portion overlaps the orthographic projection of the third light emitting layer on the first substrate 104, and is configured to transmit the light emitted by the third light emitting layer.

[0229] Optionally, the color conversion layer 10132 further includes a spacing portion 101322 between any two adjacent color conversion portions or between any two adjacent transparent portions. The spacing portion is configured to separate and distinguish the different color conversion portions and the transparent portions.

[0230] The color filter layer 10131 includes a first color resist block, a second color resist block, a third color resist block, and a black matrix 101312. In FIG. 24, only one color resist block 101311 is shown. The black matrix is located between adjacent color resist blocks. The first color resist block overlaps the orthographic projection of the first color conversion portion on the first substrate 104, and is configured to transmit the light of the corresponding color converted by the first color conversion portion, and to block the light of other colors. The second color resist block overlaps the orthographic projection of the second color conversion portion on the first substrate 104, and is configured to transmit the light of the corresponding color converted by the second color conversion portion, and to block the light of other colors. The third color resist block overlaps the orthographic projection of the transparent portion on the first substrate 104, and is configured to transmit the light of the corresponding color transmitted by the transparent portion, and to block the light of other colors.

[0231] In an example, the first color resist block is a red color resist block, the second color resist block is a green color resist block, and the third color resist block is a blue color resist block.

[0232] In the embodiments of the present application, referring to FIG. 24, the second doped layer 101333 and the multiple quantum well layer 101332 are configured to expose the target portion of the first doped layer 101331. The light emitting layer 10133 further includes a raised electrode 101334, a conductive layer 101335, and an insulating layer 101336.

[0233] The target part of the cushioning electrode 101334 is connected with the first doped layer 101331, the conductive layer 101335 is located on the side of the second doped layer 101333 away from the first substrate 104, and the insulating layer 101336 is located on the side of the cushioning electrode 101334 and the conductive layer 101335 away from the first substrate 104. The insulating layer 101336 has a first via hole (N-type via hole) and a second via hole (P-type via hole). The first via hole is used to expose the cushioning electrode 101334, and the cushioning electrode 101334 and the first electrode 1011 are connected through the first via hole. The second via hole is used to expose the conductive layer 101335, and the conductive layer 101335 and the second electrode 1012 are connected through the second via hole. Optionally, the material of the conductive layer 101335 can be indium tin oxide (ITO), and the insulating layer 101336 can be a passivation layer (PVX).

[0234] It can also be seen from FIG. 24 that the light emitting unit 101 further includes an adhesive layer 10134 and a buffer layer n3. The adhesive layer and the buffer layer n3 are both located between the color conversion layer 10132 and the light emitting layer 10133. The adhesive layer is used to adhere the color conversion layer 10132 and the buffer layer n3. The material of the buffer layer n3 can be GaN.

[0235] In summary, the embodiment of the present application provides a light emitting assembly, which includes a light emitting unit and a driving unit. The third electrode of the driving unit is electrically connected with the first electrode of the light emitting unit, and the fourth electrode of the driving unit is electrically connected with the second electrode of the light emitting unit, so that the driving unit drives the light emitting unit to emit light. The first transistor and the second transistor in series in the inverter included in the driving circuit in the driving unit are different in type and are both double-gate transistors. Since the double-gate transistors have stable current output and low leakage current, the power consumption of the inverter can be small, which is conducive to reducing the power consumption of the light emitting assembly.

[0236] FIG. 25 is a flowchart of a method for manufacturing a light emitting assembly according to an embodiment of the present application. Referring to FIG. 25, the method includes the following steps.

[0237] In step S101, a first substrate and a light emitting unit on the first substrate are obtained.

[0238] In the embodiment of the present application, the orthographic projection of the light emitting unit 101 on the first substrate 104 is located in the first substrate 104. The light emitting unit 101 includes a first electrode 1011, a second electrode 1012, and a light emitting part 1013 electrically connected with the first electrode 1011 and the second electrode 1012.

[0239] In step S102, a second substrate and a driving unit on the second substrate are obtained.

[0240] In the embodiment of the present application, the driving unit 102 includes a third electrode 1021, a fourth electrode 1022, and a driving circuit 1023. The third electrode 1021 and the fourth electrode 1022 are both located on the side of the driving unit 102 away from the second substrate, and the third electrode 1021 and the fourth electrode 1022 are respectively connected with the driving circuit 1023.

[0241] The driving circuit 1023 includes an inverter 10231, and the inverter 10231 includes a first transistor T1 and a second transistor T2 connected in series. The first transistor T1 and the second transistor T2 are different in type, and both the first transistor T1 and the second transistor T2 are double-gate transistors.

[0242] In the embodiment of the present application, the different types of the first transistor T1 and the second transistor T2 can mean that one of the first transistor T1 and the second transistor T2 is a P-type transistor, and the other is an N-type transistor. The double-gate transistor is a transistor with a double-gate structure, and its principle is to change the conductivity of the channel by controlling the gate voltage.

[0243] The double-gate transistor is composed of a channel separated by two gates and an insulating layer, one of which is used to connect to the input signal source to control the main flow path of the current, and the other is used to connect to the bias voltage source to assist in adjusting the main flow path.

[0244] Compared with the single-gate transistor, the output current of the double-gate transistor is greater than that of the single-gate transistor, which can help to reduce the size of the light-emitting unit 101 included in the light-emitting assembly and improve the pixel density (PPI). The stability of the on-state current of the double-gate transistor is higher than that of the single-gate transistor, so the use of the double-gate transistor in the inverter 10231 can improve the stability of the current output and thus improve the uniformity of the display brightness. The drain current of the double-gate transistor is smaller than that of the single-gate transistor, thereby reducing the power consumption of the light-emitting assembly. The subthreshold swing of the double-gate transistor is smaller than that of the single-gate transistor, thereby being able to improve the response speed of the inverter 10231.

[0245] In the embodiment of the present application, referring to FIG. 26, the process of obtaining the second substrate and the driving unit 102 located on the second substrate includes:

[0246] In step S1021, the second substrate is obtained, and a substrate, a connection pad, and a connection trace are formed on one side of the second substrate.

[0247] In the embodiment of the present application, referring to FIG. 27, the connection pad 1025 is located inside the substrate 1024, and the connection trace 1026 is connected with the connection pad 1025 through a via on the substrate 1024.

[0248] Step S1022: Form a barrier layer on the side of the connection trace away from the second substrate.

[0249] In this embodiment, referring to Figures 21 and 22, the barrier layer n1 can be located on the side of the connection trace 1026 away from the second substrate. Furthermore, the barrier layer n1 can be a single, continuous film layer. Since the other films in the driving circuit 1023 are located on the side of the barrier layer n1 away from the second substrate, to simplify the subsequent drawing of the films, the substrate 1024, connection pad 1025, connection trace 1026, and barrier layer n1 in the following figures are simplified.

[0250] Step S1023: A first gate film is formed on the side of the barrier layer away from the second substrate, and the first gate film is patterned to obtain a first gate layer.

[0251] In this embodiment, a first gate film can be deposited on the side of the barrier layer n1 away from the second substrate. The first gate film is then patterned using a photomask to obtain a first gate layer n2. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0252] Optionally, the material of the first gate film can be Mo (molybdenum), with a thickness ranging from 30 nm to 200 nm. For example, the thickness of the first gate film can be 50 nm or 100 nm. It should be noted that Mo is chosen as the material for the first gate film due to its good stability. Furthermore, the thickness of the first gate film should not be too low, otherwise the yield and uniformity of the film layer will be poor; the thickness of the first gate film should also not be too high, otherwise it will affect the flatness of the subsequently formed active layer n4, which may lead to a decrease in the crystallization effect of excimer laser annealing (ELA).

[0253] Referring to Figures 28 to 30, the first gate layer n2 includes a first gate pattern n21, which includes a first pattern portion n211 and a second pattern portion n212 of an integral structure. The first pattern portion n211 is the bottom gate of the first transistor T1, and the second pattern portion n212 is the bottom gate of the second transistor T2.

[0254] Step S1024: A buffer layer is formed on the side of the first gate layer away from the second substrate.

[0255] In this embodiment, referring to FIG31, the buffer layer n3 is located on the side of the first gate layer n2 away from the second substrate. In subsequent steps, the buffer layer n3 also needs to be provided with vias for the connection of the top gate and bottom gate of the transistor. However, in step S1024, the buffer layer n3 has not yet formed vias.

[0256] Optionally, the buffer layer n3 can be a stack of two inorganic material layers. For example, the buffer layer n3 can be a stack of SiNx (silicon nitride) and SiO2 (silicon oxide). The thickness of the silicon nitride can be 50 nm, and the thickness of the silicon oxide can be 300 nm. The silicon oxide is farther from the substrate 1024 than the silicon nitride.

[0257] In step S1025, an active thin film is formed on the side of the buffer layer away from the second substrate, and the active pattern is subjected to a patterning process to obtain an active layer.

[0258] In the embodiment of the present application, referring to FIG. 31, an amorphous silicon (a-Si) thin film can be deposited on the side of the buffer layer n3 away from the second substrate, and the a-Si is subjected to a crystallization process to obtain an active thin film. Then, the active thin film is subjected to a first doping using a first mask (a-Si mask 1) and a second doping using a second mask (a-Si mask 2). Optionally, the thickness of the active thin film can be 47 nm.

[0259] In the first doping, the thin film region of the first active pattern T11 for forming the first transistor T1 in the active thin film can be subjected to channel doping (also referred to as vth doping) so that the doped thin film region constitutes the first active pattern T11 of the first transistor T1 (P-type transistor). In the second doping, the thin film region of the second active pattern T21 for forming the second transistor T2 in the active thin film can be subjected to channel doping so that the doped thin film region constitutes the second active pattern T21 of the second transistor T2 (N-type transistor).

[0260] Since the first active pattern T11 of the first transistor T1 has completed channel doping in the second doping, in order to avoid the influence of the second patterning process on the first active pattern T11, the first active pattern T11 can be protected by photoresist in the second doping.

[0261] After the two doping processes, the active thin film can be subjected to a patterning process using a third mask (poly mask) to obtain an active layer n4. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0262] Referring to FIGS. 32-34, the first active pattern T11 and the second active pattern T21 are arranged at intervals. The orthographic projection of the first active pattern T11 on the substrate 1024 and the orthographic projection of the first pattern portion n211 on the substrate 1024 overlap. The orthographic projection of the second active pattern T21 on the substrate 1024 and the orthographic projection of the second pattern portion n212 on the substrate 1024 overlap. The region in which the first active pattern T11 and the first pattern portion n211 overlap is a first channel region of the first active pattern T11, and the region in which the second active pattern T21 and the second pattern portion n212 overlap is a second channel region of the second active pattern T21.

[0263] In step S1026, a gate insulating layer is formed on the side of the active layer away from the second substrate.

[0264] In the embodiment of the present application, referring to FIGS. 35-37, a gate insulating film can be deposited on the side of the active layer n4 away from the second substrate, and then a mask is used to pattern the gate insulating film to obtain the gate insulating layer n5.

[0265] Optionally, the gate insulating film can be two layers of inorganic material stacked. For example, the gate insulating film can be a stack of SiO2 (silicon oxide) and SiNx (silicon nitride). The thickness of the silicon oxide can be 80 nm, and the thickness of the silicon nitride can be 40 nm. The silicon nitride is away from the substrate 1024 relative to the silicon oxide.

[0266] Optionally, in the process of patterning the gate insulating film, the buffer layer n3 in step S1024 can be processed, so that the gate insulating layer n5 and the buffer layer n3 include a via (which can be used to connect the first gate pattern n21 and the subsequently formed second gate pattern n61). In the subsequent steps, the gate insulating layer n5 also needs to provide a via for the source and drain of the source and drain layer n8 to connect with the active pattern of the active layer n4. However, in step S1026, the gate insulating layer n5 has not yet formed the via.

[0267] In step S1027, a second gate film is formed on the side of the gate insulating layer away from the second substrate, and the second gate film is patterned to obtain a second gate layer.

[0268] In the embodiment of the present application, referring to FIG. 38, a second gate film is first deposited on the side of the gate insulating layer n5 away from the second substrate. Optionally, the material of the second gate film can be Mo (molybdenum), and the thickness can be 220 nm.

[0269] Then, referring to FIG. 39, a first gate mask is used to perform a first patterning on the second gate thin film to obtain a top gate pattern portion (a third pattern portion n611) of the first transistor T1. Referring to FIG. 40, the top gate pattern portion of the first transistor T1 is used as a mask, and a first doping region of a first active pattern T11 of the first transistor T1 is doped with a first doping element.

[0270] Referring to FIG. 41, a second gate mask is used to perform a second patterning on the second gate thin film to obtain a top gate pattern portion n612a of the second transistor T2. Then, referring to FIG. 42, the top gate pattern portion n612a of the second transistor T2 is used as a mask, and a first partial region of a second doping region of a second active pattern T21 of the second transistor T2 is doped for a first time with a second doping element. Referring to FIG. 43, the photoresist above the top gate pattern portion of the second transistor T2 is ashed, and the two sides of the top gate pattern portion are shrunk (the shrunk top gate pattern portion is a fourth pattern portion n612). Then, the shrunk top gate pattern portion is used as a mask, and the second partial region of the second active pattern T21 is doped for a second time with the second doping element. The doping dose for the first time is higher than the doping dose for the second time.

[0271] In step S1028, an interlayer dielectric layer is formed on a side of the second gate layer away from the second substrate.

[0272] In the embodiment of the present application, referring to FIGS. 44-46, an interlayer dielectric thin film can be deposited on a side of the second gate layer n6 away from the second substrate, and then a mask is used to pattern the interlayer dielectric thin film to obtain the interlayer dielectric layer n7.

[0273] Optionally, the interlayer dielectric thin film can be composed of two layers of inorganic material. For example, the interlayer dielectric thin film can be composed of SiO2 (silicon oxide) and SiNx (silicon nitride). The thickness of the silicon oxide can be 200 nm, and the thickness of the silicon nitride can be 300 nm. The silicon nitride is farther away from the substrate 1024 than the silicon oxide.

[0274] Optionally, in the process of patterning the interlayer dielectric thin film, the gate insulating layer n5 in step S1026 can also be processed, so that the interlayer dielectric layer n7 and the gate insulating layer n5 include a via (which can be used to connect the active pattern of the active layer n4 and the source and drain of the source-drain layer n8 to be formed later). Meanwhile, the interlayer dielectric layer n7 also includes a via for connecting the signal input end IN and the second gate pattern n61.

[0275] In step S1029, a source-drain film is formed on the side of the interlayer dielectric layer away from the second substrate, and the source-drain film is patterned to obtain a source-drain layer.

[0276] In the embodiments of the present application, referring to FIGS. 2-4, a source-drain film is deposited on the side of the interlayer dielectric layer n7 away from the second substrate. Then, the source-drain pattern is patterned using a mask to obtain the source-drain layer n8. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0277] Optionally, the material of the source-drain layer n8 can be a three-layer structure of Ti (titanium), Al (aluminum), and Ti. The thicknesses of the three layers are 50 nm, 650 nm, and 50 nm, respectively.

[0278] The source-drain layer n8 includes the first source T1_s and the first drain T1_d of the first transistor T1, and the second source T2_s and the second drain T2_d of the second transistor T2. The first source T1_s is connected to the source region of the first active pattern T11 through the via in the interlayer dielectric layer n7 and the gate insulating layer n5. The first drain T1_d is connected to the drain region of the first active pattern T11 through the via in the interlayer dielectric layer n7 and the gate insulating layer n5. The second source T2_s is connected to the source region of the second active pattern T21 through the via in the interlayer dielectric layer n7 and the gate insulating layer n5. The second drain T2_d is connected to the drain region of the second active pattern T21 through the via in the interlayer dielectric layer n7 and the gate insulating layer n5.

[0279] In the embodiments of the present application, after the source-drain layer n8 is formed, a planarization layer n9, a first passivation layer n10, a driving electrode layer (the third electrode 1021 and the fourth electrode 1022), and a second passivation layer n11 can be further formed on the side of the source-drain layer n8 away from the second substrate. The second passivation layer n11 has a via for exposing the third electrode 1021 and the fourth electrode 1022, so that the third electrode 1021 can be electrically connected to the first electrode 1011 of the light-emitting unit 101 and the fourth electrode 1022 can be electrically connected to the second electrode 1012 of the light-emitting unit 101 in subsequent processes.

[0280] In the embodiments of the present application, a plurality of light-emitting assemblies 100 can be simultaneously prepared on a large second substrate using the above preparation process. In this case, referring to FIG. 47, after the third electrode 1021 and the fourth electrode 1022 are prepared and the second passivation film (the second passivation film is an integral film without a hole) is formed, a cutting process can be used to separate the driving circuits 102 of the plurality of light-emitting assemblies 100, and then a hole is opened in the second passivation film to expose the third electrode 1021 and the fourth electrode 1022.

[0281] For example, four driving units (1023a, 1023b, 1023c and 1023d) are shown in FIG. 47. Any two adjacent driving units are cut during cutting, so that each driving unit is independently arranged. During cutting, the inorganic film layer in the driving unit 1023 can be cut first, and then the substrate 1024 can be cut. The material of the substrate 1024 can be a flexible material, such as polyimide (PI).

[0282] In step S103, the light-emitting unit and the driving unit are bonded and connected by a bonding process.

[0283] Referring to FIG. 48, after the light-emitting unit 101 and the driving unit 102 are bonded and connected by the bonding process, the third electrode 1021 and the first electrode 1011 are electrically connected, and the fourth electrode 1022 and the second electrode 1012 are electrically connected.

[0284] In step S104, the second substrate is peeled off from one side of the driving unit.

[0285] In the embodiment of the present application, referring to FIG. 49, after bonding and connection, the second substrate can be peeled off from one side of the driving unit 102 by a laser liftoff (LLO) method.

[0286] In addition, after the second substrate is peeled off from one side of the driving unit 102, the first substrate 104 can also be thinned (the thickness of the first substrate 104 after thinning is less than the thickness of the first substrate 104 before thinning), so that the total thickness of the finally formed light-emitting assembly is relatively thin, and the thinning of the display substrate is facilitated.

[0287] In step S105, a plurality of pins are formed on the side of the driving unit away from the light-emitting unit.

[0288] In the embodiment of the present application, referring to FIG. 50, the entire assembly formed by the above steps S501 to S505 can be placed in a special solution, and a plurality of pins 103 can be formed on the side of the driving unit 102 away from the light-emitting unit 101 by an electroplating process or a chemical plating process. The plurality of pins 103 can be connected with the driving unit 102, so that the driving backplane included in the display substrate can provide driving signals for the driving unit 102 through the pins 103, so that the driving unit 102 can drive the light-emitting unit 101 to emit light.

[0289] The pins 103 are connected with the driving circuit 1023 through the connection pad 1025 and the connection trace 1026 in the driving unit 102. In addition, the pins 103 cover the connection pad 1025 in the orthographic projection on the substrate 1024.

[0290] Optionally, before the driving unit 102 is prepared, a release film can be formed on the second substrate, which is used to peel off the second substrate.

[0291] In the embodiment of the present application, in the case of preparing a plurality of driving units 102 of the light emitting assembly 100 at the same time, the preparation process includes: 1. a mask for forming a connection pad, which is used for patterning; 2. a mask for forming a substrate, which is used for opening (the substrate needs to be opened for the connection of the connection wire 1026 and the connection pad 1025); 3. a mask for forming a third passivation layer, which is used for opening (the third passivation layer needs to be opened for the connection of the connection wire 1026 and the connection pad 1025); 4. a mask for the connection wire, which is used for patterning; 5. a mask for forming a first gate layer, which is used for patterning; 6. a mask for doping the first active pattern of the first transistor; 7. a mask for doping the second active pattern of the second transistor; 8. a mask for patterning the active film; 9. a mask for forming a gate insulating layer; 10. a mask for forming the active pattern of the first transistor and doping the first doped region; 11. a mask for forming the active pattern of the second transistor and doping the second doped region; 12. a mask for forming an interlayer dielectric layer, which is used for opening; 13. a mask for forming a source-drain layer, which is used for patterning; 14. a mask for forming a planarization layer, which is used for patterning; 15. a mask for forming a first passivation layer, which is used for opening; 16. a mask for forming a third electrode and a fourth electrode, which is used for patterning; 17. a mask for cutting a plurality of driving units 102; 18. a mask for forming a second passivation layer, which is used for opening. That is, in the process of preparing the driving unit 102, a total of 18 masks (18mask) can be used.

[0292] In summary, the embodiment of the present application provides a preparation method of a light emitting assembly, and the light emitting assembly prepared by the method includes a light emitting unit and a driving unit. The third electrode of the driving unit and the first electrode of the light emitting unit are electrically connected, and the fourth electrode of the driving unit and the second electrode of the light emitting unit are electrically connected, so as to drive the light emitting unit to emit light by the driving unit. The driving circuit in the driving unit includes a first transistor and a second transistor in series in an inverter, and the types of the first transistor and the second transistor are different, and both are double-gate transistors. Since the double-gate transistor has stable current output and low leakage current, the power consumption of the inverter can be small, which is conducive to reducing the power consumption of the light emitting assembly.

[0293] FIG. 51 is a structural schematic diagram of a display substrate provided by an embodiment of the present application. Referring to FIG. 51, the display substrate 00 includes a driving backplane 200 and a plurality of light emitting assemblies 100.

[0294] Referring to FIG. 51, a plurality of light emitting assemblies 100 are located in a display area 00a of a display substrate 00, and the plurality of light emitting assemblies 100 are arranged in an array. A driving backboard 200 is used to carry the light emitting assemblies 100 and provide driving signals to the light emitting assemblies 100. For example, the driving backboard 200 is used to provide driving signals to the driving units 102 through a plurality of pins 103 in the light emitting assemblies 100, so that the driving units 102 drive the light emitting units 101 to emit light.

[0295] In the display substrate 00, the plurality of light emitting assemblies 100 are independently arranged, i.e., the light emitting assemblies 100 are independent of each other, so that the maintenance and replacement of a single light emitting assembly 100 can be realized. Alternatively, the light emitting assemblies 100 can be in a chip structure, and different light emitting assemblies are distributed at intervals. For example, different light emitting assemblies 100 are isolated by air.

[0296] Alternatively, the driving backboard 200 can be a passive driving backboard. The display substrate can be a display screen in a mobile phone, a notebook computer or a flat computer, or an outdoor advertising screen.

[0297] Since the display substrate can have substantially the same technical effects as the light emitting assemblies described in the foregoing embodiments, for the purpose of brevity, the technical effects of the display substrate are not described again.

[0298] The terms used in the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings of the same to those skilled in the art.

[0299] The terminology used by the descriptions in the implementation part of the present application is only used to explain the embodiments of the present application, and is not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the implementation part of the present application should be understood as the general meaning understood by a person with ordinary skills in the art to which the present application belongs. The terms "first", "second", "third", and the like used in the patent application description and claims of the present application do not represent any order, number or importance, but are only used to distinguish different components. Similarly, "one" or "a" and the like do not represent a quantity limitation, but represent the existence of at least one. The terms "including", "containing" and the like mean that the elements or objects appearing before "including" or "containing" cover the elements or objects listed after "including" or "containing" and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0300] It should be noted that in the drawings, the sizes of the layers and regions can be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or one or more intervening layers or elements can also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or one or more intervening layers or elements can also be present. Throughout the drawings, like reference numerals indicate like elements.

[0301] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A light emitting assembly, characterized by The light-emitting component comprises: a light-emitting unit, comprising a first electrode, a second electrode, and a light-emitting part electrically connected to the first electrode and the second electrode respectively; a driving unit, comprising a third electrode, a fourth electrode, and a driving circuit, the third electrode and the fourth electrode are located on the side of the driving unit facing the light-emitting unit, the third electrode and the fourth electrode are electrically connected to the driving circuit respectively, the third electrode is electrically connected to the first electrode, and the fourth electrode is electrically connected to the second electrode; wherein the driving circuit comprises an inverter, the inverter comprises a first transistor and a second transistor connected in series, the first transistor and the second transistor are different in type, and the first transistor and the second transistor are both double-gate transistors.

2. The light emitting assembly of claim 1, wherein, The first transistor is a P-type transistor, the second transistor is an N-type transistor, the first transistor comprises a first gate, a first source and a first drain, and the second transistor comprises a second gate, a second source and a second drain; wherein the first gate and the second gate are connected, the first source is connected to a first power supply end, the first drain and the second drain are connected, the second source is connected to a second power supply end, and the first power supply signal provided by the first power supply end and the second power supply signal provided by the second power supply end are different in potential.

3. The light emitting assembly of claim 2, wherein, The potential of the first power supply signal is higher than the potential of the second power supply signal.

4. The light emitting assembly of claim 2, wherein, The threshold voltage conditions of the first transistor and the second transistor are: the threshold voltage of the first transistor is less than 0, and the threshold voltage of the second transistor is greater than 0; the difference between the absolute value of the threshold voltage of the first transistor and the absolute value of the threshold voltage of the second transistor is less than or equal to 0.5V.

5. The light emitting assembly of claim 5, wherein, The difference between the absolute value of the threshold voltage of the first transistor and the absolute value of the threshold voltage of the second transistor is less than or equal to 0.3V.

6. A light emitting assembly according to claim 4 or 5, characterized in that The first transistor comprises a first active pattern, the first active pattern comprises a first source region, a first drain region and a first channel region, the first source region and the first drain region are both first doped regions, the first doped regions are doped with a first type of doped elements, the first channel region is the region where the first gate and the first active pattern overlap, the first source is electrically connected to the first source region, and the first drain is electrically connected to the first drain region; The second transistor comprises a second active pattern, the second active pattern comprises a second source region, a second drain region and a second channel region, the second source region and the second drain region are both second doped regions, the second doped regions are doped with a second type of doped elements, the second channel region is the region where the second gate and the second active pattern overlap, the second source is electrically connected to the second source region, and the second drain is electrically connected to the second drain region; wherein the first type of doped elements and the second type of doped elements are different in type.

7. The light emitting assembly of claim 6, wherein, The first type of doped elements is boron, and the second type of doped elements is phosphorus.

8. The light emitting assembly of claim 6, wherein, The first channel region is doped with a first target doping element, and the second channel region is doped with a second target doping element, the first target doping element and the second target doping element are one of the first type of doping element and the second type of doping element; A first target transistor in the first transistor and the second transistor has a first threshold voltage, and a second target transistor has any second threshold voltage in a second threshold voltage set, the second threshold voltage set includes a plurality of the second threshold voltage, and each of the second threshold voltage and the first threshold voltage satisfies the threshold voltage condition; The first threshold voltage corresponds to a first dose range of the first target doping element, and each of the second threshold voltage corresponds to a second dose range of the second target doping element, and the dose range of the second threshold voltage set is the union of the second dose range of the second threshold voltage set including a plurality of the second threshold voltage. In the case that the length of the first channel region and the length of the second channel region are normalized lengths, the second width-length ratio of the second channel region is 75% to 85% of the first width-length ratio of the first channel region; 9. The light emitting assembly of claim 6, wherein, Wherein, the first width-length ratio is the value of the width of the first channel region divided by the length of the first channel region, and the second width-length ratio is the value of the width of the second channel region to the length of the second channel region. The second width-length ratio is 80% of the first width-length ratio.

10. The light emitting assembly of claim 9, wherein, In the case that the length of the first channel region and the length of the second channel region are equal, the width of the second channel region is 80% of the width of the first channel region.

11. The light emitting assembly of claim 9, wherein, The absolute value of the difference between the logic threshold voltage of the inverter and half of the potential of the first power signal is less than or equal to 5% of the potential of the first power signal.

12. The light emitting assembly of claim 2, wherein, The light-emitting component further comprises a pin, and the driving unit further comprises a substrate, a connection pad and a connection trace; 13. The light emitting assembly according to any of claims 1 to 5, and 7 to 12, characterized in that, The connection pad is located inside the substrate, the pin is located on the side of the substrate away from the driving unit, and the pin and the connection pad are connected, and the connection trace is connected with the connection pad through a via on the substrate; the driving circuit is located on the side of the connection trace away from the substrate and is connected with the connection trace. The driving circuit comprises, in sequence from the side away from the substrate, a barrier layer, a first gate layer, a buffer layer, an active layer, a gate insulating layer, a second gate layer, an interlayer dielectric layer, a source-drain layer and a planar layer; the third electrode and the fourth electrode are located on the side of the planar layer away from the substrate; 14. The light emitting assembly of claim 13, wherein, The first gate layer comprises a first gate pattern, and the first gate pattern comprises a first pattern portion and a second pattern portion in an integrated structure, the first pattern portion is a bottom gate of the first transistor, and the second pattern portion is a bottom gate of the second transistor; ​ The active layer comprises a first active pattern of the first transistor and a second active pattern of the second transistor, the first active pattern and the second active pattern are arranged at intervals, a projection of the first active pattern on the substrate and a projection of the first pattern part on the substrate are overlapped, a projection of the second active pattern on the substrate and a projection of the second pattern part on the substrate are overlapped; The second gate layer comprises a second gate pattern, the second gate pattern is connected with the first gate pattern through the via in the gate insulating layer and the buffer layer, the second gate pattern comprises a third pattern part and a fourth pattern part in an integrated structure, the third pattern part is a top gate of the first transistor, a projection of the third pattern part on the substrate and a projection of the first active pattern on the substrate are overlapped, the fourth pattern part is a top gate of the second transistor, a projection of the fourth pattern part on the substrate and a projection of the first active pattern on the substrate are overlapped; The source-drain layer comprises a first source and a first drain of the first transistor, and a second source and a second drain of the second transistor, the first source is connected with a source region of the first active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer, the first drain is connected with a drain region of the first active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer, the second source is connected with a source region of the second active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer, and the second drain is connected with a drain region of the second active pattern through the via in the interlayer dielectric layer, the gate insulating layer and the buffer layer.

15. The light emitting assembly according to any of claims 2 to 5, and 7 to 12, characterized in that, The driving circuit further comprises: a data writing circuit, the data writing circuit is coupled with the gate signal end, the data signal end and the first node respectively, and the data writing circuit is configured to control the data signal end and the first node to be turned on or turned off in response to the gate driving signal provided by the gate signal end; a pixel driving circuit, the driving circuit is coupled with the first node, the second node and the third node respectively, and the driving circuit is configured to transmit a driving signal to the second node in response to the potential of the first node and the potential of the third node; a first light emitting control circuit, the first light emitting control circuit is coupled with the first light emitting control signal end, the driving power supply end and the first node respectively, and the first light emitting control circuit is configured to control the driving power supply end and the first node to be turned on or turned off in response to the light emitting control signal provided by the first light emitting control signal end; a second light emitting control circuit, the second light emitting control circuit is coupled with the second node, the light emitting unit and the fourth node respectively, and the second light emitting control circuit is configured to control the second node and the light emitting unit to be turned on or turned off in response to the potential of the fourth node. a compensation circuit coupled to the gate signal terminal, the second node and the third node, and configured to control the connection between the second node and the third node in response to the gate driving signal; a first reset circuit coupled to a reset signal terminal, a pull-down power supply terminal and the third node, and configured to control the connection between the pull-down power supply terminal and the third node in response to a reset signal provided by the reset signal terminal; a second reset circuit coupled to the reset signal terminal, the pull-down power supply terminal and the light emitting unit, and configured to control the connection between the pull-down power supply terminal and the light emitting unit in response to the reset signal; a transmission gate circuit coupled to the fourth node, a signal input terminal and the inverter, and configured to transmit the first light emitting control signal to the fourth node or transmit a second light emitting control signal provided by a second light emitting control signal terminal in response to an input signal of the signal input terminal and an output signal provided by a signal output terminal of the inverter; an adjusting circuit coupled to the third node and the driving power supply terminal, and configured to adjust the potential of the third node based on the driving power supply signal; wherein the inverter is coupled to the transmission gate circuit and the signal input terminal, and configured to transmit the first power supply signal or the second power supply signal to the transmission gate circuit in response to the input signal of the signal input terminal.

16. The light emitting assembly of claim 15, wherein, The data writing circuit comprises a data writing transistor; a gate of the data writing transistor is coupled to the gate signal terminal; a first electrode of the data writing transistor is coupled to the data signal terminal; and a second electrode of the data writing transistor is coupled to the first node. The pixel driving circuit comprises a driving transistor; a gate of the driving transistor is coupled to the third node; a first electrode of the driving transistor is coupled to the first node; and a second electrode of the driving transistor is coupled to the second node. The first light emitting control circuit comprises a first light emitting control transistor; a gate of the first light emitting control transistor is coupled to the first light emitting control signal terminal; a first electrode of the first light emitting control transistor is coupled to the driving power supply terminal; and a second electrode of the first light emitting control transistor is coupled to the first node. The second light emitting control circuit comprises a second light emitting control transistor; a gate of the second light emitting control transistor is coupled to the fourth node; a first electrode of the second light emitting control transistor is coupled to the second node; and a second electrode of the second light emitting control transistor is coupled to the light emitting unit. The compensation circuit comprises a compensation transistor; a gate of the compensation transistor is coupled to the gate signal terminal; a first electrode of the compensation transistor is coupled to the second node; and a second electrode of the compensation transistor is coupled to the third node. The first reset circuit comprises a first reset transistor; a gate of the first reset transistor is coupled with the reset signal end, a first pole of the first reset transistor is coupled with the pull-down power supply end, and a second pole of the first reset transistor is coupled with the third node; The second reset circuit comprises a second reset transistor; a gate of the second reset transistor is coupled with the reset signal end, a first pole of the second reset transistor is coupled with the pull-down power supply end, and a second pole of the second reset transistor is coupled with the light-emitting unit; The transmission gate circuit comprises a first transmission gate and a second transmission gate; the first transmission gate comprises a first transmission transistor and a second transmission transistor; a gate of the first transmission transistor is coupled with the signal input end, a gate of the second transmission transistor is coupled with the signal output end, a first pole of the first transmission transistor and a first pole of the second transmission transistor are both coupled with the second light-emitting control signal end, and a second pole of the first transmission transistor and a second pole of the second transmission transistor are coupled; the second transmission gate comprises a third transmission transistor and a fourth transmission transistor; a gate of the third transmission transistor is coupled with the signal output end, a gate of the fourth transmission transistor is coupled with the signal input end, a first pole of the third transmission transistor and a first pole of the fourth transmission transistor are both coupled with the first light-emitting control signal end, and a second pole of the third transmission transistor and a second pole of the fourth transmission transistor are coupled; wherein, the first transmission transistor and the second transmission transistor are of different types, and the third transmission transistor and the fourth transmission transistor are of different types. The data writing transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the compensation transistor, the second transmission transistor and the fourth transmission transistor are all P-type transistors and are prepared by using the same preparation process as the first transistor; 17. The light emitting assembly of claim 16, wherein, The first reset transistor, the second reset transistor, the first transmission transistor and the third transmission transistor are all N-type transistors and are prepared by using the same preparation process as the second transistor. The light-emitting assembly comprises a plurality of light-emitting units and the driving units corresponding to the plurality of light-emitting units; 18. The light emitting assembly according to any of claims 1-5 and 7-12, characterized by The plurality of light-emitting units comprise light-emitting units of a first color, light-emitting units of a second color and light-emitting units of a third color, and the first color, the second color and the third color are different from each other. The light-emitting assembly further comprises a first substrate located away from the driving units with respect to the light-emitting units; the light-emitting part comprises, in sequence from the first substrate, a color film layer, a color conversion layer and a light-emitting layer; the light-emitting layer has a blue light-emitting color; 19. The light emitting assembly of claim 18, wherein, The light-emitting layer comprises a first doped layer, a multi-quantum well layer and a second doped layer which are stacked; the first doped layer is electrically connected with the first electrode, and the second doped layer is electrically connected with the second electrode. ​ 20. A display substrate, comprising: The display substrate comprises a driving backboard and a plurality of light-emitting components as claimed in any one of claims 1 to 19 arranged in an array on one side of the driving backboard. The driving backboard is a passive matrix driving backboard, and the driving backboard is used for carrying the light-emitting components and providing driving signals to the light-emitting components.

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