Pixel driving circuit, driving method of pixel driving circuit and display panel

Abstract

The invention provides a pixel driving circuit, a driving method of the pixel driving circuit and a display panel, and relates to the technical field of display. The pixel driving circuit comprises a driving transistor, a data write-in sub-circuit, a first reset sub-circuit, a first light-emitting control sub-circuit and a first energy storage sub-circuit, wherein the data writing sub-circuit is used for responding to a gate level of a data writing signal so as to write a data voltage to a second node; the first reset sub-circuit is used for responding to a gate level of a first reset signal so as to load a reference voltage to a second node; the first light-emitting control sub-circuit is used for responding to a gate level of a first light-emitting control signal so as to load a driving power supply voltage to a first pole of the driving transistor; one end of the first energy storage sub-circuit is electrically connected with the second node, and the other end, the fourth node and the light-emitting element are electrically connected. The display quality of the display panel can be improved.

Description

Pixel driving circuit, driving method of pixel driving circuit and display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a pixel driving circuit, a driving method of pixel driving circuit and a display panel. BACKGROUND

[0002] Organic Light-emitting Diode (OLED) is a new flat panel display device. It has the advantages of self-luminous, high contrast, wide color gamut and wide temperature range of use.

[0003] Although the OLED display has many advantages described above, the threshold voltage of the driving transistor of the pixel driving circuit of the OLED display will be different due to process deviation in the manufacturing process. And with the extension of working time and the change of use environment, the threshold voltage of the driving transistor will drift, so that the driving current of each sub-pixel is not the same, thereby affecting the display quality.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0005] SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a pixel driving circuit, a driving method of pixel driving circuit and a display panel. The present disclosure can improve the display quality of the display panel.

[0007] According to a first aspect of the present disclosure, a pixel driving circuit is provided, comprising a driving transistor, a data writing sub-circuit, a first reset sub-circuit, a first light emitting control sub-circuit, a first energy storage sub-circuit, and a light emitting element.

[0008] The data writing sub-circuit is configured to write a data voltage to the second node in response to a gating level of a data writing signal.

[0009] The first reset sub-circuit is configured to load a reference voltage to the second node in response to a gating level of a first reset signal.

[0010] The first light emitting control sub-circuit is configured to load a driving power voltage to the first electrode of the driving transistor in response to a gating level of a first light emitting control signal.

[0011] The driving transistor is configured to control the size of the driving current according to the voltage on the second node.

[0012] One end of the first energy storage sub-circuit is electrically connected with the second node, and the other end of the first energy storage sub-circuit, the fourth node and the light emitting element are electrically connected with each other.

[0013] In an embodiment of the present disclosure, the first energy storage sub-circuit comprises a first capacitor and a second capacitor; and the pixel driving circuit comprises a second reset sub-circuit.

[0014] The first end of the first capacitor, the first end of the second capacitor and the first node are electrically connected with each other, the second end of the first capacitor is electrically connected with the fourth node, and the second end of the second capacitor is electrically connected with the second node.

[0015] The second reset sub-circuit is configured to load any one of a reference voltage and an initialization signal to the first node in response to a gating level of a second reset signal.

[0016] In an embodiment of the present disclosure, the first end of the second reset sub-circuit is electrically connected with the second node, the second end of the second reset sub-circuit is electrically connected with the first node, and the control end of the second reset sub-circuit is electrically connected with a second reset signal end.

[0017] Alternatively, the first end of the second reset sub-circuit is electrically connected with a reference voltage end, the second end of the second reset sub-circuit is electrically connected with the first node, and the control end of the second reset sub-circuit is electrically connected with a second reset signal end.

[0018] In an embodiment of the present disclosure, the first end of the second reset sub-circuit is electrically connected with an initialization signal end, the second end of the second reset sub-circuit is electrically connected with the first node, and the control end of the second reset sub-circuit is electrically connected with a second reset signal end.

[0019] In an embodiment of the present disclosure, the first energy storage sub-circuit comprises a first capacitor; the first end of the first capacitor is electrically connected with the second node, and the second end of the first capacitor is electrically connected with the fourth node.

[0020] In an embodiment of the present disclosure, the pixel driving circuit further comprises a second energy storage sub-circuit; one end of the second energy storage sub-circuit is electrically connected with the fourth node, and the other end of the second energy storage sub-circuit is configured to load a constant voltage.

[0021] In an embodiment of the present disclosure, the second energy storage sub-circuit comprises a third capacitor; the first end of the third capacitor is configured to load a constant voltage, and the second end of the third capacitor is electrically connected with the fourth node.

[0022] In an embodiment of the present disclosure, the pixel driving circuit further comprises a third reset sub-circuit; the third reset sub-circuit is configured to load an initialization signal to the fourth node in response to a gating level of a third reset signal.

[0023] In an embodiment of the present disclosure, the pixel driving circuit further comprises a second light emitting control sub-circuit; the second light emitting control sub-circuit is configured to electrically connect the light emitting element with the fourth node in response to a gating level of a second light emitting control signal.

[0024] In an embodiment of the present disclosure, the pixel driving circuit further comprises a third capacitor; a first end of the third capacitor is configured to load a constant voltage, and a second end of the third capacitor is electrically connected with the fourth node.

[0025] The data writing sub-circuit comprises a data writing transistor.

[0026] A first pole of the data writing transistor is electrically connected with a data voltage end, a second pole of the data writing transistor is electrically connected with the first node, and a control pole of the data writing transistor is electrically connected with a data writing signal end.

[0027] The first reset sub-circuit comprises a first reset transistor.

[0028] A first pole of the first reset transistor is electrically connected with a reference voltage end, a second pole of the first reset transistor is electrically connected with the second node, and a control pole of the first reset transistor is electrically connected with a first reset signal end.

[0029] The first light emitting control sub-circuit comprises a first light emitting control transistor.

[0030] A first pole of the first light emitting control transistor is electrically connected with a driving power voltage end, a second pole of the first light emitting control transistor is electrically connected with the first pole of the driving transistor, and a control pole of the first light emitting control transistor is electrically connected with a first light emitting control signal end.

[0031] In an embodiment of the present disclosure, the second reset sub-circuit comprises a second reset transistor.

[0032] A first pole of the second reset transistor is electrically connected with the second node, a second pole of the second reset transistor is electrically connected with the first node, and a control pole of the second reset transistor is electrically connected with a second reset signal end.

[0033] Alternatively, a first pole of the second reset transistor is electrically connected with a reference voltage end, a second pole of the second reset transistor is electrically connected with the first node, and a control pole of the second reset transistor is electrically connected with a second reset signal end.

[0034] Alternatively, a first electrode of the second reset transistor is electrically connected with an initialization signal terminal, a second electrode of the second reset transistor is electrically connected with the first node, and a control electrode of the second reset transistor is electrically connected with a second reset signal terminal.

[0035] In an embodiment of the present disclosure, the pixel driving circuit further comprises a third reset sub-circuit and a second light-emitting control sub-circuit.

[0036] The third reset sub-circuit comprises a third reset transistor, a first electrode of the third reset transistor is electrically connected with an initialization signal terminal, a second electrode of the third reset transistor, a light-emitting element and a third node are electrically connected with each other, and a control electrode of the third reset transistor is electrically connected with a third reset signal terminal.

[0037] The second light-emitting control sub-circuit comprises a second light-emitting control transistor, a first electrode of the second light-emitting control transistor is electrically connected with the fourth node, a second electrode of the second light-emitting control transistor, the light-emitting element and the third node are electrically connected with each other, and a control electrode of the second light-emitting control transistor is electrically connected with a second light-emitting control signal terminal.

[0038] In an embodiment of the present disclosure, the pixel driving circuit does not comprise a second reset sub-circuit, the first energy storage sub-circuit comprises only a first capacitor, a first end of the first capacitor is electrically connected with the second node, a second end of the first capacitor is electrically connected with the fourth node, and the first node and the second node are the same node.

[0039] In an embodiment of the present disclosure, the pixel driving circuit further comprises a third reset sub-circuit.

[0040] The data writing sub-circuit comprises a data writing transistor.

[0041] A first electrode of the data writing transistor is electrically connected with a data voltage terminal, a second electrode of the data writing transistor is electrically connected with the first node, and a control electrode of the data writing transistor is electrically connected with a data writing signal terminal.

[0042] The first reset sub-circuit comprises a first reset transistor.

[0043] A first electrode of the first reset transistor is electrically connected with a reference voltage terminal, a second electrode of the first reset transistor is electrically connected with the second node, and a control electrode of the first reset transistor is electrically connected with a first reset signal terminal.

[0044] The third reset sub-circuit comprises a third reset transistor; a first pole of the third reset transistor is electrically connected with an initialization signal terminal, a second pole of the third reset transistor, the light-emitting element and a fourth node are mutually electrically connected, and a control pole of the third reset transistor is electrically connected with a third reset signal terminal;

[0045] The first light-emitting control sub-circuit comprises a first light-emitting control transistor;

[0046] A first pole of the first light-emitting control transistor is electrically connected with a driving power supply voltage terminal, a second pole of the first light-emitting control transistor is electrically connected with a first pole of the driving transistor, and a control pole of the first light-emitting control transistor is electrically connected with a first light-emitting control signal terminal.

[0047] In an embodiment of the present disclosure, the first reset signal, the third reset signal and the second reset signal are the same signal.

[0048] In an embodiment of the present disclosure, the constant voltage is any one of a driving power supply voltage, a reference voltage and an initialization signal.

[0049] In an embodiment of the present disclosure, a material of a channel region of at least one transistor is a metal oxide semiconductor material.

[0050] The driving transistor is an N-type transistor.

[0051] According to a second aspect of the present disclosure, a driving method of a pixel driving circuit is provided, which is applied to the pixel driving circuit described above; the driving method of the pixel driving circuit comprises:

[0052] In the reset stage, a gating level of the first reset signal is loaded to the pixel driving circuit.

[0053] In the compensation stage, a gating level of the first reset signal and the first light-emitting control signal is loaded to the pixel driving circuit.

[0054] In the writing stage, a gating level of the data writing signal is loaded to the pixel driving circuit.

[0055] In the light-emitting stage, a gating level of the first light-emitting control signal is loaded to the pixel driving circuit.

[0056] In an embodiment of the present disclosure, the pixel driving circuit further comprises a third reset transistor, a second reset transistor and a second light-emitting control transistor;

[0057] A first pole of the third reset transistor is electrically connected with an initialization signal terminal, a second pole of the third reset transistor, the light-emitting element and a third node are mutually electrically connected, and a control pole of the third reset transistor is electrically connected with a third reset signal terminal.

[0058] a first electrode of the second light-emitting control transistor is electrically connected with the fourth node, a second electrode of the second light-emitting control transistor is electrically connected with the third node, and a control electrode of the second light-emitting control transistor is electrically connected with a second light-emitting control signal terminal;

[0059] a first electrode of the second reset transistor is electrically connected with the second node, a second electrode of the second reset transistor is electrically connected with the first node, and a control electrode of the second reset transistor is electrically connected with a second reset signal terminal;

[0060] alternatively, a first electrode of the second reset transistor is electrically connected with an initialization signal terminal, a second electrode of the second reset transistor is electrically connected with the first node, and a control electrode of the second reset transistor is electrically connected with a second reset signal terminal;

[0061] a driving method of the pixel driving circuit comprises:

[0062] in the reset stage, the pixel driving circuit is loaded with a first reset signal, a second light-emitting control signal, a third reset signal, and a second reset signal in a gating level;

[0063] in the compensation stage, the pixel driving circuit is loaded with a first reset signal, a third reset signal, a second reset signal, and a first light-emitting control signal in a gating level;

[0064] in the writing stage, the pixel driving circuit is loaded with a data writing signal in a gating level;

[0065] in the light-emitting stage, the pixel driving circuit is loaded with a first light-emitting control signal and a second light-emitting control signal in a gating level.

[0066] in an embodiment of the present disclosure, the pixel driving circuit further comprises a third reset transistor and a second light-emitting control transistor;

[0067] a first electrode of the third reset transistor is electrically connected with an initialization signal terminal, a second electrode of the third reset transistor, a light-emitting element, and a third node are electrically connected with each other, and a control electrode of the third reset transistor is electrically connected with a third reset signal terminal;

[0068] a first electrode of the second light-emitting control transistor is electrically connected with the fourth node, a second electrode of the second light-emitting control transistor is electrically connected with the third node, and a control electrode of the second light-emitting control transistor is electrically connected with a second light-emitting control signal terminal;

[0069] a driving method of the pixel driving circuit comprises:

[0070] In the reset stage, the pixel driving circuit is loaded with a first reset signal, a second emission control signal, and a gate level of a third reset signal;

[0071] In the compensation stage, the pixel driving circuit is loaded with a first reset signal, a third reset signal, and a gate level of a first emission control signal;

[0072] In the write stage, the pixel driving circuit is loaded with a gate level of a data write signal;

[0073] In the emission stage, the pixel driving circuit is loaded with a gate level of a first emission control signal and a second emission control signal.

[0074] According to a third aspect of the present disclosure, a driving method of a pixel driving circuit is provided, which is applied to the pixel driving circuit described above; the driving method of the pixel driving circuit comprises:

[0075] In the reset stage, the pixel driving circuit is loaded with a first reset signal, a third reset signal, and a gate level of a second reset signal;

[0076] In the compensation stage, the pixel driving circuit is loaded with a first reset signal, a second reset signal, and a gate level of a first emission control signal;

[0077] In the write stage, the pixel driving circuit is loaded with a gate level of a data write signal;

[0078] In the emission stage, the pixel driving circuit is loaded with a gate level of a first emission control signal.

[0079] According to a fourth aspect of the present disclosure, a display panel is provided, which comprises the pixel driving circuit described above.

[0080] In an embodiment of the present disclosure, the display area of the display panel has a plurality of pixel driving circuit rows arranged in an array, and at least two pixel driving circuits in a same pixel driving circuit row share a first emission control sub-circuit.

[0081] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0082] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0083] FIG. 1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0084] FIG. 2 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0085] FIG. 3 is a simulation diagram of driving current in a pixel driving circuit in the related art.

[0086] FIG. 4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0087] FIG. 5 is a simulation diagram of driving current in a pixel driving circuit in one embodiment of the present disclosure.

[0088] FIG. 6 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0089] FIG. 7 is a driving timing diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0090] FIG. 8-1 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0091] FIG. 8-2 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0092] FIG. 8-3 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0093] FIG. 8-4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0094] FIG. 9 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0095] FIG. 10 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0096] FIG. 11 is a driving timing diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0097] FIG. 12-1 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0098] FIG. 12-2 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0099] FIG. 12-3 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0100] FIG. 12-4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0101] FIG. 13 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0102] FIG. 14 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0103] FIG. 15 is a driving timing diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0104] FIG. 16 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0105] FIG. 17 is a driving timing diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0106] FIG. 18 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0107] FIG. 19 is a driving timing diagram of the pixel driving circuit in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0108] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus a detailed description of the same will not be repeated. In addition, the drawings are only schematic and are non-limiting.

[0109] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component as the device is positioned in a particular orientation, such terminology is used herein for convenience only and is not limiting, unless otherwise indicated. It will be understood that when a device is inverted, such terminology can be reversed. When a structure is "on" or "under" another structure, it can mean that the structure is formed directly on the other structure or that the structure is indirectly on the other structure by having one or more intervening structures disposed therebetween.

[0110] The terms "a", "an", "the" and "at least one" are used to mean one or more elements / components / etc.; the terms "comprises", "comprising", "includes", "including" and the like are used to mean including, but not limited to; the term "consisting of" is used to mean including, and the only components / elements listed after the term; and the term "consisting essentially of" is used to mean including at least the recited components / elements, but excluding others not specifically recited.

[0111] The structural layer A is formed on the side of the structural layer B away from the substrate. It is understood that the structural layer A is formed on the side of the structural layer B away from the substrate. When the structural layer B is a patterned structure, part of the structure of the structural layer A can also be at the same physical height as the structural layer B or below the physical height of the structural layer B, wherein the substrate is the height reference.

[0112] In this embodiment of the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region refers to a region through which current mainly flows.

[0113] In this embodiment of the present disclosure, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using transistors with opposite polarities or in the case of changing the current direction in the operation of a circuit. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other. In this embodiment of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor, and the gate electrode is referred to as a control electrode of the transistor. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In this embodiment of the present disclosure, at least part of a signal has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can cause a transistor to be controlled to be on; the other of the high level and the low level can be a gate-off level of the signal, which can cause the transistor to be controlled to be off. For example, for a signal for controlling a P-type transistor (which can be applied to a control terminal of the P-type transistor), the gate-on level thereof is the low level and the gate-off level thereof is the high level. For another example, for a signal for controlling an N-type transistor (which can be applied to a control terminal of the N-type transistor), the gate-on level thereof is the high level and the gate-off level thereof is the low level.

[0114] In this embodiment of the present disclosure, each signal has a signal terminal, so that the signal can be applied to the signal terminal. For example, a first reset signal can be applied to a first reset signal terminal. For another example, a data voltage can be applied to a data voltage terminal.

[0115] The display panel PNL provided by the embodiment of the present disclosure includes a display area AA and a peripheral area BB located at least one side of the display area AA. The display area AA of the display panel PNL includes an array of display units. The display unit includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The display panel PNL has a plurality of scan lines GL arranged along the row direction DH in the display area AA, each scan line GL is arranged one-to-one corresponding to each display unit row; the scan line GL is connected with each pixel driving circuit PDC of the corresponding display unit row. The display panel PNL has a plurality of data lines DL arranged along the column direction DV in the display area AA, each data line DL is arranged one-to-one corresponding to each display unit column; the data line DL is connected with each pixel driving circuit PDC of the corresponding display unit column. In this way, the pixel driving circuit PDC of each display unit is connected with one scan line GL and one data line DL. When the selection signal is loaded on the scan line GL, the data voltage loaded on the data line DL can be loaded to the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0116] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, Micro LED, Mini LED and the like. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0117] In an embodiment of the present disclosure, referring to FIG. 2, the display panel PNL can include a substrate BP, a driving layer DRL and a pixel layer PIXL arranged in sequence. The pixel layer PIXL is provided with sub-pixels PIX, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixel PIX; each sub-pixel PIX can emit light under the driving of the pixel driving circuit PDC to display a picture. Further, the display panel PNL further includes a thin film encapsulation layer TFE located away from the substrate BP on the side of the pixel layer PIXL, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0118] Optionally, the substrate BP can be a substrate of inorganic material, or a substrate of organic material, or a composite substrate of a substrate of inorganic material and a substrate of organic material. For example, in some embodiments of the present disclosure, the substrate BP can be made of glass material such as soda lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the substrate BP can be made of poly(methyl methacrylate), polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate BP can be a flexible substrate, for example, the substrate BP can include polyimide.

[0119] Optionally, in the driving layer DRL, any one of the pixel driving circuits PDC can include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0120] It can be understood that in the pixel driving circuit PDC, the types of any two of the transistors can be the same or different. For example, in some embodiments, in one pixel driving circuit PDC, some of the transistors can be N-type transistors and some of the transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit PDC, the material of the active layer of some of the transistors can be low-temperature polysilicon semiconductor material and the material of the active layer of some of the transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some of the thin film transistors are low-temperature polysilicon transistors and some of the thin film transistors are metal oxide transistors.

[0121] Optionally, the driving layer DRL can include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc. which are stacked between the substrate base plate BP and the pixel layer PIXL. Each thin film transistor and storage capacitor can be located in the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, etc. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form part of the wiring or conductive structure by being conductive if necessary. The gate layer GT can be used to form one or more of the gate layer GT wiring such as the write control wiring, the reset control wiring, the light-emitting control wiring, etc., and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor. The source-drain metal layer SD can be used to form the data wiring, the driving power voltage wiring, etc. of the source-drain metal layer wiring, and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, for example, it can also include a light shielding layer between the semiconductor layer SCL and the substrate base plate BP, etc. As needed, any one of the above-mentioned semiconductor layer SCL, gate layer GT, source-drain metal layer SD, etc. film layer can also be multi-layered, for example, the driving layer DRL can include two different semiconductor layers SCL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layer in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) can be adaptively increased or reduced, or new insulating film layers can be added as needed.

[0122] Optionally, the driving layer DRL can also include a passivation layer, which can be arranged on the surface of the source-drain metal layer SD away from the substrate base plate BP, so as to protect the source-drain metal layer SD.

[0123] As an example, referring to FIG. 2, the driving layer DRL can include a buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD and a planarization layer PLN which are sequentially stacked, and the thin film transistor formed in this way is a top gate type thin film transistor.

[0124] In an embodiment of the present disclosure, the sub-pixel PIX in the pixel layer PIXL is a thin film light emitting element, which can include two electrodes and a light emitting functional unit arranged between the two electrodes. For example, referring to FIG. 2, the pixel layer PIXL can include a light emitting element layer PEL, a light emitting functional layer EFL and a common electrode layer COML arranged in sequence. The light emitting element layer PEL has a plurality of light emitting elements PE in the display area of the display panel; the light emitting functional layer EFL has a part connected with the light emitting element PE as the light emitting functional unit of the sub-pixel PIX, and the common electrode layer COML is electrically connected with the light emitting functional unit of each sub-pixel PIX as a common electrode.

[0125] Further, the pixel layer PIXL can further include a pixel definition layer PDL between the light emitting element layer PEL and the light emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of light emitting elements PE, and any one pixel opening exposes at least a part of the corresponding light emitting element. For example, the pixel definition layer PDL covers the edges of the light emitting element PE and exposes at least a part of the internal area of the light emitting element PE, so that the pixel definition layer PDL can effectively define the actual effective area of the light emitting element PE (the area directly connected with the light emitting functional unit), and further define the light emitting area and the light emitting area of the sub-pixel PIX. The light emitting functional layer EFL at least covers the light emitting element PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light emitting functional layer EFL in the display area. The light emitting element PE and the common electrode layer COML provide carriers such as electrons and holes to the light emitting functional layer EFL, so that the light emitting functional layer EFL emits light. The part of the light emitting functional layer EFL between the light emitting element layer PEL and the common electrode layer COML can be used as a light emitting functional unit. The light emitting element PE, the common electrode layer COML and the light emitting functional unit form the sub-pixel PIX. One of the light emitting element PE and the common electrode layer COML is an anode of the sub-pixel PIX, and the other is a cathode of the sub-pixel PIX.

[0126] In an example, the light emitting element PE is an anode of the sub-pixel PIX, and the common electrode layer COML is a cathode of the sub-pixel PIX.

[0127] It can be understood that the type of light emitting element is different, and the material and film layer of the light emitting functional unit are different. For example, when the light emitting element is an OLED, the light emitting functional unit can include an organic electroluminescent material layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer.

[0128] Referring to FIG. 2, a thin film encapsulation layer TFE can be disposed on a surface of the pixel layer PIXL away from the substrate BP, which can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layers can effectively block moisture and oxygen from the outside, avoiding the invasion of water and oxygen into the pixel layer PIXL and causing the material in the pixel layer PIXL to age. Optionally, the edges of the inorganic encapsulation layers can be located in the peripheral region. The organic encapsulation layers are located between two adjacent inorganic encapsulation layers to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edges of the organic encapsulation layers can be located between the edges of the display region and the edges of the inorganic encapsulation layers. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 stacked in sequence on a side of the pixel layer PIXL away from the substrate BP. The first inorganic encapsulation layer CVD1 covers the display region and extends to the outside of the barrier wall; the organic encapsulation layer IJP covers the display region and extends to the inside of the barrier wall; and the second inorganic encapsulation layer CVD2 covers the organic encapsulation layer IJP and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer CVD2 is in contact with the first inorganic encapsulation layer CVD1. In this way, the organic encapsulation layer IJP is enclosed by the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and the stress on the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 is balanced. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 enclose the organic encapsulation layer IJP, isolating the organic encapsulation layer IJP from water and oxygen.

[0129] In some embodiments of the present disclosure, referring to FIG. 2, the display panel PNL can further include a touch function layer TSL, which can be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel PNL has a touch function.

[0130] Optionally, the pixel driving circuit PDC at least includes a data writing transistor, a driving transistor and a storage capacitor, a gate of the driving transistor can be electrically connected with one of the electrode plates of the storage capacitor. A source of the data writing transistor can be electrically connected with the data line DL, and a gate of the data writing transistor can be electrically connected with the scan line GL. The pixel driving circuit PDC is configured such that when a scan signal is loaded on the scan line GL, the data writing transistor is turned on, so that a driving voltage on the data line DL is written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on the gate thereof. It can be understood that the pixel driving circuit PDC of the embodiments of the present disclosure can also include other transistors or capacitors to make the pixel driving circuit PDC have better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), 8T1C (8 thin film transistors and one storage capacitor) or other architecture of pixel driving circuit.

[0131] In the related art, the organic light-emitting diode OLED can emit light driven by the driving current generated when the driving transistor works in the saturation state. However, process deviation can cause differences in threshold voltages of the driving transistors of different pixel driving circuits, and the threshold voltages of the driving transistors can drift with the extension of working time and the change of use environment, so that the driving currents of the sub-pixels are different, which affects the display quality of the display panel PNL. For example, referring to FIG. 3, when the threshold voltages of the driving transistors are -1V, -0.5V, 0V, 0.5V and 1V respectively, the driving currents generated are different in size, which causes the display panel PNL to display unevenly.

[0132] To solve the above problems, the embodiments of the present disclosure provide a pixel driving circuit PDC applied to a display panel PNL. Referring to FIG. 4, the pixel driving circuit PDC includes a driving transistor T6, a data writing sub-circuit SW1, a first reset sub-circuit SW2, a first light-emitting control sub-circuit SW5, a first energy storage sub-circuit CC1 and a light-emitting element.

[0133] The first end of the data write-in sub-circuit SW1 is electrically connected with the data voltage terminal, the second end of the data write-in sub-circuit SW1 is electrically connected with the second node N2, and the control end of the data write-in sub-circuit SW1 is electrically connected with the data write-in signal terminal; the data write-in sub-circuit SW1 is used for writing the data voltage Vdata into the second node N2 in response to the gating level of the data write-in signal G1; in an example, the data write-in sub-circuit SW1 can be electrically connected with the second node N2 through a capacitor, so that the data voltage Vdata is written into the second node N2 through the coupling effect of the capacitor. In another example, the data write-in sub-circuit SW1 can be directly electrically connected with the second node N2, so that the data voltage Vdata is directly written into the second node N2.

[0134] The first end of the first reset sub-circuit SW2 is electrically connected with the reference voltage terminal, the second end of the first reset sub-circuit SW2 is electrically connected with the second node N2, and the control end of the first reset sub-circuit SW2 is electrically connected with the first reset signal terminal; the first reset sub-circuit SW2 is used for loading the reference voltage Vref into the second node N2 in response to the gating level of the first reset signal G2, so as to reset the second node N2.

[0135] The first end of the first light-emitting control sub-circuit SW5 is electrically connected with the driving power voltage terminal, the second end of the first light-emitting control sub-circuit SW5 is electrically connected with the first end of the second light-emitting control sub-circuit SW6, and the control end of the first light-emitting control sub-circuit SW5 is electrically connected with the first light-emitting control signal terminal; the first light-emitting control sub-circuit SW5 is used for loading the driving power voltage VDD into the first electrode of the driving transistor T6 in response to the gating level of the first light-emitting control signal EM.

[0136] The driving transistor T6 is used for controlling the size of the driving current according to the voltage on the second node N2; the driving transistor T6 is an N-type transistor.

[0137] One end of the first energy storage sub-circuit CC1 is electrically connected with the second node N2, and the other end of the first energy storage sub-circuit CC1, the fourth node N4 and the light-emitting element are electrically connected with each other.

[0138] In this way, on the one hand, by setting the driving transistor T6 as an N-type transistor, the drain of the driving transistor T6 is electrically connected to the second terminal of the first light-emitting control sub-circuit SW5, and the source of the driving transistor T6 is electrically connected to the fourth node N4, so that in the light-emitting stage, the gate-source voltage of the driving transistor T6 is independent of the driving power supply voltage VDD, thereby achieving compensation for the driving power supply voltage VDD voltage drop. On the other hand, by turning on the driving transistor T6 and the first light-emitting control sub-circuit SW5, the driving power supply voltage VDD is loaded to the fourth node N4, and since the driving transistor T6 is an N-type transistor, the fourth node N4 is discharged until the driving transistor T6 is turned off, thereby achieving compensation of the threshold voltage of the driving transistor T6 to the fourth node N4, so as to reduce the difference between the driving currents of each sub-pixel and improve the display quality of the display panel PNL. In addition, by electrically connecting the second terminal of the data writing sub-circuit SW1 to the second node N2, and electrically connecting the second terminal of the first light-emitting control sub-circuit SW5 to the first electrode of the driving transistor T6, the threshold compensation stage and the data writing stage of the pixel driving circuit PDC can be performed independently, and the threshold compensation stage is no longer limited by the time length of the data writing stage, so as to more fully compensate the threshold voltage of the pixel driving circuit PDC, reduce the possibility of display unevenness of the display panel PNL, and further improve the display quality of the display panel PNL.

[0139] Referring to FIG. 5, when the threshold voltages of the driving transistor T6 are -1V, -0.5V, 0V, 0.5V and 1V respectively, the driving currents generated after threshold compensation of the driving transistor T6 are the same, thereby improving the display uniformity of the display panel PNL.

[0140] In an embodiment of the present disclosure, referring to FIG. 4, the first energy storage sub-circuit CC1 includes a first capacitor C1 and a second capacitor C2; and the pixel driving circuit PDC further includes a second reset sub-circuit SW4.

[0141] The first terminal of the first capacitor C1, the first terminal of the second capacitor C2 and the first node N1 are electrically connected to each other, the second terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the second capacitor C2 is electrically connected to the second node N2, so that the voltage of the first node N1 is coupled to the second node N2.

[0142] A first end of a second reset sub-circuit SW4 is electrically connected to any one of the second node N2, the initialization signal terminal, and the reference voltage terminal, a second end of the second reset sub-circuit SW4 is electrically connected to the first node N1, and a control end of the second reset sub-circuit SW4 is electrically connected to the second reset signal terminal; the second reset sub-circuit SW4 is configured to load any one of the reference voltage Vref and the initialization signal Vini to the first node N1 in response to a gating level of the second reset signal G4. In an example, referring to FIG. 4, the first end of the second reset sub-circuit SW4 is electrically connected to the second node N2; the second reset sub-circuit SW4 is configured to load the reference voltage Vref to the first node N1 in response to the gating level of the second reset signal G4. In another example, referring to FIG. 9, the first end of the second reset sub-circuit SW4 is electrically connected to the initialization signal terminal; the second reset sub-circuit SW4 is configured to load the initialization signal Vini to the first node N1 in response to the gating level of the second reset signal G4.

[0143] In an embodiment of the present disclosure, the first reset signal G2 and the second reset signal G4 can be the same signal, so as to simultaneously control the conduction and the cutoff of the first reset sub-circuit SW2 and the second reset sub-circuit SW4. In an example, the first reset signal G2 and the second reset signal G4 can be loaded on the same wire. In another example, the first reset signal G2 and the second reset signal G4 can be loaded on different wires.

[0144] It should be noted that, in the embodiment of the present disclosure, the reference voltage Vref and the initialization signal Vini are both constant voltages.

[0145] In an embodiment of the present disclosure, the first end of the second reset sub-circuit SW4 is electrically connected to the second node N2, the second end of the second reset sub-circuit SW4 is electrically connected to the first node N1, and the control end of the second reset sub-circuit SW4 is electrically connected to the second reset signal terminal.

[0146] In an embodiment of the present disclosure, the first end of the second reset sub-circuit SW4 is electrically connected to the reference voltage terminal, the second end of the second reset sub-circuit SW4 is electrically connected to the first node N1, and the control end of the second reset sub-circuit SW4 is electrically connected to the second reset signal terminal.

[0147] In an embodiment of the present disclosure, referring to FIG. 9, the first end of the second reset sub-circuit SW4 is electrically connected to the initialization signal terminal, the second end of the second reset sub-circuit SW4 is electrically connected to the first node N1, and the control end of the second reset sub-circuit SW4 is electrically connected to the second reset signal terminal.

[0148] In an embodiment of the present disclosure, referring to FIG. 13, the first energy storage sub-circuit CC1 only includes a first capacitor C1. A first terminal of the first capacitor C1 is electrically connected with the second node N2, and a second terminal of the first capacitor C1 is electrically connected with the fourth node N4. In this way, the number of capacitors in the pixel driving circuit PDC can be reduced, so as to reduce the occupied space of the pixel driving circuit PDC, and facilitate the thinning of the display panel PNL.

[0149] In an embodiment of the present disclosure, referring to FIG. 4, the pixel driving circuit PDC further includes a second energy storage sub-circuit CC2. One end of the second energy storage sub-circuit CC2 is electrically connected with the fourth node N4, and the other end is used to load a constant voltage V0. In this way, the fourth node N4 is electrically connected with the constant voltage V0 through the second energy storage sub-circuit CC2, so as to stabilize the voltage of the fourth node N4.

[0150] In an embodiment of the present disclosure, referring to FIG. 4, the second energy storage sub-circuit CC2 includes a third capacitor C3. A first terminal of the third capacitor C3 is used to load the constant voltage V0, and a second terminal of the third capacitor C3 is electrically connected with the fourth node N4. For example, the first terminal of the third capacitor C3 is directly electrically connected with the constant voltage terminal. For another example, the first terminal of the third capacitor C3 is electrically connected with the constant voltage terminal through at least one transistor.

[0151] In an embodiment of the present disclosure, referring to FIG. 4, the pixel driving circuit PDC further includes a third reset sub-circuit SW3. A first terminal of the third reset sub-circuit SW3 is electrically connected with an initialization signal terminal, a second terminal of the third reset sub-circuit SW3 is electrically connected with the third node N3, and a control terminal of the third reset sub-circuit SW3 is electrically connected with a third reset signal terminal; the third reset sub-circuit SW3 is used to load the initialization signal Vini to the third node N3 in response to the gating level of the third reset signal G3; the light emitting element is electrically connected with the third node N3. The first reset signal G2, the third reset signal G3, and the second reset signal G4 can be the same signal, so as to simultaneously control the conduction and the cut-off of the first reset sub-circuit SW2, the third reset sub-circuit SW3, and the second reset sub-circuit SW4. In an example, the first reset signal G2, the third reset signal G3, and the second reset signal G4 can be loaded on the same wire. In another example, the first reset signal G2, the third reset signal G3, and the second reset signal G4 can be loaded on different wires. In this way, the third node N3 is reset by turning on the third reset sub-circuit SW3.

[0152] In an embodiment of the present disclosure, referring to FIG. 4, the third reset sub-circuit SW3 includes a third reset transistor T3. A first electrode of the third reset transistor T3 is electrically connected to the initialization signal terminal, a second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected to each other, and a control electrode of the third reset transistor T3 is electrically connected to the third reset signal terminal; the third reset transistor T3 is configured to load the initialization signal Vini to the third node N3 in response to a gating level of the third reset signal G3. In other embodiments of the present disclosure, the third reset sub-circuit SW3 can include a plurality of third reset transistors T3 connected in series or in parallel.

[0153] In an embodiment of the present disclosure, the first reset signal G2, the third reset signal G3 and the second reset signal G4 are the same signal, so as to simultaneously control the conduction and the cutoff of the first reset sub-circuit SW2, the third reset sub-circuit SW3 and the second reset sub-circuit SW4. In an example, the first reset signal G2, the third reset signal G3 and the second reset signal G4 can be loaded on the same wire. In another example, the first reset signal G2, the third reset signal G3 and the second reset signal G4 can be loaded on different wires.

[0154] In an embodiment of the present disclosure, the first reset signal G2 and the second reset signal G4 are the same signal, so as to simultaneously control the conduction and the cutoff of the first reset sub-circuit SW2 and the second reset sub-circuit SW4.

[0155] In an embodiment of the present disclosure, referring to FIG. 4, the pixel driving circuit PDC further includes a second light emitting control sub-circuit SW6. A first end of the second light emitting control sub-circuit SW6 is electrically connected to the fourth node N4, a second end of the second light emitting control sub-circuit SW6, the light emitting element and the third node N3 are electrically connected to each other, and a control end of the second light emitting control sub-circuit SW6 is electrically connected to the second light emitting control signal terminal; the second light emitting control sub-circuit SW6 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to a gating level of the second light emitting control signal EM2. By turning on the second light emitting control sub-circuit SW6, on the one hand, the initialization signal Vini can be loaded to the fourth node N4 to reset the fourth node N4; on the other hand, in the light emitting stage, the driving current generated by the driving transistor T6 can be loaded to the third node N3 to make the light emitting element emit light.

[0156] In an embodiment of the present disclosure, referring to FIG. 4, the second light-emitting control sub-circuit SW6 comprises a second light-emitting control transistor T7. The first electrode of the second light-emitting control transistor T7 is electrically connected with the fourth node N4, the second electrode of the second light-emitting control transistor T7, the light-emitting element and the third node N3 are electrically connected with each other, and the control electrode of the second light-emitting control transistor T7 is electrically connected with the second light-emitting control signal end. The second light-emitting control transistor T7 is used to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the second light-emitting control signal EM2. In other embodiments of the present disclosure, the second light-emitting control sub-circuit SW6 can further comprise a plurality of second light-emitting control transistors T7 connected in series or in parallel.

[0157] In an embodiment of the present disclosure, referring to FIG. 4, the pixel driving circuit PDC further comprises a third capacitor C3; the first end of the third capacitor C3 is used to load a constant voltage V0, and the second end is electrically connected with the fourth node N4.

[0158] The data writing sub-circuit SW1 comprises a data writing transistor T1. The first electrode of the data writing transistor T1 is electrically connected with the data voltage end, the second electrode of the data writing transistor T1 is electrically connected with the first node N1, and the control electrode of the data writing transistor T1 is electrically connected with the data writing signal end; the data writing transistor T1 is used to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. In other embodiments of the present disclosure, the data writing sub-circuit SW1 can further comprise a plurality of data writing transistors T1 connected in series or in parallel.

[0159] The first reset sub-circuit SW2 comprises a first reset transistor T2. The first electrode of the first reset transistor T2 is electrically connected with the reference voltage end, the second electrode of the first reset transistor T2 is electrically connected with the second node N2, and the control electrode of the first reset transistor T2 is electrically connected with the first reset signal end; the first reset transistor T2 is used to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2, so as to reset the second node N2. In other embodiments of the present disclosure, the first reset sub-circuit SW2 can further comprise a plurality of first reset transistors T2 connected in series or in parallel.

[0160] The second reset sub-circuit SW4 includes a second reset transistor T4. A first electrode of the second reset transistor T4 is electrically connected with the second node N2, a second electrode of the second reset transistor T4 is electrically connected with the first node N1, and a control electrode of the second reset transistor T4 is electrically connected with a second reset signal terminal. The second reset transistor T4 is configured to load a voltage of the second node N2 to the first node N1 in response to a gating level of the second reset signal G4, so as to reset the first node N1. In some embodiments of the present disclosure, the second reset sub-circuit SW4 can further include a plurality of second reset transistors T4 connected in series or in parallel.

[0161] The first light emitting control sub-circuit SW5 includes a first light emitting control transistor T5. A first electrode of the first light emitting control transistor T5 is electrically connected with the driving power supply voltage terminal, a second electrode of the first light emitting control transistor T5 is electrically connected with a first electrode of the driving transistor T6, and a control electrode of the first light emitting control transistor T5 is electrically connected with a first light emitting control signal terminal. The first light emitting control transistor T5 is configured to load the driving power supply voltage VDD to the first electrode of the driving transistor T6 in response to a gating level of the first light emitting control signal EM. In some embodiments of the present disclosure, the first light emitting control sub-circuit SW5 can further include a plurality of first light emitting control transistors T5 connected in series or in parallel.

[0162] In some embodiments of the present disclosure, the second reset sub-circuit SW4 includes a second reset transistor T4.

[0163] A first electrode of the second reset transistor T4 is electrically connected with the second node N2, a second electrode of the second reset transistor T4 is electrically connected with the first node N1, and a control electrode of the second reset transistor T4 is electrically connected with a second reset signal terminal.

[0164] In some embodiments of the present disclosure, a first electrode of the second reset transistor T4 is electrically connected with a reference voltage terminal, a second electrode of the second reset transistor T4 is electrically connected with the first node N1, and a control electrode of the second reset transistor T4 is electrically connected with a second reset signal terminal.

[0165] In some embodiments of the present disclosure, referring to FIG. 9, a first electrode of the second reset transistor T4 is electrically connected with an initialization signal terminal, a second electrode of the second reset transistor T4 is electrically connected with the first node N1, and a control electrode of the second reset transistor T4 is electrically connected with a second reset signal terminal.

[0166] In some embodiments of the present disclosure, the pixel driving circuit PDC further includes a third reset sub-circuit SW3 and a second light emitting control sub-circuit SW6.

[0167] The third reset sub-circuit SW3 includes a third reset transistor T3. A first electrode of the third reset transistor T3 is electrically connected with the initialization signal terminal, a second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected with each other, and a control electrode of the third reset transistor T3 is electrically connected with the third reset signal terminal.

[0168] The second light emitting control sub-circuit SW6 includes a second light emitting control transistor T7. A first electrode of the second light emitting control transistor T7 is electrically connected with the fourth node N4, a second electrode of the second light emitting control transistor T7, the light emitting element and the third node N3 are electrically connected with each other, and a control electrode of the second light emitting control transistor T7 is electrically connected with the second light emitting control signal terminal.

[0169] In an embodiment of the present disclosure, referring to FIG. 10, the pixel driving circuit PDC does not include the third capacitor C3, and further includes a third reset transistor T3. A first electrode of the third reset transistor T3 is electrically connected with the initialization signal terminal, a second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected with each other, and a control electrode of the third reset transistor T3 is electrically connected with the third reset signal terminal. The third node N3 and the fourth node N4 are the same node. In this way, the number of transistors and capacitors in the pixel driving circuit PDC can be reduced, so as to reduce the occupied space of the pixel driving circuit PDC, and facilitate the thinning of the display panel PNL.

[0170] In an embodiment of the present disclosure, referring to FIG. 13, the pixel driving circuit PDC does not include the second reset sub-circuit SW4. The first energy storage sub-circuit CC1 includes only the first capacitor C1. A first end of the first capacitor C1 is electrically connected with the second node N2, and a second end of the first capacitor C1 is electrically connected with the fourth node N4. The first node N1 and the second node N2 are the same node. In this way, the number of transistors and capacitors in the pixel driving circuit PDC can be reduced, so as to reduce the occupied space of the pixel driving circuit PDC, and facilitate the thinning of the display panel PNL.

[0171] In an embodiment of the present disclosure, the pixel driving circuit PDC does not include the second capacitor C2 and the second reset transistor T4. The first node N1 and the second node N2 are the same node. In this way, the number of transistors and capacitors in the pixel driving circuit PDC can be reduced, so as to reduce the occupied space of the pixel driving circuit PDC, and facilitate the thinning of the display panel PNL.

[0172] In an embodiment of the present disclosure, the constant voltage V0 is any one of the driving power supply voltage VDD, the reference voltage Vref, and the initialization signal Vini, so as to stabilize the fourth node N4 by the third capacitor C3. In an example, the constant voltage V0 is the driving power supply voltage VDD. In another example, the constant voltage V0 is the reference voltage Vref. In other examples, the constant voltage V0 is the initialization signal Vini.

[0173] In an embodiment of the present disclosure, the material of the channel region of at least one transistor is metal oxide semiconductor material. For example, the material of the channel region of the data writing transistor T1, the first reset transistor T2, and the second reset transistor T4 is metal oxide semiconductor material, so as to prevent the data writing transistor T1, the first reset transistor T2, and the second reset transistor T4 from leaking current, facilitate normal light emission of the light emitting element, and improve the display quality of the display panel PNL. For another example, the material of the channel region of the driving transistor T6 is metal oxide semiconductor material, so as to reduce the electron mobility of the driving transistor T6 and improve the low gray scale quality of the display panel PNL. In an example, the material of the channel region of all the transistors is metal oxide semiconductor material. In an embodiment of the present disclosure, the metal oxide semiconductor material can be indium gallium zinc oxide (IGZO) or the like.

[0174] In an embodiment of the present disclosure, the display area AA of the display panel PNL has a plurality of pixel driving circuit rows arranged in an array, and at least two pixel driving circuits PDC in the same pixel driving circuit row share one first light emitting control sub-circuit SW5. The first light emitting control sub-circuit SW5 includes a first light emitting control transistor T5. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel share one first light emitting control transistor T5. On the one hand, the number of transistors can be reduced; on the other hand, the display uniformity of the display panel PNL can be improved by controlling the sub-pixels to emit light at the same time. In other embodiments of the present disclosure, the SW can also include a plurality of first light emitting control transistors T5 connected in series or in parallel.

[0175] The pixel driving circuit PDC provided by the present disclosure is further described below through seven examples.

[0176] In the first example, referring to FIG. 6, the pixel driving circuit PDC includes a data writing transistor T1, a second light emitting control transistor T7, and a first capacitor C1, a third capacitor C3, and a light emitting element. The first electrode of the data writing transistor T1 is electrically connected to a data voltage terminal, the second electrode of the data writing transistor T1 is electrically connected to a first node N1, and the control electrode of the data writing transistor T1 is electrically connected to a data writing signal terminal. The data writing transistor T1 is configured to load a data voltage Vdata to the first node N1 in response to a gating level of a data writing signal G1. The first electrode of a first reset transistor T2 is electrically connected to a reference voltage terminal, the second electrode of the first reset transistor T2 is electrically connected to a second node N2, and the control electrode of the first reset transistor T2 is electrically connected to a first reset signal terminal. The first reset transistor T2 is configured to load a reference voltage Vref to the second node N2 in response to a gating level of a first reset signal G2. The first electrode of a third reset transistor T3 is electrically connected to an initialization signal terminal, the second electrode of the third reset transistor T3, the light emitting element, and the third node N3 are electrically connected to each other, and the control electrode of the third reset transistor T3 is electrically connected to the first reset signal terminal. The third reset transistor T3 is configured to load an initialization signal Vini to the third node N3 in response to a gating level of the first reset signal G2. The first electrode of a second reset transistor T4 is electrically connected to the second node N2, the second electrode of the second reset transistor T4 is electrically connected to the first node N1, and the control electrode of the second reset transistor T4 is electrically connected to the first reset signal terminal. The second reset transistor T4 is configured to load the voltage of the second node N2 to the first node N1 in response to a gating level of the first reset signal G2. The first electrode of a first light emitting control transistor T5 is electrically connected to a driving power voltage terminal, the second electrode of the first light emitting control transistor T5 is electrically connected to the first electrode of a driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected to a first light emitting control signal terminal. The first light emitting control transistor T5 is configured to load a driving power voltage VDD to the first electrode of the driving transistor T6 in response to a gating level of a first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected to the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected to a fourth node N4, and the control electrode of the driving transistor T6 is electrically connected to the second node N2. The driving transistor T6 is configured to control the size of a driving current according to the voltage of the second node N2. The first electrode of a second light emitting control transistor T7 is electrically connected to the fourth node N4, the second electrode of the second light emitting control transistor T7, the light emitting element, and the third node N3 are electrically connected to each other, and the control electrode of the second light emitting control transistor T7 is electrically connected to a second light emitting control signal terminal. The second light emitting control transistor T7 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to a gating level of a second light emitting control signal EM2.The first end of the first capacitor C1, the first end of the second capacitor C2 and the first node N1 are electrically connected to each other, the second end of the first capacitor C1, the second end of the third capacitor C3 and the fourth node N4 are electrically connected to each other; the second end of the second capacitor C2 is electrically connected to the second node N2; and the first end of the third capacitor C3 is used to load the constant voltage V0.

[0177] The driving method of the pixel driving circuit PDC in the example is exemplarily described as follows by taking the pixel driving circuit PDC shown in FIG. 6 as an example and referring to the timing diagram shown in FIG. 7.

[0178] In the P1 stage (reset stage), referring to FIG. 7 and FIG. 8-1, the pixel driving circuit PDC is loaded with the gating level of the first reset signal G2 and the second emission control signal EM2, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4 and the second emission control transistor T7 are turned on; the reference voltage Vref is loaded to the first node N1 and the second node N2, so that the driving transistor T6 is turned on; the initialization signal Vini is loaded to the third node N3 and the fourth node N4, so as to reset the first node N1, the second node N2, the third node N3 and the fourth node N4. The pixel driving circuit PDC is loaded with the data write signal G1 and the cutoff level of the first emission control signal EM, so that the data write transistor T1 and the first emission control transistor T5 are cut off.

[0179] In the P2 stage (threshold compensation stage), referring to FIG. 7 and FIG. 8-2, the pixel driving circuit PDC is loaded with the gating level of the first reset signal G2 and the first emission control signal EM, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4 and the first emission control transistor T5 are turned on; the pixel driving circuit PDC is loaded with the data write signal G1 and the cutoff level of the second emission control signal EM2, so that the data write transistor T1 and the second emission control transistor T7 are cut off. Then the reference voltage Vref is loaded to the first node N1 and the second node N2, so as to reset the first node N1 and the second node N2, and the driving transistor T6 is turned on; the driving power voltage VDD is loaded to the fourth node N4, so that when the voltage of the fourth node N4 is discharged to Vref-Vth, the driving transistor T6 is just cut off, and the voltage of the fourth node N4 is locked, so as to realize the threshold voltage compensation of the driving transistor T6 to the fourth node N4; at the same time, the initialization signal Vini is loaded to the third node N3, so as to reset the third node N3.

[0180] In the P3 stage (data writing stage), referring to FIG. 7 and FIG. 8-3, the gate of the pixel driving circuit PDC is loaded with a gate-on level of the data writing signal G1, so that the data writing transistor T1 is turned on; the gate of the pixel driving circuit PDC is loaded with an off level of the first reset signal G2, the first emission control signal EM and the second emission control signal EM2, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4, the first emission control transistor T5 and the second emission control transistor T7 are turned off. Then the data voltage Vdata is written into the first node N1, and the voltage of the second node N2 is also the data voltage Vdata due to the coupling effect of the second capacitor C2; the voltage of the fourth node N4 is (Vdata-Vref)*[C1 / (C1+C3)]+Vref-Vth due to the coupling effect of the first capacitor C1 and the third capacitor C3; and Vgs=[C3 / (C1+C3)]*(Vdata-Vref)+Vth.

[0181] In the P4 stage (emission stage), referring to FIG. 7 and FIG. 8-4, the gate of the pixel driving circuit PDC is loaded with a gate-on level of the first emission control signal EM and the second emission control signal EM2, so that the first emission control transistor T5 and the second emission control transistor T7 are turned on; the gate of the pixel driving circuit PDC is loaded with an off level of the data writing signal G1 and the first reset signal G2, so that the data writing transistor T1, the first reset transistor T2, the third reset transistor T3 and the second reset transistor T4 are turned off. The driving transistor T6 is turned on due to the bootstrap of the second capacitor C2, so that the driving current I=K*(Vgs-Vth)^2=K*{[C3 / (C1+C3)]*(Vdata-Vref)}^2. Wherein, K is a constant. The driving current in the above formula is irrelevant to the driving power voltage VDD and Vth, thereby solving the problem of the voltage drop of the driving power voltage VDD and the drift of Vth, so as to more fully compensate the threshold of the driving transistor T6 and improve the display quality of the display panel PNL.

[0182] It should be noted that in this example, each transistor is an N-type transistor. The gate-on level of each signal is high, and the off level of each signal is low. Vgs is the gate-source voltage difference of the driving transistor T6, and Vth is the threshold voltage of the driving transistor T6.

[0183] In the second example, referring to FIG. 9, the pixel driving circuit PDC includes a data writing transistor T1~a second light emitting control transistor T7, and a first capacitor C1~a third capacitor C3, a light emitting element. The first electrode of the data writing transistor T1 is electrically connected with a data voltage terminal, the second electrode of the data writing transistor T1 is electrically connected with a first node N1, and the control electrode of the data writing transistor T1 is electrically connected with a data writing signal terminal; the data writing transistor T1 is used to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. The first electrode of the first reset transistor T2 is electrically connected with a reference voltage terminal, the second electrode of the first reset transistor T2 is electrically connected with a second node N2, and the control electrode of the first reset transistor T2 is electrically connected with a first reset signal terminal; the first reset transistor T2 is used to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2. The first electrode of the third reset transistor T3 is electrically connected with an initialization signal terminal, the second electrode of the third reset transistor T3, the light emitting element, and the third node N3 are electrically connected with each other, and the control electrode of the third reset transistor T3 is electrically connected with the first reset signal terminal; the third reset transistor T3 is used to load the initialization signal Vini to the third node N3 in response to the gating level of the first reset signal G2. The first electrode of the second reset transistor T4 is electrically connected with the initialization signal terminal, the second electrode of the second reset transistor T4 is electrically connected with the first node N1, and the control electrode of the second reset transistor T4 is electrically connected with the first reset signal terminal; the second reset transistor T4 is used to load the initialization signal Vini to the first node N1 in response to the gating level of the first reset signal G2. The first electrode of the first light emitting control transistor T5 is electrically connected with a driving power voltage terminal, the second electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected with a first light emitting control signal terminal. The first light emitting control transistor T5 is used to load the driving power voltage VDD to the first electrode of the driving transistor T6 in response to the gating level of the first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected with the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected with a fourth node N4, and the control electrode of the driving transistor T6 is electrically connected with the second node N2; the driving transistor T6 is used to control the size of the driving current according to the voltage of the second node N2. The first electrode of the second light emitting control transistor T7 is electrically connected with the fourth node N4, the second electrode of the second light emitting control transistor T7, the light emitting element, and the third node N3 are electrically connected with each other, and the control electrode of the second light emitting control transistor T7 is electrically connected with a second light emitting control signal terminal. The second light emitting control transistor T7 is used to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the second light emitting control signal EM2.The first end of the first capacitor C1, the first end of the second capacitor C2 and the first node N1 are electrically connected to each other, the second end of the first capacitor C1, the second end of the third capacitor C3 and the fourth node N4 are electrically connected to each other; the second end of the second capacitor C2 is electrically connected to the second node N2; and the first end of the third capacitor C3 is used for loading a constant voltage V0.

[0184] The driving timing diagram of this example is the same as that of the first example.

[0185] It should be noted that in this example, each transistor is an N-type transistor. The gating voltage of each signal is high, and the cutoff voltage of each signal is low.

[0186] In a third example, referring to FIG. 10, the pixel driving circuit PDC includes data writing transistor T1~driving transistor T6, and first capacitor C1, second capacitor C2, light emitting element. Among them, the first electrode of the data writing transistor T1 is electrically connected with the data voltage end, the second electrode of the data writing transistor T1 is electrically connected with the first node N1, and the control electrode of the data writing transistor T1 is electrically connected with the data writing signal end; the data writing transistor T1 is used to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. The first electrode of the first reset transistor T2 is electrically connected with the reference voltage end, the second electrode of the first reset transistor T2 is electrically connected with the second node N2, and the control electrode of the first reset transistor T2 is electrically connected with the first reset signal end; the first reset transistor T2 is used to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2. The first electrode of the third reset transistor T3 is electrically connected with the initialization signal end, the second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected with each other, and the control electrode of the third reset transistor T3 is electrically connected with the third reset signal end; the third reset transistor T3 is used to load the initialization signal Vini to the third node N3 in response to the gating level of the third reset signal G3. The first electrode of the second reset transistor T4 is electrically connected with the initialization signal end, the second electrode of the second reset transistor T4 is electrically connected with the first node N1, and the control electrode of the second reset transistor T4 is electrically connected with the first reset signal end; the second reset transistor T4 is used to load the initialization signal Vini to the first node N1 in response to the gating level of the first reset signal G2. The first electrode of the first light emitting control transistor T5 is electrically connected with the driving power voltage end, the second electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected with the first light emitting control signal end. The first light emitting control transistor T5 is used to load the driving power voltage VDD to the first electrode of the driving transistor T6 in response to the gating level of the first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected with the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected with the fourth node N4, and the control electrode of the driving transistor T6 is electrically connected with the second node N2; the driving transistor T6 is used to control the size of the driving current according to the voltage of the second node N2. The first end of the first capacitor C1, the first end of the second capacitor C2 and the first node N1 are electrically connected with each other, the second end of the first capacitor C1 is electrically connected with the fourth node N4; the second end of the second capacitor C2 is electrically connected with the second node N2. The third node N3 and the fourth node N4 are the same node.

[0187] As follows, taking the pixel driving circuit PDC shown in FIG. 10 as an example, referring to the timing diagram shown in FIG. 11, the driving method of the pixel driving circuit PDC of this example is exemplarily described.

[0188] In the P1 stage (reset stage), referring to FIG. 11 and FIG. 12-1, the first reset signal G2 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the gate-on level, so that the first reset transistor T2, the third reset transistor T3 and the second reset transistor T4 are turned on; the reference voltage Vref is loaded to the first node N1 and the second node N2, so that the driving transistor T6 is turned on; the initialization signal Vini is loaded to the third node N3 and the fourth node N4, so as to reset the first node N1, the second node N2, the third node N3 and the fourth node N4. The data write signal G1 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-off level, so that the data write transistor T1 and the first emission control transistor T5 are turned off.

[0189] In the P2 stage (threshold compensation stage), referring to FIG. 11 and FIG. 12-2, the first reset signal G2 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-on level, so that the first reset transistor T2, the second reset transistor T4 and the first emission control transistor T5 are turned on; the data write signal G1 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the gate-off level, so that the data write transistor T1 and the third reset transistor T3 are turned off. Then the reference voltage Vref is loaded to the first node N1 and the second node N2, so as to reset the first node N1 and the second node N2, and the driving transistor T6 is turned on; the driving power voltage VDD is loaded to the third node N3 and the fourth node N4, so that the voltage of the third node N3 and the fourth node N4 is discharged to Vref-Vth, and the driving transistor T6 is just turned off, and the voltage of the third node N3 and the fourth node N4 is locked, so as to realize the threshold voltage compensation of the driving transistor T6 to the fourth node N4.

[0190] In the P3 stage (data write stage), referring to FIG. 11 and FIG. 12-3, the data write signal G1 is loaded to the pixel driving circuit PDC at the gate-on level, so that the data write transistor T1 is turned on; the first reset signal G2, the third reset signal G3 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-off level, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4 and the first emission control transistor T5 are turned off. Then the data voltage Vdata is written to the first node N1, and the voltage of the second node N2 is also the data voltage Vdata through the coupling effect of the second capacitor C2; the voltage of the fourth node N4 is (Vdata-Vref)*[C1 / (C1+C2)]+Vref-Vth through the coupling effect of the first capacitor C1 and C2; Vgs=[C1 / (C1+C2)]*Vdata+Vref-Vth; and the driving transistor T6 is turned off. 发 发 发 发 ​​​(Vdata-Vref)+Vth. Wherein, C 发 is the capacitance of the light emitting element.

[0191] In the P4 stage (light emitting stage), referring to FIG. 11 and FIG. 12-4, the first light emitting control signal EM is loaded with a gating level to the pixel driving circuit PDC, so that the first light emitting control transistor T5 is turned on; the data write signal G1, the first reset signal G2, and the third reset signal G3 are loaded with an off level to the pixel driving circuit PDC, so that the data write transistor T1, the first reset transistor T2, the third reset transistor T3, and the second reset transistor T4 are turned off. Due to the self-boosting of the second capacitor C2, the driving transistor T6 is turned on, so the driving current I=K*(Vgs-Vth)^2=K*{[C 发 / (C1+C 发 )]*(Vdata-Vref)}^2. Wherein, K is a constant. In the above formula, the driving current is irrelevant to the driving power voltage VDD and Vth, thereby solving the problem of the voltage drop of the driving power voltage VDD and the Vth drift, so as to more fully compensate the threshold of the driving transistor T6, and improve the display quality of the display panel PNL.

[0192] It should be noted that in this example, each transistor is an N-type transistor. The gating level of each signal is high, and the off level of each signal is low. Vgs is the gate-source voltage difference of the driving transistor T6, and Vth is the threshold voltage of the driving transistor T6.

[0193] In the fourth example, referring to FIG. 13, the pixel driving circuit PDC includes a data writing transistor T1~a third reset transistor T3, a first light emitting control transistor T5~a second light emitting control transistor T7, and a first capacitor C1, a third capacitor C3, and a light emitting element. The first electrode of the data writing transistor T1 is electrically connected with a data voltage terminal, the second electrode of the data writing transistor T1 is electrically connected with a first node N1, and the control electrode of the data writing transistor T1 is electrically connected with a data writing signal terminal; the data writing transistor T1 is configured to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. The first electrode of the first reset transistor T2 is electrically connected with a reference voltage terminal, the second electrode of the first reset transistor T2 is electrically connected with a second node N2, and the control electrode of the first reset transistor T2 is electrically connected with a first reset signal terminal; the first reset transistor T2 is configured to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2. The first electrode of the third reset transistor T3 is electrically connected with an initialization signal terminal, the second electrode of the third reset transistor T3, the light emitting element, and the third node N3 are electrically connected with each other, and the control electrode of the third reset transistor T3 is electrically connected with the first reset signal terminal; the third reset transistor T3 is configured to load the initialization signal Vini to the third node N3 in response to the gating level of the first reset signal G2. The first electrode of the first light emitting control transistor T5 is electrically connected with a driving power voltage terminal, the second electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of a driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected with a first light emitting control signal terminal. The first light emitting control transistor T5 is configured to load the driving power voltage VDD to the first electrode of the driving transistor T6 in response to the gating level of the first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected with the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected with a fourth node N4, and the control electrode of the driving transistor T6 is electrically connected with the second node N2; the driving transistor T6 is configured to control the size of the driving current according to the voltage of the second node N2. The first electrode of the second light emitting control transistor T7 is electrically connected with the fourth node N4, the second electrode of the second light emitting control transistor T7, the light emitting element, and the third node N3 are electrically connected with each other, and the control electrode of the second light emitting control transistor T7 is electrically connected with a second light emitting control signal terminal. The second light emitting control transistor T7 is configured to make the third node N3 and the fourth node N4 communicate with each other in response to the gating level of the second light emitting control signal EM2. The first terminal of the first capacitor C1 is electrically connected with the first node N1, the second terminal of the first capacitor C1, the second terminal of the third capacitor C3, and the fourth node N4 are electrically connected with each other; the first terminal of the third capacitor C3 is configured to load the constant voltage V0. The first node N1 and the second node N2 are the same node.

[0194] The driving timing chart of this example is the same as that of the first example.

[0195] Note that in this example, each of the transistors is an N-type transistor. The on voltage of each signal is high, and the off voltage of each signal is low.

[0196] In the fifth example, referring to FIG. 14, the pixel driving circuit PDC includes data writing transistor T1~driving transistor T6, and first capacitor C1, second capacitor C2, light emitting element. Among them, the first electrode of the data writing transistor T1 is electrically connected with the data voltage end, the second electrode of the data writing transistor T1 is electrically connected with the first node N1, and the control electrode of the data writing transistor T1 is electrically connected with the data writing signal end; the data writing transistor T1 is used to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. The first electrode of the first reset transistor T2 is electrically connected with the reference voltage end, the second electrode of the first reset transistor T2 is electrically connected with the second node N2, and the control electrode of the first reset transistor T2 is electrically connected with the first reset signal end; the first reset transistor T2 is used to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2. The first electrode of the third reset transistor T3 is electrically connected with the initialization signal end, the second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected with each other, and the control electrode of the third reset transistor T3 is electrically connected with the third reset signal end; the third reset transistor T3 is used to load the initialization signal Vini to the third node N3 in response to the gating level of the third reset signal G3. The first electrode of the second reset transistor T4 is electrically connected with the initialization signal end, the second electrode of the second reset transistor T4 is electrically connected with the first node N1, and the control electrode of the second reset transistor T4 is electrically connected with the first reset signal end; the second reset transistor T4 is used to load the initialization signal Vini to the first node N1 in response to the gating level of the first reset signal G2. The first electrode of the first light emitting control transistor T5 is electrically connected with the driving power voltage end, the second electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected with the first light emitting control signal end. The first light emitting control transistor T5 is used to load the driving power voltage VDD to the first electrode of the driving transistor T6 in response to the gating level of the first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected with the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected with the fourth node N4, and the control electrode of the driving transistor T6 is electrically connected with the second node N2; the driving transistor T6 is used to control the size of the driving current according to the voltage of the second node N2. The first end of the first capacitor C1, the first end of the second capacitor C2 and the first node N1 are electrically connected with each other, the second end of the first capacitor C1 is electrically connected with the fourth node N4; the second end of the second capacitor C2 is electrically connected with the second node N2. The third node N3 and the fourth node N4 are the same node.

[0197] As follows, taking the pixel driving circuit PDC shown in FIG. 14 as an example, referring to the timing diagram shown in FIG. 15, the driving method of the pixel driving circuit PDC of this example is exemplarily described.

[0198] In the P1 stage (reset stage), referring to FIG. 14 and FIG. 15, the first reset signal G2 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the gate-on level, so that the first reset transistor T2, the third reset transistor T3 and the second reset transistor T4 are turned on; the reference voltage Vref is loaded to the first node N1 and the second node N2, so that the driving transistor T6 is turned on; the initialization signal Vini is loaded to the third node N3 and the fourth node N4, so as to reset the first node N1, the second node N2, the third node N3 and the fourth node N4. The data write signal G1 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-off level, so that the data write transistor T1 and the first emission control transistor T5 are turned off.

[0199] In the P2 stage (threshold compensation stage), referring to FIG. 14 and FIG. 15, the first reset signal G2 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-on level, so that the first reset transistor T2, the second reset transistor T4 and the first emission control transistor T5 are turned on; the data write signal G1 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the gate-off level, so that the data write transistor T1 and the third reset transistor T3 are turned off. Then the reference voltage Vref is loaded to the first node N1 and the second node N2, so as to reset the first node N1 and the second node N2, and the driving transistor T6 is turned on; the driving power voltage VDD is loaded to the third node N3 and the fourth node N4, so that when the voltage of the third node N3 and the fourth node N4 is discharged to Vref-Vth, the driving transistor T6 is just turned off, and the voltage of the third node N3 and the fourth node N4 is locked, so as to realize the threshold voltage compensation of the driving transistor T6 to the fourth node N4.

[0200] In the P3 stage (data write stage), referring to FIG. 14 and FIG. 15, the data write signal G1 is loaded to the pixel driving circuit PDC at the gate-on level, so that the data write transistor T1 is turned on; the first reset signal G2, the third reset signal G3 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-off level, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4 and the first emission control transistor T5 are turned off. Then the data voltage Vdata is written to the first node N1, and the voltage of the second node N2 is also the data voltage Vdata through the coupling effect of the second capacitor C2; the voltage of the fourth node N4 is (Vdata-Vref)*[C1 / (C1+C2)]+Vref-Vth through the coupling effect of the first capacitor C1 and the second capacitor C2; Vgs=[C1 / (C1+C2)]*Vdata+Vref-Vth; Vth=Vth0+Vgs. 发 发 发 发 ​​​(Vdata-Vref)+Vth. Wherein, C 发 is the capacitance of the light emitting element.

[0201] In the P4 stage (light emitting stage), referring to FIG. 14 and FIG. 15, the first light emitting control signal EM is loaded with a gating level to the pixel driving circuit PDC, so that the first light emitting control transistor T5 is turned on; the data write signal G1, the first reset signal G2, and the third reset signal G3 are loaded with an off level to the pixel driving circuit PDC, so that the data write transistor T1, the first reset transistor T2, the third reset transistor T3, and the second reset transistor T4 are turned off. Due to the self-boosting of the second capacitor C2, the driving transistor T6 is turned on, so the driving current I=K*(Vgs-Vth)^2=K*{[C 发 / (C1+C 发 )]*(Vdata-Vref)}^2. Wherein, K is a constant. In the above formula, the driving current is irrelevant to the driving power voltage VDD and Vth, thereby solving the problem of the voltage drop of the driving power voltage VDD and the Vth drift, so as to more fully compensate the threshold of the driving transistor T6, and improve the display quality of the display panel PNL.

[0202] It should be noted that in this example, except that the first light emitting control transistor T5 is a P-type transistor, the rest of the transistors are N-type transistors. The gating level of the data write signal G1, the first reset signal G2, and the third reset signal G3 is high, and the off level of the data write signal G1, the first reset signal G2, and the third reset signal G3 is low. The gating level of the first light emitting control signal EM is low, and the off level of the first light emitting control signal EM is high. Vgs is the gate-source voltage difference of the driving transistor T6, and Vth is the threshold voltage of the driving transistor T6.

[0203] In the sixth example, referring to FIG. 16, the pixel driving circuit PDC includes data writing transistor T1~driving transistor T6, and first capacitor C1, second capacitor C2, light emitting element. Among them, the first electrode of the data writing transistor T1 is electrically connected with the data voltage end, the second electrode of the data writing transistor T1 is electrically connected with the first node N1, and the control electrode of the data writing transistor T1 is electrically connected with the data writing signal end; the data writing transistor T1 is used to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. The first electrode of the first reset transistor T2 is electrically connected with the reference voltage end, the second electrode of the first reset transistor T2 is electrically connected with the second node N2, and the control electrode of the first reset transistor T2 is electrically connected with the first reset signal end; the first reset transistor T2 is used to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2. The first electrode of the third reset transistor T3 is electrically connected with the initialization signal end, the second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected with each other, and the control electrode of the third reset transistor T3 is electrically connected with the third reset signal end; the third reset transistor T3 is used to load the initialization signal Vini to the third node N3 in response to the gating level of the third reset signal G3. The first electrode of the second reset transistor T4 is electrically connected with the initialization signal end, the second electrode of the second reset transistor T4 is electrically connected with the first node N1, and the control electrode of the second reset transistor T4 is electrically connected with the first reset signal end; the second reset transistor T4 is used to load the initialization signal Vini to the first node N1 in response to the gating level of the first reset signal G2. The first electrode of the first light emitting control transistor T5 is electrically connected with the driving power voltage end, the second electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected with the first light emitting control signal end. The first light emitting control transistor T5 is used to load the driving power voltage VDD to the first electrode of the driving transistor T6 in response to the gating level of the first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected with the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected with the fourth node N4, and the control electrode of the driving transistor T6 is electrically connected with the second node N2; the driving transistor T6 is used to control the size of the driving current according to the voltage of the second node N2. The first end of the first capacitor C1, the first end of the second capacitor C2 and the first node N1 are electrically connected with each other, the second end of the first capacitor C1 is electrically connected with the fourth node N4; the second end of the second capacitor C2 is electrically connected with the second node N2. The third node N3 and the fourth node N4 are the same node.

[0204] As follows, taking the pixel driving circuit PDC shown in FIG. 16 as an example, referring to the timing diagram shown in FIG. 17, the driving method of the pixel driving circuit PDC of this example is exemplarily described.

[0205] In the P1 stage (reset stage), referring to FIG. 16 and FIG. 17, the first reset signal G2 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the gate-on level, so that the first reset transistor T2, the third reset transistor T3 and the second reset transistor T4 are turned on; the reference voltage Vref is loaded to the first node N1 and the second node N2, so that the driving transistor T6 is turned on; the initialization signal Vini is loaded to the third node N3 and the fourth node N4, so as to reset the first node N1, the second node N2, the third node N3 and the fourth node N4. The data write signal G1 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-off level, so that the data write transistor T1 and the first emission control transistor T5 are turned off.

[0206] In the P2 stage (threshold compensation stage), referring to FIG. 16 and FIG. 17, the first reset signal G2 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-on level, so that the first reset transistor T2, the second reset transistor T4 and the first emission control transistor T5 are turned on; the data write signal G1 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the gate-off level, so that the data write transistor T1 and the third reset transistor T3 are turned off. Then the reference voltage Vref is loaded to the first node N1 and the second node N2, so as to reset the first node N1 and the second node N2, and the driving transistor T6 is turned on; the driving power voltage VDD is loaded to the third node N3 and the fourth node N4, so that when the voltage of the third node N3 and the fourth node N4 is discharged to Vref-Vth, the driving transistor T6 is just turned off, and the voltage of the third node N3 and the fourth node N4 is locked, so as to realize the threshold voltage compensation of the driving transistor T6 to the fourth node N4.

[0207] In the P3 stage (data write stage), referring to FIG. 16 and FIG. 17, the data write signal G1 is loaded to the pixel driving circuit PDC at the gate-on level, so that the data write transistor T1 is turned on; the first reset signal G2, the third reset signal G3 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate-off level, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4 and the first emission control transistor T5 are turned off. Then the data voltage Vdata is written to the first node N1, and the voltage of the second node N2 is also the data voltage Vdata through the coupling effect of the second capacitor C2; the voltage of the fourth node N4 is (Vdata-Vref)*[C1 / (C1+C2)]+Vref-Vth through the coupling effect of the first capacitor C1 and the second capacitor C2; Vgs=[C1 / (C1+C2)]*Vdata+Vref-Vth; Vth=Vth0+Vgs. 发 发 发 发 ​​​(Vdata-Vref)+Vth. Wherein, C 发 is the capacitance of the light emitting element.

[0208] In the P4 stage (light emitting stage), referring to FIG. 16 and FIG. 17, the gate of the first light emitting control transistor T5 is loaded with the gate on level of the first light emitting control signal EM, so that the first light emitting control transistor T5 is turned on; the gates of the data writing transistor T1, the first reset transistor T2, the third reset transistor T3 and the second reset transistor T4 are loaded with the gate off levels of the data writing signal G1, the first reset signal G2 and the third reset signal G3, so that the data writing transistor T1, the first reset transistor T2, the third reset transistor T3 and the second reset transistor T4 are turned off. The driving transistor T6 is turned on due to the bootstrap of the second capacitor C2, so that the driving current I=K*(Vgs-Vth)^2=K*{[C 发 / (C1+C 发 )]*(Vdata-Vref)}^2. Wherein, K is a constant. The driving current in the above formula is irrelevant to the driving power voltage VDD and Vth, so as to solve the problem of the voltage drop of the driving power voltage VDD and the drift of Vth, so as to more fully compensate the threshold of the driving transistor T6, and improve the display quality of the display panel PNL.

[0209] It should be noted that in this example, except that the first reset transistor T2 and the second reset transistor T4 are P-type transistors, the other transistors are N-type transistors. The gate on levels of the data writing signal G1, the third reset signal G3 and the first light emitting control signal EM are high levels, and the gate off levels of the data writing signal G1, the third reset signal G3 and the first light emitting control signal EM are low levels. The gate on level of the first reset signal G2 is a low level, and the gate off level of the first reset signal G2 is a high level. Vgs is the gate-source voltage difference of the driving transistor T6, and Vth is the threshold voltage of the driving transistor T6.

[0210] In the seventh example, referring to FIG. 18, the pixel driving circuit PDC includes data writing transistor T1~driving transistor T6, and first capacitor C1, second capacitor C2, light emitting element. Among them, the first electrode of the data writing transistor T1 is electrically connected with the data voltage end, the second electrode of the data writing transistor T1 is electrically connected with the first node N1, and the control electrode of the data writing transistor T1 is electrically connected with the data writing signal end; the data writing transistor T1 is used to load the data voltage Vdata to the first node N1 in response to the gating level of the data writing signal G1. The first electrode of the first reset transistor T2 is electrically connected with the reference voltage end, the second electrode of the first reset transistor T2 is electrically connected with the second node N2, and the control electrode of the first reset transistor T2 is electrically connected with the first reset signal end; the first reset transistor T2 is used to load the reference voltage Vref to the second node N2 in response to the gating level of the first reset signal G2. The first electrode of the third reset transistor T3 is electrically connected with the initialization signal end, the second electrode of the third reset transistor T3, the light emitting element and the third node N3 are electrically connected with each other, and the control electrode of the third reset transistor T3 is electrically connected with the third reset signal end; the third reset transistor T3 is used to load the initialization signal Vini to the third node N3 in response to the gating level of the third reset signal G3. The first electrode of the second reset transistor T4 is electrically connected with the initialization signal end, the second electrode of the second reset transistor T4 is electrically connected with the first node N1, and the control electrode of the second reset transistor T4 is electrically connected with the second reset signal end; the second reset transistor T4 is used to load the initialization signal Vini to the first node N1 in response to the gating level of the second reset signal G4. The first electrode of the first light emitting control transistor T5 is electrically connected with the driving power voltage end, the second electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T6, and the control electrode of the first light emitting control transistor T5 is electrically connected with the first light emitting control signal end. The first light emitting control transistor T5 is used to load the driving power voltage VDD to the first electrode of the driving transistor T6 in response to the gating level of the first light emitting control signal EM. The first electrode of the driving transistor T6 is electrically connected with the second electrode of the first light emitting control transistor T5, the second electrode of the driving transistor T6 is electrically connected with the fourth node N4, and the control electrode of the driving transistor T6 is electrically connected with the second node N2; the driving transistor T6 is used to control the size of the driving current according to the voltage of the second node N2. The first end of the first capacitor C1, the first end of the second capacitor C2 and the first node N1 are electrically connected with each other, the second end of the first capacitor C1 is electrically connected with the fourth node N4; the second end of the second capacitor C2 is electrically connected with the second node N2. The third node N3 and the fourth node N4 are the same node.

[0211] As follows, taking the pixel driving circuit PDC shown in FIG. 18 as an example, referring to the timing diagram shown in FIG. 19, the driving method of the pixel driving circuit PDC of this example is exemplarily described.

[0212] In the P1 stage (reset stage), referring to FIG. 18 and FIG. 19, the first reset signal G2, the third reset signal G3, and the second reset signal G4 are loaded to the pixel driving circuit PDC at the gate level, so that the first reset transistor T2, the third reset transistor T3, and the second reset transistor T4 are turned on; the reference voltage Vref is loaded to the first node N1 and the second node N2, so that the driving transistor T6 is turned on; the initialization signal Vini is loaded to the third node N3 and the fourth node N4, so as to reset the first node N1, the second node N2, the third node N3, and the fourth node N4. The data write signal G1 and the first emission control signal EM are loaded to the pixel driving circuit PDC at the off level, so that the data write transistor T1 and the first emission control transistor T5 are turned off.

[0213] In the P2 stage (threshold compensation stage), referring to FIG. 18 and FIG. 19, the first reset signal G2, the second reset signal G4, and the first emission control signal EM are loaded to the pixel driving circuit PDC at the gate level, so that the first reset transistor T2, the second reset transistor T4, and the first emission control transistor T5 are turned on; the data write signal G1 and the third reset signal G3 are loaded to the pixel driving circuit PDC at the off level, so that the data write transistor T1 and the third reset transistor T3 are turned off. Then, the reference voltage Vref is loaded to the first node N1 and the second node N2, so as to reset the first node N1 and the second node N2, and the driving transistor T6 is turned on; the driving power voltage VDD is loaded to the third node N3 and the fourth node N4, so that when the voltage of the third node N3 and the fourth node N4 is discharged to Vref-Vth, the driving transistor T6 is just turned off, and the voltage of the third node N3 and the fourth node N4 is locked, so as to realize threshold voltage compensation of the driving transistor T6 to the fourth node N4.

[0214] In the P3 stage (data write stage), referring to FIG. 18 and FIG. 19, the data write signal G1 is loaded to the pixel driving circuit PDC at the gate level, so that the data write transistor T1 is turned on; the first reset signal G2, the third reset signal G3, the second reset signal G4, and the first emission control signal EM are loaded to the pixel driving circuit PDC at the off level, so that the first reset transistor T2, the third reset transistor T3, the second reset transistor T4, and the first emission control transistor T5 are turned off. Then, the data voltage Vdata is written to the first node N1, and the voltage of the second node N2 is also the data voltage Vdata through the coupling effect of the second capacitor C2; the voltage of the fourth node N4 is (Vdata-Vref)*[C1 / (C1+C2)]+Vref-Vth through the coupling effect of the first capacitor C1 and the second capacitor C2; Vgs=C1 / (C1+C2)*Vdata+Vref-Vth; and the driving transistor T6 is turned off. 发 发 发 ​​ / (C1+C 发 )]*(Vdata-Vref)+Vth. Where, C 发 The capacitor is the light-emitting element.

[0215] In stage P4 (light emission stage), referring to Figures 18 and 19, the first light emission control signal EM is applied to the pixel driving circuit PDC, causing the first light emission control transistor T5 to conduct; the data write signal G1, the first reset signal G2, the third reset signal G3, and the second reset signal G4 are applied to the pixel driving circuit PDC, causing the data write transistor T1, the first reset transistor T2, the third reset transistor T3, and the second reset transistor T4 to be cut off. Due to the bootstrapping of the second capacitor C2, the driving transistor T6 conducts, and the driving current I = K*(Vgs-Vth)^2 = K*{[C 发 / (C1+C 发 The formula is: )]*(Vdata-Vref)}^2. Where K is a constant. In the above formula, the driving current is independent of the driving power supply voltages VDD and Vth, thus solving the problems of voltage drop in VDD and drift in Vth. This allows for more adequate compensation of the threshold of the driving transistor T6, improving the display quality of the display panel PNL.

[0216] It should be noted that in this example, all transistors except the first reset transistor T2, which is a P-type transistor, are N-type transistors. The gating levels of data write signal G1, the third reset signal G3, the second reset signal G4, and the first light emission control signal EM are all high, and the cutoff levels of these signals are all low. The gating level of the first reset signal G2 is low, and the cutoff level is high. Vgs is the gate-source voltage difference of the driving transistor T6, and Vth is the threshold voltage of the driving transistor T6.

[0217] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

A pixel driving circuit includes a driving transistor, a data writing sub-circuit, a first reset sub-circuit, a first light emission control sub-circuit, a first energy storage sub-circuit, and a light emission element; in, The data writing sub-circuit is used to write data voltage to the second node in response to the strobe level of the data writing signal; The first reset sub-circuit is used to apply a reference voltage to the second node in response to the strobe level of the first reset signal; The first light emission control sub-circuit is used to apply the driving power supply voltage to the first terminal of the driving transistor in response to the gating level of the first light emission control signal; The driving transistor is used to control the magnitude of the driving current according to the voltage on the second node; One end of the first energy storage sub-circuit is electrically connected to the second node, and the other end of the first energy storage sub-circuit, the fourth node, and the light-emitting element are electrically connected to each other. According to the pixel driving circuit of claim 1, wherein, The first energy storage sub-circuit includes a first capacitor and a second capacitor; the pixel driving circuit includes a second reset sub-circuit. Wherein, the first end of the first capacitor, the first end of the second capacitor, and the first node are electrically connected to each other, the second end of the first capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the second node; The second reset sub-circuit is used to apply either the reference voltage or the initialization signal to the first node in response to the strobe level of the second reset signal. According to the pixel driving circuit of claim 2, wherein, The first terminal of the second reset sub-circuit is electrically connected to the second node, the second terminal of the second reset sub-circuit is electrically connected to the first node, and the control terminal of the second reset sub-circuit is electrically connected to the second reset signal terminal; Alternatively, the first terminal of the second reset sub-circuit is electrically connected to the reference voltage terminal, the second terminal of the second reset sub-circuit is electrically connected to the first node, and the control terminal of the second reset sub-circuit is electrically connected to the second reset signal terminal. According to the pixel driving circuit of claim 2, wherein, The first terminal of the second reset sub-circuit is electrically connected to the initialization signal terminal, and the second terminal of the second reset sub-circuit is electrically connected to the initialization signal terminal. The first node is electrically connected, and the control terminal of the second reset sub-circuit is electrically connected to the second reset signal terminal. According to the pixel driving circuit of claim 1, wherein, The first energy storage sub-circuit includes a first capacitor; a first terminal of the first capacitor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to the fourth node. According to the pixel driving circuit of claim 1, wherein, The pixel driving circuit also includes a second energy storage sub-circuit; one end of the second energy storage sub-circuit is electrically connected to the fourth node, and the other end is used to apply a constant voltage. According to the pixel driving circuit of claim 6, wherein, The second energy storage sub-circuit includes a third capacitor; the first end of the third capacitor is used to apply a constant voltage, and the second end is electrically connected to the fourth node. According to the pixel driving circuit of claim 1, wherein, The pixel driving circuit further includes a third reset sub-circuit; the third reset sub-circuit is used to load the initialization signal to the fourth node in response to the strobe level of the third reset signal. According to the pixel driving circuit of claim 1, wherein, The pixel driving circuit further includes a second light-emitting control sub-circuit; the second light-emitting control sub-circuit is used to electrically connect the light-emitting element to the fourth node in response to the selection level of the second light-emitting control signal. According to the pixel driving circuit of claim 2, wherein, The pixel driving circuit also includes a third capacitor; the first end of the third capacitor is used to apply a constant voltage, and the second end is electrically connected to the fourth node. The data writing sub-circuit includes a data writing transistor; The first terminal of the data writing transistor is electrically connected to the data voltage terminal, the second terminal of the data writing transistor is electrically connected to the first node, and the control terminal of the data writing transistor is electrically connected to the data writing signal terminal. The first reset sub-circuit includes a first reset transistor; The first terminal of the first reset transistor is electrically connected to the reference voltage terminal, the second terminal of the first reset transistor is electrically connected to the second node, and the control terminal of the first reset transistor is electrically connected to the first reset signal terminal. The first light-emitting control sub-circuit includes a first light-emitting control transistor; The first terminal of the first light-emitting control transistor is electrically connected to the driving power supply voltage terminal, the second terminal of the first light-emitting control transistor is electrically connected to the first terminal of the driving transistor, and the control terminal of the first light-emitting control transistor is electrically connected to the first light-emitting control signal terminal. According to the pixel driving circuit of claim 10, wherein, The second reset sub-circuit includes a second reset transistor; The first terminal of the second reset transistor is electrically connected to the second node, the second terminal of the second reset transistor is electrically connected to the first node, and the control terminal of the second reset transistor is electrically connected to the second reset signal terminal. Alternatively, the first terminal of the second reset transistor is electrically connected to the reference voltage terminal, the second terminal of the second reset transistor is electrically connected to the first node, and the control terminal of the second reset transistor is electrically connected to the second reset signal terminal. Alternatively, the first terminal of the second reset transistor is electrically connected to the initialization signal terminal, the second terminal of the second reset transistor is electrically connected to the first node, and the control terminal of the second reset transistor is electrically connected to the second reset signal terminal. According to the pixel driving circuit of claim 11, wherein, The pixel driving circuit also includes a third reset sub-circuit and a second light emission control sub-circuit; The third reset sub-circuit includes a third reset transistor; the first terminal of the third reset transistor is electrically connected to the initialization signal terminal, the second terminal of the third reset transistor, the light-emitting element, and the third node are electrically connected to each other, and the control terminal of the third reset transistor is electrically connected to the third reset signal terminal. The second light-emitting control sub-circuit includes a second light-emitting control transistor; the first electrode of the second light-emitting control transistor is electrically connected to the fourth node, the second electrode of the second light-emitting control transistor, the light-emitting element, and the third node are electrically connected to each other, and the control electrode of the second light-emitting control transistor is electrically connected to the second light-emitting control signal terminal. According to the pixel driving circuit of claim 12, wherein, The pixel driving circuit does not have a second reset sub-circuit; the first energy storage sub-circuit only includes a first capacitor; the first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the fourth node; the first node and the second node are the same node. According to the pixel driving circuit of claim 2, wherein, The pixel driving electric The circuit also includes a third reset circuit; The data writing sub-circuit includes a data writing transistor; The first terminal of the data writing transistor is electrically connected to the data voltage terminal, the second terminal of the data writing transistor is electrically connected to the first node, and the control terminal of the data writing transistor is electrically connected to the data writing signal terminal. The first reset sub-circuit includes a first reset transistor; The first terminal of the first reset transistor is electrically connected to the reference voltage terminal, the second terminal of the first reset transistor is electrically connected to the second node, and the control terminal of the first reset transistor is electrically connected to the first reset signal terminal. The third reset sub-circuit includes a third reset transistor; the first terminal of the third reset transistor is electrically connected to the initialization signal terminal, the second terminal of the third reset transistor, the light-emitting element, and the fourth node are electrically connected to each other, and the control terminal of the third reset transistor is electrically connected to the third reset signal terminal. The first light-emitting control sub-circuit includes a first light-emitting control transistor; The first terminal of the first light-emitting control transistor is electrically connected to the driving power supply voltage terminal, the second terminal of the first light-emitting control transistor is electrically connected to the first terminal of the driving transistor, and the control terminal of the first light-emitting control transistor is electrically connected to the first light-emitting control signal terminal. The pixel driving circuit according to any one of claims 12 to 14, wherein, The first reset signal, the third reset signal, and the second reset signal are the same signal. The pixel driving circuit according to any one of claims 6, 7, and 10, wherein, The constant voltage can be any one of the drive power supply voltage, reference voltage, or initialization signal. The pixel driving circuit according to any one of claims 1 to 14, wherein, The channel region of at least one transistor is made of a metal-oxide-semiconductor material; The driving transistor is an N-type transistor. A driving method for a pixel driving circuit, applied to the pixel driving circuit of claim 1; wherein, The driving method of the pixel driving circuit includes: During the reset phase, the gating level of the first reset signal is applied to the pixel driving circuit; During the compensation phase, the gating levels of the first reset signal and the first light emission control signal are applied to the pixel driving circuit; During the writing phase, the strobe level of the data writing signal is applied to the pixel driving circuit; During the light emission stage, the gating level of the first light emission control signal is applied to the pixel driving circuit. The driving method for the pixel driving circuit according to claim 18, wherein, The pixel driving circuit also includes a third reset transistor, a second reset transistor, and a second light-emitting control transistor. The first terminal of the third reset transistor is electrically connected to the initialization signal terminal, the second terminal of the third reset transistor, the light-emitting element, and the third node are electrically connected to each other, and the control terminal of the third reset transistor is electrically connected to the third reset signal terminal. The first electrode of the second light-emitting control transistor is electrically connected to the fourth node, the second electrode of the second light-emitting control transistor is electrically connected to the third node, and the control electrode of the second light-emitting control transistor is electrically connected to the second light-emitting control signal terminal. The first terminal of the second reset transistor is electrically connected to the second node, the second terminal of the second reset transistor is electrically connected to the first node, and the control terminal of the second reset transistor is electrically connected to the second reset signal terminal. Alternatively, the first terminal of the second reset transistor is electrically connected to the initialization signal terminal, the second terminal of the second reset transistor is electrically connected to the first node, and the control terminal of the second reset transistor is electrically connected to the second reset signal terminal. The driving method of the pixel driving circuit includes: During the reset phase, a first reset signal, a second light emission control signal, a third reset signal, and the gating level of the second reset signal are applied to the pixel driving circuit. During the compensation phase, the gating levels of the first reset signal, the third reset signal, the second reset signal, and the first light emission control signal are applied to the pixel driving circuit; During the writing phase, the strobe level of the data writing signal is applied to the pixel driving circuit; During the light emission stage, the gating levels of the first light emission control signal and the second light emission control signal are applied to the pixel driving circuit. The driving method for the pixel driving circuit according to claim 18, wherein, The pixel driving circuit also includes a third reset crystal and a second light-emitting control transistor. The first terminal of the third reset transistor is electrically connected to the initialization signal terminal. The second electrode of the bit transistor, the light-emitting element, and the third node are electrically connected to each other, and the control electrode of the third reset transistor is electrically connected to the third reset signal terminal. The first electrode of the second light-emitting control transistor is electrically connected to the fourth node, the second electrode of the second light-emitting control transistor is electrically connected to the third node, and the control electrode of the second light-emitting control transistor is electrically connected to the second light-emitting control signal terminal. The driving method of the pixel driving circuit includes: During the reset phase, the gating levels of the first reset signal, the second light emission control signal, and the third reset signal are applied to the pixel driving circuit; During the compensation phase, the gating levels of the first reset signal, the third reset signal, and the first light emission control signal are applied to the pixel driving circuit; During the writing phase, the strobe level of the data writing signal is applied to the pixel driving circuit; During the light emission stage, the gating levels of the first light emission control signal and the second light emission control signal are applied to the pixel driving circuit. A driving method for a pixel driving circuit, applied to the pixel driving circuit of claim 14; wherein, The driving method of the pixel driving circuit includes: During the reset phase, the gating levels of the first reset signal, the third reset signal, and the second reset signal are applied to the pixel driving circuit; During the compensation phase, the gating levels of the first reset signal, the second reset signal, and the first light emission control signal are applied to the pixel driving circuit; During the writing phase, the strobe level of the data writing signal is applied to the pixel driving circuit; During the light emission stage, the gating level of the first light emission control signal is applied to the pixel driving circuit. A display panel, wherein, Includes the pixel driving circuit as described in any one of claims 1 to 17. The display panel according to claim 22, wherein, The display panel has multiple rows of pixel driving circuits arranged in an array, and at least two pixel driving circuits in the same row of pixel driving circuits share a first light emission control sub-circuit.

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