Array substrate, display device and method for manufacturing array substrate

Abstract

The array substrate comprises a plurality of pixel driving circuits. Each pixel driving circuit includes a driving transistor, a first switching transistor, and a storage capacitor. The array substrate comprises a substrate base plate, a first electrode and a second electrode, the active layer of the driving transistor is positioned on the substrate; the second capacitor electrode of the storage capacitor is positioned on one side, far away from the substrate, of the active layer of the driving transistor; the connecting electrode and the active layer of the first switching transistor are located on the side, away from the substrate, of the second capacitor electrode; and the first electrode and the second electrode of the first switch transistor are positioned on one side, far away from the substrate, of the connecting electrode and the active layer of the first switch transistor.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate, a display device, and a method for manufacturing the array substrate. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit includes a driving transistor, a first switching transistor, and a storage capacitor; wherein the array substrate includes: a substrate; an active layer of the driving transistor located on the substrate; a second capacitor electrode of the storage capacitor located on the side of the active layer of the driving transistor away from the substrate; a connection electrode and an active layer of the first switching transistor located on the side of the second capacitor electrode away from the substrate; and a first electrode and a second electrode of the first switching transistor located on the side of the connection electrode and the active layer of the first switching transistor away from the substrate; wherein the connection electrode extends through a via to connect to the active layer of the driving transistor, the via extending through one or more insulating layers; the connection electrode is connected to the active layer of the first switching transistor and connected to the first electrode of the first switching transistor; the first electrode of the first switching transistor is in direct contact with the connection electrode; and the connection electrode is in direct contact with the active layer of the first switching transistor.

[0004] Optionally, each pixel driving circuit further includes a switching transistor; and the connection electrode and the second electrode of the switching transistor are located on the same layer.

[0005] Optionally, the gate of the first switching transistor is located on the side of the connection electrode and the second electrode of the switching transistor away from the substrate.

[0006] Optionally, the connecting electrode, the second electrode of the switching transistor, and the gate of the first switching transistor are located on the same layer.

[0007] Optionally, the connecting electrode extends through the second buffer layer and the first interlayer dielectric layer to connect to the second capacitor electrode, and extends through the second buffer layer, the first interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to connect to the active layer of the driving transistor.

[0008] Optionally, the connecting electrode extends through the second interlayer dielectric layer, the third gate insulating layer, the second buffer layer, and the first interlayer dielectric layer to connect to the second capacitor electrode, and extends through the second interlayer dielectric layer, the third gate insulating layer, the second buffer layer, the first interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to connect to the active layer of the driving transistor.

[0009] Optionally, the active layer of the first switching transistor and the first electrode of the first switching transistor are located on the same side of the connecting electrode away from the substrate.

[0010] Optionally, the active layer of the first switching transistor and the first electrode of the first switching transistor are located on opposite sides of the connection electrode.

[0011] Optionally, the second electrode of the first switching transistor and the first electrode of the driving transistor are located on the same layer; at least one of the second electrode of the first switching transistor or the first electrode of the driving transistor is not in direct contact with the corresponding active layer; and the first switching transistor and the driving transistor are different types of transistors selected from n-type transistors and p-type transistors.

[0012] Optionally, the second electrode of the first switching transistor and the first electrode of the driving transistor are located on different layers; the second electrode of the first switching transistor is in direct contact with the active layer of the first switching transistor; the first electrode of the driving transistor is in direct contact with the active layer of the driving transistor; and the first switching transistor and the driving transistor are different types of transistors selected from n-type transistors and p-type transistors.

[0013] Optionally, the first electrode of the first switching transistor is not in direct contact with the active layer of the first switching transistor.

[0014] Optionally, a connecting electrode extends through the via to connect to the second capacitor electrode, the via extending through the one or more insulating layers.

[0015] Optionally, the second electrode of the first switching transistor is in direct contact with the active layer of the first switching transistor.

[0016] Optionally, the array substrate further includes a support electrode; the support electrode is in direct contact with the active layer of the first switching transistor and in direct contact with the second electrode of the first switching transistor; the second electrode of the first switching transistor is not in direct contact with the active layer of the first switching transistor; each pixel driving circuit further includes a switching transistor; and the support electrode, the connection electrode, and the second electrode of the switching transistor are located on the same layer.

[0017] Optionally, the array substrate further includes a plurality of signal lines located on the side of the active layer of the connecting electrode and the first switching transistor away from the substrate; each of the plurality of signal lines extends through a plurality of insulating layers to connect to the active layer of the driving transistor; and a portion of each of the signal lines serves as a first electrode of the driving transistor.

[0018] In another aspect, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a first switching transistor, and a storage capacitor; wherein the array substrate includes: a substrate; an active layer of the driving transistor located on the substrate; a second capacitor electrode of the storage capacitor located on the side of the active layer of the driving transistor away from the substrate; a connection electrode and an active layer of the first switching transistor located on the side of the second capacitor electrode away from the substrate; and a plurality of signal lines located on the side of the connection electrode and the active layer of the first switching transistor away from the substrate; wherein the connection electrode extends through a via to connect to the active layer of the driving transistor, the via extending through one or more insulating layers; the connection electrode is connected to the active layer of the first switching transistor and to a first electrode of the first switching transistor; and each of the plurality of signal lines extends through one or more insulating layers to connect to the first electrode of the driving transistor.

[0019] Optionally, the first electrode of the driving transistor and the second capacitor electrode are located on the same layer.

[0020] Optionally, the first electrode of the driving transistor and the connection electrode are located on the same layer.

[0021] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate.

[0022] In another aspect, this disclosure provides a method for manufacturing an array substrate, including forming a plurality of pixel driving circuits; wherein forming each pixel driving circuit in the plurality of pixel driving circuits includes forming a driving transistor, forming a first switching transistor, and forming a storage capacitor; wherein the method includes: forming an active layer of the driving transistor on a substrate; forming a second capacitor electrode of the storage capacitor on a side of the active layer of the driving transistor away from the substrate; forming an active layer of the storage capacitor and a connection electrode on a side of the second capacitor electrode away from the substrate; forming an active layer of the storage capacitor and the first switching transistor on a side of the second capacitor electrode away from the substrate; and forming an active layer of the storage capacitor and the first switching transistor on a side of the active layer of the storage capacitor away from the substrate. A first electrode and a second electrode of the first switching transistor are formed on one side of a substrate; and a plurality of signal lines are formed on the side of the active layer of the connecting electrode and the first switching transistor away from the substrate; wherein the method further includes: forming vias configured to accommodate a portion of a corresponding signal line among the plurality of signal lines; and forming vias configured to accommodate the first electrode or the second electrode of the first switching transistor; wherein the vias configured to accommodate the portions of the corresponding signal lines and the vias configured to accommodate the first electrode or the second electrode of the first switching transistor are formed in the same patterning process.

[0023] Optionally, the via configured to accommodate the portion of the corresponding signal line, the via configured to accommodate the first electrode of the first switching transistor, and the via configured to accommodate the second electrode of the first switching transistor are formed in the same patterning process.

[0024] Optionally, the via configured to accommodate the portion of the corresponding signal line and the via configured to accommodate the first electrode of the first switching transistor are formed in the same patterning process; and the via configured to accommodate the second electrode of the first switching transistor and the via configured to accommodate the portion of the corresponding signal line and the via configured to accommodate the first electrode of the first switching transistor are formed in different patterning processes.

[0025] Optionally, the method includes: forming a via configured to receive a first electrode of the driving transistor, thereby exposing a portion of the active layer of the driving transistor; and performing an etching process on the portion of the active layer of the driving transistor to remove an oxide layer on the surface of the portion of the active layer of the driving transistor; wherein, after performing the etching process, in the same patterning process, forming the via configured to receive the portion of the corresponding signal line and forming the via configured to receive the first electrode or the second electrode of the first switching transistor are performed.

[0026] Alternatively, the etching process is a buffered oxide etching process using an etchant solution.

[0027] Optionally, forming the respective pixel driving circuit further includes forming a switching transistor; wherein the method further includes forming a via configured to accommodate a first electrode of the switching transistor; wherein forming the via configured to accommodate the first electrode of the driving transistor and forming the via configured to accommodate the first electrode of the switching transistor are performed in the same patterning process.

[0028] Optionally, the method further includes forming a via extending through one or more insulating layers; wherein the connection electrode extends through the via to connect to the active layer of the driving transistor and to the second capacitor electrode, the via extending through the one or more insulating layers; and the connection electrode is connected to the active layer of the first switching transistor and to the first electrode of the first switching transistor.

[0029] Optionally, during the same patterning process, the via configured to accommodate the first electrode of the driving transistor and the via configured to accommodate the connection electrode are formed.

[0030] Optionally, forming the respective pixel driving circuit further includes forming a switching transistor; wherein the method further includes forming a via configured to accommodate a second electrode of the switching transistor; wherein, in the same patterning process, forming the via configured to accommodate a first electrode of the driving transistor, forming the via configured to accommodate the connection electrode, and forming the via configured to accommodate a second electrode of the switching transistor are performed.

[0031] Optionally, the via configured to accommodate the portion of the corresponding signal line exposes a portion of the active layer of the driving transistor; wherein the method further includes performing a dry etching process on the portion of the active layer of the driving transistor to remove an oxide layer on the surface of the portion of the active layer of the driving transistor; wherein, after performing the dry etching process, in the same patterning process, the corresponding signal line and the first electrode or the second electrode of the first switching transistor are formed; and the respective signal line is in direct contact with the active layer of the driving transistor and serves as the first electrode of the driving transistor.

[0032] Alternatively, a fluorine-containing gas may be used to perform the dry etching process.

[0033] Optionally, the via configured to accommodate the portion of the corresponding signal line exposes a portion of the active layer of the driving transistor; the via configured to accommodate the first electrode of the first switching transistor exposes a portion of the connection electrode but does not expose any portion of the active layer of the first switching transistor; and in the same patterning process, the via configured to accommodate the portion of the corresponding signal line and the via configured to accommodate the first electrode of the first switching transistor are formed; wherein the method further includes performing an etching process on the portion of the active layer of the driving transistor to remove an oxide layer on the surface of the portion of the active layer of the driving transistor; and the connection electrode is connected to the active layer of the driving transistor, connected to the second capacitor electrode, and connected to the active layer of the first switching transistor.

[0034] Alternatively, the etching process is a buffered oxide etching process using an etchant solution.

[0035] Optionally, the method further includes forming the corresponding signal line and the first electrode of the first switching transistor in the same patterning process after performing the etching process.

[0036] Optionally, the method further includes: forming a support electrode; and forming the active layer of the first switching transistor on the support electrode; wherein the support electrode is in direct contact with the active layer of the first switching transistor; wherein the method further includes forming a via configured to accommodate the second electrode of the first switching transistor to expose a portion of the support electrode but not any portion of the active layer of the first switching transistor; wherein, in the same patterning process, forming the via configured to accommodate the portion of the corresponding signal line, forming the via configured to accommodate the first electrode of the first switching transistor, and forming the via configured to accommodate the second electrode of the first switching transistor are performed.

[0037] Optionally, the method further includes forming the corresponding signal line, the first electrode of the first switching transistor, and the second electrode of the first switching transistor in the same patterning process after performing the etching process.

[0038] Optionally, after forming the supporting electrode, the active layer for forming the first switching transistor is performed.

[0039] Optionally, the method further includes forming a plurality of sensing lines after forming the first electrode of the first switching transistor; wherein each of the plurality of sensing lines extends through a plurality of insulating layers to connect to the active layer of the first switching transistor; and a portion of each sensing line serves as the second electrode of the first switching transistor.

[0040] Optionally, after forming the connection electrode, the active layer for forming the first switching transistor is performed.

[0041] Optionally, the connection electrode is formed after the active layer of the first switching transistor is formed. Attached Figure Description

[0042] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0043] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 2 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0045] Figure 3 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0046] Figure 4 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0047] Figures 5A to 5H The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0048] Figures 6A to 6E The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0049] Figures 7A to 7F The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0050] Figures 8A to 8F The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0051] Figures 9A to 9C The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0052] Figures 10A to 10D The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0053] Figures 11A to 11E The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0054] Figures 12A to 12G The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0055] Figures 13A to 13H The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated.

[0056] Figure 14 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0057] Figure 15 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0058] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0059] Various suitable pixel driving circuits can be used in the array substrate of this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 3T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate of this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0060] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components such as a light-emitting element. In one example, the light-emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and a plurality of second voltage supply lines Vss. Each sub-pixel Sp is driven to emit light by the respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through each of the plurality of first voltage supply lines Vdd; a low voltage signal (e.g., VSS signal) is input to the cathode of the light-emitting element through the low voltage supply lines. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is the driving voltage ΔV that drives the light-emitting element to emit light.

[0061] Figure 2 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) Figure 2In some embodiments, each pixel driving circuit (PDC) is connected to a corresponding light-emitting element (LE). In some embodiments, each pixel driving circuit (PDC) includes a storage capacitor (Cst) having a first capacitor electrode coupled to a first node N1 and a second capacitor electrode coupled to a second node N2; a driving transistor (Td) having a first electrode coupled to a corresponding voltage supply line among a plurality of first voltage supply lines (Vdd), a second electrode coupled to the second node N2, and a gate coupled to the first node N1; a switching transistor (Tw) having a first electrode coupled to a corresponding data line among a plurality of data lines (DL), a second electrode coupled to the first node N1, and a gate coupled to a corresponding first gate line among a plurality of first gate lines (GL1); and a sensing transistor (Ts) having a first electrode coupled to the second node N2, a second electrode coupled to a corresponding sensing line among a plurality of sensing lines (SL), and a gate coupled to a corresponding second gate line among a plurality of second gate lines (GL2). The first node N1 is coupled to the gate of the driving transistor Td, the second electrode of the switching transistor Tw, and the first capacitor electrode of the storage capacitor (Cst). The second node N2 is coupled to the second electrode of the driving transistor Td, the first electrode of the sensing transistor Ts, the second capacitor electrode of the storage capacitor Cst, and the anode of the corresponding light-emitting element LE.

[0062] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to the active layer of the transistor. The direction of current flow through the transistor can be configured from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flow through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0063] In some embodiments, each pixel driving circuit further includes a first switch SW1 and a second switch SW2. The first switch SW1 is configured to control the connection between a corresponding sensing line of the plurality of sensing lines SL and a reference voltage signal line Vref. The second switch SW2 is configured to control the connection between a corresponding sensing line of the plurality of sensing lines SL and a sensing circuit SC. In one example, the reference voltage signal line Vref is configured to provide a ground voltage signal, such as a voltage signal with 0V.

[0064] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2The sensing transistor Ts is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while other transistors are p-type transistors, such as polysilicon transistors. For a p-type transistor, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For an n-type transistor, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0065] Figure 3 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2 and Figure 3 During one frame of an image, the operation of the pixel driving circuit includes a first sub-stage t1, a second sub-stage t2, and a third sub-stage t3.

[0066] In the first sub-stage t1, a gate control signal is provided to the gate of the switching transistor Tw through the corresponding first gate line to turn on the switching transistor Tw, allowing the data signal from the corresponding data line to be transmitted from the first electrode of the switching transistor Tw to the second electrode of the switching transistor Tw; and sequentially transmitted to the first node N1. The first switch SW1 is turned on to allow the reference signal to be transmitted from the reference signal line Vref to the corresponding sensing line. A gate control signal is provided to the gate of the sensing transistor Ts through the corresponding second gate line to turn on the sensing transistor Ts, allowing the reference signal from the corresponding sensing line to be transmitted from the first electrode of the sensing transistor Ts to the second electrode of the sensing transistor Ts; and sequentially transmitted to the second node N2.

[0067] In the second sub-stage t2, the first switch SW1 is opened to disconnect the reference signal line Vref from the corresponding sensing line. The gate-source voltage difference Vgs increases to (Vdata - Vref), where Vdata is the voltage level of the data voltage signal and Vref is the voltage level of the reference signal. When the gate-source voltage difference Vgs is greater than the threshold voltage Vth of the driving transistor Td, the driving transistor Td is turned on to allow the high voltage signal from the corresponding first voltage signal line to be transmitted from the first electrode of the driving transistor Td to the second electrode of the driving transistor Td. The high voltage signal continuously charges the second node N2. As the potential at N2 increases, the Vgs difference decreases. The degree of opening of the driving transistor Td gradually decreases until the source voltage (Vs) of the driving transistor Td is charged to a point where it differs from Vgs by Vth, at which point the driving transistor Td is fully closed. At this time, the first node has the voltage level Vdata of the data signal, and the second node N2 has a voltage level of (Vdata - Vth).

[0068] In the third sub-stage t3, the second switch SW2 is turned on to allow the corresponding sensing line to connect to the sensing circuit SC. In the third sub-stage t3, the voltage level of each sensing line is (Vdata - Vth), which is read by the sensing circuit SC. The sensing circuit SC is configured to extract the voltage level (Vdata - Vth) and transmit this value to an integrated circuit (e.g., a field-programmable gate array (FPGA)). The integrated circuit is then configured to calculate a compensation value using a compensation algorithm. The integrated circuit is also configured to transmit the compensation value to a data driver integrated circuit. The data driver integrated circuit is configured to use the compensation value to compensate the corresponding data signal.

[0069] Figure 4 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 4 In some embodiments, the array substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the array substrate in a display panel that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the array substrate in a display panel where various circuits and wires are provided for transmitting signals to the display substrate. To increase the transparency of the display device, opaque or non-transparent components of the display panel (e.g., batteries, printed circuit boards, metal frames) may be disposed in the peripheral area instead of the display area.

[0070] In some embodiments, the array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the first semiconductor material layer SML1. 1. The side away from the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on the side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the side of the second buffer layer. BUF2 is located on the side away from the substrate BS; the second semiconductor material layer SML2 is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3 is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3 is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2 is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2 is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. A first passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; a third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; a planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; an anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0071] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to a first electrode of the switching transistor Tw. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SL1. For example, conductive materials can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer SL1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0072] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the light-shielding layer LSL. For example, conductive materials can be deposited on the substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the light-shielding layer LSL include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0073] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0074] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer CT1. For example, conductive materials can be deposited on the substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0075] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second conductive layer CT2. For example, conductive materials can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer CT2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0076] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE and a second electrode Dw for a switching transistor Tw. The connection electrode CNE is connected to a first electrode Ss of a sensing transistor Ts, a second capacitor electrode Ce2 of a storage capacitor, and serves as the second electrode Dd of a driving transistor Td. The connection electrode layer CEL can be fabricated using a variety of suitable electrode materials and a variety of suitable fabrication methods. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the connection electrode layer CEL include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0077] In some embodiments, the second semiconductor material layer SML2 includes active layers ACTs of sensing transistors Ts. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (such as indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (such as zinc oxynitride).

[0078] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts. Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the third conductive layer CT3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third conductive layer CT3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0079] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second signal line layer SL2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer SL2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0080] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third signal line layer SL3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer SL3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0081] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0082] Figures 5A to 5H The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 5AIn some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0083] In some embodiments, the method further includes forming a first via v1 extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0084] In some embodiments, the method further includes forming a second via v2 extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0085] In some embodiments, the method further includes forming a third via v3 extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0086] In some embodiments, refer to Figure 5A and Figure 5B The method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via v1 to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 also includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via v2 and a third via v3, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0087] In some embodiments, reference Figure 5CThe method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0088] In some embodiments, the method further includes forming a fourth via v4 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0089] In some embodiments, the method further includes forming a fifth via v5 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0090] In some embodiments, reference Figure 5C and Figure 5D The method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE and forming a second electrode Dw for the switching transistor Tw. The connection electrode CNE extends through a fourth via v4 to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via v5 to connect to the active layer ACTw of the switching transistor Tw.

[0091] In some embodiments, reference Figure 5E The method further includes forming a second semiconductor material layer SML2 on the side of the connecting electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0092] In some embodiments, refer to Figure 5F The method further includes forming a sixth via v6 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the sixth via v6 exposes a portion of the active layer ACTd of the driving transistor Td.

[0093] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0094] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0095] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0096] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the sixth via v6. In some embodiments, the etching process is a buffered oxide etching process. Buffered oxide etching, commonly abbreviated as BOE, is an etching process that uses a wet etchant solution. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant includes hydrofluoric acid. In another example, the etchant includes hydrofluoric acid and a buffer, such as ammonium fluoride. The buffer is configured to modulate the activity of the hydrofluoric acid.

[0097] In some embodiments, the method further includes removing an oxide layer (e.g., silicon oxide) from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6. By removing the oxide layer from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6, the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td can be reduced.

[0098] In some embodiments, refer to Figure 5G The method further includes forming a tenth via v10 that extends through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0099] In some embodiments, the method further includes forming an eleventh via v11 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The eleventh via v11 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0100] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0101] In some embodiments, refer to Figures 5F to 5H The method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through a sixth via v6 to connect to the active layer ACTd of the driving transistor Td, thereby forming the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through a tenth via v10 to connect to the active layer ACTs of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts extends through an eleventh via v11 to connect to the active layer ACTs of the sensing transistor Ts.

[0102] In some embodiments, reference Figure 4 The method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS, forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS, forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0103] Reference Figure 5F and Figure 5GForming the sixth via v6, tenth via v10, and eleventh via v11 requires two patterning processes. This is because an etching process is needed after forming the sixth via v6 to remove the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is exposed by the sixth via v6. The active layer ACTd of the driving transistor Td comprises a semiconductor material different from the semiconductor material of the active layer ACTs of the sensing transistor Ts. In one example, the active layer ACTd of the driving transistor Td comprises silicon, while the active layer ACTs of the sensing transistor Ts comprises metal oxide. If the sixth via v6, tenth via v10, and eleventh via v11 are formed in the same patterning process, the etchant used to remove the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is exposed by the sixth via v6, will remove (e.g., completely remove) the metal oxide material in the active layer ACTs of the sensing transistor Ts. This is because the etchant has different selectivity between silicon-based semiconductor materials and metal oxide-based semiconductor materials.

[0104] The inventors of this disclosure discovered that, Figures 5A to 5H The manufacturing process shown involves various patterning processes for forming the sixth via v6, the tenth via v10, and the eleventh via v11, thus increasing manufacturing costs. The inventors of this disclosure have discovered additional problems associated with this manufacturing process. After removing the oxide layer on the surface of the active layer ACTd of the driving transistor Td exposed by the sixth via v6, and before forming the second signal line layer SL2 including the first electrode Sd of the driving transistor Td, the manufacturing process includes forming the tenth via v10, the eleventh via v11, and the twelfth via v12. During the formation of the tenth via v10, the eleventh via v11, and the twelfth via v12, a new oxide layer is formed on the surface of the etched portion of the active layer ACTd of the driving transistor Td, thereby increasing the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td. As described above, after forming the tenth via v10, the eleventh via v11, and the twelfth via v12, the etching process cannot be performed again, otherwise the active layer ACTs of the sensing transistor Ts may be removed. The new oxide layer will affect the characteristics and performance of the driving transistor Td.

[0105] The inventors of this disclosure have discovered a novel manufacturing process in which vias accommodating portions of corresponding first voltage supply lines among a plurality of first voltage supply lines Vdd, vias accommodating the first electrode Ss of a sensing transistor Ts, and vias accommodating the second electrode Ds of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have found that the new manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0106] Figures 6A to 6E The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 6A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0107] In some embodiments, the method further includes forming a first via v1 extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0108] In some embodiments, the method further includes forming a second via v2 extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0109] In some embodiments, the method further includes forming a third via v3 extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0110] In some embodiments, the method further includes forming a thirteenth via v13 extending through at least one (e.g., all) of the second gate insulating layer GI2 and the first gate insulating layer GI1.

[0111] In some embodiments, the first via v1 and the thirteenth via v13 are formed in the same patterning process.

[0112] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the thirteenth via v13. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant includes hydrofluoric acid. In another example, the etchant includes hydrofluoric acid and a buffer, such as ammonium fluoride.

[0113] In some embodiments, refer to Figure 6A and Figure 6B The method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor, a first electrode Sd for a driving transistor Td, and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via v1 to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. The first electrode Sd of the driving transistor Td extends through a thirteenth via v13 to connect to the active layer ACTd of the driving transistor Td. Optionally, forming the second conductive layer CT2 also includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via v2 and a third via v3, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0114] In some embodiments, reference Figure 6CThe method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS. In some embodiments, the method further includes forming a fourth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the method further includes forming a fifth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE and a second electrode Dw forming a switching transistor Tw. The connection electrode CNE extends through the fourth via to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via to connect to the active layer ACTw of the switching transistor Tw. In some embodiments, the method further includes forming a second semiconductor material layer SML2 on the side of the connection electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0115] In some embodiments, reference Figure 6C The method further includes forming a fourteenth via v14 that extends through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0116] In some embodiments, the method further includes forming a tenth via v10 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0117] In some embodiments, the method further includes forming an eleventh via v11 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The eleventh via v11 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0118] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0119] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0120] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0121] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0122] In some embodiments, the fourteenth via v14, the tenth via v10, the eleventh via v11, the twelfth via v12, the seventh via v7, the eighth via v8, and the ninth via v9 are formed in the same patterning process.

[0123] In some embodiments, refer to Figure 6C and Figure 6D The method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through a fourteenth via v14 to connect to the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through a tenth via v10 to connect to the active layer ACTs of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts extends through an eleventh via v11 to connect to the active layer ACTs of the sensing transistor Ts.

[0124] In some embodiments, reference Figure 6E The method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS, forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS, forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0125] exist Figures 6A to 6E In the manufacturing process shown, vias (fourteenth via v14) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, vias (tenth via v10) accommodating the first electrode Ss of the sensing transistor Ts, and vias (eleventh via v11) accommodating the second electrode Ds of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the novel manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0126] In some embodiments, reference Figure 6EThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0127] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0128] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0129] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0130] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0131] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw, a first electrode Sd of the driving transistor Td, and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0132] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE and a second electrode Dw for the switching transistor Tw. The connection electrode CNE is connected to a first electrode Ss of the sensing transistor Ts, a second capacitor electrode Ce2 of the storage capacitor, and serves as the second electrode Dd of the driving transistor Td.

[0133] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0134] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0135] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0136] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL.

[0137] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0138] Figures 7A to 7F The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 7A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0139] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0140] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0141] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0142] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0143] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0144] In some embodiments, the method further includes forming a fourth via v4 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0145] In some embodiments, the method further includes forming a fifth via v5 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0146] In some embodiments, the method further includes forming a fifteenth via v15 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0147] In some embodiments, the fourth via v4, the fifth via v5, and the fifteenth via v15 are formed in the same patterning process.

[0148] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the fifteenth via v15. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant comprises hydrofluoric acid. In another example, the etchant comprises hydrofluoric acid and a buffer, such as ammonium fluoride.

[0149] In some embodiments, reference Figure 7A and Figure 7BThe method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE, forming a first electrode Sd of the driving transistor Td, and forming a second electrode Dw of the switching transistor Tw. The connection electrode CNE extends through a fourth via v4 to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to connect to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The first electrode Sd of the driving transistor Td extends through a fifteenth via v15 to connect to the active layer ACTd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via v5 to connect to the active layer ACTw of the switching transistor Tw.

[0150] In some embodiments, reference Figure 7C The method further includes forming a second semiconductor material layer SML2 on the side of the connecting electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0151] In some embodiments, refer to Figure 7D The method further includes forming a sixteenth via v16 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3.

[0152] In some embodiments, the method further includes forming a tenth via v10 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0153] In some embodiments, the method further includes forming an eleventh via v11 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The eleventh via v11 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0154] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0155] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0156] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0157] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0158] In some embodiments, the sixteenth via v16, the tenth via v10, the eleventh via v11, the twelfth via v12, the seventh via v7, the eighth via v8, and the ninth via v9 are formed in the same patterning process.

[0159] In some embodiments, refer to Figure 7D and Figure 7E The method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through a sixteenth via v16 to connect to the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through a tenth via v10 to connect to the active layer ACTs of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts extends through an eleventh via v11 to connect to the active layer ACTs of the sensing transistor Ts.

[0160] In some embodiments, reference Figure 7FThe method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS, forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS, forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0161] exist Figures 7A to 7F In the manufacturing process shown, vias (sixteenth via v16) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, vias (tenth via v10) accommodating the first electrode Ss of the sensing transistor Ts, and vias (eleventh via v11) accommodating the second electrode Ds of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the novel manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0162] In some embodiments, reference Figure 7FThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0163] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0164] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0165] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0166] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0167] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0168] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE, a first electrode Sd of the driving transistor Td, and a second electrode Dw of the switching transistor Tw. The connection electrode CNE is connected to the first electrode Ss of the sensing transistor Ts, connected to the second capacitor electrode Ce2 of the storage capacitor, and serves as the second electrode Dd of the driving transistor Td.

[0169] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0170] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0171] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0172] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL.

[0173] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0174] Figures 8A to 8F The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 8A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0175] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0176] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0177] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0178] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0179] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0180] In some embodiments, the method further includes forming a fourth via v4 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0181] In some embodiments, the method further includes forming a fifth via v5 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0182] In some embodiments, the method further includes forming a fifteenth via v15 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0183] In some embodiments, the method further includes forming a seventeenth via v17 extending through at least one (e.g., all) of the second buffer layer BUF2 and the first interlayer dielectric layer ILD1.

[0184] In some embodiments, the method further includes forming an eighteenth via v18 extending through at least one (e.g., all) of the second buffer layer BUF2 and the first interlayer dielectric layer ILD1.

[0185] In some embodiments, the method further includes forming a nineteenth via v19 extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0186] In some embodiments, the fourth via v4, the fifth via v5, the fifteenth via v15, the seventeenth via v17, the eighteenth via v18, and the nineteenth via v19 are formed in the same patterning process.

[0187] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the fifteenth via v15. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant comprises hydrofluoric acid. In another example, the etchant comprises hydrofluoric acid and a buffer, such as ammonium fluoride.

[0188] In some embodiments, reference Figure 8A and Figure 8B The method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE, forming a first electrode Sd of the driving transistor Td, and forming a second electrode Dw of the switching transistor Tw. The connection electrode CNE extends through a fourth via v4 to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to connect to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The first electrode Sd of the driving transistor Td extends through a fifteenth via v15 to connect to the active layer ACTd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via v5 to connect to the active layer ACTw of the switching transistor Tw.

[0189] In some embodiments, forming the connection electrode layer CEL further includes forming a first relay electrode RE1, a second relay electrode RE2, and a third relay electrode RE3. The first relay electrode RE1 extends through a seventeenth via v17 to connect to the connection electrode of a first signal supply line. The second relay electrode RE2 extends through an eighteenth via v18 to connect to the connection electrode of a second signal supply line. The third relay electrode RE3 extends through a nineteenth via v19 to connect to the connection electrode of a third signal supply line.

[0190] In some embodiments, reference Figure 8C The method further includes forming a second semiconductor material layer SML2 on the side of the connecting electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0191] In some embodiments, refer to Figure 8D The method further includes forming a sixteenth via v16 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3.

[0192] In some embodiments, the method further includes forming a tenth via v10 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0193] In some embodiments, the method further includes forming an eleventh via v11 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The eleventh via v11 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0194] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0195] In some embodiments, the method further includes forming a 25th via v25 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3.

[0196] In some embodiments, the method further includes forming a second sixteenth via v26 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3.

[0197] In some embodiments, the method further includes forming a twenty-seventh via v27 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3.

[0198] In some embodiments, the sixteenth via v16, the tenth via v10, the eleventh via v11, the twelfth via v12, the twenty-fifth via v25, the twenty-sixth via v26, and the twenty-seventh via v27 are formed in the same patterning process.

[0199] In some embodiments, refer to Figure 8D and Figure 8EThe method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through a sixteenth via v16 to connect to the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through a tenth via v10 to connect to the active layer ACTs of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts extends through an eleventh via v11 to connect to the active layer ACTs of the sensing transistor Ts. The first signal supply line SSL1 extends through a twenty-fifth via v25 to connect to the first relay electrode RE1. The second signal supply line SSL2 extends through a twenty-sixth via v26 to connect to the second relay electrode RE2. The third signal supply line SSL3 extends through the twenty-seventh via v27 to connect to the third relay electrode RE3.

[0200] In some embodiments, reference Figure 8F The method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS, forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS, forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0201] exist Figures 8A to 8F In the manufacturing process shown, vias (sixteenth via v16) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, vias (tenth via v10) accommodating the first electrode Ss of the sensing transistor Ts, and vias (eleventh via v11) accommodating the second electrode Ds of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the novel manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0202] In some embodiments, reference Figure 8FThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0203] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0204] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0205] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0206] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0207] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0208] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE, a first electrode Sd of the driving transistor Td, a second electrode Dw of the switching transistor Tw, a first relay electrode RE1, a second relay electrode RE2, and a third relay electrode RE3. The connection electrode CNE is connected to the first electrode Ss of the sensing transistor Ts, connected to the second capacitor electrode Ce2 of the storage capacitor, and serves as the second electrode Dd of the driving transistor Td.

[0209] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0210] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0211] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0212] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL.

[0213] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0214] Figures 9A to 9C The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 9A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0215] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0216] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0217] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0218] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0219] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0220] In some embodiments, the method further includes forming a fourth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0221] In some embodiments, the method further includes forming a fifth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0222] In some embodiments, the method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE and a second electrode Dw for forming a switching transistor Tw. The connection electrode CNE extends through a fourth via to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via to connect to the active layer ACTw of the switching transistor Tw.

[0223] In some embodiments, the method further includes forming a second semiconductor material layer SML2 on the side of the connecting electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0224] In some embodiments, the method further includes forming a sixth via v6 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the sixth via v6 exposes a portion of the active layer ACTd of the driving transistor Td.

[0225] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0226] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0227] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0228] In some embodiments, the method further includes forming a tenth via v10 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0229] In some embodiments, the method further includes forming an eleventh via v11 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The eleventh via v11 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0230] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0231] In some embodiments, the sixth via v6, the seventh via v7, the eighth via v8, the ninth via v9, the tenth via v10, the eleventh via v11, and the twelfth via v12 are formed in the same patterning process.

[0232] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the sixth via v6. In some embodiments, the etching process is a dry etching process. Optionally, a fluorine-containing gas is used to perform the etching process. In one example, the dry etchant includes one or more of trifluoromethane, carbon tetrafluoride, and sulfur hexafluoride.

[0233] In some embodiments, the method further includes removing an oxide layer (e.g., silicon oxide) from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6. By removing the oxide layer from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6, the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td can be reduced.

[0234] Reference Figure 9A Only one patterning process is needed to form the sixth via v6, the tenth via v10, and the eleventh via v11. This is because the etching process uses a dry etchant to remove the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is partially exposed by the sixth via v6. Figure 9A The manufacturing process shown does not use a buffered oxide etching process with wet etchant. The dry etchant does not cause etch damage to the active layer ACTs of the sensing transistor Ts exposed by the tenth via v10 and the eleventh via v11, or causes only minimal etch damage, and does not affect the electrical connection between the active layer ACTs of the sensing transistor Ts and the first electrode Ss, nor does it affect the electrical connection between the active layer ACTs of the sensing transistor Ts and the second electrode Ds.

[0235] In some embodiments, reference Figure 9A and Figure 9BAfter removing the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is partially exposed by the sixth via v6, the method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through the sixth via v6 to connect to the active layer ACTd of the driving transistor Td to form the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through the tenth via v10 to connect to the active layer ACTs of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts extends through the eleventh via v11 to connect to the active layer ACTs of the sensing transistor Ts.

[0236] In some embodiments, reference Figure 9C The method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS, forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS, forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0237] exist Figures 9A to 9C In the manufacturing process shown, vias (sixth via v6) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, vias (tenth via v10) accommodating the first electrode Ss of the sensing transistor Ts, and vias (eleventh via v11) accommodating the second electrode Ds of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the new manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0238] In some embodiments, reference Figure 9CThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0239] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0240] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0241] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0242] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0243] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0244] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE and a second electrode Dw for the switching transistor Tw. The connection electrode CNE is connected to a first electrode Ss of the sensing transistor Ts, a second capacitor electrode Ce2 of the storage capacitor, and serves as the second electrode Dd of the driving transistor Td.

[0245] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0246] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0247] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0248] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL.

[0249] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0250] Figures 10A to 10D The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 10A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0251] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0252] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0253] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0254] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0255] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0256] In some embodiments, the method further includes forming a fourth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0257] In some embodiments, the method further includes forming a fifth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0258] In some embodiments, the method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE, forming a second electrode Dw of the switching transistor Tw, and forming a support electrode SE. The connection electrode CNE extends through a fourth via to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via to connect to the active layer ACTw of the switching transistor Tw.

[0259] In some embodiments, reference Figure 10B The method further includes forming a second semiconductor material layer SML2 on the side of the connection electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS. In some embodiments, forming the second semiconductor material layer SML2 includes forming an active layer ACTs for a sensing transistor Ts. The active layer ACTs of the sensing transistor Ts is in direct contact with the connection electrode CNE and in direct contact with the support electrode SE.

[0260] In some embodiments, the method further includes forming a sixth via v6 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the sixth via v6 exposes a portion of the active layer ACTd of the driving transistor Td.

[0261] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0262] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0263] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0264] In some embodiments, the method further includes forming a tenth via v10 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the connection electrode CNE. Optionally, the tenth via v10 does not expose any portion of the active layers ACTs of the sensing transistor Ts.

[0265] In some embodiments, the method further includes forming an eleventh via v11 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The eleventh via v11 exposes a portion of the support electrode SE. Optionally, the eleventh via v11 does not expose any portion of the active layers ACTs of the sensing transistor Ts.

[0266] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0267] In some embodiments, the sixth via v6, the seventh via v7, the eighth via v8, the ninth via v9, the tenth via v10, the eleventh via v11, and the twelfth via v12 are formed in the same patterning process.

[0268] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the sixth via v6. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant comprises hydrofluoric acid. In another example, the etchant comprises hydrofluoric acid and a buffer, such as ammonium fluoride.

[0269] In some embodiments, the method further includes removing an oxide layer (e.g., silicon oxide) from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6. By removing the oxide layer from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6, the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td can be reduced.

[0270] Reference Figure 10B Forming the sixth via v6, tenth via v10, and eleventh via v11 requires only one patterning process. This is because the tenth via v10 does not expose any part of the active layer ACTs of the sensing transistor Ts, and the eleventh via v11 does not expose any part of the active layer ACTs of the sensing transistor Ts. Instead, the tenth via v10 exposes a portion of the connection electrode CNE, and the eleventh via v11 exposes a portion of the support electrode SE. The etchant used during the etching process does not directly contact the active layer ACTs of the sensing transistor Ts. Therefore, the etchant used during the etching process does not cause etch damage to the active layer of the sensing transistor Ts, or causes only minimal etch damage.

[0271] In some embodiments, reference Figure 10B and Figure 10CAfter removing the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is partially exposed by the sixth via v6, the method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of the sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through the sixth via v6 to connect to the active layer ACTd of the driving transistor Td to form the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through the tenth via v10 to connect to the connection electrode CNE, which is connected to the active layer ACTs of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts extends through the eleventh via v11 to connect to the support electrode SE, which is connected to the active layer ACTs of the sensing transistor Ts.

[0272] In some embodiments, reference Figure 10D The method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS, forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS, forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0273] exist Figures 10A to 10D In the manufacturing process shown, vias (sixth via v6) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, vias (tenth via v10) accommodating the first electrode Ss of the sensing transistor Ts, and vias (eleventh via v11) accommodating the second electrode Ds of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the new manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0274] In some embodiments, reference Figure 10DThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0275] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0276] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0277] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0278] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0279] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0280] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE, a support electrode SE, and a second electrode Dw for the switching transistor Tw. The connection electrode CNE is connected to the first electrode Ss of the sensing transistor Ts, to the active layer ACTs of the sensing transistor Ts, to the second capacitor electrode Ce2 of the storage capacitor, and serves as the second electrode Dd of the driving transistor Td. The support electrode SE is connected to the second electrode Ds of the sensing transistor Ts and to the active layer ACTs of the sensing transistor Ts.

[0281] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0282] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0283] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd, a first electrode Ss and a second electrode Ds of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0284] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL.

[0285] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0286] Figures 11A to 11E The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 11A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0287] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0288] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0289] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0290] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0291] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0292] In some embodiments, the method further includes forming a fourth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0293] In some embodiments, the method further includes forming a fifth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0294] In some embodiments, the method further includes forming a connection electrode layer CEL on the side of the second buffer layer BUF2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE and a second electrode Dw for forming a switching transistor Tw. The connection electrode CNE extends through a fourth via to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via to connect to the active layer ACTw of the switching transistor Tw.

[0295] In some embodiments, the method further includes forming a second semiconductor material layer SML2 on the side of the connection electrode layer CEL away from the substrate BS, forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS. In some embodiments, forming the second semiconductor material layer SML2 includes forming an active layer ACTs for a sensing transistor Ts. The active layer ACTs of the sensing transistor Ts is in direct contact with the connection electrode CNE.

[0296] In some embodiments, the method further includes forming a sixth via v6 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the sixth via v6 exposes a portion of the active layer ACTd of the driving transistor Td.

[0297] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0298] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0299] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0300] In some embodiments, the method further includes forming a tenth via v10 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The tenth via v10 exposes a portion of the connection electrode CNE. Optionally, the tenth via v10 does not expose any portion of the active layers ACTs of the sensing transistor Ts.

[0301] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0302] In some embodiments, the sixth via v6, the seventh via v7, the eighth via v8, the ninth via v9, the tenth via v10, and the twelfth via v12 are formed in the same patterning process.

[0303] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the sixth via v6. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant comprises hydrofluoric acid. In another example, the etchant comprises hydrofluoric acid and a buffer, such as ammonium fluoride.

[0304] In some embodiments, the method further includes removing an oxide layer (e.g., silicon oxide) from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6. By removing the oxide layer from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6, the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td can be reduced.

[0305] Reference Figure 11A Forming the sixth via v6 and the tenth via v10 requires only one patterning process. This is because the tenth via v10 does not expose any part of the active layer ACTs of the sensing transistor Ts. Instead, the tenth via v10 exposes a portion of the connection electrode CNE. The etchant used during the etching process does not directly contact the active layer ACTs of the sensing transistor Ts. Therefore, the etchant used during the etching process does not cause etch damage to the active layer of the sensing transistor Ts, or causes only minimal etch damage to it.

[0306] In some embodiments, reference Figure 11A and Figure 11B After removing the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is partially exposed by the sixth via v6, the method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss of the sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through the sixth via v6 to connect to the active layer ACTd of the driving transistor Td to form the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through the tenth via v10 to connect to a connection electrode CNE, which is connected to the active layer ACTs of the sensing transistor Ts.

[0307] In some embodiments, the method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS. In some embodiments, refer to... Figure 11C The method further includes forming a twentieth via v20 extending through at least one (e.g., all) of a first passivation layer PVX1, a second interlayer dielectric layer ILD2, and a third gate insulating layer GI3. The twentieth via v20 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0308] In some embodiments, refer to Figure 11C and Figure 11D The method further includes forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS. In some embodiments, forming the third signal line layer SL3 includes forming a plurality of sensing lines SL. Each sensing line of the plurality of sensing lines SL extends through a 20 via v20 to connect to the active layer ACTs of the sensing transistor Ts. A portion of each sensing line in contact with the active layer ACTs of the sensing transistor Ts serves as a second electrode Ds of the sensing transistor Ts.

[0309] In some embodiments, refer to Figure 11E The method further includes forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0310] exist Figures 11A to 11E In the manufacturing process shown, vias (sixth via v6) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, and vias (tenth via v10) accommodating the first electrode Ss of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the novel manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0311] In some embodiments, reference Figure 11EThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0312] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0313] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0314] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0315] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0316] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0317] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE and a second electrode Dw for the switching transistor Tw. The connection electrode CNE is connected to the first electrode Ss of the sensing transistor Ts, to the active layer ACTs of the sensing transistor Ts, to the second capacitor electrode Ce2 of the storage capacitor, and serves as the second electrode Dd for the driving transistor Td.

[0318] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0319] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0320] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd and a first electrode Ss of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0321] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL. Each sensing line of the plurality of sensing lines SL extends through a 20th via v20 to connect to the active layer ACTs of the sensing transistor Ts. A portion of each sensing line that contacts the active layer ACTs of the sensing transistor Ts serves as a second electrode Ds of the sensing transistor Ts.

[0322] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0323] Figures 12A to 12G The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 12A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0324] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0325] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0326] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0327] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0328] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0329] In some embodiments, the method further includes forming a second semiconductor material layer SML2 on the side of the second buffer layer BUF2 away from the substrate BS. In some embodiments, forming the second semiconductor material layer SML2 includes forming an active layer ACTs for a sensing transistor Ts.

[0330] In some embodiments, reference Figure 12B The method further includes forming a fourth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0331] In some embodiments, the method further includes forming a fifth via extending through at least one (e.g., all) of the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0332] In some embodiments, the method further includes forming a connection electrode layer CEL on the side of the second semiconductor material layer SML2 away from the substrate BS. Optionally, forming the connection electrode layer CEL includes forming a connection electrode CNE and forming a second electrode Dw for the switching transistor Tw. The connection electrode CNE is formed on the side of the active layer ACTs of the sensing transistor Ts away from the substrate BS and is in direct contact with the active layer ACTs of the sensing transistor Ts. The connection electrode CNE extends through a fourth via to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a fifth via to connect to the active layer ACTw of the switching transistor Tw.

[0333] In some embodiments, refer to Figure 12C The method further includes forming a third gate insulating layer GI3 on ​​the side of the connecting electrode layer CEL away from the substrate BS, forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS, and forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0334] In some embodiments, the method further includes forming a sixth via v6 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the sixth via v6 exposes a portion of the active layer ACTd of the driving transistor Td.

[0335] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0336] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0337] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0338] In some embodiments, the method further includes forming a 21st via v21 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2 and the third gate insulating layer GI3. The 21st via v21 exposes a portion of the connection electrode CNE. Optionally, the 21st via v21 does not expose any portion of the active layers ACTs of the sensing transistor Ts.

[0339] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0340] In some embodiments, the sixth via v6, the seventh via v7, the eighth via v8, the ninth via v9, the twenty-first via v21, and the twelfth via v12 are formed in the same patterning process.

[0341] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the sixth via v6. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant comprises hydrofluoric acid. In another example, the etchant comprises hydrofluoric acid and a buffer, such as ammonium fluoride.

[0342] In some embodiments, the method further includes removing an oxide layer (e.g., silicon oxide) from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6. By removing the oxide layer from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6, the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td can be reduced.

[0343] Reference Figure 12C Forming the sixth via v6 and the twenty-first via v21 requires only one patterning process. This is because the twenty-first via v21 does not expose any part of the active layer ACTs of the sensing transistor Ts. Instead, the twenty-first via v21 exposes a portion of the connection electrode CNE, which is located on the side of the active layer ACTs of the sensing transistor Ts away from the substrate BS. The etchant used during the etching process does not directly contact the active layer ACTs of the sensing transistor Ts. Therefore, the etchant used during the etching process does not cause etch damage to the active layer of the sensing transistor Ts, or causes only minimal etch damage.

[0344] In some embodiments, reference Figure 12C and Figure 12DAfter removing the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is partially exposed by the sixth via v6, the method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss of the sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through the sixth via v6 to connect to the active layer ACTd of the driving transistor Td to form the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through the twenty-first via v21 to connect to a connection electrode CNE, which is connected to the active layer ACTs of the sensing transistor Ts.

[0345] In some embodiments, the method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS. In some embodiments, refer to... Figure 12E The method further includes forming a twentieth via v20 extending through at least one (e.g., all) of a first passivation layer PVX1, a second interlayer dielectric layer ILD2, and a third gate insulating layer GI3. The twentieth via v20 exposes a portion of the active layers ACTs of the sensing transistors Ts.

[0346] In some embodiments, refer to Figure 12E and Figure 12F The method further includes forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS. In some embodiments, forming the third signal line layer SL3 includes forming a plurality of sensing lines SL. Each sensing line of the plurality of sensing lines SL extends through a 20 via v20 to connect to the active layer ACTs of the sensing transistor Ts. A portion of each sensing line in contact with the active layer ACTs of the sensing transistor Ts serves as a second electrode Ds of the sensing transistor Ts.

[0347] In some embodiments, refer to Figure 12G The method further includes forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0348] exist Figures 12A to 12GIn the manufacturing process shown, vias (sixth via v6) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, and vias (twenty-first via v21) accommodating the first electrode Ss of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the new manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0349] In some embodiments, reference Figure 12GThe array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a second semiconductor material layer SML2, located on the second buffer layer... BUF2 is located on the side away from the substrate BS; the connecting electrode layer CEL is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third gate insulating layer GI3 is located on the side of the connecting electrode layer CEL away from the substrate BS; the third conductive layer CT3 is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2 is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2 is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0350] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0351] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0352] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0353] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0354] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0355] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE and a second electrode Dw for the switching transistor Tw. The connection electrode CNE is connected to the first electrode Ss of the sensing transistor Ts, to the active layer ACTs of the sensing transistor Ts, to the second capacitor electrode Ce2 of the storage capacitor, to the active layer ACTd of the driving transistor Td, and serves as the second electrode Dd of the driving transistor Td.

[0356] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0357] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0358] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd and a first electrode Ss of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0359] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL. Each sensing line of the plurality of sensing lines SL extends through a 20th via v20 to connect to the active layer ACTs of the sensing transistor Ts. A portion of each sensing line that contacts the active layer ACTs of the sensing transistor Ts serves as a second electrode Ds of the sensing transistor Ts.

[0360] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0361] Figures 13A to 13H The manufacturing process of an array substrate according to some embodiments of the present disclosure is illustrated. Reference Figure 13A In some embodiments, the method includes forming a first signal line layer SL1 on a substrate BS, forming a barrier layer BAR on the side of the first signal line layer SL1 away from the substrate BS, forming a light-shielding layer LSL on the side of the barrier layer BAR away from the substrate BS, forming a first buffer layer BUF1 on the side of the light-shielding layer LSL away from the substrate BS, forming a first semiconductor material layer SML1 on the side of the first buffer layer BUF1 away from the substrate BS, forming a first gate insulating layer GI1 on the side of the first semiconductor material layer SML1 away from the substrate BS, forming a first conductive layer CT1 on the side of the first gate insulating layer GI1 away from the substrate BS, and forming a second gate insulating layer GI2 on the side of the first conductive layer CT1 away from the substrate BS.

[0362] In some embodiments, the method further includes forming a first via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0363] In some embodiments, the method further includes forming a second via extending through at least one (e.g., all) of the second gate insulating layer GI2, the first gate insulating layer GI1, and the first buffer layer BUF1.

[0364] In some embodiments, the method further includes forming a third via extending through at least one (e.g., all) of a second gate insulating layer GI2, a first gate insulating layer GI1, a first buffer layer BUF1, and a barrier layer BAR.

[0365] In some embodiments, the method further includes forming a second conductive layer CT2 on the side of the second gate insulating layer GI2 away from the substrate BS. Optionally, forming the second conductive layer CT2 includes forming a second capacitor electrode Ce2 for a storage capacitor and a first electrode Sw for a switching transistor Tw. The first electrode Sw of the switching transistor Tw extends through a first via to connect to a corresponding data line among a plurality of data lines DL located in the first signal line layer SL1, and to the active layer ACTw of the switching transistor Tw located in the first semiconductor material layer SML1. Optionally, forming the second conductive layer CT2 further includes forming connection electrodes for a first signal supply line and a second signal supply line. The connection electrodes extend through a second via and a third via, respectively, to connect to signal lines located in the light-shielding layer LSL and the first signal line layer SL1, respectively.

[0366] In some embodiments, the method further includes forming a first interlayer dielectric layer ILD1 on the side of the second conductive layer CT2 away from the substrate BS, and forming a second buffer layer BUF2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS.

[0367] In some embodiments, the method further includes forming a second semiconductor material layer SML2 on the side of the second buffer layer BUF2 away from the substrate BS and forming a third gate insulating layer GI3 on ​​the side of the second semiconductor material layer SML2 away from the substrate BS. In some embodiments, forming the second semiconductor material layer SML2 includes forming an active layer ACTs for a sensing transistor Ts.

[0368] In some embodiments, refer to Figure 13B The method further includes forming a 22nd via v22 extending through at least one (e.g., all) of the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0369] In some embodiments, the method further includes forming a twenty-third via v23 extending through at least one (e.g., all) of the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0370] In some embodiments, refer to Figure 13B and Figure 13CThe method further includes forming a third conductive layer CT3 on the side of the third gate insulating layer GI3 away from the substrate BS. Optionally, forming the third conductive layer CT3 includes forming a connection electrode CNE, forming the gate Gs of the sensing transistor Ts, and forming the second electrode Dw of the switching transistor Tw. The connection electrode CNE is formed on the side of the active layer ACTs of the sensing transistor Ts away from the substrate BS and is in direct contact with the active layer ACTs of the sensing transistor Ts. The connection electrode CNE extends through a twenty-second via v22 to connect to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2. The connection electrode CNE serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw extends through a twenty-third via v23 to connect to the active layer ACTw of the switching transistor Tw.

[0371] In some embodiments, refer to Figure 13D The method further includes forming a second interlayer dielectric layer ILD2 on the side of the third conductive layer CT3 away from the substrate BS.

[0372] In some embodiments, the method further includes forming a sixth via v6 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In some embodiments, the sixth via v6 exposes a portion of the active layer ACTd of the driving transistor Td.

[0373] In some embodiments, the method further includes forming a seventh via v7 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0374] In some embodiments, the method further includes forming an eighth via v8 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1.

[0375] In some embodiments, the method further includes forming a ninth via v9 extending through at least one (e.g., all) of the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, and the second gate insulating layer GI2.

[0376] In some embodiments, the method further includes forming a second fourteenth via v24 extending through the second interlayer dielectric layer ILD2. The second fourteenth via v24 exposes a portion of the connection electrode CNE. Optionally, the second fourteenth via v24 does not expose any portion of the active layers ACTs of the sensing transistors Ts.

[0377] In some embodiments, the method further includes forming a twelfth via v12 extending through at least the second interlayer dielectric layer ILD2.

[0378] In some embodiments, the sixth via v6, the seventh via v7, the eighth via v8, the ninth via v9, the twenty-fourth via v24, and the twelfth via v12 are formed in the same patterning process.

[0379] In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td exposed by the sixth via v6. In some embodiments, the etching process is a buffered oxide etching process. Optionally, the etching process is performed using a fluorinated reagent. In one example, the etchant comprises hydrofluoric acid. In another example, the etchant comprises hydrofluoric acid and a buffer, such as ammonium fluoride.

[0380] In some embodiments, the method further includes removing an oxide layer (e.g., silicon oxide) from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6. By removing the oxide layer from the surface of the active layer ACTd of the driving transistor Td, which is exposed by a sixth via v6, the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td can be reduced.

[0381] Reference Figure 13D Forming the sixth via v6 and the twenty-fourth via v24 requires only one patterning process. This is because the twenty-fourth via v24 does not expose any part of the active layer ACTs of the sensing transistor Ts. Instead, the twenty-fourth via v24 exposes a portion of the connection electrode CNE, which is located on the side of the active layer ACTs of the sensing transistor Ts away from the substrate BS. The etchant used during the etching process does not directly contact the active layer ACTs of the sensing transistor Ts. Therefore, the etchant used during the etching process does not cause etch damage to the active layer of the sensing transistor Ts, or causes only minimal etch damage to it.

[0382] In some embodiments, reference Figure 13D and Figure 13EAfter removing the oxide layer on the surface of the active layer ACTd of the driving transistor Td, which is partially exposed by the sixth via v6, the method further includes forming a second signal line layer SL2 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS. In some embodiments, forming the second signal line layer SL2 includes forming a plurality of first voltage supply lines Vdd, a first electrode Ss of the sensing transistor Ts, a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4. Each of the plurality of first voltage supply lines Vdd extends through the sixth via v6 to connect to the active layer ACTd of the driving transistor Td to form the first electrode Sd of the driving transistor Td. The first electrode Ss of the sensing transistor Ts extends through the twenty-first via v21 to connect to a connection electrode CNE, which is connected to the active layer ACTs of the sensing transistor Ts.

[0383] In some embodiments, reference Figure 13F The method further includes forming a first passivation layer PVX1 on the side of the second signal line layer SL2 away from the substrate BS. In some embodiments, the method further includes forming a second twentieth via v20 extending through at least one (e.g., all) of the first passivation layer PVX1, the second interlayer dielectric layer ILD2, and the third gate insulating layer GI3. The second twentieth via v20 exposes a portion of the active layers ACTs of the sensing transistor Ts.

[0384] In some embodiments, refer to Figure 13F and Figure 13G The method further includes forming a third signal line layer SL3 on the side of the first passivation layer PVX1 away from the substrate BS. In some embodiments, forming the third signal line layer SL3 includes forming a plurality of sensing lines SL. Each sensing line of the plurality of sensing lines SL extends through a 20 via v20 to connect to the active layer ACTs of the sensing transistor Ts. A portion of each sensing line in contact with the active layer ACTs of the sensing transistor Ts serves as a second electrode Ds of the sensing transistor Ts.

[0385] In some embodiments, refer to Figure 13H The method further includes forming a planarization layer PLN on the side of the third signal line layer SL3 away from the substrate BS, forming a second passivation layer PVX2 on the side of the planarization layer PLN away from the substrate BS, forming an anode layer ANL on the side of the second passivation layer PVX2 away from the substrate BS, and forming a pixel defining layer PDL on the side of the anode layer ANL away from the substrate BS.

[0386] exist Figures 13A to 13HIn the manufacturing process shown, vias (sixth via v6) accommodating a portion of a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd, and vias (twenty-fourth via v24) accommodating the first electrode Ss of the sensing transistor Ts are formed in the same patterning process. The inventors of this disclosure have discovered that the new manufacturing process not only reduces manufacturing costs but also significantly reduces the contact resistance between the active layer ACTd of the driving transistor Td and the first electrode Sd of the driving transistor Td, thereby improving the characteristics and performance of the driving transistor Td.

[0387] In some embodiments, reference Figure 13G The array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first conductive layer CT1 located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2 located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2 located on the side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1 located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2 located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; and a second semiconductor... The system comprises: a material layer SML2 located on the side of the second buffer layer BUF2 away from the substrate BS; a third gate insulating layer GI3 located on the side of the second semiconductor material layer SML2 away from the substrate BS; a third conductive layer CT3 located on the side of the third gate insulating layer GI3 away from the substrate BS; a second interlayer dielectric layer ILD2 located on the side of the third conductive layer CT3 away from the substrate BS; a second signal line layer SL2 located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; a first passivation layer PVX1 located on the side of the second signal line layer SL2 away from the substrate BS; a third signal line layer SL3 located on the side of the first passivation layer PVX1 away from the substrate BS; a planarization layer PLN located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 located on the side of the planarization layer PLN away from the substrate BS; an anode layer ANL located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL located on the side of the anode layer ANL away from the substrate BS.

[0388] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0389] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0390] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0391] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0392] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0393] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0394] In some embodiments, the third conductive layer CT3 includes a connection electrode CNE, a gate Gs of a sensing transistor Ts, and a second electrode Dw of a switching transistor Tw. The connection electrode CNE is located on the side of the active layer ACTs of the sensing transistor Ts away from the substrate BS and is in direct contact with the active layer ACTs of the sensing transistor Ts. The connection electrode CNE is connected to the first electrode Ss of the sensing transistor Ts, to the active layer ACTs of the sensing transistor Ts, to the second capacitor electrode Ce2 of the storage capacitor located in the second conductive layer CT2, and to the active layer ACTd of the driving transistor Td located in the first semiconductor material layer SML1, and serves as the second electrode Dd of the driving transistor Td. The second electrode Dw of the switching transistor Tw is connected to the active layer ACTw of the switching transistor Tw.

[0395] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd and a first electrode Ss of a sensing transistor Ts. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0396] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL. Each sensing line of the plurality of sensing lines SL extends through a 20th via v20 to connect to the active layer ACTs of the sensing transistor Ts. A portion of each sensing line that contacts the active layer ACTs of the sensing transistor Ts serves as a second electrode Ds of the sensing transistor Ts.

[0397] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0398] Reference Figure 10D , Figure 11E , Figure 12G and Figure 13H In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits, wherein each pixel driving circuit includes a driving transistor Td, a sensing transistor Ts, and a storage capacitor. In some embodiments, the array substrate includes a substrate BS; an active layer ACTd of the driving transistor Td located on the substrate BS; a second capacitor electrode of the storage capacitor located on the side of the active layer ACTd of the driving transistor Td away from the substrate BS; an active layer ACTs of the connecting electrode CNE and the sensing transistor Ts located on the side of the second capacitor electrode away from the substrate BS; and a first electrode Ss and a second electrode Ds of the sensing transistor Ts located on the side of the active layer ACTs of the connecting electrode CNE and the sensing transistor Ts away from the substrate BS.

[0399] In some embodiments, the connection electrode CNE extends through a via to connect to the active layer ACTd of the driving transistor Td and to the second capacitor electrode, the via extending through one or more insulating layers. The connection electrode CNE is connected to the active layer ACTs of the sensing transistor Ts and to the first electrode Ss of the sensing transistor Ts.

[0400] In some embodiments, the first electrode Ss of the sensing transistor Ts is in direct contact with the connection electrode CNE, and the connection electrode CNE is in direct contact with the active layer ACTs of the sensing transistor Ts. Alternatively, the first electrode Ss of the sensing transistor Ts is not in direct contact with the active layer ACTs of the sensing transistor Ts.

[0401] In some embodiments, each pixel driving circuit further includes a switching transistor Tw. In some embodiments, the connection electrode CNE and the second electrode Dw of the switching transistor Tw are located in the same layer. As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, the connection electrode CNE and the second electrode Dw of the switching transistor Tw are located in the same layer when they are formed as a result of one or more steps of the same patterning process performed on material deposited in the same deposition process. In another example, the connection electrode CNE and the second electrode Dw of the switching transistor Tw can be formed in the same layer by simultaneously performing the steps of forming the connection electrode CNE and forming the second electrode Dw of the switching transistor Tw. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0402] In some embodiments, the gate Gs of the sensing transistor Ts is located on the side of the second electrode Dw of the connecting electrode CNE and the switching transistor Tw that is away from the substrate BS. Figure 10D , Figure 11E and Figure 12G In an alternative embodiment, the connecting electrode CNE, the second electrode Dw of the switching transistor Tw, and the gate Gs of the sensing transistor Ts are located on the same layer. Figure 13H ).

[0403] In some embodiments, refer to Figure 10D , Figure 11E and Figure 12G The connecting electrode CNE extends through the second buffer layer BUF2 and the first interlayer dielectric layer ILD1 to connect to the second capacitor electrode Ce2, and extends through the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to connect to the active layer ACTd of the driving transistor Td. In an alternative embodiment, refer to... Figure 13HThe connecting electrode CNE extends through the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, and the first interlayer dielectric layer ILD1 to connect to the second capacitor electrode Ce2, and extends through the second interlayer dielectric layer ILD2, the third gate insulating layer GI3, the second buffer layer BUF2, the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to connect to the active layer ACTd of the driving transistor Td.

[0404] In some embodiments, refer to Figure 10D and Figure 11E The active layer ACTs of the sensing transistor Ts and the first electrode Ss of the sensing transistor Ts are located on the same side of the connection electrode CNE away from the substrate BS. In an alternative embodiment, refer to Figure 12G and Figure 13H The active layer ACTs of the sensing transistor Ts and the first electrode Ss of the sensing transistor Ts are located on opposite sides of the connecting electrode CNE.

[0405] In some embodiments, refer to Figure 11E , Figure 12G and Figure 13H The second electrode Ds of the sensing transistor Ts is in direct contact with the active layer ACTs of the sensing transistor Ts. In an alternative embodiment, reference... Figure 10D The array substrate also includes a support electrode SE. The support electrode SE is in direct contact with the active layer ACTs of the sensing transistor Ts and with the second electrode Ds of the sensing transistor Ts. The second electrode Ds of the sensing transistor Ts is not in direct contact with the active layer ACTs of the sensing transistor Ts. Optionally, each pixel driving circuit also includes a switching transistor Tw; the support electrode SE, the connection electrode CNE, and the second electrode Dw of the switching transistor Tw are located on the same layer.

[0406] In some embodiments, refer to Figure 10D , Figure 11E , Figure 12G and Figure 13H The array substrate also includes multiple first voltage supply lines Vdd located on the side of the active layer ACTs that connects the electrode CNE and the sensing transistor Ts, away from the substrate BS. Each of the multiple first voltage supply lines Vdd extends through multiple insulating layers to connect to the active layer ACTd of the driving transistor Td. A portion of each first voltage supply line serves as the first electrode of the driving transistor Td.

[0407] Reference Figure 6E , Figure 7F and Figure 8FIn another aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits, wherein each pixel driving circuit includes a driving transistor Td, a sensing transistor Ts, and a storage capacitor. In some embodiments, the array substrate includes a substrate BS; an active layer ACTd of the driving transistor Td located on the substrate BS; a second capacitor electrode of the storage capacitor located on the side of the active layer ACTd of the driving transistor Td away from the substrate BS; an active layer ACTs connecting the electrode CNE and the sensing transistor Ts located on the side of the second capacitor electrode away from the substrate BS; and a plurality of first voltage supply lines Vdd located on the side of the active layer ACTs connecting the electrode CNE and the sensing transistor Ts away from the substrate BS.

[0408] In some embodiments, the connection electrode CNE extends through a via to connect to the active layer ACTd of the driving transistor Td and to the second capacitor electrode, the via extending through one or more insulating layers. The connection electrode CNE is connected to the active layer ACTs of the sensing transistor Ts and to the first electrode Ss of the sensing transistor Ts.

[0409] In some embodiments, each of the plurality of first voltage supply lines Vdd extends through one or more insulating layers to connect to the first electrode Sd of the driving transistor Td.

[0410] In some embodiments, the first electrode Sd of the driving transistor Td and the second capacitor electrode Ce2 are located on the same layer. In an alternative embodiment, the first electrode Sd of the driving transistor Td and the connection electrode CNE are located on the same layer.

[0411] Reference Figures 6A to 6E , Figures 7A to 7F , Figures 8A to 8F , Figures 9A to 9C , Figures 10A to 10D , Figures 11A to 11E , Figures 12A to 12G as well as Figures 13A to 13HIn another aspect, this disclosure provides a method for fabricating an array substrate. In some embodiments, the method includes forming a plurality of pixel driving circuits. In some embodiments, each pixel driving circuit in forming the plurality of pixel driving circuits includes forming a driving transistor Td, forming a sensing transistor Ts, and forming a storage capacitor. In some embodiments, the method includes forming an active layer ACTd of the driving transistor Td on a substrate BS, forming a second capacitor electrode of the storage capacitor on the side of the active layer ACTd of the driving transistor Td away from the substrate BS, forming an active layer ACTd connecting an electrode CNE and a sensing transistor Ts on the side of the second capacitor electrode away from the substrate BS, forming a first electrode Ss and a second electrode Ds of the sensing transistor Ts on the side of the active layer ACTs connecting the electrode CNE and the sensing transistor Ts away from the substrate BS, and forming a plurality of first voltage supply lines Vdd on the side of the active layer ACTs connecting the electrode CNE and the sensing transistor Ts away from the substrate BS.

[0412] In some embodiments, the method further includes forming vias configured to accommodate portions of a respective first voltage supply line among a plurality of first voltage supply lines Vdd, and forming vias configured to accommodate a first electrode Ss or a second electrode Ds of a sensing transistor Ts. Optionally, the vias configured to accommodate portions of a respective first voltage supply line and the vias configured to accommodate the first electrode Ss or the second electrode Ds of the sensing transistor Ts are formed in the same patterning process.

[0413] In some embodiments, a via configured to accommodate a portion of a corresponding first voltage supply line, a via configured to accommodate a first electrode Ss of a sensing transistor Ts, and a via configured to accommodate a second electrode Ds of the sensing transistor Ts are formed in the same patterning process. In an alternative embodiment, the via configured to accommodate a portion of a corresponding first voltage supply line and the via configured to accommodate a first electrode Ss of the sensing transistor Ts are formed in the same patterning process; the via configured to accommodate a second electrode Ds of the sensing transistor Ts is formed in a different patterning process than the via configured to accommodate a portion of a corresponding first voltage supply line and the via configured to accommodate a first electrode Ss of the sensing transistor Ts.

[0414] In some embodiments, refer to Figure 6E , Figure 7F and Figure 8FThe method includes forming a via configured to accommodate a first electrode Sd of a driving transistor Td, thereby exposing a portion of an active layer ACTd of the driving transistor Td; etching the portion of the active layer ACTd of the driving transistor Td to remove an oxide layer on the surface of the portion of the active layer ACTd of the driving transistor Td; wherein, after performing the etching process, the via configured to accommodate the portion of the corresponding first voltage supply line and the via configured to accommodate the first electrode Ss or the second electrode Ds of the sensing transistor Ts are formed in the same patterning process.

[0415] In some embodiments, the etching process is a buffered oxide etching process using an etchant solution.

[0416] In some embodiments, forming the respective pixel driving circuitry further includes forming a switching transistor Tw. In some embodiments, the method further includes forming a via configured to receive a first electrode Sw of the switching transistor Tw. In some embodiments, refer to... Figure 6E The formation of vias configured to accommodate the first electrode Sd of the driving transistor Td and the formation of vias configured to accommodate the first electrode Sw of the switching transistor Tw are performed in the same patterning process.

[0417] In some embodiments, reference Figures 6A to 6E , Figures 7A to 7F , Figures 8A to 8F , Figures 9A to 9C , Figures 10A to 10D , Figures 11A to 11E , Figures 12A to 12G as well as Figures 13A to 13H The method further includes forming a via extending through one or more insulating layers, wherein a connection electrode CNE extends through the via to connect to the active layer ACTd of the driving transistor Td, and to a second capacitor electrode, the via extending through one or more insulating layers. The connection electrode CNE is connected to the active layer ACTs of the sensing transistor Ts, and to a first electrode Ss of the sensing transistor Ts.

[0418] In some embodiments, reference Figures 8A to 8F The formation of a via configured to accommodate the first electrode Sd of the driving transistor Td and the formation of a via configured to accommodate the connection electrode CNE are performed in the same patterning process.

[0419] In some embodiments, forming the respective pixel driving circuitry further includes forming a switching transistor Tw. In some embodiments, the method further includes forming a via configured to accommodate a second electrode Dw of the switching transistor Tw. In some embodiments, forming a via configured to accommodate a first electrode Sd of a driving transistor Td, forming a via configured to accommodate a connection electrode CNE, and forming a via configured to accommodate a second electrode Dw of the switching transistor Tw are performed in the same patterning process.

[0420] In some embodiments, reference Figures 9A to 9C The method involves forming vias configured to accommodate portions of a corresponding first voltage supply line, exposing a portion of the active layer ACTd of a driving transistor Td. In some embodiments, the method further includes performing a dry etching process on a portion of the active layer ACTd of the driving transistor Td to remove an oxide layer on the surface of the portion of the active layer ACTd of the driving transistor Td. In some embodiments, the method further includes forming a corresponding first voltage supply line and forming a first electrode Ss or a second electrode Ds of a sensing transistor Ts in the same patterning process after performing the dry etching process. Each first voltage supply line is in direct contact with the active layer ACTd of the driving transistor Td and serves as the first electrode Sd of the driving transistor Td.

[0421] In some embodiments, a dry etching process is performed using a fluorine-containing gas.

[0422] In some embodiments, reference Figures 10A to 10D , Figures 11A to 11E , Figures 12A to 12G ,as well as Figures 13A to 13H The method involves forming a via configured to accommodate a portion of a corresponding first voltage supply line, exposing a portion of the active layer ACTd of the driving transistor Td; and forming a via configured to accommodate a first electrode Ss of the sensing transistor Ts, exposing a portion of the connection electrode CNE, but not exposing any portion of the active layer ACTs of the sensing transistor Ts. The formation of the via configured to accommodate a portion of the corresponding first voltage supply line and the formation of the via configured to accommodate the first electrode Ss of the sensing transistor Ts are performed in the same patterning process. In some embodiments, the method further includes performing an etching process on a portion of the active layer ACTd of the driving transistor Td to remove an oxide layer on the surface of the portion of the active layer ACTd of the driving transistor Td. The connection electrode CNE is connected to the active layer ACTd of the driving transistor Td, connected to a second capacitor electrode, and connected to the active layer ACTs of the sensing transistor Ts.

[0423] In some embodiments, the etching process is a buffered oxide etching process using an etchant solution.

[0424] In some embodiments, the method further includes forming the first electrode Ss of each first voltage supply line and sensing transistor Ts in the same patterning process after performing the etching process.

[0425] In some embodiments, reference Figures 10A to 10D The method further includes forming a support electrode SE and an active layer ACTs on the support electrode SE for forming a sensing transistor Ts. The support electrode SE is in direct contact with the active layer ACTs of the sensing transistor Ts. In some embodiments, the method further includes forming a via configured to receive a second electrode Ds of the sensing transistor Ts, exposing a portion of the support electrode SE but not any portion of the active layer ACTs of the sensing transistor Ts. Forming the via configured to receive the portion of a corresponding first voltage supply line, forming the via configured to receive the first electrode Ss of the sensing transistor Ts, and forming the via configured to receive the second electrode Ds of the sensing transistor Ts are performed in the same patterning process.

[0426] In some embodiments, the method further includes forming, in the same patterning process, respective first voltage supply lines, first electrodes Ss of sensing transistors Ts, and second electrodes Ds of sensing transistors Ts after performing the etching process.

[0427] In some embodiments, the active layers ACTs that form the sensing transistors Ts are performed after the support electrodes SE are formed.

[0428] In some embodiments, refer to Figures 11A to 11E , Figures 12A to 12G as well as Figures 13A to 13H The method further includes forming a plurality of sensing lines SL after forming a first electrode Ss of a sensing transistor Ts. Each sensing line of the plurality of sensing lines SL extends through a plurality of insulating layers to connect to the active layers ACTs of the sensing transistor Ts. A portion of each sensing line serves as a second electrode Ds of the sensing transistor Ts.

[0429] In some embodiments, refer to Figures 10A to 10D and Figures 11A to 11E After forming the connection electrode CNE, the active layer ACTs of the sensing transistor Ts is formed. In an alternative embodiment, refer to... Figures 12A to 12G and Figures 13A to 13H After forming the active layer ACTs of the sensing transistor Ts, the connection electrode CNE is formed.

[0430] Figure 14 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 14In some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of a fourth transistor T4 and the anode of the light-emitting element LE; a third reset transistor Tr3 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; and a first crystal. Transistor T1 (e.g., a data write transistor) has a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of a driving transistor Td; a second transistor T2 (e.g., a compensation transistor) has a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to a first capacitor electrode Ce1 of a storage capacitor Cst and a gate of a driving transistor Td, and a second electrode connected to a second electrode of a driving transistor Td; a third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding first voltage supply line Vdd among a plurality of first voltage supply lines, and a second electrode connected to a first electrode of a driving transistor Td and a second electrode of a first transistor T1; and a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a second electrode of a driving transistor Td and a second transistor T2, and a second electrode connected to the anode of a light-emitting element LE and a second electrode of a second reset transistor Tr2. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0431] refer to Figure 14In an alternative embodiment, the first reset transistor Tr1 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. In another alternative embodiment, the fourth transistor T4 is an n-type transistor, such as a MOS transistor, while the other transistors are p-type transistors, such as polysilicon transistors. In yet another alternative embodiment, the second reset transistor Tr2 is an n-type transistor, such as a MOS transistor, while the other transistors are p-type transistors, such as polysilicon transistors. In yet another alternative embodiment, one or more of the first reset transistor Tr1, the second transistor T2, the fourth transistor T4, and the second reset transistor Tr2 are n-type transistors, such as MOS transistors, while the other transistors are p-type transistors, such as polysilicon transistors.

[0432] Figure 15 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Reference Figure 15The array substrate includes a substrate BS; a first signal line layer SL1 located on the substrate BS; a barrier layer BAR located on the side of the first signal line layer SL1 away from the substrate BS; a light-shielding layer LSL located on the side of the barrier layer BAR away from the substrate BS; a first buffer layer BUF1 located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the first buffer layer BUF1 away from the substrate BS; and a first gate insulating layer GI1 located on the side of the first semiconductor material layer SML1 away from the substrate BS. One side of the substrate BS; a first conductive layer CT1, located on the side of the first gate insulating layer GI1 away from the substrate BS; a second gate insulating layer GI2, located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2, located on one side of the second gate insulating layer GI2; a first interlayer dielectric layer ILD1, located on the side of the second conductive layer CT2 away from the substrate BS; a second buffer layer BUF2, located on the side of the first interlayer dielectric layer ILD1 away from the substrate BS; a connecting electrode layer CEL, located on the second buffer layer BUF2. The side away from the substrate BS; the second semiconductor material layer SML2, which is located on the side of the connecting electrode layer CEL away from the substrate BS; the third gate insulating layer GI3, which is located on the side of the second semiconductor material layer SML2 away from the substrate BS; the third conductive layer CT3, which is located on the side of the third gate insulating layer GI3 away from the substrate BS; the second interlayer dielectric layer ILD2, which is located on the side of the third conductive layer CT3 away from the substrate BS; the second signal line layer SL2, which is located on the side of the second interlayer dielectric layer ILD2 away from the substrate BS; the first The passivation layer PVX1 is located on the side of the second signal line layer SL2 away from the substrate BS; the third signal line layer SL3 is located on the side of the first passivation layer PVX1 away from the substrate BS; the planarization layer PLN is located on the side of the third signal line layer SL3 away from the substrate BS; the second passivation layer PVX2 is located on the side of the planarization layer PLN away from the substrate BS; the anode layer ANL is located on the side of the second passivation layer PVX2 away from the substrate BS; and the pixel defining layer PDL is located on the side of the anode layer ANL away from the substrate BS.

[0433] In some embodiments, the first signal line layer SL1 includes a plurality of data lines DL. Each of the plurality of data lines DL is connected to the first electrode of the switching transistor Tw.

[0434] In some embodiments, the light-shielding layer LSL includes a plurality of first light-shielding elements LS1. The orthographic projection of each of the plurality of first light-shielding elements LS1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate.

[0435] In some embodiments, the first semiconductor material layer SML1 includes an active layer ACTd for driving transistors and / or an active layer ACTw for switching transistors Tw.

[0436] In some embodiments, the first conductive layer CT1 includes the gate Gd of the driving transistor Td and / or the gate Gw of the switching transistor Tw. In some embodiments, the first conductive layer CT1 includes a plurality of second light-shielding elements LS2. The orthographic projection of each of the plurality of second light-shielding elements LS2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTs of the sensing transistor Ts onto the substrate.

[0437] In some embodiments, the second conductive layer CT2 includes a first electrode Sw of the switching transistor Tw, a first electrode Sd of the driving transistor Td, and a second capacitor electrode Ce2 of the storage capacitor. Optionally, the gate Gd serves as the first capacitor electrode of the storage capacitor.

[0438] In some embodiments, the connection electrode layer CEL includes a connection electrode CNE and a second electrode Dw of the switching transistor Tw. The connection electrode CNE is connected to the first electrode S3 of the third transistor T3, serves as the second electrode Dd of the driving transistor Td, and also serves as the first electrode S3 of the third transistor T3.

[0439] In some embodiments, the second semiconductor material layer SML2 includes the active layer ACTs of the sensing transistors Ts.

[0440] In some embodiments, the third conductive layer CT3 includes the gate Gs of the sensing transistor Ts.

[0441] In some embodiments, the second signal line layer SL2 includes a plurality of first voltage supply lines Vdd and a second electrode D3 of the third transistor T3. Optionally, the second signal line layer SL2 further includes a first signal supply line SSL1, a second signal supply line SSL2, a third signal supply line SSL3, and a fourth signal supply line SSL4 in the peripheral region PA. The first signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the first signal line layer SL1. The second signal supply line SSL2 is configured to supply a voltage signal to one or more signal lines located in the light-shielding layer LSL. The third signal supply line SSL3 is configured to supply a voltage signal to one or more signal lines located in the first conductive layer CT1. The fourth signal supply line SSL1 is configured to supply a voltage signal to one or more signal lines located in the third conductive layer CT3.

[0442] In some embodiments, the third signal line layer SL3 includes a plurality of sensing lines SL.

[0443] In some embodiments, the anode layer ANL includes a plurality of anode ANDs located in a plurality of sub-pixels.

[0444] Reference Figure 10D , Figure 11E , Figure 12G , Figure 13H and Figure 15 In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits, wherein each pixel driving circuit includes a driving transistor Td, a first switching transistor (e.g., Figure 10D , Figure 11E , Figure 12G , Figure 13H The sensing transistor Ts in the middle; or Figure 15 The array substrate includes a second transistor T2 and a storage capacitor. In some embodiments, the array substrate includes a substrate BS; an active layer ACTd of a driving transistor Td located on the substrate BS; a second capacitor electrode of the storage capacitor located on the side of the active layer ACTd of the driving transistor Td away from the substrate BS; an active layer connecting the electrode CNE and the first switching transistor located on the side of the second capacitor electrode away from the substrate BS; and a first electrode Ss and a second electrode of the first switching transistor located on the side of the active layer connecting the electrode CNE and the first switching transistor away from the substrate BS.

[0445] In some embodiments, the connection electrode CNE extends through a via to connect to the active layer ACTd of the driving transistor Td, the via extending through one or more insulating layers. The connection electrode CNE is connected to the active layer of the first switching transistor and to the first electrode of the first switching transistor.

[0446] In some embodiments, the first electrode of the first switching transistor is in direct contact with the connection electrode CNE, and the connection electrode CNE is in direct contact with the active layer of the first switching transistor.

[0447] In an alternative embodiment, when the first switching transistor is an n-type transistor, it can be any one of the first reset transistor Tr1, the fourth transistor T4, and the second reset transistor Tr2.

[0448] In another aspect, this disclosure provides a display device comprising an array substrate manufactured as described herein or by methods thereof, and one or more integrated circuits connected to said array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. In one example, the display device is an augmented reality or virtual reality display device.

[0449] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising multiple pixel driving circuits; in, Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a first switching transistor, and a storage capacitor. The array substrate includes: Substrate; The active layer of the driving transistor is located on the substrate. The second capacitor electrode of the storage capacitor is located on the side of the active layer of the driving transistor away from the substrate. An active layer connecting the electrode and the first switching transistor is located on the side of the second capacitor electrode away from the substrate; and The first electrode and the second electrode of the first switching transistor are located on the side of the connection electrode and the active layer of the first switching transistor away from the substrate. The connection electrode extends through a via to connect to the active layer of the driving transistor, and the via extends through one or more insulating layers. The connection electrode is connected to the active layer of the first switching transistor and to the first electrode of the first switching transistor; The first electrode of the first switching transistor is in direct contact with the connection electrode; and The connection electrode is in direct contact with the active layer of the first switching transistor.

2. The array substrate according to claim 1, wherein, Each pixel driving circuit also includes a switching transistor; and The connecting electrode and the second electrode of the switching transistor are located on the same layer.

3. The array substrate according to claim 2, wherein, The gate of the first switching transistor is located on the side of the connection electrode and the second electrode of the switching transistor away from the substrate.

4. The array substrate according to claim 2, wherein, The connecting electrode, the second electrode of the switching transistor, and the gate of the first switching transistor are located on the same layer.

5. The array substrate according to any one of claims 1 to 4, wherein, The connection electrode extends through the second buffer layer and the first interlayer dielectric layer to connect to the second capacitor electrode, and extends through the second buffer layer, the first interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to connect to the active layer of the driving transistor.

6. The array substrate according to any one of claims 1 to 4, wherein, The connection electrode extends through the second interlayer dielectric layer, the third gate insulating layer, the second buffer layer, and the first interlayer dielectric layer to connect to the second capacitor electrode, and extends through the second interlayer dielectric layer, the third gate insulating layer, the second buffer layer, the first interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to connect to the active layer of the driving transistor.

7. The array substrate according to any one of claims 1 to 4, wherein, The active layer of the first switching transistor and the first electrode of the first switching transistor are located on the same side of the connecting electrode away from the substrate.

8. The array substrate according to any one of claims 1 to 4, wherein, The active layer of the first switching transistor and the first electrode of the first switching transistor are located on opposite sides of the connection electrode.

9. The array substrate according to any one of claims 1 to 4, wherein, The second electrode of the first switching transistor and the first electrode of the driving transistor are located on the same layer; At least one of the second electrode of the first switching transistor or the first electrode of the driving transistor is not in direct contact with the corresponding active layer. as well as The first switching transistor and the driving transistor are different types of transistors selected from n-type transistors and p-type transistors.

10. The array substrate according to any one of claims 1 to 4, wherein, The second electrode of the first switching transistor and the first electrode of the driving transistor are located on different layers; The second electrode of the first switching transistor is in direct contact with the active layer of the first switching transistor; The first electrode of the driving transistor is in direct contact with the active layer of the driving transistor; as well as The first switching transistor and the driving transistor are different types of transistors selected from n-type transistors and p-type transistors.

11. The array substrate according to any one of claims 1 to 4, wherein, The first electrode of the first switching transistor is not in direct contact with the active layer of the first switching transistor.

12. The array substrate according to any one of claims 1 to 4, wherein, The connection electrode extends through the via to connect to the second capacitor electrode, the via extending through the one or more insulating layers.

13. The array substrate according to any one of claims 1 to 4, wherein, The second electrode of the first switching transistor is in direct contact with the active layer of the first switching transistor.

14. The array substrate according to any one of claims 1 to 4, wherein, The array substrate also includes supporting electrodes; The supporting electrode is in direct contact with the active layer of the first switching transistor and in direct contact with the second electrode of the first switching transistor. The second electrode of the first switching transistor is not in direct contact with the active layer of the first switching transistor; Each pixel driving circuit also includes a switching transistor; and The supporting electrode, the connecting electrode, and the second electrode of the switching transistor are located on the same layer.

15. The array substrate according to any one of claims 1 to 4, wherein, The array substrate also includes a plurality of signal lines located on the side of the active layer of the connecting electrode and the first switching transistor away from the substrate. Each of the plurality of signal lines extends through a plurality of insulating layers to connect to the active layer of the driving transistor; as well as A portion of each signal line serves as the first electrode of the driving transistor.

16. An array substrate comprising multiple pixel driving circuits; in, Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a first switching transistor, and a storage capacitor. The array substrate includes: Substrate; The active layer of the driving transistor is located on the substrate. The second capacitor electrode of the storage capacitor is located on the side of the active layer of the driving transistor away from the substrate. An active layer connecting the electrode and the first switching transistor is located on the side of the second capacitor electrode away from the substrate; and Multiple signal lines are located on the side of the active layer of the connecting electrode and the first switching transistor away from the substrate. The connection electrode extends through a via to connect to the active layer of the driving transistor, and the via extends through one or more insulating layers. The connection electrode is connected to the active layer of the first switching transistor and to the first electrode of the first switching transistor; and Each of the plurality of signal lines extends through one or more insulating layers to connect to the first electrode of the driving transistor.

17. The array substrate according to claim 12, wherein, The first electrode and the second capacitor electrode of the driving transistor are located on the same layer.

18. The array substrate according to claim 12, wherein, The first electrode and the connection electrode of the driving transistor are located on the same layer.

19. A display device comprising an array substrate according to any one of claims 1 to 14, and one or more integrated circuits connected to the array substrate.

20. A method of manufacturing an array substrate, comprising forming a plurality of pixel driving circuits; in, Each pixel driving circuit in the plurality of pixel driving circuits includes forming a driving transistor, forming a first switching transistor, and forming a storage capacitor; The method includes: An active layer of the driving transistor is formed on a substrate. A second capacitor electrode of the storage capacitor is formed on the side of the active layer of the driving transistor away from the substrate. An active layer connecting the second capacitor electrode and the first switching transistor is formed on the side of the second capacitor electrode away from the substrate. A first electrode and a second electrode of the first switching transistor are formed on the side of the active layer away from the substrate, where the connecting electrode and the first switching transistor are located; and Multiple signal lines are formed on the side of the active layer of the connecting electrode and the first switching transistor away from the substrate. The method further includes: Forming vias, the vias being configured to accommodate a portion of a respective signal line among the plurality of signal lines; and A via is formed, the via being configured to accommodate the first electrode or the second electrode of the first switching transistor; The vias configured to accommodate portions of the corresponding signal lines and the vias configured to accommodate the first electrode or the second electrode of the first switching transistor are formed in the same patterning process.

21. The method according to claim 20, wherein, The via configured to accommodate the portion of the corresponding signal line, the via configured to accommodate the first electrode of the first switching transistor, and the via configured to accommodate the second electrode of the first switching transistor are formed in the same patterning process.

22. The method according to claim 20, wherein, The via configured to accommodate the portion of the corresponding signal line and the via configured to accommodate the first electrode of the first switching transistor are formed in the same patterning process; as well as The via configured to accommodate the second electrode of the first switching transistor, the via configured to accommodate the portion of the corresponding signal line, and the via configured to accommodate the first electrode of the first switching transistor are formed in different patterning processes.

23. The method according to any one of claims 20 to 22, comprising: A via is formed, the via being configured to accommodate a first electrode of the driving transistor, thereby exposing a portion of the active layer of the driving transistor; as well as An etching process is performed on the portion of the active layer of the driving transistor to remove the oxide layer on the surface of the portion of the active layer of the driving transistor; In the same patterning process, after the etching process is performed, vias configured to accommodate the portions of the corresponding signal lines and vias configured to accommodate the first electrode or the second electrode of the first switching transistor are formed.

24. The method according to claim 23, wherein, The etching process is a buffered oxide etching process using an etchant solution.

25. The method according to any one of claims 20 to 24, wherein, Forming the pixel driving circuits further includes forming switching transistors; The method further includes forming a via configured to accommodate a first electrode of the switching transistor; In the same patterning process, the via configured to accommodate the first electrode of the driving transistor and the via configured to accommodate the first electrode of the switching transistor are formed.

26. The method according to any one of claims 20 to 25, further comprising forming a via extending through one or more insulating layers; in, The connection electrode extends through the via to connect to the active layer of the driving transistor and to the second capacitor electrode, the via extending through the one or more insulating layers; as well as The connection electrode is connected to the active layer of the first switching transistor and to the first electrode of the first switching transistor.

27. The method according to claim 26, wherein, In the same patterning process, the via configured to accommodate the first electrode of the driving transistor and the via configured to accommodate the connection electrode are formed.

28. The method according to claim 26, wherein, Forming the pixel driving circuits further includes forming switching transistors; The method further includes forming a via, the via being configured to accommodate a second electrode of the switching transistor; In the same patterning process, the via configured to accommodate the first electrode of the driving transistor, the via configured to accommodate the connection electrode, and the via configured to accommodate the second electrode of the switching transistor are formed.

29. The method according to claim 26, wherein, The via, configured to accommodate a portion of the corresponding signal line, exposes a portion of the active layer of the driving transistor; The method further includes performing a dry etching process on the portion of the active layer of the driving transistor to remove the oxide layer on the surface of the portion of the active layer of the driving transistor. Wherein, after performing the dry etching process, in the same patterning process, the corresponding signal lines and the first or second electrode of the first switching transistor are formed; and Each signal line is in direct contact with the active layer of the driving transistor and serves as the first electrode of the driving transistor.

30. The method according to claim 27, wherein, The dry etching process is performed using a fluorine-containing gas.

31. The method according to any one of claims 20 to 25, wherein, The via, configured to accommodate a portion of the corresponding signal line, exposes a portion of the active layer of the driving transistor; The via configured to accommodate the first electrode of the first switching transistor exposes a portion of the connection electrode but does not expose any portion of the active layer of the first switching transistor; as well as In the same patterning process, the via configured to accommodate the portion of the corresponding signal line and the via configured to accommodate the first electrode of the first switching transistor are formed. The method further includes performing an etching process on the portion of the active layer of the driving transistor to remove the oxide layer on the surface of the portion of the active layer of the driving transistor. as well as The connection electrode is connected to the active layer of the driving transistor, to the second capacitor electrode, and to the active layer of the first switching transistor.

32. The method according to claim 31, wherein, The etching process is a buffered oxide etching process using an etchant solution.

33. The method of claim 31, further comprising forming the corresponding signal line and the first electrode of the first switching transistor in the same patterning process after performing the etching process.

34. The method according to any one of claims 31 to 33, further comprising: Form a supporting electrode; as well as The active layer of the first switching transistor is formed on the supporting electrode; The supporting electrode is in direct contact with the active layer of the first switching transistor; The method further includes forming a via configured to accommodate the second electrode of the first switching transistor to expose a portion of the supporting electrode but not any portion of the active layer of the first switching transistor; In the same patterning process, the vias configured to accommodate the portions of the corresponding signal lines, the vias configured to accommodate the first electrode of the first switching transistor, and the vias configured to accommodate the second electrode of the first switching transistor are formed.

35. The method of claim 34, further comprising, after performing the etching process, forming the corresponding signal line, the first electrode of the first switching transistor, and the second electrode of the first switching transistor in the same patterning process.

36. The method according to claim 34, wherein, After the support electrode is formed, the active layer for forming the first switching transistor is performed.

37. The method according to any one of claims 31 to 33, further comprising forming a plurality of sensing lines after forming the first electrode of the first switching transistor; in, Each of the plurality of sensing lines extends through a plurality of insulating layers to connect to the active layer of the first switching transistor; as well as A portion of each sensing line serves as the second electrode of the first switching transistor.

38. The method according to any one of claims 31 to 33, wherein, After the connection electrode is formed, the active layer for forming the first switching transistor is performed.

39. The method according to any one of claims 31 to 33, wherein, After the active layer of the first switching transistor is formed, the connection electrode is formed.

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