A wide-range 1PPS time difference measurement method, system, device and medium

Abstract

This application provides a wide-range 1PPS time difference measurement method, system, device, and medium. The method includes: acquiring a first 1PPS signal and a second 1PPS signal; conditioning and synchronizing the two 1PPS signals respectively; inputting the processed two 1PPS signals into a multi-phase sampling module for multi-phase sampling to generate an M-phase base clock sequence for phase interpolation; a high-linearity multi-phase clock interpolator, based on a phase control word, performs multi-phase weighted mixing based on a target phase interpolation clock on the M-phase base clock sequence; triggering time measurements when the first 1PPS signal and the second 1PPS signal arrive respectively, forming a first timestamp for the first 1PPS signal and a second timestamp for the second 1PPS signal respectively; and generating a time difference measurement result for the two 1PPS signals based on the difference between the first timestamp and the second timestamp. This application achieves wide dynamic range and high-precision 1PPS time difference measurement.

Description

Technical Field

[0001] This application relates to the field of electronic measurement technology, and in particular to a wide-range 1PPS time difference measurement method, system, device and medium. Background Technology

[0002] With the increasing demands for time synchronization accuracy in applications such as satellite navigation systems, distributed scientific experiments, and high-speed communication networks, higher precision and measurement range requirements are being placed on the measurement of time differences between 1-second pulse (1PPS) signals. Field-programmable gate arrays (FPGAs), due to their reconfigurability, strong parallel processing capabilities, and abundant internal resources, have become an important platform for achieving high-precision time interval measurement. Existing FPGA-based time-to-digital converters (TDCs) often employ direct counting, digital delay chain, or clock multi-phase sampling methods, but they still have significant limitations in simultaneously achieving high precision and wide measurement range.

[0003] Common time interval measurement methods in the prior art include the following categories:

[0004] TDC technology based on digital delay chain

[0005] This technique utilizes the inherent delays of internal logic units or wiring within an FPGA to form a delay chain, obtaining the time interval by detecting the propagation positions of start and stop signals within the delay chain. Theoretically, this type of method can achieve high resolution, but the delay chain is significantly affected by process, voltage, and temperature variations (PVT), resulting in poor linearity, a limited measurement range, and making it unsuitable for achieving long-term stable wide-range measurements.

[0006] TDC technology based on clock multiplexing

[0007] These methods typically rely on an external clock management chip to generate multiple clocks of the same frequency but different phases for multi-phase sampling of the same signal, thereby refining the time measurement resolution. Although this method offers better linearity than delay chain schemes, it requires the construction of complex external multi-phase clock generation and distribution circuitry, resulting in high hardware costs and system complexity. Furthermore, the phase relationship between the multiple clocks is easily affected by PCB routing and signal integrity, making it difficult to maintain stability at high frequencies and limiting further improvements in measurement accuracy.

[0008] TDC technology based on FPGA internal SerDes resources

[0009] In recent years, utilizing high-speed serializers / deserializers (SerDes) embedded in FPGAs to implement time-of-conversion (TDC) has become a new trend. SerDes have extremely high operating clock frequencies, enabling direct sampling of high-speed signals and achieving picosecond-level resolution. Their low-speed parallel output after deserialization also facilitates subsequent logic processing, theoretically extending the measurement range to the second level. However, such schemes typically still rely on phase interpolators to refine the multi-phase sampling results, and phase interpolators have inherent nonlinear errors. Furthermore, existing SerDes-based TDCs often lack adaptive online calibration mechanisms, making it difficult to maintain long-term stable measurement accuracy under varying PVT conditions.

[0010] However, the existing technology has the following problems:

[0011] It is difficult to balance measurement accuracy and measurement range.

[0012] Delay chain methods are susceptible to PVT and have limited measurement range; multiphase clock methods rely on complex external circuits; while SerDes sampling has potential, it lacks an effective high-linearity interpolation structure.

[0013] The phase interpolator has nonlinear errors.

[0014] The final accuracy of SerDes-based TDC is limited by the integral nonlinearity (INL) and differential nonlinearity (DNL) of the phase interpolator, and existing schemes lack effective compensation methods.

[0015] It lacks environmental adaptability and self-calibration mechanisms.

[0016] The delay chain method is sensitive to PVT; the SerDes scheme also lacks real-time calibration means, and long-term operation or environmental changes will cause a decrease in interpolation accuracy.

[0017] The system has a high degree of complexity.

[0018] To achieve high accuracy and a wide measurement range, some solutions require external multi-channel clocks or complex front-end circuits, which increases system cost, design complexity, and resource consumption.

[0019] Therefore, there is an urgent need for a wide-range 1PPS time difference measurement method, system, device and medium. On the single-chip structure inside the FPGA, the SerDes multiphase sampling, phase interpolation and adaptive online calibration mechanism can be used to realize high-precision, wide dynamic range and high-stability 1PPS time difference measurement. Summary of the Invention

[0020] This application provides a wide-range 1PPS time difference measurement method, system, device, and medium to solve the problems of the prior art.

[0021] In a first aspect, this application provides a wide-range 1PPS time difference measurement method, including:

[0022] Step S101: Obtain the first 1PPS signal and the second 1PPS signal, perform signal conditioning and synchronization on the first 1PPS signal and the second 1PPS signal respectively, and input the processed first 1PPS signal and the second 1PPS signal to the multi-phase sampling module for multi-phase sampling to generate an M-phase basic clock sequence for phase interpolation.

[0023] Step S102: The high linearity multi-phase clock interpolator performs multi-phase weighted mixing on the M-phase base clock sequence based on the phase control word, including:

[0024] The phase control word is decoded into a first weight and a second weight by a weight decoder;

[0025] The Nth phase base clock and the N+1th phase base clock are weighted using a current-steering DAC array, respectively.

[0026] The target phase interpolation clock is obtained by current synthesis of the weighted clock signal through the phase synthesis output stage.

[0027] Step S103: Based on the target phase interpolation clock, time measurement is triggered when the first 1PPS signal and the second 1PPS signal arrive respectively. The coarse time value is recorded by a coarse counter driven by the reference clock, and the phase position of the target phase interpolation clock is extracted by a fine time encoder to obtain the corresponding fine time value. The coarse time value and the fine time value are combined to form the first timestamp of the first 1PPS signal and the second timestamp of the second 1PPS signal respectively.

[0028] Step S104: Generate the time difference measurement result between the first 1PPS signal and the second 1PPS signal based on the difference between the first timestamp and the second timestamp.

[0029] In one possible design, the phase control word is pre-distorted based on phase error compensation data in the phase error lookup table before being fed into the weighted decoder. This pre-distortion calibration is used to compensate for the integral and differential nonlinear errors generated during the multi-phase weighted mixing process performed by the high linearity multi-phase clock interpolator.

[0030] In one possible design, the weighted decoder uses temperature code encoding to decode the phase control word, in order to suppress phase glitches and differential nonlinearities caused by asynchronous switching of phase control word bits.

[0031] In one possible design, both the first and second timestamps include a coarse time value provided by a coarse counter and a fine time value provided by a fine time encoder, wherein:

[0032] The coarse counter is used to characterize the number of reference clock cycles corresponding to the arrival time of the 1PPS signal;

[0033] The fine-time encoder is used to characterize the phase difference of the 1PPS signal relative to the most recent rising edge of the reference clock;

[0034] By combining the coarse time value and the fine time value, a wide range of coarse time magnitudes and phase-level fine time magnitudes can be jointly measured for the arrival time of the 1PPS signal.

[0035] In one possible design, the method further includes updating the phase error lookup table based on an adaptive online calibration engine;

[0036] The adaptive online calibration engine includes a calibration sequence generator, a phase error detector, a calibration control state machine, and a memory for storing calibration coefficients, wherein:

[0037] The calibration sequence generator is used to generate a preset calibration pulse after the first and second timestamps are generated, which is used to trigger the online calibration process.

[0038] The phase error detector is used to acquire the measurement error generated by the high linearity multi-phase clock interpolator at multiple phase interpolation points based on the calibration pulse;

[0039] The calibration control state machine is used to calculate phase error compensation data based on the measurement error and update the phase error lookup table, so that subsequent pre-distortion calibration can be performed based on the updated compensation data.

[0040] In one possible design, the phase control word is used to determine the weighting ratio of the Nth phase base clock and the N+1th phase base clock, so that the phase of the generated target phase interpolation clock falls between the phases of the Nth phase base clock and the N+1th phase base clock.

[0041] In one possible design, the reference clock is generated by a high-stability crystal oscillator at a preset high-speed reference frequency, which drives the coarse counter to achieve wide-range time counting.

[0042] Secondly, this application provides a wide-range 1PPS time difference measurement system, comprising:

[0043] The multiphase sampling module is used to perform signal conditioning and synchronization processing on the input first 1PPS signal and second 1PPS signal, and to perform multiphase sampling on the processed first 1PPS signal and second 1PPS signal to generate an M-phase basic clock sequence for phase interpolation.

[0044] A high linearity multi-phase clock interpolator is used to perform multi-phase weighted mixing on the M-phase base clock sequence based on a phase control word and output a target phase interpolated clock. The high linearity multi-phase clock interpolator includes a weight decoder, a current-steering DAC array, and a phase synthesis output stage.

[0045] A wide-range, high-precision timestamp generation module is used to generate a first timestamp and a second timestamp based on the target phase interpolation clock. Both the first timestamp and the second timestamp include a coarse time value provided by a coarse counter and a fine time value provided by a fine time encoder.

[0046] An adaptive online calibration engine is used to update the phase error lookup table based on the measurement error triggered by the calibration pulse. The adaptive online calibration engine includes a calibration sequence generator, a phase error detector, a calibration control state machine, and a memory for storing calibration coefficients.

[0047] The 1PPS time difference calculation and output module is used to generate and output time difference measurement results based on the difference between the first timestamp and the second timestamp.

[0048] Thirdly, this application provides an electronic device, comprising:

[0049] Processor; and,

[0050] Memory for storing the executable instructions of the processor;

[0051] The processor is configured to perform any of the possible methods described in the first aspect by executing the executable instructions.

[0052] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement any of the possible methods described in the first aspect.

[0053] Compared with the prior art, this application has the following beneficial effects:

[0054] This application provides a wide-range 1PPS time difference measurement method, system, device, and medium. The method generates an M-phase basic clock sequence through a multi-phase sampling module, and performs phase-level weighted mixing using a high-linearity multi-phase clock interpolator, significantly improving phase resolution. Based on this, a combination of a coarse counter and a fine time encoder is used to generate a high-precision timestamp, thus achieving both picosecond-level resolution and second-level range time interval measurement without relying on complex external circuitry.

[0055] Furthermore, this application effectively suppresses integral and differential nonlinearities in the multi-phase weighted mixing process by introducing pre-distortion calibration of the phase error lookup table, a weighted decoder using temperature code encoding, and a joint measurement mechanism of coarse and fine time values. Simultaneously, the adaptive online calibration engine can update the phase error lookup table in real time based on calibration pulses after timestamp generation, compensating for interpolation characteristic drift caused by process, voltage, and temperature variations, thereby further improving measurement accuracy and long-term stability.

[0056] Furthermore, the wide-range 1PPS time difference measurement system provided by this invention is implemented through a modular structure. The system integrates a multi-phase sampling module, a high-linearity multi-phase clock interpolator, a wide-range high-precision timestamp generation module, an adaptive online calibration engine, and a 1PPS time difference calculation and output module. These modules collaborate within the FPGA via data paths. This structure fully utilizes the SerDes hard core resources and programmable logic of the FPGA to achieve a single-chip high-precision time difference measurement solution without the need for external multi-chip or complex clock networks, reducing system complexity and overall cost. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0058] Figure 1 This is a schematic flowchart illustrating a wide-range 1PPS time difference measurement method according to an example embodiment of this application;

[0059] Figure 2 This is a schematic diagram of a high linearity multiphase clock interpolator according to an example embodiment of this application;

[0060] Figure 3 This is a schematic diagram of the structure of an adaptive online calibration engine according to an example embodiment of this application;

[0061] Figure 4 This is a schematic diagram of the structure of a wide-range 1PPS time difference measurement system according to an example embodiment of this application;

[0062] Figure 5 This is a schematic diagram of the structure of an electronic device according to an example embodiment of this application.

[0063] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0064] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0065] This embodiment proposes a wide-range 1PPS time difference measurement method, system, device, and medium. The core of this application lies in the synergistic effect of SerDes multi-phase clock interpolation technology and adaptive online calibration mechanism to realize a 1PPS time difference measurement scheme with high precision, wide range, high stability, and good engineering feasibility on a single FPGA platform.

[0066] Figure 1 This is a schematic flowchart illustrating a wide-range 1PPS time difference measurement method according to an example embodiment of this application. Figure 1 As shown, the wide-range 1PPS time difference measurement method provided in this embodiment includes:

[0067] Step S101: Obtain the first 1PPS signal and the second 1PPS signal, perform signal conditioning and synchronization on the first 1PPS signal and the second 1PPS signal respectively, and input the processed first 1PPS signal and the second 1PPS signal to the multi-phase sampling module for multi-phase sampling to generate an M-phase basic clock sequence for phase interpolation.

[0068] In this step, the multiphase sampling module is built based on the SerDes hard-core receiver inside the FPGA. The multiphase sampling module includes a differential input buffer, a programmable delay unit, and multiple parallel deserializers, used for multiphase sampling of the first 1PPS signal and the second 1PPS signal after signal conditioning and synchronization processing. Wherein:

[0069] Differential input buffers are used to be compatible with the level format of external inputs and provide stable differential input signals.

[0070] Programmable delay units are used to finely adjust the delay of the sampling path to improve the consistency of multi-phase sampling.

[0071] Multiple deserializers operate in parallel to perform serial-to-parallel conversion on the input signal according to the oversampling method of the SerDes hard core and output an M-phase base clock sequence for phase interpolation.

[0072] The first 1PPS signal and the second 1PPS signal (e.g., LVTTL / LVCMOS level) are level-converted and then input as a serial data stream to the RX port of the multiphase sampling module.

[0073] The multiphase sampling module operates in oversampling mode. Its internal clock data recovery circuit locks the input serial data stream and generates a baseband reference clock for sampling. It should be noted that this embodiment does not directly use this baseband reference clock for sampling. Instead, it generates an M-phase base clock sequence based on the phase interpolation controller within the SerDes, where M is a preset positive integer determined by the multiphase generation capability of the SerDes hard-core receiver. This M-phase base clock sequence consists of M base clocks with the same frequency and uniformly spaced phases, where the phase interval between adjacent base clocks can be 360° / M.

[0074] Through the multi-phase sampling module, the M-phase base clock sequence simultaneously performs multi-phase sampling on the input first 1PPS signal and the second 1PPS signal, which is equivalent to increasing the sampling rate to M times the original sampling rate, thereby significantly improving the capture accuracy of the 1PPS signal transition edge.

[0075] This embodiment utilizes the high-speed sampling and phase interpolation capabilities of the SerDes hard core. Through multi-phase oversampling, the capture resolution of the 1PPS signal transition edge is improved from the nanosecond level to the picosecond level, providing a foundation for subsequent high-linearity multi-phase clock interpolators to perform fine time interpolation.

[0076] Step S102: The high linearity multiphase clock interpolator performs multiphase weighted mixing on the M-phase basic clock sequence based on the phase control word.

[0077] In this step, the high linearity multi-phase clock interpolator is the core solution to phase nonlinearity error, responsible for performing fine phase interpolation on the M-phase basic clock sequence.

[0078] like Figure 2 As shown, the high linearity multi-phase clock interpolator includes a weighted decoder, a current-steering DAC array, and a phase synthesis output stage. Wherein:

[0079] The weight decoder generates a first weight and a second weight for weighting based on the input phase control word. The first and second weights indicate the weighting ratio between the Nth phase base clock and the (N+1)th phase base clock. Here, N is an integer and satisfies 0 ≤ N. <M-1;

[0080] The current-weighted DAC array is used to perform current weighting on the basic clock of each phase under the action of the first weight and the second weight, so as to generate the corresponding weighted clock signal.

[0081] The phase synthesis output stage is used to perform current synthesis on multiple weighted clock signals to generate a target phase interpolated clock with a phase located between the Nth phase base clock and the N+1th phase base clock.

[0082] The workflow of a high-linearity multi-phase clock interpolator includes:

[0083] The phase control word is decoded into a first weight and a second weight by a weight decoder;

[0084] The Nth phase base clock and the N+1th phase base clock are weighted using a current-steering DAC array, respectively.

[0085] The target phase interpolated clock is obtained by performing current synthesis on the weighted clock signal through the phase synthesis output stage.

[0086] In this embodiment, the phase control word is used to determine the weighting ratio of the Nth phase base clock and the N+1th phase base clock, so that the phase of the generated target phase interpolation clock falls between the phases of the Nth phase base clock and the N+1th phase base clock.

[0087] The weighted decoder uses temperature code encoding to decode the phase control word, which is used to suppress phase glitches and differential nonlinearities caused by asynchronous switching of phase control word bits.

[0088] Before being sent to the weighted decoder, the phase control word undergoes pre-distortion calibration based on phase error compensation data in the phase error lookup table. This pre-distortion calibration compensates for the integral and differential nonlinearity errors generated during the multi-phase weighted mixing process of the high-linearity multi-phase clock interpolator. Specifically, a phase error lookup table is pre-stored in the FPGA's block RAM to record the deviation between each ideal phase control word and its corresponding actual output phase. This deviation includes integral nonlinearity (INL) and differential nonlinearity (DNL) errors. When a target phase control word is received, the calibration logic reads the corresponding error compensation data from the phase error lookup table and corrects the target phase control word in real time to obtain a calibrated phase control word, which is then sent to the weighted decoder for multi-phase weighted mixing. This pre-distortion calibration effectively reduces the inherent phase nonlinearity caused by transistor mismatch, temperature drift, and other factors, improving the linearity of the interpolation phase control process.

[0089] This embodiment combines pre-distortion calibration based on a phase error lookup table with temperature code encoding and decoding to correct the phase control process of a high-linearity multi-phase clock interpolator, making the correspondence between the phase control word and the output phase more linear. This results in a more uniform actual phase step size generated by phase interpolation, significantly reducing differential and integral nonlinear deviations during interpolation, thereby improving the accuracy and stability of 1PPS signal time difference measurement.

[0090] Step S103: Based on the target phase interpolation clock, time measurements are triggered when the first 1PPS signal and the second 1PPS signal arrive, respectively. The corresponding coarse time value is recorded using a coarse counter driven by a reference clock, and the phase position of the target phase interpolation clock is extracted by a fine time encoder to obtain the corresponding fine time value. The coarse time value and the fine time value are combined to form the first timestamp of the first 1PPS signal and the second timestamp of the second 1PPS signal, respectively.

[0091] In this step, both the first timestamp and the second timestamp include a coarse time value provided by a coarse counter and a fine time value provided by a fine time encoder, wherein:

[0092] The coarse counter is used to characterize the number of reference clock cycles corresponding to the arrival time of the 1PPS signal. The reference clock is generated by a high-stability crystal oscillator at a preset high-speed reference frequency, which drives the coarse counter to achieve wide-range time counting.

[0093] The fine-time encoder is used to characterize the phase difference of the 1PPS signal relative to the most recent rising edge of the reference clock;

[0094] By combining the coarse time value and the fine time value, a wide range of coarse time magnitudes and phase-level fine time magnitudes can be jointly measured for the arrival time of the 1PPS signal.

[0095] It should be noted that the coarse time value is implemented by a coarse counter driven by a reference clock generated by a high-stability crystal oscillator. The reference clock frequency can be a preset high-speed frequency (e.g., 125MHz), and the corresponding clock period serves as the smallest unit for coarse time counting. The coarse counter counts continuously under the drive of the reference clock, and is used to characterize the coarse time value on the order of "seconds" or "milliseconds" when the 1PPS signal arrives.

[0096] When the rising edge of the 1PPS signal arrives, the fine-time encoder locks the phase state of the current high-linearity multi-phase clock interpolator. This phase state reflects the phase difference between the rising edge of the 1PPS signal and the most recent rising edge of the reference clock. The fine-time encoder generates a corresponding fine-time value based on this phase difference, achieving sub-nanosecond or even picosecond time resolution. Combining the coarse-time value with the fine-time value forms a corresponding high-precision timestamp.

[0097] This embodiment employs a hybrid measurement architecture combining coarse counting and fine time interpolation. A coarse counter driven by a reference clock achieves a wide range of time counting on timescales of seconds or even longer, while a fine time resolution on the sub-nanosecond or even picosecond scale is obtained by relying on SerDes multi-phase sampling and a high-linearity multi-phase clock interpolator. This hybrid measurement architecture effectively balances measurement range and accuracy, resolving the technical contradiction of traditional time-to-digital conversion methods in simultaneously achieving wide dynamic range and high resolution.

[0098] Step S104: Generate the time difference measurement result between the first 1PPS signal and the second 1PPS signal based on the difference between the first timestamp and the second timestamp.

[0099] In this step, based on the first timestamp and the second timestamp, a subtraction operation is used to calculate the difference between the two to obtain the time difference measurement result between the first 1PPS signal and the second 1PPS signal.

[0100] The time difference measurement results can be transmitted to a host computer or external device via SPI interface or other data output interfaces for subsequent time synchronization processing or system scheduling. This step realizes time difference calculation and output, with a simple structure and reliable implementation.

[0101] Figure 3 This is a schematic diagram illustrating the structure of an adaptive online calibration engine according to an example embodiment of this application. Figure 3 As shown, the adaptive online calibration engine provided in this embodiment includes:

[0102] In this step, the phase error lookup table is updated based on the adaptive online calibration engine;

[0103] The adaptive online calibration engine includes a calibration sequence generator, a phase error detector, a calibration control state machine, and a memory for storing calibration coefficients, wherein:

[0104] The calibration sequence generator is used to generate a preset calibration pulse after the first and second timestamps are generated, which is used to trigger the online calibration process.

[0105] The phase error detector is used to acquire the measurement error generated by the high linearity multi-phase clock interpolator at multiple phase interpolation points based on the calibration pulse;

[0106] The calibration control state machine is used to calculate phase error compensation data based on the measurement error and update the phase error lookup table, so that subsequent pre-distortion calibration can be performed based on the updated compensation data.

[0107] The workflow of the adaptive online calibration engine includes:

[0108] The adaptive online calibration engine is invoked during initialization or periodic triggering when triggered by conditions such as power-on initialization, the arrival of a preset calibration cycle, or the detection of temperature changes or power supply voltage changes.

[0109] A calibration signal is injected, and the calibration sequence generator produces a preset, steep-edge calibration pulse. This calibration pulse is injected simultaneously into both the measurement link and the calibration reference link via a fixed path with good symmetry within the FPGA to construct a known time reference.

[0110] Error detection and acquisition: The phase error detector calculates the deviation between the first and second timestamps output by the measurement link and the ideal reference time, obtaining the measurement error of the current high-linearity multi-phase clock interpolator at each phase interpolation point. Error acquisition is repeatedly performed at multiple interpolation phase positions to comprehensively characterize the nonlinear characteristics of the interpolator.

[0111] The coefficient calculation and updating process involves the calibration control state machine calculating phase error compensation data based on the collected measurement errors using a preset fitting algorithm (such as least squares fitting), and updating the phase error lookup table accordingly, so that subsequent pre-distortion calibration is performed based on the updated compensation data.

[0112] Once calibration is complete and the phase error lookup table is updated, the system returns to normal measurement mode (i.e., executes the 1PPS time difference measurement procedure). The updated phase error compensation data effectively suppresses phase interpolation nonlinear drift caused by differences in device process technology, voltage fluctuations, and temperature changes, maintaining high-precision measurement performance even under long-term operation and wide temperature range conditions.

[0113] Figure 4 This is a schematic diagram of a wide-range 1PPS time difference measurement system according to an example embodiment of this application. Figure 4 As shown, the wide-range 1PPS time difference measurement system 400 provided in this embodiment includes: a multi-phase sampling module 410, a high-linearity multi-phase clock interpolator 420, a wide-range high-precision timestamp generation module 430, an adaptive online calibration engine 440, and a 1PPS time difference calculation and output module 450.

[0114] The multiphase sampling module 410 is used to perform signal conditioning and synchronization processing on the input first 1PPS signal and second 1PPS signal, and to perform multiphase sampling on the processed first 1PPS signal and second 1PPS signal to generate an M-phase basic clock sequence for phase interpolation.

[0115] A high linearity multi-phase clock interpolator 420 is used to perform multi-phase weighted mixing on the M-phase basic clock sequence based on a phase control word and output a target phase interpolated clock. The high linearity multi-phase clock interpolator includes a weight decoder, a current-steering DAC array, and a phase synthesis output stage.

[0116] A wide-range, high-precision timestamp generation module 430 is used to generate a first timestamp and a second timestamp based on the target phase interpolation clock. Both the first timestamp and the second timestamp include a coarse time value provided by a coarse counter and a fine time value provided by a fine time encoder.

[0117] An adaptive online calibration engine 440 is used to update a phase error lookup table based on measurement errors triggered by calibration pulses. The adaptive online calibration engine includes a calibration sequence generator, a phase error detector, a calibration control state machine, and a memory for storing calibration coefficients.

[0118] The 1PPS time difference calculation and output module 450 is used to generate and output time difference measurement results based on the difference between the first timestamp and the second timestamp. The 1PPS time difference calculation and output module 450 can realize time difference calculation through the arithmetic unit running in the FPGA programmable logic, and output the time difference measurement results through the data output interface.

[0119] The workflow of the wide-range 1PPS time difference measurement system 400 includes:

[0120] Step S101: Acquire the first 1PPS signal and the second 1PPS signal, perform signal conditioning and synchronization on the first 1PPS signal and the second 1PPS signal respectively, and input the processed first 1PPS signal and the second 1PPS signal to the multiphase sampling module 410 for multiphase sampling to generate an M-phase basic clock sequence for phase interpolation.

[0121] Step S102: The high linearity multi-phase clock interpolator 420 performs multi-phase weighted mixing on the M-phase basic clock sequence based on the phase control word to obtain the target phase interpolated clock.

[0122] Step S103: The wide-range high-precision timestamp generation module 430 triggers time measurement when the first 1PPS signal and the second 1PPS signal arrive based on the target phase interpolation clock. It records the corresponding coarse time value using a coarse counter driven by a reference clock, and extracts the phase position of the target phase interpolation clock through a fine time encoder to obtain the corresponding fine time value. The coarse time value and the fine time value are combined to form the first timestamp of the first 1PPS signal and the second timestamp of the second 1PPS signal, respectively.

[0123] Step S104: Based on the difference between the first timestamp and the second timestamp, the 1PPS time difference calculation and output module 450 generates the time difference measurement result between the first 1PPS signal and the second 1PPS signal.

[0124] The wide-range 1PPS time difference measurement system 400 also includes an adaptive online calibration engine 440 for updating the phase error lookup table. The adaptive online calibration engine is invoked upon system power-on initialization, the arrival of a preset calibration cycle, or the detection of trigger conditions such as temperature changes or power supply voltage changes. Once the phase error lookup table is updated, the system returns to normal measurement mode (i.e., executes the 1PPS time difference measurement procedure).

[0125] Figure 5 This is a schematic diagram of the structure of an electronic device according to an example embodiment of this application. For example... Figure 5 As shown, the electronic device 500 provided in this embodiment includes: a processor 501 and a memory 502. Wherein:

[0126] Memory 502 is used to store computer programs, and the memory may also be flash memory.

[0127] Processor 501 is used to execute the execution instructions stored in the memory to implement the various steps in the above method. For details, please refer to the relevant descriptions in the preceding method embodiments.

[0128] Alternatively, the memory 502 can be either standalone or integrated with the processor 501.

[0129] When the memory 502 is a device independent of the processor 501, the electronic device 500 may further include:

[0130] Bus 503 is used to connect the memory 502 and the processor 501.

[0131] This embodiment also provides a readable storage medium storing a computer program, which, when executed by at least one processor of an electronic device, enables the electronic device to perform the methods provided in the various embodiments described above.

[0132] This embodiment also provides a program product including a computer program stored in a readable storage medium. At least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the electronic device to perform the methods provided in the various embodiments described above.

[0133] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the foregoing claims.

[0134] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A wide-range 1PPS time difference measurement method, characterized in that, include: Step S101: Obtain the first 1PPS signal and the second 1PPS signal, perform signal conditioning and synchronization on the first 1PPS signal and the second 1PPS signal respectively, and input the processed first 1PPS signal and the second 1PPS signal to the multi-phase sampling module for multi-phase sampling to generate an M-phase basic clock sequence for phase interpolation. Step S102: The high linearity multi-phase clock interpolator performs multi-phase weighted mixing on the M-phase base clock sequence based on the phase control word, including: The phase control word is decoded into a first weight and a second weight by a weight decoder; The Nth phase base clock and the N+1th phase base clock are weighted using a current-steering DAC array, respectively. The target phase interpolation clock is obtained by current synthesis of the weighted clock signal through the phase synthesis output stage. Step S103: Based on the target phase interpolation clock, time measurement is triggered when the first 1PPS signal and the second 1PPS signal arrive respectively. The coarse time value is recorded by a coarse counter driven by the reference clock, and the phase position of the target phase interpolation clock is extracted by a fine time encoder to obtain the corresponding fine time value. The coarse time value and the fine time value are combined to form the first timestamp of the first 1PPS signal and the second timestamp of the second 1PPS signal respectively. Step S104: Generate the time difference measurement result between the first 1PPS signal and the second 1PPS signal based on the difference between the first timestamp and the second timestamp.

2. The wide-range 1PPS time difference measurement method according to claim 1, characterized in that, Before being sent to the weighted decoder, the phase control word is pre-distorted based on the phase error compensation data in the phase error lookup table. This pre-distortion calibration is used to compensate for the integral and differential nonlinear errors generated during the multi-phase weighted mixing process of the high linearity multi-phase clock interpolator.

3. The wide-range 1PPS time difference measurement method according to claim 1, characterized in that, The weighted decoder uses temperature code encoding to decode the phase control word, which is used to suppress phase glitches and differential nonlinearities caused by asynchronous switching of phase control word bits.

4. The wide-range 1PPS time difference measurement method according to claim 1, characterized in that, Both the first and second timestamps include a coarse time value provided by a coarse counter and a fine time value provided by a fine time encoder, wherein: The coarse counter is used to characterize the number of reference clock cycles corresponding to the arrival time of the 1PPS signal; The fine-time encoder is used to characterize the phase difference of the 1PPS signal relative to the most recent rising edge of the reference clock; By combining the coarse time value and the fine time value, a wide range of coarse time magnitudes and phase-level fine time magnitudes can be jointly measured for the arrival time of the 1PPS signal.

5. The wide-range 1PPS time difference measurement method according to claim 2, characterized in that, The method also includes updating the phase error lookup table based on an adaptive online calibration engine; The adaptive online calibration engine includes a calibration sequence generator, a phase error detector, a calibration control state machine, and a memory for storing calibration coefficients, wherein: The calibration sequence generator is used to generate a preset calibration pulse after the first and second timestamps are generated, which is used to trigger the online calibration process. The phase error detector is used to acquire the measurement error generated by the high linearity multi-phase clock interpolator at multiple phase interpolation points based on the calibration pulse; The calibration control state machine is used to calculate phase error compensation data based on the measurement error and update the phase error lookup table, so that subsequent pre-distortion calibration can be performed based on the updated compensation data.

6. The wide-range 1PPS time difference measurement method according to claim 1, characterized in that, The phase control word is used to determine the weighting ratio of the Nth phase base clock and the N+1th phase base clock, so that the phase of the generated target phase interpolation clock falls between the phases of the Nth phase base clock and the N+1th phase base clock.

7. The wide-range 1PPS time difference measurement method according to claim 1, characterized in that, The reference clock is generated by a high-stability crystal oscillator with a preset high-speed reference frequency, which is used to drive the coarse counter to achieve wide-range time counting.

8. A wide-range 1PPS time difference measurement system for performing the method according to any one of claims 1 to 7, characterized in that, include: The multiphase sampling module is used to perform signal conditioning and synchronization processing on the input first 1PPS signal and second 1PPS signal, and to perform multiphase sampling on the processed first 1PPS signal and second 1PPS signal to generate an M-phase basic clock sequence for phase interpolation. A high linearity multi-phase clock interpolator is used to perform multi-phase weighted mixing on the M-phase base clock sequence based on a phase control word and output a target phase interpolated clock. The high linearity multi-phase clock interpolator includes a weight decoder, a current-steering DAC array, and a phase synthesis output stage. A wide-range, high-precision timestamp generation module is used to generate a first timestamp and a second timestamp based on the target phase interpolation clock. Both the first timestamp and the second timestamp include a coarse time value provided by a coarse counter and a fine time value provided by a fine time encoder. An adaptive online calibration engine is used to update the phase error lookup table based on the measurement error triggered by the calibration pulse. The adaptive online calibration engine includes a calibration sequence generator, a phase error detector, a calibration control state machine, and a memory for storing calibration coefficients. The 1PPS time difference calculation and output module is used to generate and output time difference measurement results based on the difference between the first timestamp and the second timestamp.

9. An electronic device, characterized in that, include: processor; as well as, Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 7.

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